52025 lines
3.7 MiB
52025 lines
3.7 MiB
; --------------------------------------------------------------------------------
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; @Title: AWR On-Chip Peripherals
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; @Props: Released
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; @Author: MTR, RMG, KWI, KOL, ASK, MHM, STR, MRO, KOP, CEZ, DLI, DOR, KRZ, PAK,
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; KOF, DAS, TRJ
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; @Changelog: 2016-11-24 ASK
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; 2018-03-02 KOL
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; 2019-01-16 PEG
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; 2019-03-23 MRO
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; 2019-07-18 KOP
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; 2020-12-03 KOF
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; @Manufacturer: TI - Texas Instruments
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; @Doc: AWR16xx_14xx (Technical Reference Manual) [swru520].pdf (Rev. SWRU520, 2017-05)
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; AWR1443 (Data Sheet) [swrs202].pdf (Rev. SWRS202, 2017-05)
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; AWR1642 (Data Sheet) [swrs203].pdf (Rev. SWRS203, 2017-05)
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; AWR1843.pdf (Rev. SWRS222, 2018-12)
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; swru520a.pdf (Rev. A, 2017-06)
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; swru520c.pdf (Rev. C, 2018-12)
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; swrz072a.pdf (Rev. A, 2017-05)
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; swru526b.pdf (Rev. B, 2018-10)
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; swru520e.pdf (Rev. E, 2020-05)
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; @Core: Cortex-R4F, C674x
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; @Chip: AWR1843, AWR1843-CORE1, AWR1843DSP, AWR1642, AWR1443, AWR6843,
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; AWR6843-CORE1, AWR6843DSP
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; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perawr.per 13121 2021-03-30 07:13:08Z bschroefel $
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; Known Problems:
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; MODULE REGISTER DESCRIPTION
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; MIBSPI TGITFLG Incompatibility between access type and description for INTFLGRDY
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; MIBSPI PAR_ECC_STAT Incompatibility between access type and description for all bits
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; AWR SYSRSTCAUSECLR Missing information about register access type
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; SECURERAMREG Missing information about bit SECURERAMKEYRD access type
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; MEMINITSTARTSHMEM Missing information about register access type
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; GPIO ALL Inconsistency between "awr6843 - Data Sheet.pdf" and "swru520e - TRM.pdf",
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; currently the GIO registers were written out according to TRM
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config 16. 8.
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sif (CORENAME()=="CORTEXR4F")
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tree "Core Registers (Cortex-R4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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width 0x8
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; --------------------------------------------------------------------------------
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; Identification registers
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; --------------------------------------------------------------------------------
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tree "ID Registers"
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rgroup c15:0x0--0x0
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line.long 0x0 "MIDR,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup c15:0x100--0x100
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line.long 0x0 "CTR,Cache Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
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bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
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textline " "
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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rgroup c15:0x200--0x200
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line.long 0x0 "TCMSR,Tighly-Coupled Memory Status Register"
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bitfld.long 0x0 16.--19. " DTCMS ,Data Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0.--3. " ITCMS ,Instruction Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup c15:0x400--0x400
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line.long 0x0 "MPUIR,MPU type register"
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hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions"
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bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated"
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rgroup c15:0x500--0x500
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line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
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hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2"
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hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1"
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hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0"
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textline " "
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rgroup c15:0x0410++0x00
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line.long 0x00 "MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
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rgroup c15:0x0510++0x00
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line.long 0x00 "MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
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rgroup c15:0x0610++0x00
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line.long 0x00 "MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
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bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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rgroup c15:0x0710++0x00
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line.long 0x00 "MMFR3,Memory Model Feature Register 3"
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bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
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rgroup c15:0x0020++0x00
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line.long 0x00 "ISAR0,Instruction Set Attribute Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0120++0x00
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line.long 0x00 "ISAR1,Instruction Set Attribute Register 1"
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bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0220++0x00
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line.long 0x00 "ISAR2,Instruction Set Attribute Register 2"
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bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0320++0x00
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line.long 0x00 "ISAR3,Instruction Set Attribute Register 3"
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bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0420++0x00
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line.long 0x00 "ISAR4,Instruction Set Attribute Register 4"
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bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
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rgroup c15:0x0520++0x00
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line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
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rgroup c15:0x0620++0x00
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line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
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rgroup c15:0x0720++0x00
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line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
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rgroup c15:0x0010++0x00
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
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rgroup c15:0x0110++0x00
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line.long 0x00 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
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bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
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textline " "
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rgroup c15:0x0210++0x00
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line.long 0x00 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
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rgroup c15:0x0310++0x00
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line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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tree.end
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width 0x8
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tree "System Control and Configuration"
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group c15:0x1--0x1
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line.long 0x0 "SCTLR,Control Register"
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bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big"
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bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
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bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
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bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
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bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
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textline " "
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bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
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bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored"
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bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable"
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bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable"
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bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
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bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
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textline " "
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bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
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bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
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bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable"
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bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
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bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable"
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textline " "
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group c15:0x101--0x101
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line.long 0x0 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 31. " DICDI ,Disable Case C dual issue control" "Enable,Disable"
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bitfld.long 0x00 30. " DIB2DI ,Disable Case B2 dual issue control" "Enable,Disable"
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bitfld.long 0x00 29. " DIB1DI ,Disable Case B1 dual issue control" "Enable,Disable"
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textline " "
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bitfld.long 0x00 28. " DIADI ,Disable Case A dual issue control" "Enable,Disable"
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bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
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bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
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textline " "
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bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
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bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "Disable,Enable"
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bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "Disable,Enable"
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textline " "
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bitfld.long 0x00 22. " DILSM ,Disable LIL on load/store multiples" "Disable,Enable"
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bitfld.long 0x00 21. " DEOLP ,Disable end of loop prediction" "Disable,Enable"
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bitfld.long 0x00 20. " DBHE ,Disable BH extension" "Enable,Disable"
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textline " "
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bitfld.long 0x00 19. " FRCDIS ,Fetch rate control disable" "Enable,Disable"
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bitfld.long 0x00 17. " RSDIS ,Return stack disable" "Enable,Disable"
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bitfld.long 0x00 15.--16. " BP ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..."
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textline " "
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bitfld.long 0x00 14. " DBWR ,Disable write_burst on AXI master" "Enable,Disable"
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bitfld.long 0x00 13. " DSWT ,Disable should_wait on AXI master" "Enable,Disable"
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bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "Disable,Enable"
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textline " "
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bitfld.long 0x00 11. " DOLT ,Disable outstanding line fill on AXI master" "Enable,Disable"
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bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced"
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bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced"
|
|
textline " "
|
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bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced"
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|
bitfld.long 0x00 7. " sMOV ,sMOV disabled" "Enabled,Disabled"
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bitfld.long 0x0 6. " DILS ,Disable low interrupt latency on all load/store instructions" "Enable,Disable"
|
|
textline " "
|
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bitfld.long 0x00 5. " DA ,DA Disable abort on cache parity error" "Enable,Disable"
|
|
bitfld.long 0x00 4. " EHR ,Enable hardware recovery from cache parity errors" "Disable,Enable"
|
|
bitfld.long 0x00 2. " I1TCMECEN ,Instruction 1 TCM error check enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I0TCMECEN ,Instruction 1 TCM error check enable" "Disable,Enable"
|
|
bitfld.long 0x00 0. " ITCMECEN ,Instruction TCM error check enable" "Disable,Enable"
|
|
textline " "
|
|
group c15:0x0f--0x0f
|
|
line.long 0x0 "SACTLR,Secondary Auxiliary Control Register"
|
|
bitfld.long 0x00 22. " DCHE ,Disable hard-error support in the caches" "Enable,Disable"
|
|
bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable"
|
|
bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,Disable"
|
|
bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,Disable"
|
|
bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate"
|
|
textline " "
|
|
bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 9. " DZC ,Floating-point divide-by-zero exception output mask" "Mask,Propagate"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate"
|
|
bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,Disable"
|
|
bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,Disable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "Disable,Enable"
|
|
bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "Disable,Enable"
|
|
textline " "
|
|
group c15:0x201--0x201
|
|
line.long 0x0 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
group.long c15:0x0b--0x0b
|
|
line.long 0x00 "SPC,Slave Port Control"
|
|
bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only"
|
|
bitfld.long 0x00 0. " AXISLEN ,AXI slave port disable" "Enabled,Disabled"
|
|
tree.end
|
|
width 0x8
|
|
tree "MPU Control and Configuration"
|
|
group c15:0x0001--0x0001
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
|
|
bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored"
|
|
bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable"
|
|
bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable"
|
|
bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
|
|
bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
|
|
bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable"
|
|
textline " "
|
|
group.long c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x0015++0x00
|
|
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
|
|
group.long c15:0x0006++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
group.long c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR"
|
|
bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
|
|
group.long c15:0x0115++0x00
|
|
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
|
|
group.long c15:0x0206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
line.long 0x00 "RBAR,Region Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
line.long 0x00 "RSER,Region Size and Enable Register"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
line.long 0x00 "RACR,Region Access Control Register"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
group c15:0x0026++0x00
|
|
line.long 0x00 "MRNR,Memory Region Number Register"
|
|
bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
group c15:0x010d++0x00
|
|
line.long 0x00 "CIDR,Context ID Register"
|
|
group.long c15:0x20d++0x00
|
|
line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register"
|
|
group.long c15:0x30d++0x00
|
|
line.long 0x00 "TIDRURO,User read only Thread and Process ID Register"
|
|
group.long c15:0x40d++0x00
|
|
line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register"
|
|
tree "MPU regions"
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RBAR0,Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RSER0,Region Size and Enable Register 0"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x0
|
|
line.long 0x00 "RACR0,Region Access Control Register 0"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RBAR1,Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RSER1,Region Size and Enable Register 1"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x1
|
|
line.long 0x00 "RACR1,Region Access Control Register 1"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RBAR2,Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RSER2,Region Size and Enable Register 2"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x2
|
|
line.long 0x00 "RACR2,Region Access Control Register 2"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RBAR3,Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RSER3,Region Size and Enable Register 3"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x3
|
|
line.long 0x00 "RACR3,Region Access Control Register 3"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RBAR4,Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RSER4,Region Size and Enable Register 4"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x4
|
|
line.long 0x00 "RACR4,Region Access Control Register 4"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RBAR5,Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RSER5,Region Size and Enable Register 5"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x5
|
|
line.long 0x00 "RACR5,Region Access Control Register 5"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RBAR6,Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RSER6,Region Size and Enable Register 6"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x6
|
|
line.long 0x00 "RACR6,Region Access Control Register 6"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RBAR7,Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RSER7,Region Size and Enable Register 7"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x7
|
|
line.long 0x00 "RACR7,Region Access Control Register 7"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RBAR8,Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RSER8,Region Size and Enable Register 8"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x8
|
|
line.long 0x00 "RACR8,Region Access Control Register 8"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RBAR9,Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RSER9,Region Size and Enable Register 9"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0x9
|
|
line.long 0x00 "RACR9,Region Access Control Register 9"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RBAR10,Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RSER10,Region Size and Enable Register 10"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xA
|
|
line.long 0x00 "RACR10,Region Access Control Register 10"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
group c15:0x0016++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RBAR11,Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " BA ,Base address"
|
|
group c15:0x0216++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RSER11,Region Size and Enable Register 11"
|
|
bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D"
|
|
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
|
|
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
|
|
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
|
|
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
|
|
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
|
|
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
|
|
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
|
|
bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
group c15:0x0416++0x00
|
|
saveout c15:0x26 %l 0xB
|
|
line.long 0x00 "RACR11,Region Access Control Register 11"
|
|
bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec"
|
|
bitfld.long 0x00 2. " S ,Share" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
|
|
bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
|
|
textline " "
|
|
tree.end
|
|
tree.end
|
|
width 0x9
|
|
tree "TCM Control and Configuration"
|
|
rgroup.long c15:0x200++0x00
|
|
line.long 0x00 "TCMTR,TCM Type Register"
|
|
bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x019++0x00
|
|
line.long 0x00 "BTCMRR,BTCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,?..."
|
|
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled"
|
|
group.long c15:0x119++0x00
|
|
line.long 0x00 "ATCMRR,ATCM Region Register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)"
|
|
bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,?..."
|
|
bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled"
|
|
rgroup.long c15:0x29++0x00
|
|
line.long 0x00 "TCMSEL,TCM Selection Register"
|
|
tree.end
|
|
width 0xC
|
|
tree "Cache Control and Configuration"
|
|
rgroup.long c15:0x1100--0x1100
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LoU ,Level of Unification" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " LoC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7"
|
|
rgroup.long c15:0x1000++0x00
|
|
line.long 0x00 "CCSIDR,Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported"
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported"
|
|
textline " "
|
|
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7"
|
|
group.long c15:0x2000--0x2000
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " Level ,Cache level to select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " InD ,Instruction or data or unified cache to use" "Data/unified,Instruction"
|
|
group.long c15:0x03f++0x00
|
|
line.long 0x00 "CFLR,Correctable Fault Location Register"
|
|
bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred"
|
|
bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP"
|
|
rgroup.long c15:0x0ef++0x0
|
|
line.long 0x00 "CSOR,Cache Size Override Register"
|
|
bitfld.long 0x00 4.--6. " Dcache ,Validation data cache size" "Not presented,Reserved,Reserved,4k,8k,16k,32k,64k"
|
|
bitfld.long 0x00 0.--2. " Icache ,Validation instruction cache size" "Not presented,Reserved,Reserved,4k,8k,16k,32k,64k"
|
|
tree.end
|
|
width 8.
|
|
tree "System Performance Monitor"
|
|
group c15:0xC9--0xC9
|
|
line.long 0x0 "PMNC,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle"
|
|
bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled"
|
|
group c15:0x1C9--0x1C9
|
|
line.long 0x0 "CNTENS,Count Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group c15:0x2C9--0x2C9
|
|
line.long 0x0 "CNTENC,Count Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group c15:0x3C9--0x3C9
|
|
line.long 0x0 "FLAG,Overflow Flag Status Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow"
|
|
group c15:0x4C9--0x4C9
|
|
line.long 0x0 "SWINCR,Software Increment Register"
|
|
eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment"
|
|
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group c15:0x5C9--0x5C9
|
|
line.long 0x0 "PMNXSEL,Performance Counter Selection Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,?..."
|
|
group c15:0xD9--0xD9
|
|
line.long 0x0 "CCNT,Cycle Count Register"
|
|
group c15:0x01d9++0x00
|
|
line.long 0x00 "ESR,Event Selection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
line.long 0x00 "PMCR,Performance Monitor Count Register"
|
|
group c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x0
|
|
line.long 0x00 "ESR0,Event Selection Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x0
|
|
line.long 0x00 "PMCR0,Performance Monitor Count Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x1
|
|
line.long 0x00 "ESR1,Event Selection Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x1
|
|
line.long 0x00 "PMCR1,Performance Monitor Count Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group c15:0x01d9++0x00
|
|
saveout c15:0x5C9 %l 0x2
|
|
line.long 0x00 "ESR2,Event Selection Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
saveout c15:0x5C9 %l 0x2
|
|
line.long 0x00 "PMCR2,Performance Monitor Count Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
|
|
group c15:0xE9--0xE9
|
|
line.long 0x0 "USEREN,User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled"
|
|
group c15:0x1E9--0x1E9
|
|
line.long 0x0 "INTENS,Interrupt Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
group c15:0x2E9--0x2E9
|
|
line.long 0x0 "INTENC,Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
tree.end
|
|
width 8.
|
|
tree "Debug Registers"
|
|
width 11.
|
|
tree "Processor Identifier Registers"
|
|
rgroup c14:0x340--0x340
|
|
line.long 0x00 "MIDR,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture"
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
|
|
rgroup c14:0x341--0x341
|
|
line.long 0x00 "CACHETYPE,Cache Type Register"
|
|
bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
rgroup c14:0x343--0x343
|
|
line.long 0x00 "TLBTYPE,TLB Type Register"
|
|
hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries"
|
|
hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries"
|
|
textline " "
|
|
bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate"
|
|
rgroup c14:0x348--0x348
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x349--0x349
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x34a--0x34a
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
|
|
rgroup c14:0x34b--0x34b
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
|
|
rgroup c14:0x34c--0x34c
|
|
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x34d--0x34d
|
|
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
|
|
rgroup c14:0x34e--0x34e
|
|
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup c14:0x34f--0x34f
|
|
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x350--0x350
|
|
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x351--0x351
|
|
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x352--0x352
|
|
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x353--0x353
|
|
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x354--0x354
|
|
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
|
|
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x355--0x355
|
|
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
|
|
tree.end
|
|
tree "Coresight Management Registers"
|
|
width 0xC
|
|
textline " "
|
|
group c14:0x03bd++0x00
|
|
line.long 0x00 "ITCTRL_IOC,Integration Internal Output Control Register"
|
|
bitfld.long 0x00 5. " I_DBGTRIGGER ,Internal DBGTRIGGER" "0,1"
|
|
bitfld.long 0x00 4. " I_DBGRESTARTED ,Internal DBGRESTARTED" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I_NPMUIRQ ,Internal nPMUIRQ" "0,1"
|
|
bitfld.long 0x00 2. " InternalCOMMTX ,Internal COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I_COMMRX ,Internal COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " I_DBGACK ,Internal DBGACK" "0,1"
|
|
group c14:0x03be++0x00
|
|
line.long 0x00 "ITCTRL_EOC,Integration External Output Control Register"
|
|
bitfld.long 0x00 7. " NDMAEXTERRIQ ,External nDMAEXTERRIRQ" "0,1"
|
|
bitfld.long 0x00 6. " NDMASIRQ ,External nDMASIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NDMAIRQ ,External nDMAIRQ" "0,1"
|
|
bitfld.long 0x00 4. " NPMUIRQ ,External nPMUIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STANDBYWFI ,External STANDBYWFI" "0,1"
|
|
bitfld.long 0x00 2. " COMMTX ,External COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " COMMRX ,External COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " DBGACK ,External DBGACK" "0,1"
|
|
rgroup c14:0x03bf++0x00
|
|
line.long 0x00 "ITCTRL_IS,Integration Input Status Register"
|
|
bitfld.long 0x00 11. " CTI_DBGRESTART ,CTI Debug Restart" "0,1"
|
|
bitfld.long 0x00 10. " CTI_EDBGRQ ,CTI Debug Request" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTI_PMUEXTIN[1] ,CTI PMUEXTIN[1] Signal" "0,1"
|
|
bitfld.long 0x00 8. " CTI_PMUEXTIN[0] ,CTI PMUEXTIN[0] Signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NFIQ ,nFIQ Input" "0,1"
|
|
bitfld.long 0x00 1. " NIRQ ,nIRQ Input" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EDBGRQ ,EDBGRQ Input" "0,1"
|
|
group c14:0x3c0--0x3c0
|
|
line.long 0x0 "ITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled"
|
|
group c14:0x3e8--0x3e8
|
|
line.long 0x0 "CLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set"
|
|
group c14:0x3e9--0x3e9
|
|
line.long 0x0 "CLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared"
|
|
wgroup c14:0x3ec--0x3ec
|
|
line.long 0x0 "LAR,Lock Access Register"
|
|
hexmask.long.long 0x0 0.--31. 1. " LACK ,Lock Access Control Key"
|
|
rgroup c14:0x3ed--0x3ed
|
|
line.long 0x0 "LSR,Lock Status Register"
|
|
bitfld.long 0x0 2. " 32ACND ,32-bit Access Needed" "Needed,Not needed"
|
|
bitfld.long 0x0 1. " WLCK ,Writes Lock" "Permitted,Ignored"
|
|
textline " "
|
|
bitfld.long 0x0 0. " LI ,Lock Implementation" "Lock ignored,Unlock required"
|
|
rgroup c14:0x3ee--0x3ee
|
|
line.long 0x0 "AUTHSTATUS,Authentication Status Register"
|
|
bitfld.long 0x0 7. " SNIDFI ,Secure Non-invasive Debug Features Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 6. " SNIDE ,Secure Non-invasive Debug Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " SIDFI ,Secure Invasive Debug Feauter Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 4. " SIDE ,Secure Invasive Debug Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " NSNIDFI ,Non-secure Non-invasive Debug Feature Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 2. " NSNIDE ,Non-secure Non-invasive Debug Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " NSIDFI ,Non-secure Invasive Debug Implemented" "Not Implemented,Implemented"
|
|
bitfld.long 0x0 0. " NSIDE ,Non-secure Invasive Debug Enable" "Disabled,Enabled"
|
|
hgroup c14:0x3f2--0x3f2
|
|
hide.long 0x0 "DEVID,Device Identifier (RESERVED)"
|
|
rgroup c14:0x3f3--0x3f3
|
|
line.long 0x0 "DEVTYPE,Device Type"
|
|
hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class"
|
|
rgroup c14:0x3f8--0x3f8
|
|
line.long 0x0 "PID0,Peripherial ID0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PN ,Part Number [7:0]"
|
|
rgroup c14:0x3f9--0x3f9
|
|
line.long 0x0 "PID1,Peripherial ID1"
|
|
hexmask.long.byte 0x0 4.--7. 1. " JEP106 ,JEP106 Identity Code [3:0]"
|
|
hexmask.long.byte 0x0 0.--3. 1. " PN ,Part Number [11:8]"
|
|
rgroup c14:0x3fa--0x3fa
|
|
line.long 0x0 "PID2,Peripherial ID2"
|
|
hexmask.long.byte 0x0 4.--7. 1. " REV ,Revision"
|
|
hexmask.long.byte 0x0 0.--2. 1. " JEP106 ,JEP106 Identity Code [6:4]"
|
|
rgroup c14:0x3fb--0x3fb
|
|
line.long 0x0 "PID3,Peripherial ID3"
|
|
hexmask.long.byte 0x0 4.--7. 1. " REVA ,RevAnd"
|
|
hexmask.long.byte 0x0 0.--3. 1. " CMOD ,Customer Modified"
|
|
rgroup c14:0x3f4--0x3f4
|
|
line.long 0x0 "PID4,Peripherial ID4"
|
|
bitfld.long 0x0 4.--7. " 4KBC ,Number of 4KB Blocks Occupied" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x0 0.--3. " JEP106 ,JEP106 Continuation Code" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
rgroup c14:0x3fc--0x3fc
|
|
line.long 0x0 "COMPONENTID0,Component ID0"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble"
|
|
rgroup c14:0x3fd--0x3fd
|
|
line.long 0x0 "COMPONENTID1,Component ID1"
|
|
hexmask.long.byte 0x0 4.--7. 1. " CCLASS ,Component Class (CoreSight Component)"
|
|
hexmask.long.byte 0x0 0.--3. 1. " PRBL ,Preamble"
|
|
rgroup c14:0x3fe--0x3fe
|
|
line.long 0x0 "COMPONENTID2,Component ID2"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble"
|
|
rgroup c14:0x3ff--0x3ff
|
|
line.long 0x0 "COMPONENTID3,Component ID3"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble"
|
|
tree.end
|
|
textline " "
|
|
width 0x7
|
|
rgroup c14:0x000--0x000
|
|
line.long 0x0 "DIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " VERSION ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,?..."
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSAMPLE ,PC Sample register implemented" "Low,High"
|
|
bitfld.long 0x0 12. " SECURITY ,Security Extensions implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " VARIANT ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " REVISION ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group c14:0x22--0x22
|
|
line.long 0x0 "DSCR,Debug Status and Control Register"
|
|
bitfld.long 0x0 30. " DTRRXFULL ,The DTRRX Full Flag" "Empty,Full"
|
|
bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DTRRXFULL_L ,The DTRRX Full Flag 1" "Empty,Full"
|
|
bitfld.long 0x00 26. " DTRTXFULL_L ,The DTRTX Full Flag 1" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SPA ,Sticky Pipeline Advance" "No effect,Instruction retired"
|
|
bitfld.long 0x0 24. " IC ,Instruction Complete" "Executing,Not executing"
|
|
textline " "
|
|
bitfld.long 0x0 20.--21. " DTR ,DTR Access Mode" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x0 19. " NSWS ,Imprecise Data Aborts discarded" "Not discarded,Discarded"
|
|
textline " "
|
|
bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured"
|
|
bitfld.long 0x0 17. " NSPNIDEN ,Secure Non-invasive Debug Disabled" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 16. " NSPIDEN ,Secure Invasive Debug Disabled" "Enabled,Disabled"
|
|
bitfld.long 0x0 15. " MONITOR ,Monitor Debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 14. " HDEN ,Halting Debug-mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 13. " EXECUTE ,Execute instruction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " COMMS ,User mode access to Comms Channel disable" "Enabled,Disabled"
|
|
bitfld.long 0x0 11. " INTDIS ,Disable Interrupts" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " DBGACK ,Force Debug Acknowledge" "Not forced,Forced"
|
|
bitfld.long 0x0 8. " UEXT ,Sticky Undefined Exception" "No exception,Exception"
|
|
textline " "
|
|
bitfld.long 0x0 7. " IABORT ,Sticky Imprecise Abort" "Not aborted,Aborted"
|
|
bitfld.long 0x0 6. " PABORT ,Sticky Precise Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Debug Entry,Breakpoint,Imprecise Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,?..."
|
|
bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited"
|
|
textline " "
|
|
bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state"
|
|
if (((data.long(c14:0x00))&0x01000)==0x00000)
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "VCR,Vector Catch Register"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
else
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "VCR,Vector Catch Register"
|
|
bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
endif
|
|
hgroup c14:0x020--0x020
|
|
hide.long 0x0 "DTRRX,Target -> Host Data Transfer Register"
|
|
in
|
|
group c14:0x023--0x023
|
|
line.long 0x0 "DTRTX,Host -> Target Data Transfer Register"
|
|
hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data"
|
|
group c14:0x09++0x00
|
|
line.long 0x00 "ECR,Event Catch Register"
|
|
bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled"
|
|
group c14:0x0a++0x00
|
|
line.long 0x00 "DSCCR,Debug State Cache Control Register"
|
|
bitfld.long 0x00 2. " NWT ,Not Write-Through" "Forced,Normal"
|
|
bitfld.long 0x00 0. " DUCL ,Data and Unified Cache Linefill" "Disabled,Normal"
|
|
wgroup c14:0x21++0x00
|
|
line.long 0x00 "ITR,Instruction Transfer Register"
|
|
hexmask.long 0x00 0.--31. 1. " Data ,ARM Instruction for the Processor in Debug State Execute"
|
|
wgroup c14:0x24++0x00
|
|
line.long 0x00 "DRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested"
|
|
wgroup c14:0xc0++0x00
|
|
line.long 0x00 "OSLAR,Operating System Lock Access Register"
|
|
hexmask.long 0x00 0.--31. 1. " OSLA ,OS Lock Access"
|
|
rgroup c14:0xc1++0x00
|
|
line.long 0x00 "OSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 2. " 32_BA ,32-Bit Access" "Not required,Required"
|
|
bitfld.long 0x00 1. " LB ,Locked Bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LIB ,Lock Implemented Bit" "Not implemented,Implemented"
|
|
group c14:0xc2++0x00
|
|
line.long 0x00 "OSSRR,Operating System Save and Restore Register"
|
|
hexmask.long 0x00 0.--31. 1. " OSSR ,OS Save and Restore"
|
|
group c14:0xc4++0x00
|
|
line.long 0x00 "PRCR,Device Power-Down and Reset Control Register"
|
|
bitfld.long 0x00 2. " HIR ,Hold Internal Reset" "Not held,Held"
|
|
bitfld.long 0x00 1. " FIR ,Force Internal Reset" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high"
|
|
hgroup c14:0xc5++0x00
|
|
hide.long 0x00 "PRSR,Device Power-Down and Reset Status Register"
|
|
in
|
|
tree.end
|
|
tree "Breakpoint Registers"
|
|
group c14:0x40++0x00
|
|
line.long 0x00 "BVR0,Breakpoint Value Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0"
|
|
group c14:0x50++0x00
|
|
line.long 0x00 "BCR0,Breakpoint Control Register 0"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x41++0x00
|
|
line.long 0x00 "BVR1,Breakpoint Value Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1"
|
|
group c14:0x51++0x00
|
|
line.long 0x00 "BCR1,Breakpoint Control Register 1"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x42++0x00
|
|
line.long 0x00 "BVR2,Breakpoint Value Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2"
|
|
group c14:0x52++0x00
|
|
line.long 0x00 "BCR2,Breakpoint Control Register 2"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x43++0x00
|
|
line.long 0x00 "BVR3,Breakpoint Value Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3"
|
|
group c14:0x53++0x00
|
|
line.long 0x00 "BCR3,Breakpoint Control Register 3"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x44++0x00
|
|
line.long 0x00 "BVR4,Breakpoint Value Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4"
|
|
group c14:0x54++0x00
|
|
line.long 0x00 "BCR4,Breakpoint Control Register 4"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x45++0x00
|
|
line.long 0x00 "BVR5,Breakpoint Value Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5"
|
|
group c14:0x55++0x00
|
|
line.long 0x00 "BCR5,Breakpoint Control Register 5"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x46++0x00
|
|
line.long 0x00 "BVR6,Breakpoint Value Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6"
|
|
group c14:0x56++0x00
|
|
line.long 0x00 "BCR6,Breakpoint Control Register 6"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x47++0x00
|
|
line.long 0x00 "BVR7,Breakpoint Value Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7"
|
|
group c14:0x57++0x00
|
|
line.long 0x00 "BCR7,Breakpoint Control Register 7"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Watchpoint Control Registers"
|
|
group c14:0x60++0x00
|
|
line.long 0x00 "WVR0,Watchpoint Value Register 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group c14:0x70--0x70
|
|
line.long 0x0 "WCR0,Watchpoint Control Register 0"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x61++0x00
|
|
line.long 0x00 "WVR1,Watchpoint Value Register 1"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1"
|
|
group c14:0x71--0x71
|
|
line.long 0x0 "WCR1,Watchpoint Control Register 1"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x62++0x00
|
|
line.long 0x00 "WVR2,Watchpoint Value Register 2"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA2 ,Watchpoint Address 2"
|
|
group c14:0x72--0x72
|
|
line.long 0x0 "WCR2,Watchpoint Control Register 2"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x63++0x00
|
|
line.long 0x00 "WVR3,Watchpoint Value Register 3"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA3 ,Watchpoint Address 3"
|
|
group c14:0x73--0x73
|
|
line.long 0x0 "WCR3,Watchpoint Control Register 3"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x64++0x00
|
|
line.long 0x00 "WVR4,Watchpoint Value Register 4"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA4 ,Watchpoint Address 4"
|
|
group c14:0x74--0x74
|
|
line.long 0x0 "WCR4,Watchpoint Control Register 4"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x65++0x00
|
|
line.long 0x00 "WVR5,Watchpoint Value Register 5"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA5 ,Watchpoint Address 5"
|
|
group c14:0x75--0x75
|
|
line.long 0x0 "WCR5,Watchpoint Control Register 5"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x66++0x00
|
|
line.long 0x00 "WVR6,Watchpoint Value Register 6"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA6 ,Watchpoint Address 6"
|
|
group c14:0x76--0x76
|
|
line.long 0x0 "WCR6,Watchpoint Control Register 6"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x67++0x00
|
|
line.long 0x00 "WVR7,Watchpoint Value Register 7"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA7 ,Watchpoint Address 7"
|
|
group c14:0x77--0x77
|
|
line.long 0x0 "WCR7,Watchpoint Control Register 7"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x006--0x006
|
|
line.long 0x0 "WFAR,Watchpoint Fault Address Register"
|
|
hexmask.long.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction"
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
sif cpuis("AWR1443*")
|
|
tree "AWR (Power, Reset, Clock Management and Control Registers)"
|
|
base ad:0xFFFFE100
|
|
width 22.
|
|
tree.open "MSS TOPRCM Registers"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "BSSCTL,Control Signals To BSS"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BSSCPUHALT ,Halt BSS CR4 to halt"
|
|
group.long 0x10++0x1B
|
|
line.long 0x00 "EXTCLKDIV,Clock Divide Value For MCU_CLKOUT And PMIC_CLKOUT"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK2DIV ,Divide value for PMIC_CLKOUT source clock"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EXTCLK1DIV ,Divide value for MCU_CLKOUT"
|
|
line.long 0x04 "EXTCLKSRCSEL,Clock Source Select Value For MCU_CLKOUT And PMIC_CLKOUT"
|
|
bitfld.long 0x04 8.--11. " EXTCLK2SRCSEL ,Select clock source for PMIC_CLKOUT" "CPUCLK,RCCLK,600-mHz PLL,,RCCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
bitfld.long 0x04 0.--3. " EXTCLK1SRCSEL ,Select clock source for MCU_CLKOUT" "CPUCLK,RCCLK,600-mHz PLL,,RCCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
line.long 0x08 "EXTCLKCTL,Clock Gate Control For MCU_CLKOUT And PMIC_CLKOUT"
|
|
hexmask.long.byte 0x08 8.--15. 1. " EXTCLK2GATE ,Pre clock divider gate for PMIC_CLKOUT"
|
|
hexmask.long.byte 0x08 0.--7. 1. " EXTCLK1GATE ,Pre clock divider gate for MCU_CLKOUT"
|
|
line.long 0x0C "SOFTSYSRST,Software Triggered Warm Reset"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " SOFTSYSRST ,Software trigger warm reset"
|
|
line.long 0x10 "WDRSTEN,Issue Warm Reset Upon MSS Watch Dog Reset"
|
|
hexmask.long.byte 0x10 0.--7. 1. " WDRSTEN ,Watchdog trigger warm reset"
|
|
line.long 0x14 "SYSRSTCAUSE,Reset Cause Register"
|
|
bitfld.long 0x14 0.--3. " SYSRSTCAUSE ,System reset cause" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x18 "SYSRSTCAUSECLR,Clear Reset Cause Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " SYSRSTCAUSECLR ,System reset clear cause"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "MISCCAPT,Capture Required Status Values Across The Chip"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DCDCCTL0,PMIC_CLKOUT Dethering Control"
|
|
line.long 0x04 "DCDCCTL1,PMIC_CLKOUT Dethering Control"
|
|
hexmask.long 0x04 2.--31. 1. " DCDCCTL1 ,PMIC_CLKOUT dethering control"
|
|
bitfld.long 0x04 1. " DCDCLKEN ,PMIC_CLKOUT dethering control block Enable Multi Bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " DCDCRST ,PMI clock out dethering control block reset Multi Bit" "No reset,Reset"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MISCCTL,Miscellaneous Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SWITCHCCCA ,Write 0xAD to switch the clock to RCCLK (limp mode) whenever the CCCA gives an error"
|
|
hexmask.long.byte 0x00 16.--23. 1. " HINTTRIG ,Write 0xAD to trigger host Interrupt"
|
|
bitfld.long 0x00 14. " RS232SWOVRVAL ,RS232_clk_mode SW override value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GATECLKDBGSS ,Gate the clock to dbgss" "0,1,2,3,4,5,6,Gated"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SWITCHDCCA ,Write 0xAD to switch the clock to RCCLK (limp mode) whenever the DCCA gives an error"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "USERMODEEN,User Mode Access Enable"
|
|
line.long 0x04 "LVDSPADCTL0,LVDS Pad Control 0"
|
|
line.long 0x08 "LVDSPADCTL1,LVDS Pad Control 1"
|
|
group.long 0x60++0x17
|
|
line.long 0x00 "DFTREG0,DFTREG0"
|
|
line.long 0x04 "DFTREG1,DFTREG1"
|
|
line.long 0x08 "DFTREG2,DFTREG2"
|
|
line.long 0x0C "DFTREG3,DFTREG3"
|
|
line.long 0x10 "DFTREG4,DFTREG4"
|
|
line.long 0x14 "DFTREG5,DFTREG5"
|
|
group.long 0x78++0x07
|
|
line.long 0x00 "SHMEMINITADDR,Start And End Address for Shared Memory Initialization"
|
|
hexmask.long.word 0x00 16.--31. 1. " INITENDADDR ,End address for memory initialization of shared memory"
|
|
hexmask.long.word 0x00 0.--15. 1. " INITSTARTADDR ,Start address for memory initialization of shared memory"
|
|
line.long 0x04 "SHMEMINITECC,ECC Value To Be Written Into Shared Memory During Initialization"
|
|
hexmask.long.byte 0x04 0.--7. 1. " INITECCVAL ,ECC value to be written in above start-end address range for shared memory"
|
|
group.long 0xA0++0x0B
|
|
line.long 0x00 "DSSMEMBANKEN,Shared Memory Bank Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. " DSSBANKEN ,Defines which all banks are enabled for DSS"
|
|
line.long 0x04 "DSSMEMTAB0,Shared Memory Table 0"
|
|
line.long 0x08 "DSSMEMTAB1,Shared Memory Table 1"
|
|
group.long 0xB0++0x0B
|
|
line.long 0x00 "TCMAMEMBANK_EN,Shared Memory Bank Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. " TCMABANKEN ,TCMABANKEN"
|
|
line.long 0x04 "TCMAMEMTAB0,Shared Memory Table 0"
|
|
line.long 0x08 "TCMAMEMTAB1,Shared Memory Table 1"
|
|
group.long 0xC0++0x0B
|
|
line.long 0x00 "TCMBMEMBANKEN,Shared Memory Bank Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. " TCMBMEMBANKEN ,TCMBMEMBANKEN"
|
|
line.long 0x04 "TCMBMEMTAB0,Shared Memory Table"
|
|
line.long 0x08 "TCMBMEM_TAB1,Shared Memory Table"
|
|
group.long 0xD8++0x07
|
|
line.long 0x00 "MEMINITSTART,Memory Initialization Trigger Bit For Memories In BSS And DSS"
|
|
bitfld.long 0x00 16. " SHMEMSTART ,Memory initialization for shared memory" "Not initialized,Initialized"
|
|
line.long 0x04 "MEMINITDONE,Memory Initialization Done Status"
|
|
bitfld.long 0x04 16. " SHMEM ,Memory initialization done status for shared memory" "Not done,Done"
|
|
bitfld.long 0x04 9. " BSSVIMMEM ,Memory Initialization done status for BSS VIM memory" "Not done,Done"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "MSS_SIGNATURE,Spare Register"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "MISCCTL1,Miscellaneous Control Register"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "USERMODEEN2,User Mode Access Enable 2"
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "SYSTICK,SYSTICK"
|
|
tree.end
|
|
base ad:0xFFFFFF00
|
|
tree.open "MSS RCM Registers"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SOFTRST2,System Software Reset 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIMRST ,VIM only reset"
|
|
group.long 0x18++0x0B
|
|
line.long 0x00 "CLKDIVCTL0,Clock Divider"
|
|
hexmask.long.byte 0x00 24.--31. 1. " FDCANCLKDIV ,Divide value for FDCAN source clock"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DCANCLKDIV ,Divide value for DCAN source clock"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VCLKCLKDIV ,Divide value for MSS subsystem source clock"
|
|
line.long 0x04 "CLKSRCSEL0,CLKSRCSEL"
|
|
bitfld.long 0x04 16.--19. " QSPICLKSRCSEL ,Select clock source for QSPI baud clock" "MSS_VCLK,RCCLK,600-mHz PLL,,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
bitfld.long 0x04 8.--11. " FRAYCLKSRCSEL ,Select clock source for FRAY" "MSS_VCLK,RCCLK,600-mHz PLL,,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
bitfld.long 0x04 0.--3. " DCANCLKSRCSEL ,Select clock source for DCAN" "MSS_VCLK,RCCLK,600-mHz PLL,,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
line.long 0x08 "CR4CTL,CR4CTL"
|
|
hexmask.long.byte 0x08 16.--23. 1. " MEMSWAPWAIT ,MEMSWAPWAIT"
|
|
hexmask.long.byte 0x08 8.--15. 1. " CR4MEMSWAP ,CR4MEMSWAP"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CLKGATE,Clock Gate"
|
|
bitfld.long 0x00 5. " FDCANCLKGATE ,Pre clock divider gate for FDCAN clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DCANCLKGATE ,Pre clock divider gate for DCAN clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " QSPICLKGATE ,Pre clock divider gate for QSPI clock" "Disabled,Enabled"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CLKSRCSEL1,Clock Source Select"
|
|
bitfld.long 0x00 0.--3. " VCLKCLKSRCSEL ,Select clock source for MSS subsystem VCLK" "CPUCLK,RCCLK,600-mHz,,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "CURRCLKDIV0,Current Clock Divider 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " FRAYCURRCLKDIV ,Current divide value of FRAY baud clock divider"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DCANCURRCLKDIV ,Current divide value of DCAN baud clock divider"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VCLKCURRCLKDIV ,Current divide value of VCLK divider"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "MEMINITSTART,Memory Initialization Trigger"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MEMINITKEY ,Memory hardware initialization global enable key"
|
|
bitfld.long 0x00 8. " BSSMBOX4MSSMEM ,BSS mail box FO MSS memory initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 7. " MSSMBOX4BSSMEM ,MSS mail box FO BSS memory initialization" "Not initialized,Initialized"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DCANMEM ,DCAN memory initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 4. " SPIAMEM ,SPIA memory initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 3. " VIMMEM ,VIM memory initialization" "Not initialized,Initialized"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DMAMEM ,DMA memory initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 1. " CR4TCMBMEM ,MSS TCMA memory initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 0. " CR4TCMAMEM ,MSS TCMA memory initialization" "Not initialized,Initialized"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "CURRCLKDIV1,Current Clock Divider 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " QSPICURRCLKDIV ,Current divide value of QSPI_CLK divider"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "MEMINITDONE,Memory Initialization Done"
|
|
bitfld.long 0x00 8. " BSSMBOX4MSSMEM ,Memory initialization done status for BSS mailbox MSS memory" "Not done,Done"
|
|
bitfld.long 0x00 7. " MSSMBOX4BSSMEM ,Memory initialization done status for MSS mailbox for BSS memory" "Not done,Done"
|
|
bitfld.long 0x00 6. " DCANMEM ,Memory initialization done status for DCAN memory" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SPIAMEM ,Memory initialization done status for MSS SPIA memory" "Not done,Done"
|
|
bitfld.long 0x00 3. " VIMMEM ,Memory initialization done status for MSS VIM memory" "Not done,Done"
|
|
bitfld.long 0x00 2. " DMAMEM ,Memory initialization done status for MSS DMA memory" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CR4TCMBMEM ,Memory initialization done status for MSS TCMB memory" "Not done,Done"
|
|
bitfld.long 0x00 0. " CR4TCMAMEM ,Memory initialization done status for MSS TCMA memory" "Not done,Done"
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "USERMODEEN,User Mode Access Enable"
|
|
line.long 0x04 "NSYSPERUSERMODEN,NSYSPERUSERMODEN"
|
|
group.long 0x90++0x13
|
|
line.long 0x00 "ESMGATE0,ESMGATE0"
|
|
line.long 0x04 "ESMGATE1,ESMGATE1"
|
|
line.long 0x08 "ESMGATE2,ESMGATE2"
|
|
line.long 0x0C "ESMGATE3,ESMGATE3"
|
|
line.long 0x10 "ESMGATE4,ESMGATE4"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "KEY,CFGREG Access Key"
|
|
group.long 0xB8++0x1B
|
|
line.long 0x00 "SWIRQA,SWIRQ0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SWIRQ1 ,System software interrupt trigger 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SWIRQ1DAT ,System software interrupt data"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SWIRQ0 ,System software interrupt trigger 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SWIRQ0DAT ,System software interrupt data"
|
|
line.long 0x04 "SWIRQB,SWIRQ1"
|
|
hexmask.long.byte 0x04 24.--31. 1. " SWIRQ3 ,System software interrupt trigger 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SWIRQ3DAT ,System software interrupt data"
|
|
hexmask.long.byte 0x04 8.--15. 1. " SWIRQ2 ,System software interrupt trigger 2"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " SWIRQ2DAT ,System software interrupt data"
|
|
line.long 0x08 "MISCCTL0,Miscellaneous Control Register"
|
|
bitfld.long 0x08 22.--24. " TCMB1EZDIS ,TCMB1EZDIS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 19.--21. " TCMB0EZDIS ,TCMB0EZDIS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 16.--18. " TCMAEZDIS ,TCMAEZDIS" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "ATCMERRCAPTCTL,ATCMERRCAPTCTL"
|
|
hexmask.long.tbyte 0x0C 8.--27. 1. " ERRATCADDR ,TCM address for which parity error happened"
|
|
bitfld.long 0x0C 3.--5. " ATCFORCEERR ,ATCFORCEERR" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 0.--2. " ERRATCADDRCLR ,ERRATCADDRCLR" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "B0TCMERRCAPTCTL,B0TCMERRCAPTCTL"
|
|
hexmask.long.tbyte 0x10 8.--27. 1. " ERRB0TCADDR ,TCM address for which parity error happened"
|
|
bitfld.long 0x10 3.--5. " B0TCFORCEERR ,B0TCFORCEERR" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0.--2. " ERRB0TCADDRCLR ,ERRB0TCADDRCLR" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "B1TCMERRCAPTCTL,B1TCMERRCAPTCTL"
|
|
hexmask.long.tbyte 0x14 8.--27. 1. " ERRB1TCADDR ,TCM address for which parity error happened"
|
|
bitfld.long 0x14 3.--5. " B1TCFORCEERR ,B1TCFORCEERR" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 0.--2. " ERRB1TCADDRCLR ,ERRB1TCADDRCLR" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SOFTCORERST,Software CORE Reset Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " RST_WFICHECKEN ,RST WFICHECKEN"
|
|
hexmask.long.byte 0x18 8.--15. 1. " RSTTOASSRTDLY ,Programmed number of clock cycle before reset is asserted"
|
|
rgroup.long 0xD8++0x07
|
|
line.long 0x00 "RSTCAUSE,MSS RST Cause"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MSS_RCM ,RST cause"
|
|
line.long 0x04 "RSTCAUSECLR,MSS RST Cause Clear"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RSTCAUSECLR ,RST cause clear"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "SPITRIGSRC,SPI Trigger Source"
|
|
bitfld.long 0x00 24. " SPIBTRIG1 ,1st bit of trigger source input of SPIB" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SPIBTRIG0 ,0th bit of trigger source input of SPIB" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SPIATRIG1 ,1st bit of trigger source input of SPIA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SPIATRIG0 ,0th bit of trigger source input of SPIA" "Disabled,Enabled"
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "CLKINUSE,MSS Clock In Use"
|
|
bitfld.long 0x00 12.--15. " QSPICLKINUSE ,Current clock source select MUX value for QSPI clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DCANCLKINUSE ,Current clock source select MUX value for DCAN clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " FRAYCLKINUSE ,Current clock source select MUX value for fray clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " VCLKINUSE ,Current clock source select MUX value for VCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "ECCEN,MSS ECC Enable"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "ECCCAPT,MSS ECC Capture"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CLKDIVCTL2,CLKDIVCTL2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " QSPICLKDIV ,Divide value for QSPI baud clock selected by field QSPICLKSRCSEL"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "SWIRQC,SW IRQ2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SWIRQ5 ,Trigger interrupt 5"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SWIRQ5DAT ,System software interrupt data 5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SWIRQ4 ,Trigger interrupt 4"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SWIRQ4DAT ,System software interrupt data 4"
|
|
tree.end
|
|
base ad:0xFFFFF800
|
|
tree.open "MSS GPCFG REG Registers"
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "GPCFG0,GPCFG0"
|
|
line.long 0x04 "GPCFG1,GPCFG1"
|
|
line.long 0x08 "GPCFG2,GPCFG2"
|
|
line.long 0x0C "GPCFG3,GPCFG3"
|
|
line.long 0x10 "GPCFG4,GPCFG4"
|
|
group.long 0xD0++0x1F
|
|
line.long 0x00 "CCCACFG0,CCCA CFG0"
|
|
hexmask.long.word 0x00 16.--31. 1. " MARGIN_COUNT ,Margin value for clock comparison"
|
|
bitfld.long 0x00 8. " SINGLE_SHOT_MODE ,Single shot mode" "Single shot,Continuous"
|
|
bitfld.long 0x00 7. " ENABLE_MODULE ,Enable for CCC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DISABLE_CLOCKS ,Disable clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--5. " CLOCK1_SEL ,Selection for clock 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CLOCK0_SEL ,Selection for clock 0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "CCCACFG1,CCCA CFG1"
|
|
line.long 0x08 "CCCACFG2,CCCA CFG2"
|
|
line.long 0x0C "CCCACFG3,CCCA CFG3"
|
|
line.long 0x10 "CCCBCFG0,CCCB CFG0"
|
|
hexmask.long.word 0x10 16.--31. 1. " MARGIN_COUNT ,Margin value for clock comparison"
|
|
bitfld.long 0x10 8. " SINGLE_SHOT_MODE ,Single shot mode" "Single shot,Continuous"
|
|
bitfld.long 0x10 7. " ENABLE_MODULE ,Enable for CCC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 6. " DISABLE_CLOCKS ,Disable clocks" "Disabled,Enabled"
|
|
bitfld.long 0x10 3.--5. " CLOCK1_SEL ,Selection for clock 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0.--2. " CLOCK0_SEL ,Selection for clock 0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "CCCBCFG1,CCCB CFG1"
|
|
line.long 0x18 "CCCBCFG2,CCCB CFG2"
|
|
line.long 0x1C "CCCBCFG3,CCCB CFG3"
|
|
rgroup.long 0xF0++0x0B
|
|
line.long 0x00 "CCCACNTVAL,CCCACNTVAL"
|
|
line.long 0x04 "CCCBCNTVAL,CCCBCNTVAL"
|
|
line.long 0x08 "CCCABERRSTAT,CCCABERRSTAT"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "USERMODEEN,User Mode Access Enable"
|
|
tree.end
|
|
base ad:0x50000400
|
|
tree.open "DSS REG Registers"
|
|
group.long 0x5C++0x13
|
|
line.long 0x00 "ADCBUFCFG1,ADCBUFCFG1"
|
|
bitfld.long 0x00 17.--21. " ADCBUFNUMCHRP ,Number of chirps to be stored in each ping and pong buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 15. " ADCBUFCONTSTOPPL ,Stop Pulse for continuous mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ADCBUFCONTSTRTPL ,Start Pulse for continuous mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ADCBUFCONTMODEEN ,Continuous mode enable for ADC buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ADCBUFWRITEMODE ,ADCBUFWRITEMODE" "Interleaved,Non interleaved"
|
|
bitfld.long 0x00 9. " RX3EN ,Enable for Rx3 write" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RX2EN ,Enable for Rx2 write" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RX1EN ,Enable for Rx1 write" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RX0EN ,Enable for Rx0 write" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ADCBUFIQSWAP ,ADCBUFIQSWAP" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ADCBUFREALONLYMODE ,ADCBUFREALONLYMODE" "Complex data mode,Real data mode"
|
|
line.long 0x04 "ADCBUFCFG2,ADCBUFCFG2"
|
|
hexmask.long.word 0x04 16.--26. 1. " ADCBUFADDRX1 ,Internal address pointer for Rx1 writes in non-interleaved mode"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--10. 1. " ADCBUFADDRX0 ,Internal address pointer for Rx0 writes in non-interleaved mode"
|
|
line.long 0x08 "ADCBUFCFG3,ADCBUFCFG3"
|
|
hexmask.long.word 0x08 16.--25. 1. " ADCBUFADDRX3 ,Internal address pointer for Rx3 writes in Non-interleaved mode"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--9. 1. " ADCBUFADDRX2 ,Internal address pointer for Rx2 writes in non-interleaved mode"
|
|
line.long 0x0C "ADCBUFCFG4,ADCBUFCFG4"
|
|
hexmask.long.word 0x0C 0.--13. 1. " ADCBUFSAMPCNT ,Number of samples to store in each Ping and Pong register in continuous mode of ADC Buffer"
|
|
line.long 0x10 "CSICFG1,CSICFG1"
|
|
hexmask.long.byte 0x10 24.--30. 1. " CQ2BASEADDR ,Address to be added to be internal address pointer for CQ2"
|
|
textline " "
|
|
hexmask.long.byte 0x10 16.--22. 1. " CQ1BASEADDR ,Address to be added to be internal address pointer for CQ1"
|
|
hexmask.long.byte 0x10 4.--10. 1. " CQ0BASEADDR ,Address to be added to be internal address pointer for CQ0"
|
|
textline " "
|
|
bitfld.long 0x10 3. " CQ96BITPACKEN ,This is used to pack the CQ data into only the LSB 96 bits of each row of the CQ memory" "0,1"
|
|
bitfld.long 0x10 0.--1. " CQDATAWIDTH ,This is used to appropriately pack the valid CQ data bits in appropriate bits in the CQ memory" "0,Raw 16,Raw 12,Raw 14"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TPCCPARSTATCFG,TPCCPARSTATCFG"
|
|
bitfld.long 0x00 10. " TPCCPARITYTSTEN ,Enable bit for the self test of the parity logic in TPCC" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TPCCPARITYEN ,Enable bit for the parity computation in TPCC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TPCCPARITYCLR ,Clear bit for the parity error from TPCC" "No error,Error"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TPCCPARITYSTAT ,Parity address from TPCC"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CSI2TXPARSTATCFG,CSI2TXPARSTATCFG"
|
|
bitfld.long 0x00 10. " CSI2TXPARITYTSTEN ,Enable bit for the self test of the parity logic in CSI2" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CSI2TXPARITYEN ,Enable bit for the parity computation in CSI2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CSI2TXPARITYCLR ,Clear bit for the parity error from CSI2" "No error,Error"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CSI2TXPARITYSTAT ,Parity address from CSI2"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CSICFG1,CSICFG1"
|
|
bitfld.long 0x00 23. " CSIPIPD4 ,Connected to CSI2 protocol port name CSI_PIPD4" "Not connected,Connected"
|
|
bitfld.long 0x00 22. " CSIPIPD3 ,Connected to CSI2 protocol port name CSI_PIPD3" "Not connected,Connected"
|
|
bitfld.long 0x00 21. " CSIPIPD2 ,Connected to CSI2 protocol port name CSI_PIPD2" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CSIPIPD1 ,Connected to CSI2 protocol port name CSI_PIPD1" "Not connected,Connected"
|
|
bitfld.long 0x00 19. " CSIPIPD0 ,Connected to CSI2 protocol port name CSI_PIPD0" "Not connected,Connected"
|
|
rbitfld.long 0x00 17. " CSISIDLEACK ,Connected to CSI2 protocol port name CSI_PO_SIDLEACK" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 12.--16. " CSILANEENABLE ,Connected to CSI2 protocol port name CSI_LANEENABLE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 9. " CSIMIDLEREQ ,Connected to CSI2 Protocol port name CSI_PI_MIDLEREQ" "Not connected,Connected"
|
|
group.long 0x104++0x3F
|
|
line.long 0x00 "TPTC0WRMPUSTADD0,TPTC0WRMPUSTADD0"
|
|
line.long 0x04 "TPTC0WRMPUSTADD1,TPTC0WRMPUSTADD1"
|
|
line.long 0x08 "TPTC0WRMPUSTADD2,TPTC0WRMPUSTADD2"
|
|
line.long 0x0C "TPTC0WRMPUSTADD3,TPTC0WRMPUSTADD3"
|
|
line.long 0x10 "TPTC0WRMPUSTADD4,TPTC0WRMPUSTADD4"
|
|
line.long 0x14 "TPTC0WRMPUSTADD5,TPTC0WRMPUSTADD5"
|
|
line.long 0x18 "TPTC0WRMPUSTADD6,TPTC0WRMPUSTADD6"
|
|
line.long 0x1C "TPTC0WRMPUSTADD7,TPTC0WRMPUSTADD7"
|
|
line.long 0x20 "TPTC0WRMPUENDADD0,TPTC0WRMPUENDADD0"
|
|
line.long 0x24 "TPTC0WRMPUENDADD1,TPTC0WRMPUENDADD1"
|
|
line.long 0x28 "TPTC0WRMPUENDADD2,TPTC0WRMPUENDADD2"
|
|
line.long 0x2C "TPTC0WRMPUENDADD3,TPTC0WRMPUENDADD3"
|
|
line.long 0x30 "TPTC0WRMPUENDADD4,TPTC0WRMPUENDADD4"
|
|
line.long 0x34 "TPTC0WRMPUENDADD5,TPTC0WRMPUENDADD5"
|
|
line.long 0x38 "TPTC0WRMPUENDADD6,TPTC0WRMPUENDADD6"
|
|
line.long 0x3C "TPTC0WRMPUENDADD7,TPTC0WRMPUENDADD7"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "TPTC0WRMPUERRADD,TPTC0WRMPUERRADD"
|
|
group.long 0x148++0x3F
|
|
line.long 0x00 "TPTC0RDMPUSTADD0,TPTC0RDMPUSTADD0"
|
|
line.long 0x04 "TPTC0RDMPUSTADD1,TPTC0RDMPUSTADD1"
|
|
line.long 0x08 "TPTC0RDMPUSTADD2,TPTC0RDMPUSTADD2"
|
|
line.long 0x0C "TPTC0RDMPUSTADD3,TPTC0RDMPUSTADD3"
|
|
line.long 0x10 "TPTC0RDMPUSTADD4,TPTC0RDMPUSTADD4"
|
|
line.long 0x14 "TPTC0RDMPUSTADD5,TPTC0RDMPUSTADD5"
|
|
line.long 0x18 "TPTC0RDMPUSTADD6,TPTC0RDMPUSTADD6"
|
|
line.long 0x1C "TPTC0RDMPUSTADD7,TPTC0RDMPUSTADD7"
|
|
line.long 0x20 "TPTC0RDMPUSTADD0,TPTC0RDMPUSTADD0"
|
|
line.long 0x24 "TPTC0RDMPUSTADD1,TPTC0RDMPUSTADD1"
|
|
line.long 0x28 "TPTC0RDMPUSTADD2,TPTC0RDMPUSTADD2"
|
|
line.long 0x2C "TPTC0RDMPUSTADD3,TPTC0RDMPUSTADD3"
|
|
line.long 0x30 "TPTC0RDMPUSTADD4,TPTC0RDMPUSTADD4"
|
|
line.long 0x34 "TPTC0RDMPUSTADD5,TPTC0RDMPUSTADD5"
|
|
line.long 0x38 "TPTC0RDMPUSTADD6,TPTC0RDMPUSTADD6"
|
|
line.long 0x3C "TPTC0RDMPUSTADD7,TPTC0RDMPUSTADD7"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "TPTC0RDMPUERRADD,TPTC0RDMPUERRADD"
|
|
group.long 0x18C++0x3F
|
|
line.long 0x00 "TPTC1WRMPUSTADD0,TPTC1WRMPUSTADD0"
|
|
line.long 0x04 "TPTC1WRMPUSTADD1,TPTC1WRMPUSTADD1"
|
|
line.long 0x08 "TPTC1WRMPUSTADD2,TPTC1WRMPUSTADD2"
|
|
line.long 0x0C "TPTC1WRMPUSTADD3,TPTC1WRMPUSTADD3"
|
|
line.long 0x10 "TPTC1WRMPUSTADD4,TPTC1WRMPUSTADD4"
|
|
line.long 0x14 "TPTC1WRMPUSTADD5,TPTC1WRMPUSTADD5"
|
|
line.long 0x18 "TPTC1WRMPUSTADD6,TPTC1WRMPUSTADD6"
|
|
line.long 0x1C "TPTC1WRMPUSTADD7,TPTC1WRMPUSTADD7"
|
|
line.long 0x20 "TPTC1WRMPUENDADD0,TPTC1WRMPUENDADD0"
|
|
line.long 0x24 "TPTC1WRMPUENDADD1,TPTC1WRMPUENDADD1"
|
|
line.long 0x28 "TPTC1WRMPUENDADD2,TPTC1WRMPUENDADD2"
|
|
line.long 0x2C "TPTC1WRMPUENDADD3,TPTC1WRMPUENDADD3"
|
|
line.long 0x30 "TPTC1WRMPUENDADD4,TPTC1WRMPUENDADD4"
|
|
line.long 0x34 "TPTC1WRMPUENDADD5,TPTC1WRMPUENDADD5"
|
|
line.long 0x38 "TPTC1WRMPUENDADD6,TPTC1WRMPUENDADD6"
|
|
line.long 0x3C "TPTC1WRMPUENDADD7,TPTC1WRMPUENDADD7"
|
|
rgroup.long 0x1CC++0x03
|
|
line.long 0x00 "TPTC1WRMPUERRADD,TPTC1WRMPUERRADD"
|
|
group.long 0x1D0++0x3F
|
|
line.long 0x00 "TPTC1RDMPUSTADD0,TPTC1RDMPUSTADD0"
|
|
line.long 0x04 "TPTC1RDMPUSTADD1,TPTC1RDMPUSTADD1"
|
|
line.long 0x08 "TPTC1RDMPUSTADD2,TPTC1RDMPUSTADD2"
|
|
line.long 0x0C "TPTC1RDMPUSTADD3,TPTC1RDMPUSTADD3"
|
|
line.long 0x10 "TPTC1RDMPUSTADD4,TPTC1RDMPUSTADD4"
|
|
line.long 0x14 "TPTC1RDMPUSTADD5,TPTC1RDMPUSTADD5"
|
|
line.long 0x18 "TPTC1RDMPUSTADD6,TPTC1RDMPUSTADD6"
|
|
line.long 0x1C "TPTC1RDMPUSTADD7,TPTC1RDMPUSTADD7"
|
|
line.long 0x20 "TPTC1RDMPUENDADD0,TPTC1RDMPUENDADD0"
|
|
line.long 0x24 "TPTC1RDMPUENDADD1,TPTC1RDMPUENDADD1"
|
|
line.long 0x28 "TPTC1RDMPUENDADD2,TPTC1RDMPUENDADD2"
|
|
line.long 0x2C "TPTC1RDMPUENDADD3,TPTC1RDMPUENDADD3"
|
|
line.long 0x30 "TPTC1RDMPUENDADD4,TPTC1RDMPUENDADD4"
|
|
line.long 0x34 "TPTC1RDMPUENDADD5,TPTC1RDMPUENDADD5"
|
|
line.long 0x38 "TPTC1RDMPUENDADD6,TPTC1RDMPUENDADD6"
|
|
line.long 0x3C "TPTC1RDMPUENDADD7,TPTC1RDMPUENDADD7"
|
|
rgroup.long 0x210++0x03
|
|
line.long 0x00 "TPTC1RDMPUERRADD,TPTC1RDMPUERRADD"
|
|
group.long 0x214++0x07
|
|
line.long 0x00 "TPTCMPUVALIDCFG,TPTCMPUVALIDCFG"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TPTC1RDMPURNGVLD ,Valid bit for each address range for the MPU in the read port of TPTC1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TPTC1WRMPURNGVLD ,Valid bit for each address range for the MPU in the read port of TPTC1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TPTC0RDMPURNGVLD ,Valid bit for each address range for the MPU in the read port of TPTC1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " TPTC0WRMPURNGVLD ,Valid bit for each address range for the MPU in the read port of TPTC1"
|
|
line.long 0x04 "TPTCMPUENCFG,TPTCMPUENCFG"
|
|
bitfld.long 0x04 7. " TPTC1RDMPUERRCLR ,Clear flag for error from the MPU in the read port of TPTC1" "No error,Error"
|
|
bitfld.long 0x04 6. " TPTC1WRMPUERRCLR ,Clear flag for error from the MPU in the write port of TPTC1" "No error,Error"
|
|
bitfld.long 0x04 5. " TPTC0RDMPUERRCLR ,Clear flag for error from the MPU in the read port of TPTC0" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 4. " TPTC0WRMPUERRCLR ,Clear flag for error from the MPU in the write port of TPTC0" "No error,Error"
|
|
bitfld.long 0x04 3. " TPTC1RDMPUEN ,Enable bit for the MPU in the read port of TPTC1" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " TPTC1WRMPUEN ,Enable bit for the MPU in the write port of TPTC1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TPTC0RDMPUEN ,Enable bit for the MPU in the read port of TPTC0" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TPTC0WRMPUEN ,Enable bit for the MPU in the write port of TPTC0" "Disabled,Enabled"
|
|
group.long 0x21C++0x0F
|
|
line.long 0x00 "TESTPATTERNRX1ICFG,TESTPATTERNRX1ICFG"
|
|
hexmask.long.word 0x00 16.--31. 1. " TSTPATRX1IINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSTPATRX1IOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 0"
|
|
line.long 0x04 "TESTPATTERNRX2ICFG,TESTPATTERNRX2ICFG"
|
|
hexmask.long.word 0x04 16.--31. 1. " TSTPATRX2IINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " TSTPATRX2IOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 1"
|
|
line.long 0x08 "TESTPATTERNRX3ICFG,TESTPATTERNRX3ICFG"
|
|
hexmask.long.word 0x08 16.--31. 1. " TSTPATRX3IINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " TSTPATRX3IOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 2"
|
|
line.long 0x0C "TESTPATTERNRX4ICFG,TESTPATTERNRX4ICFG"
|
|
hexmask.long.word 0x0C 16.--31. 1. " TSTPATRX4IINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TSTPATRX4IOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 3"
|
|
group.long 0x22C++0x0F
|
|
line.long 0x00 "TESTPATTERNRX1QCFG,TESTPATTERNRX1QCFG"
|
|
hexmask.long.word 0x00 16.--31. 1. " TSTPATRX1QINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSTPATRX1QOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 0"
|
|
line.long 0x04 "TESTPATTERNRX2QCFG,TESTPATTERNRX2QCFG"
|
|
hexmask.long.word 0x04 16.--31. 1. " TSTPATRX2QINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " TSTPATRX2QOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 1"
|
|
line.long 0x08 "TESTPATTERNRX3QCFG,TESTPATTERNRX3QCFG"
|
|
hexmask.long.word 0x08 16.--31. 1. " TSTPATRX3QINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " TSTPATRX3QOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 2"
|
|
line.long 0x0C "TESTPATTERNRX4QCFG,TESTPATTERNRX4QCFG"
|
|
hexmask.long.word 0x0C 16.--31. 1. " TSTPATRX4QINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " TSTPATRX4QOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 3"
|
|
group.long 0x23C++0x23
|
|
line.long 0x00 "TESTPATTERNVLDCFG,TESTPATTERNVLDCFG"
|
|
bitfld.long 0x00 8.--10. " TSTPATGENEN ,Enable for test pattern generator" "Disabled,,,,,,,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TSTPATVLDCNT ,Number of DSS Interconnect clocks 200 MHz between successive samples for the test pattern gen"
|
|
group.long 0x240++0x07
|
|
line.long 0x00 "DSSMISC,DSSMISC"
|
|
bitfld.long 0x00 6.--8. " FFTACCSLVEN ,Enable for FFT Accelerator slaves" "Disabled,,,,,,,Enabled"
|
|
line.long 0x04 "DSSMISC2,DSSMISC2"
|
|
hexmask.long.byte 0x04 24.--29. 0x01 " MSSCFGRNG3 ,Used in place of MSB 6 bits of the address sent from DSS to MSS"
|
|
hexmask.long.byte 0x04 16.--21. 0x01 " MSSCFGRNG2 ,Used in place of MSB 6 bits of the address sent from DSS to MSS"
|
|
textline " "
|
|
hexmask.long.byte 0x04 8.--13. 0x01 " MSSCFGRNG1 ,Used in place of MSB 6 bits of the address sent from DSS to MSS"
|
|
hexmask.long.byte 0x04 0.--5. 0x01 " MSSCFGRNG0 ,Used in place of MSB 6 bits of the address sent from DSS to MSS"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
elif cpuis("AWR6843*")
|
|
tree.open "AWR (Power, Reset, Clock Management and Control Registers)"
|
|
tree "MSS TOPRCM Registers"
|
|
base ad:0xFFFFE100
|
|
width 19.
|
|
group.long 0x08++0x1B
|
|
line.long 0x00 "BSSCTL,Control Signals To BSS Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BSSCPUHALT ,Halt BSS CR4 to halt"
|
|
line.long 0x04 "DSSCTL,Control Signals To DSS Register"
|
|
bitfld.long 0x04 26. " GEMLRSTN ,DSP local reset value that will be propagated to the DSP when the DSP power FSM has switched the DSP on" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " GEMGRSTN ,DSP global reset value that will be propagated to the DSP when the DSP power FSM has switched the DSP on" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " GEMPORZ ,DSP reset value that will be propagated to the DSP when the DSP power FSM has switched the DSP on" "Disabled,Enabled"
|
|
line.long 0x08 "EXTCLKDIV,Clock Divide Value For MCU_CLKOUT And PMIC_CLKOUT Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " EXTCLK2DIV ,Divide value for PMIC_CLKOUT source clock"
|
|
hexmask.long.byte 0x08 0.--7. 1. " EXTCLK1DIV ,Divide value for MCU_CLKOUT"
|
|
line.long 0x0C "EXTCLKSRCSEL,Clock Source Select Value For MCU_CLKOUT And PMIC_CLKOUT Register"
|
|
bitfld.long 0x0C 8.--11. " EXTCLK[2]SRCSEL ,Select clock source for PMIC_CLKOUT" "CPUCLK,RCCLK,600 MHz PLL,240 MHz PLL,RCCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
bitfld.long 0x0C 0.--3. " [1] ,Select clock source for MCU_CLKOUT" "CPUCLK,RCCLK,600 MHz PLL,240 MHz PLL,RCCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
line.long 0x10 "EXTCLKCTL,Clock Gate Control For MCU_CLKOUT And PMIC_CLKOUT Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " EXTCLK[2]GATE ,Pre clock divider gate for PMIC_CLKOUT"
|
|
hexmask.long.byte 0x10 0.--7. 1. " [1] ,Pre clock divider gate for MCU_CLKOUT"
|
|
line.long 0x14 "SOFTSYSRST,Software Triggered Warm Reset Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " SOFTSYSRST ,Software trigger warm reset"
|
|
line.long 0x18 "WDRSTEN,Issue Warm Reset Upon MSS Watch Dog Reset Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " WDRSTEN ,Watchdog trigger warm reset"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SYSRSTCAUSE,Reset Cause Register"
|
|
bitfld.long 0x00 0.--3. " SYSRSTCAUSE ,System reset cause" ",,,,,,,,EXTSYSRST,NRESET,,,SOFTSYSRST,?..."
|
|
newline
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "SYSRSTCAUSECLR,Clear Reset Cause Register"
|
|
in
|
|
newline
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "MISCCAPT,Capture Required Status Values Across The Chip Register"
|
|
bitfld.long 0x00 31. " MISCCAPT[31] ,Capture required status 31" "No error,Error"
|
|
bitfld.long 0x00 30. " [30] ,Capture required status 30" "No error,Error"
|
|
bitfld.long 0x00 29. " [29] ,Capture required status 29" "No error,Error"
|
|
bitfld.long 0x00 28. " [28] ,Capture required status 28" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Capture required status 27" "No error,Error"
|
|
bitfld.long 0x00 26. " [26] ,Capture required status 26" "No error,Error"
|
|
bitfld.long 0x00 25. " [25] ,Capture required status 25" "No error,Error"
|
|
bitfld.long 0x00 24. " [24] ,Capture required status 24" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Capture required status 23" "No error,Error"
|
|
bitfld.long 0x00 22. " [22] ,Capture required status 22" "No error,Error"
|
|
bitfld.long 0x00 21. " [21] ,Capture required status 21" "No error,Error"
|
|
bitfld.long 0x00 20. " [20] ,Capture required status 20" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Capture required status 19" "No error,Error"
|
|
bitfld.long 0x00 18. " [18] ,Capture required status 18" "No error,Error"
|
|
bitfld.long 0x00 17. " [17] ,Capture required status 17" "No error,Error"
|
|
bitfld.long 0x00 16. " [16] ,Capture required status 16" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Capture required status 15" "No error,Error"
|
|
bitfld.long 0x00 14. " [14] ,Capture required status 14" "No error,Error"
|
|
bitfld.long 0x00 13. " [13] ,Capture required status 13" "No error,Error"
|
|
bitfld.long 0x00 12. " [12] ,Capture required status 12" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Capture required status 11" "No error,Error"
|
|
bitfld.long 0x00 10. " [10] ,Capture required status 10" "No error,Error"
|
|
bitfld.long 0x00 9. " [9] ,Capture required status 9" "No error,Error"
|
|
bitfld.long 0x00 8. " [8] ,Capture required status 8" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Capture required status 7" "No error,Error"
|
|
bitfld.long 0x00 6. " [6] ,Capture required status 6" "No error,Error"
|
|
bitfld.long 0x00 5. " [5] ,Capture required status 5" "No error,Error"
|
|
bitfld.long 0x00 4. " [4] ,Capture required status 4" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Capture required status 3" "No error,Error"
|
|
bitfld.long 0x00 2. " [2] ,Capture required status 2" "No error,Error"
|
|
bitfld.long 0x00 1. " [1] ,Capture required status 1" "No error,Error"
|
|
bitfld.long 0x00 0. " [0] ,Capture required status 0" "No error,Error"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DCDCCTL0,PMIC_CLKOUT Dethering Control Register"
|
|
line.long 0x04 "DCDCCTL1,PMIC_CLKOUT Dethering Control Register"
|
|
hexmask.long 0x04 2.--31. 1. " DCDCCTL1 ,PMIC_CLKOUT dethering control"
|
|
bitfld.long 0x04 1. " DCDCLKEN ,PMIC_CLKOUT dethering control block Enable Multi Bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " DCDCRST ,PMI clock out dethering control block reset Multi Bit" "No reset,Reset"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "USERMODEEN,User Mode Access Enable Register"
|
|
line.long 0x04 "LVDSPADCTL0,LVDS Pad Control 0 Register"
|
|
bitfld.long 0x04 22. " EXT_RES_EN_TX1 ,External reset enable for i_LVDS_tx1_io_cell" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " HIZ_DISABLE_TX1 ,HIZ disable for i_LVDS_tx1_io_cell" "No,Yes"
|
|
bitfld.long 0x04 20. " SUB_LVDS_EN_TX1 ,SUB_LVDS enable for i_LVDS_tx1_io_cell" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " LPSEL_TX1 ,LPSEL for i_LVDS_tx1_io_cell" "0,1"
|
|
newline
|
|
bitfld.long 0x04 18. " LOPWRB_TX1 ,LOPWRB for i_LVDS_tx1_io_cell" "0,1"
|
|
bitfld.long 0x04 17. " LOPWRA_TX1 ,LOPWRA for i_LVDS_tx1_io_cell" "0,1"
|
|
bitfld.long 0x04 16. " PWRDN_TX1 ,Power down for i_LVDS_tx1_io_cell" "Powered up,Powered down"
|
|
bitfld.long 0x04 14. " EXT_RES_EN_TX0 ,External reset enable for i_LVDS_tx0_io_cell" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " HIZ_DISABLE_TX0 ,HIZ disable for i_LVDS_tx0_io_cell" "No,Yes"
|
|
bitfld.long 0x04 12. " SUB_LVDS_EN_TX0 ,SUB_LVDS enable for i_LVDS_tx0_io_cell" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " LPSEL_TX0 ,LPSEL for i_LVDS_tx0_io_cell" "0,1"
|
|
bitfld.long 0x04 10. " LOPWRB_TX0 ,LOPWRB for i_LVDS_tx0_io_cell" "0,1"
|
|
newline
|
|
bitfld.long 0x04 9. " LOPWRA_TX0 ,LOPWRA for i_LVDS_tx0_io_cell" "0,1"
|
|
bitfld.long 0x04 8. " PWRDN_TX0 ,Power down for i_LVDS_tx0_io_cell" "Powered up,Powered down"
|
|
bitfld.long 0x04 6. " EXT_RES_EN_CLK ,External reset enable for i_LVDSclk_io_cell" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " HIZ_DISABLE_CLK ,HIZ disable for i_LVDSclk_io_cell" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 4. " SUB_LVDS_EN_CLK ,SUB_LVDS enable for i_LVDSclk_io_cell" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " LPSEL_CLK ,LPSEL for i_LVDSclk_io_cell" "0,1"
|
|
bitfld.long 0x04 2. " LOPWRB_CLK ,LOPWRB for i_LVDSclk_io_cell" "0,1"
|
|
bitfld.long 0x04 1. " LOPWRA_CLK ,LOPWRA for i_LVDSclk_io_cell" "0,1"
|
|
newline
|
|
bitfld.long 0x04 0. " PWRDN_CLK ,Power down for i_LVDSclk_io_cell" "Powered up,Powered down"
|
|
line.long 0x08 "LVDSPADCTL1,LVDS Pad Control 1 Register"
|
|
bitfld.long 0x08 25. " EFUSE_SET_BIAS ,Efuse set for lvds_bias_cell" "Not set,Set"
|
|
bitfld.long 0x08 24. " PWRDN_BIAS ,Power down for i_LVDSfrclk_io_cell" "Powered up,Powered down"
|
|
bitfld.long 0x08 14. " EXT_RES_EN_FRCLK ,External reset enable for i_LVDSfrclk_io_cell" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " HIZ_DISABLE_FRCLK ,HIZ disable for i_LVDSfrclk_io_cell" "No,Yes"
|
|
newline
|
|
bitfld.long 0x08 12. " SUB_LVDS_EN_FRCLK ,SUB_LVDS enable for i_LVDSfrclk_io_cell" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " LPSEL_FRCLK ,LPSEL for i_LVDSfrclk_io_cell" "0,1"
|
|
bitfld.long 0x08 10. " LOPWRB_FRCLK ,LOPWRB for i_LVDSfrclk_io_cell" "0,1"
|
|
bitfld.long 0x08 9. " LOPWRA_FRCLK ,LOPWRA for i_LVDSfrclk_io_cell" "0,1"
|
|
newline
|
|
bitfld.long 0x08 8. " PWRDN_FRCLK ,Power down for i_LVDSfrclk_io_cell" "Powered up,Powered down"
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "DFTREG0,DFT Register 0"
|
|
bitfld.long 0x00 31. " SELFTEST_EN[25] ,Memory group [25] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [24] ,Memory group [24] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [23] ,Memory group [23] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [22] ,Memory group [22] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [21] ,Memory group [21] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [20] ,Memory group [20] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [19] ,Memory group [19] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [18] ,Memory group [18] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [17] ,Memory group [17] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [16] ,Memory group [16] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [15] ,Memory group [15] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [14] ,Memory group [14] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [13] ,Memory group [13] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [12] ,Memory group [12] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [11] ,Memory group [11] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [10] ,Memory group [10] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [9] ,Memory group [9] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [8] ,Memory group [8] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [7] ,Memory group [7] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [6] ,Memory group [6] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [5] ,Memory group [5] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [4] ,Memory group [4] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [3] ,Memory group [3] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [2] ,Memory group [2] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [1] ,Memory group [1] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [0] ,Memory group [0] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PBIST_RST ,PBIST IP reset control" "No reset,Reset"
|
|
bitfld.long 0x00 0.--3. " SELFTEST_KEY ,MSS PBIST self-test key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "DFTREG1,DFT Register 1"
|
|
bitfld.long 0x04 31. " SELFTEST_DIS[31] ,Memory group [31] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [30] ,Memory group [30] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [29] ,Memory group [29] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [28] ,Memory group [28] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 27. " [27] ,Memory group [27] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [26] ,Memory group [26] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [25] ,Memory group [25] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [24] ,Memory group [24] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 23. " [23] ,Memory group [23] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [22] ,Memory group [22] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [21] ,Memory group [21] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [20] ,Memory group [20] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Memory group [19] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [18] ,Memory group [18] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [17] ,Memory group [17] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [16] ,Memory group [16] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " [15] ,Memory group [15] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [14] ,Memory group [14] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [13] ,Memory group [13] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [12] ,Memory group [12] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Memory group [11] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [10] ,Memory group [10] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [9] ,Memory group [9] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [8] ,Memory group [8] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Memory group [7] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [6] ,Memory group [6] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [5] ,Memory group [5] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [4] ,Memory group [4] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Memory group [3] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,Memory group [2] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [1] ,Memory group [1] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [0] ,Memory group [0] self-test enable" "Disabled,Enabled"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DFTREG5,DFT Register 5"
|
|
bitfld.long 0x00 1.--4. " PBIST_SELFTEST_KEY ,DSP PBIST self-test key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "MEMINITDONE,Memory Initialization Done Status Register"
|
|
bitfld.long 0x00 9. " BSSVIMMEM ,Memory initialization done status for BSS VIM memory" "Not done,Done"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "MSS_SIGNATURE,Spare Register"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "GEMBOOTSTCEN,GEM BOOT STC Enable Register"
|
|
bitfld.long 0x00 0. " GEMBOOTSTCEN ,Enable GEM STC during GEM power UP" "Disabled,Enabled"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "MISCCTL1,Miscellaneous Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. " EXT_CLK_EN ,External clock as QSPI baud clock source enable"
|
|
hexmask.long.word 0x00 8.--16. 1. " LVL_LB_CLK ,Board level loop back clock for QSPI enable"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WARM_RESET_EN ,Enable warm_resetn from external device in addition to internally generated warm reset"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "USERMODEEN2,User Mode Access Enable 2 Register"
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "SYSTICK,SYSTICK Register"
|
|
group.long 0x1C4++0x13
|
|
line.long 0x00 "SECURECFGREG1,Secure CFG Register 1"
|
|
bitfld.long 0x00 28.--30. " JTAGFIREWALLEN ,JTAG firewall" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled"
|
|
bitfld.long 0x00 20.--22. " SECURERAMFIREWALLEN ,Secure RAM firewall" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled"
|
|
bitfld.long 0x00 16.--18. " LOGGERFIREWALLEN ,Logger firewall" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled"
|
|
bitfld.long 0x00 12.--14. " TRACEFIREWALLEN ,Trace firewall" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " CRYPTOFIREWALLEN ,Crypto firewall" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled"
|
|
bitfld.long 0x00 4.--6. " CUSTCEKFIREWALLEN ,CEK[1/2] firewall" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled"
|
|
line.long 0x04 "SECURECFGREG2,Secure CFG Register 2"
|
|
bitfld.long 0x04 8.--10. " CUSTKEYERASE ,Erase CEK1" "0,1,2,3,4,5,6,Erased"
|
|
bitfld.long 0x04 0.--2. " DMMFIREWALLEN ,DMM firewall" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled"
|
|
line.long 0x08 "SECURECFGREG3,Secure CFG Register 3"
|
|
bitfld.long 0x08 28.--30. " JTAGSTICKYBIT ,JTAG sticky" "0,1,2,3,4,5,6,Set"
|
|
bitfld.long 0x08 20.--22. " SECURERAMSTICKYBIT ,Secure RAM sticky" "0,1,2,3,4,5,6,Set"
|
|
bitfld.long 0x08 16.--18. " TRACESTICKYBIT ,Trace sticky" "0,1,2,3,4,5,6,Set"
|
|
bitfld.long 0x08 12.--14. " CRYPTOSTICKYBIT ,Crypto sticky" "0,1,2,3,4,5,6,Set"
|
|
newline
|
|
bitfld.long 0x08 8.--10. " CUSTCEKSTICKYBIT ,CEK[1/2] sticky for firewall" "0,1,2,3,4,5,6,Set"
|
|
bitfld.long 0x08 0.--2. " LOGGERSTICKYBIT ,Logger sticky" "0,1,2,3,4,5,6,Set"
|
|
line.long 0x0C "SECURECFGREG4,Secure CFG Register 4"
|
|
bitfld.long 0x0C 0.--2. " DMMSTICKYBIT ,DMM sticky" "0,1,2,3,4,5,6,Set"
|
|
line.long 0x10 "SECURERAMREG,Secure RAM Register"
|
|
bitfld.long 0x10 24. " SECURERAMKEY255 ,Secure RAM key bit width" "128,255"
|
|
hexmask.long.byte 0x10 16.--23. 1. " SECURERAMKEYIDX ,Secure RAM index"
|
|
bitfld.long 0x10 8. " SECURERAMKEYRD ,Secure RAM load key" "Disabled,Enabled"
|
|
rbitfld.long 0x10 0. " SECURERAMRDDONE ,Secure RAM key loaded into register done" "Not done,Done"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "SPAREMULTIBIT,Spare Register"
|
|
bitfld.long 0x00 11. " SPAREMULTIBIT[11] ,MIBSPIB" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,SPIB trigger source polarity select" "Polarity 0,Polarity 1"
|
|
bitfld.long 0x00 9. " [9] ,SPIA trigger source polarity select" "Polarity 0,Polarity 1"
|
|
bitfld.long 0x00 8. " [8] ,MIBSPIB external chip select is overridden with the value of MIBSPIB CS polarity-slave mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,MIBSPIA external chip select is overridden with the value of MIBSPIB CS polarity-slave mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,MIBSPIB CS trigger SRC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,MIBSPIB CS polarity-slave mode" "High,Low"
|
|
bitfld.long 0x00 4. " [4] ,MIBSPIB MISO OE_N control based on chip select" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,MIBSPIA" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,MIBSPIA CS trigger SRC enable-slave mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,MIBSPIA CS polarity-slave mode" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,MIBSPIA MISO OE_N control based on chip" "Disabled,Enabled"
|
|
rgroup.long 0x200++0x0F
|
|
line.long 0x00 "UID31TO0,Efuse Row Capture Register For FROM1"
|
|
line.long 0x04 "UID63TO32,Efuse Row Capture Register For FROM1"
|
|
line.long 0x08 "UID95TO64,Efuse Row Capture Register For FROM1"
|
|
line.long 0x0C "UID119TO96,Efuse Row Capture Register For FROM1"
|
|
rgroup.long 0x2A8++0x07
|
|
line.long 0x00 "MEMINITSTARTSHMEM,Shared Memory Initialization Start Register"
|
|
bitfld.long 0x00 7. " MEMINITSTARTBANK[7] ,Trigger shared memory initialization for bank 7" "Not triggered,Triggered"
|
|
bitfld.long 0x00 6. " [6] ,Trigger shared memory initialization for bank 6" "Not triggered,Triggered"
|
|
bitfld.long 0x00 5. " [5] ,Trigger shared memory initialization for bank 5" "Not triggered,Triggered"
|
|
bitfld.long 0x00 4. " [4] ,Trigger shared memory initialization for bank 4" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Trigger shared memory initialization for bank 3" "Not triggered,Triggered"
|
|
bitfld.long 0x00 2. " [2] ,Trigger shared memory initialization for bank 2" "Not triggered,Triggered"
|
|
bitfld.long 0x00 1. " [1] ,Trigger shared memory initialization for bank 1" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " [0] ,Writing '1' will trigger shared memory initialization for bank 0" "Not triggered,Triggered"
|
|
line.long 0x04 "MEMINITDONESHMEM,Shared Memory Initialization End Register"
|
|
bitfld.long 0x04 7. " MEMINITDONEBANK[7] ,Memory initialization done status for shared memory for bank 7" "Pending,Done"
|
|
bitfld.long 0x04 6. " [6] ,Memory initialization done status for shared memory for bank 6" "Pending,Done"
|
|
bitfld.long 0x04 5. " [5] ,Memory initialization done status for shared memory for bank 5" "Pending,Done"
|
|
bitfld.long 0x04 4. " [4] ,Memory initialization done status for shared memory for bank 4" "Pending,Done"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Memory initialization done status for shared memory for bank 3" "Pending,Done"
|
|
bitfld.long 0x04 2. " [2] ,Memory initialization done status for shared memory for bank 2" "Pending,Done"
|
|
bitfld.long 0x04 1. " [1] ,Memory initialization done status for shared memory for bank 1" "Pending,Done"
|
|
bitfld.long 0x04 0. " [0] ,Memory initialization done status for shared memory for bank 0" "Pending,Done"
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "DSSMEMTAB0,Controls Ordering Of Banks In Shared Memory Associated With DSS Register"
|
|
bitfld.long 0x00 28.--31. " DSSMEMTAB0[7] ,DSS L3RAM shared memory bank number 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 24.--27. " [6] ,DSS L3RAM shared memory bank number 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 20.--23. " [5] ,DSS L3RAM shared memory bank number 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " [4] ,DSS L3RAM shared memory bank number 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " [3] ,DSS L3RAM shared memory bank number 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 8.--11. " [2] ,DSS L3RAM shared memory bank number 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 4.--7. " [1] ,DSS L3RAM shared memory bank number 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. " [0] ,DSS L3RAM shared memory bank number 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x2BC++0x07
|
|
line.long 0x00 "TCMAMEMTAB,Controls Ordering Of Banks In Shared Memory Associated With MSS TCMA Register"
|
|
bitfld.long 0x00 12.--15. " TCMAMEMTAB[3] ,MSS TCMA shared memory bank number 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 8.--11. " [2] ,MSS TCMA shared memory bank number 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 4.--7. " [1] ,MSS TCMA shared memory bank number 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. " [0] ,MSS TCMA shared memory bank number 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
line.long 0x04 "TCMBMEMTAB,Controls Ordering Of Banks In Shared Memory Associated With MSS TCMB Register"
|
|
bitfld.long 0x04 12.--15. " TCMBMEMTAB[3] ,MSS TCMB shared memory bank number 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x04 8.--11. " [2] ,MSS TCMB shared memory bank number 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x04 4.--7. " [1] ,MSS TCMB shared memory bank number 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " [0] ,MSS TCMB shared memory bank number 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x2C8++0x0B
|
|
line.long 0x00 "SHMEMBANKSEL3TO0,Shared Memory Master Allocation Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BANK[3] ,Bank 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " [2] ,Bank 2"
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|
hexmask.long.byte 0x00 8.--15. 1. " [1] ,Bank 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " [0] ,Bank 0"
|
|
line.long 0x04 "SHMEMBANKSEL7TO4,Shared Memory Master Allocation Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " BANK[7] ,Bank 7"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [6] ,Bank 6"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [5] ,Bank 5"
|
|
hexmask.long.byte 0x04 0.--7. 1. " [4] ,Bank 4"
|
|
line.long 0x08 "PBISTCLKCTL,PBIST Clock Control Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PBIST300MCLKGATE ,Pre clock divider gate for PBIST300M clock"
|
|
bitfld.long 0x08 4.--7. " PBIST300MCLKSRCSEL ,DSP PBIST clock source select" "CPUCLK,RCCLK,600 MHz PLL,,RCCLK,RCCLK,REFCLK,RCCLK,?..."
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|
bitfld.long 0x08 0.--3. " PBIST300MCLKDIV ,Divide value for DSP PBIST source clock" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
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|
width 0x0B
|
|
tree.end
|
|
tree "MSS RCM Registers"
|
|
base ad:0xFFFFFF00
|
|
width 18.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "SOFTRST0,System Software Reset 0 Register"
|
|
bitfld.long 0x00 24. " SYSRSTDBGRSTEN ,CR4 only reset trigger" "Not triggered,Triggered"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SYSRSTCLKGATEEN ,Clock gate"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SYSRSTIDLECHKEN ,Idle check"
|
|
newline
|
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hexmask.long.byte 0x00 0.--7. 1. " SYSRST ,MSS subsystem only reset"
|
|
line.long 0x04 "SOFTRST1,System Software Reset 1 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DMARST ,DMA only reset"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DCCBRST ,DCC B only reset"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DCCARST ,DCC A only reset"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. " CR4SYSRST ,MSS CR4 only reset"
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|
line.long 0x08 "SOFTRST2,System Software Reset 2 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " VIMRST ,VIM only reset"
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|
hexmask.long.byte 0x08 16.--23. 1. " ESMRST ,ESM only reset"
|
|
hexmask.long.byte 0x08 8.--15. 1. " RTIRST ,RTI only reset"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. " UARTARST ,UARTA/SCIA only reset"
|
|
line.long 0x0C "SOFTRST3,System Software Reset 3 Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " FRCRST ,FRC only reset"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " CRCRST ,CRC only reset"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " WDTRST ,WDT only reset"
|
|
line.long 0x10 "MCUIFSOFTRST0,MCUIF Software Reset Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " GIORST ,GIO only reset"
|
|
hexmask.long.byte 0x10 16.--23. 1. " SPIBRST ,SPIB only reset"
|
|
hexmask.long.byte 0x10 8.--15. 1. " SPIARST ,SPIA only reset"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. " QSPIRST ,QSPI only reset"
|
|
line.long 0x14 "ECUIFSOFTRST0,ECUIF Software Reset Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " UARTBRST ,UARTB/SCIB only reset"
|
|
hexmask.long.byte 0x14 16.--23. 1. " CANFDRST ,CANFD only reset"
|
|
hexmask.long.byte 0x14 8.--15. 1. " I2CRST ,I2C only reset"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. " FDCAN2RST ,FDCAN2 only reset"
|
|
line.long 0x18 "CLKDIVCTL0,Clock Divider Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " FDCANCLKDIV ,Divide value for FDCAN source clock"
|
|
hexmask.long.byte 0x18 16.--23. 1. " DCANCLKDIV ,Divide value for DCAN source clock"
|
|
hexmask.long.byte 0x18 8.--15. 1. " VCLKCLKDIV ,Divide value for MSS subsystem source clock"
|
|
line.long 0x1C "CLKSRCSEL0,Clock Source Select Register"
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|
bitfld.long 0x1C 28.--31. " RTIDCLKSRCSEL ,Select clock source for RTID baud clock" "VCLK,RCCLK,600 Mhz PLL,240 Mhz PLL,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
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bitfld.long 0x1C 24.--27. " RTICCLKSRCSEL ,Select clock source for RTIC baud clock" "VCLK,RCCLK,600 Mhz PLL,240 Mhz PLL,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
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|
bitfld.long 0x1C 16.--19. " QSPICLKSRCSEL ,Select clock source for QSPI baud clock" "VCLK,RCCLK,600 Mhz PLL,240 Mhz PLL,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
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|
newline
|
|
bitfld.long 0x1C 8.--11. " FRAYCLKSRCSEL ,Select clock source for FRAY" "VCLK,RCCLK,600 Mhz PLL,240 Mhz PLL,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
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bitfld.long 0x1C 0.--3. " DCANCLKSRCSEL ,Select clock source for DCAN" "VCLK,RCCLK,600 Mhz PLL,240 Mhz PLL,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
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|
line.long 0x20 "CR4CTL,CR4CTL Register"
|
|
hexmask.long.byte 0x20 16.--23. 1. " MEMSWAPWAIT ,MEMSWAPWAIT"
|
|
hexmask.long.byte 0x20 8.--15. 1. " CR4MEMSWAP ,CR4MEMSWAP"
|
|
line.long 0x24 "SOFTRST4,System Software Reset 4 Register"
|
|
hexmask.long.byte 0x24 8.--15. 1. " RTIDRST ,RTID only reset"
|
|
hexmask.long.byte 0x24 0.--7. 1. " RTICRST ,RTIC only reset"
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|
group.long 0x3C++0x03
|
|
line.long 0x00 "CLKGATE,Clock Gate Register"
|
|
bitfld.long 0x00 10. " FRCCLKGATE ,Pre clock divider gate for FRC clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RTIDCLKGATE ,Pre clock divider gate for RTID clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RTICCLKGATE ,Pre clock divider gate for RTIC clock" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " FDCANCLKGATE ,Pre clock divider gate for FDCAN clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DCANCLKGATE ,Pre clock divider gate for DCAN clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " QSPICLKGATE ,Pre clock divider gate for QSPI clock" "Disabled,Enabled"
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|
group.long 0x44++0x03
|
|
line.long 0x00 "CLKSRCSEL1,Clock Source Select Register"
|
|
bitfld.long 0x00 8.--11. " FRCCLKSRCSEL ,Select clock source for FRC" "CPUCLK,RCCLK,600 Mhz PLL,240 Mhz PLL,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
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bitfld.long 0x00 0.--3. " VCLKCLKSRCSEL ,Select clock source for MSS subsystem VCLK" "CPUCLK,RCCLK,600 Mhz PLL,240 Mhz PLL,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
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|
group.long 0x50++0x03
|
|
line.long 0x00 "CLKDIVCTL1,Clock Divider Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " FRCCLKDIV ,Divide value for FRC source clock"
|
|
hexmask.long.byte 0x00 8.--15. 1. " RTIDCLKDIV ,Clock source for RTID"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RTICCLKDIV ,Clock source for RTIC"
|
|
rgroup.long 0x54++0x07
|
|
line.long 0x00 "CURRCLKDIV0,Current Clock Divider 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " FDCANCURRCLKDIV ,Current divide value of FDCAN baud clock divider"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DCANCURRCLKDIV ,Current divide value of DCAN baud clock divider"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VCLKCURRCLKDIV ,Current divide value of VCLK divider"
|
|
line.long 0x04 "RTICURRCLKDIV,RTI Current Clock Divider Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " FRCCURRCLKDIV ,Current divide value of FRC clock divider"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RTIDCURRCLKDIV ,Current divide value of RTID divider"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RTICCURRCLKDIV ,Current divide value of RTIC divider"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "MEMINITSTART,Memory Initialization Trigger Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MEMINITKEY ,Memory hardware initialization global enable key"
|
|
bitfld.long 0x00 17. " BSSMBOX4GEMMEM ,DSS-BSS mailbox initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 16. " MSSMBOX4GEMMEM ,DSS-MSS mailbox initialization" "Not initialized,Initialized"
|
|
newline
|
|
bitfld.long 0x00 15. " GEMMBOX4MSSMEM ,DSS-MSS mailbox initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 14. " GEMMBOX4BSSMEM ,DSS-BSS mailbox initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 9. " DMA2MEM ,DMA2 memory initialization" "Not initialized,Initialized"
|
|
newline
|
|
bitfld.long 0x00 8. " BSSMBOX4MSSMEM ,BSS mail box FO MSS memory initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 7. " MSSMBOX4BSSMEM ,MSS mail box FO BSS memory initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 6. " DCANMEM ,DCAN memory initialization" "Not initialized,Initialized"
|
|
newline
|
|
bitfld.long 0x00 5. " SPIBMEM ,SPIB memory initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 4. " SPIAMEM ,SPIA memory initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 3. " VIMMEM ,VIM memory initialization" "Not initialized,Initialized"
|
|
newline
|
|
bitfld.long 0x00 2. " DMAMEM ,DMA memory initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 1. " CR4TCMBMEM ,MSS TCMB memory initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 0. " CR4TCMAMEM ,MSS TCMA memory initialization" "Not initialized,Initialized"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "CURRCLKDIV1,Current Clock Divider 1 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " QSPICURRCLKDIV ,Current divide value of QSPI_CLK divider"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "MEMINITDONE,Memory Initialization Done Register"
|
|
bitfld.long 0x00 17. " BSSMBOX4GEMMEM ,Memory Initialization done status for DSS- BSS mailbox" "Not done,Done"
|
|
bitfld.long 0x00 16. " MSSMBOX4GEMMEM ,Memory Initialization done status for DSS- MSS mailbox" "Not done,Done"
|
|
bitfld.long 0x00 15. " GEMMBOX4MSSMEM ,Memory Initialization done status for DSS- MSS mailbox" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 14. " GEMMBOX4BSSMEM ,Memory Initialization done status for DSS- BSS mailbox" "Not done,Done"
|
|
bitfld.long 0x00 9. " DMA2MEM ,Memory Initialization done status for MSS DMA2 memory" "Not done,Done"
|
|
bitfld.long 0x00 8. " BSSMBOX4MSSMEM ,Memory initialization done status for BSS mailbox MSS memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 7. " MSSMBOX4BSSMEM ,Memory initialization done status for MSS mailbox for BSS memory" "Not done,Done"
|
|
bitfld.long 0x00 6. " DCANMEM ,Memory initialization done status for DCAN memory" "Not done,Done"
|
|
bitfld.long 0x00 5. " SPIBMEM ,Memory initialization done status for MSS SPIB memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 4. " SPIAMEM ,Memory initialization done status for MSS SPIA memory" "Not done,Done"
|
|
bitfld.long 0x00 3. " VIMMEM ,Memory initialization done status for MSS VIM memory" "Not done,Done"
|
|
bitfld.long 0x00 2. " DMAMEM ,Memory initialization done status for MSS DMA memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 1. " CR4TCMBMEM ,Memory initialization done status for MSS TCMB memory" "Not done,Done"
|
|
bitfld.long 0x00 0. " CR4TCMAMEM ,Memory initialization done status for MSS TCMA memory" "Not done,Done"
|
|
group.long 0x70++0x33
|
|
line.long 0x00 "ECCENMSSGEM,ECC Enable MSSGEM Register"
|
|
bitfld.long 0x00 19.--21. " GEM_MSS_ADDR_CLR ,Write 3'b111 to clear address captured due to ECC error in GEM mbox for MSS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " MSS_GEM_ADDR_CLR ,Write 3'b111 to clear address captured due to ECC error in MSS mbox for GEM" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ECC_MSS_DSS_EN0 ,Enable ECC for MSS-DSS mailbox"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " ECC_MSS_DSS_EN1 ,Enable ECC for MSS-DSS mailbox"
|
|
line.long 0x04 "ECCCAPTMSSGEM,ECC CAPT MSSGEM Register"
|
|
hexmask.long.byte 0x04 24.--30. 1. " GEM_MBOX4MSS_REPAIRED_BIT ,GEM mailbox for MSS repaired bit"
|
|
hexmask.long.byte 0x04 16.--23. 0x01 " GEM_MBOX4MSS_ECC_FAULT_ADDRESS ,GEM mailbox for MSS repaired bit"
|
|
hexmask.long.byte 0x04 8.--14. 1. " MSS_MBOX4GEM_REPAIRED_BIT ,MSS mailbox for GEM repaired bit"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 0x01 " MSS_MBOX4GEM_ECC_FAULT_ADDRESS ,MSS mailbox for GEM repaired bit"
|
|
line.long 0x08 "ECCENBSSGEM,ECC Enable BSSGEM Register"
|
|
bitfld.long 0x08 19.--21. " GEM_BSS_ADDR_CLR ,Write 3'b111 to clear address captured due to ECC error in GEM mbox for BSS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 16.--18. " BSS_GEM_ADDR_CLR ,Write 3'b111 to clear address captured due to ECC error in BSS mbox for GEM" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x08 8.--15. 1. " ECC_MSS_BSS_EN1 ,Enable ECC for MSS-BSS mailbox"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. " ECC_MSS_BSS_EN0 ,Enable ECC for MSS-BSS mailbox"
|
|
line.long 0x0C "ECCCAPTBSSGEM,ECC CAPT BSSGEM Register"
|
|
hexmask.long.byte 0x0C 24.--30. 1. " GEM_MBOX4BSS_REPAIRED_BIT ,GEM mailbox for BSS repaired bit"
|
|
hexmask.long.byte 0x0C 16.--23. 0x01 " GEM_MBOX4BSS_ECC_FAULT_ADDRESS ,GEM mailbox for BSS repaired bit"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " BSS_MBOX4GEM_REPAIRED_BIT ,BSS mailbox for GEM repaired bit"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 0x01 " BSS_MBOX4GEM_ECC_FAULT_ADDRESS ,BSS mailbox for GEM repaired bit"
|
|
line.long 0x10 "USERMODEEN,User Mode Access Enable Register"
|
|
line.long 0x14 "NSYSPERUSERMODEN,NSYSPER User Mode Enable Register"
|
|
bitfld.long 0x14 24.--26. " DCAN_UM_EN ,Enable user mode access to DCAN" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 19.--21. " SCIB_UM_EN ,Enable user mode access to SCIB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 16.--18. " SCIA_UM_EN ,Enable user mode access to SCIA" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 11.--13. " QSPI_UM_EN ,Enable user mode access to QSPI" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 8.--10. " GIO_UM_EN ,Enable user mode access to GIO" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 3.--5. " SPIB_UM_EN ,Enable user mode access to SPIB" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x14 0.--2. " SPIA_UM_EN ,Enable user mode access to SPIA" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SECURERAMMMI,Secure RAM MMI Register"
|
|
rbitfld.long 0x18 16. " SECURERAMINITDONE ,Memory initialization done status for Secure Key RAM" "Not done,Done"
|
|
bitfld.long 0x18 0. " SECURERAMINIT ,Secure Key RAM memory initialization" "Not initialized,Initialized"
|
|
line.long 0x1C "SECURERAMECC,Secure RAM ECC Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " SECURERAMBIT ,Secure key RAM repaired bit"
|
|
hexmask.long.byte 0x1C 16.--23. 0x01 " SECURERAMADDR ,Secure key RAM ECC fault address"
|
|
bitfld.long 0x1C 8.--10. " SECURERAMECCCLR ,Write 3'b111 to clear address captured due to ECC error" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. " SECURERAMECCEN ,ECC for secure key RAM"
|
|
line.long 0x20 "ESMGATE0,ESM Gate 0 Register"
|
|
bitfld.long 0x20 28.--31. " LINE[7] ,Gate ESM group 2 line 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x20 24.--27. " [6] ,Gate ESM group 2 line 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x20 20.--23. " [5] ,Gate ESM group 2 line 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
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bitfld.long 0x20 16.--19. " [4] ,Gate ESM group 2 line 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 12.--15. " [3] ,Gate ESM group 2 line 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 8.--11. " [2] ,Gate ESM group 2 line 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 4.--7. " [1] ,Gate ESM group 2 line 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 0.--3. " [0] ,Gate ESM group 2 line 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x24 "ESMGATE1,ESM Gate 1 Register"
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bitfld.long 0x24 28.--31. " LINE[15] ,Gate ESM group 2 line 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 24.--27. " [14] ,Gate ESM group 2 line 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 20.--23. " [13] ,Gate ESM group 2 line 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. " [12] ,Gate ESM group 2 line 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 12.--15. " [11] ,Gate ESM group 2 line 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 8.--11. " [10] ,Gate ESM group 2 line 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 4.--7. " [9] ,Gate ESM group 2 line 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 0.--3. " [8] ,Gate ESM group 2 line 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x28 "ESMGATE2,ESM Gate 2 Register"
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bitfld.long 0x28 28.--31. " LINE[23] ,Gate ESM group 2 line 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 24.--27. " [22] ,Gate ESM group 2 line 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 20.--23. " [21] ,Gate ESM group 2 line 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 16.--19. " [20] ,Gate ESM group 2 line 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 12.--15. " [19] ,Gate ESM group 2 line 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 8.--11. " [18] ,Gate ESM group 2 line 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 4.--7. " [17] ,Gate ESM group 2 line 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 0.--3. " [16] ,Gate ESM group 2 line 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x2C "ESMGATE3,ESM Gate 3 Register"
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bitfld.long 0x2C 28.--31. " LINE[23] ,Gate ESM group 2 line 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 24.--27. " [22] ,Gate ESM group 2 line 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 20.--23. " [21] ,Gate ESM group 2 line 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 16.--19. " [20] ,Gate ESM group 2 line 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 12.--15. " [19] ,Gate ESM group 2 line 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 8.--11. " [18] ,Gate ESM group 2 line 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 4.--7. " [17] ,Gate ESM group 2 line 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 0.--3. " [16] ,Gate ESM group 2 line 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x30 "ESMGATE4,ESM Gate 4 Register"
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bitfld.long 0x30 28.--31. " LINE[7] ,Gate ESM group 3 line 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 24.--27. " [6] ,Gate ESM group 3 line 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 20.--23. " [5] ,Gate ESM group 3 line 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 16.--19. " [4] ,Gate ESM group 3 line 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 12.--15. " [3] ,Gate ESM group 3 line 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 8.--11. " [2] ,Gate ESM group 3 line 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 4.--7. " [1] ,Gate ESM group 3 line 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 0.--3. " [0] ,Gate ESM group 3 line 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xA8++0x2F
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line.long 0x00 "MSSECOSPARE,MSS COSPARE Register"
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line.long 0x04 "KEY,CFGREG Access Key Register"
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line.long 0x08 "DBGACKCTL0,Debug A Control 0 Register"
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bitfld.long 0x08 27.--29. " DCCASUSEN ,DCCA suspend operation enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled"
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bitfld.long 0x08 24.--26. " DCCBSUSEN ,DCCB suspend operation enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled"
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bitfld.long 0x08 19.--21. " DCANSUSEN ,DCAN suspend operation enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled"
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bitfld.long 0x08 16.--18. " I2CSUSEN ,I2C suspend operation enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled"
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bitfld.long 0x08 11.--13. " MCRCSUSEN ,MCRC suspend operation enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled"
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bitfld.long 0x08 8.--10. " DMASUSEN ,DMA suspend operation enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled"
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bitfld.long 0x08 3.--5. " FRCSUSEN ,FRC suspend operation enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled"
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bitfld.long 0x08 0.--2. " WDTSUSEN ,WDT suspend operation enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled"
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line.long 0x0C "DBGACKCTL1,Debug A Control 1 Register"
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bitfld.long 0x0C 24.--26. " CCMR4SUSEN ,CCMR4 suspend operation enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled"
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bitfld.long 0x0C 19.--21. " CCCASUSEN ,CCCA suspend operation enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled"
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bitfld.long 0x0C 16.--18. " CCCBSUSEN ,CCCB suspend operation enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled"
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bitfld.long 0x0C 11.--13. " UARTASUSEN ,UARTA suspend operation enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled"
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bitfld.long 0x0C 8.--10. " UARTBSUSEN ,UARTB suspend operation enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled"
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bitfld.long 0x0C 3.--5. " RTISUSEN ,RTI suspend operation enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled"
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bitfld.long 0x0C 0.--2. " BSSSUSEN ,BSS suspend operation enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled"
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line.long 0x10 "SWIRQA,SWIRQ 0 Register"
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hexmask.long.byte 0x10 24.--31. 1. " SWIRQ[1] ,System software interrupt trigger 1"
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hexmask.long.byte 0x10 8.--15. 1. " [0] ,System software interrupt trigger 0"
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line.long 0x14 "SWIRQB,SWIRQ 1 Register"
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hexmask.long.byte 0x14 24.--31. 1. " SWIRQ[3] ,System software interrupt trigger 3"
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hexmask.long.byte 0x14 8.--15. 1. " [2] ,System software interrupt trigger 2"
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line.long 0x18 "MISCCTL0,Miscellaneous Control Register"
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bitfld.long 0x18 22.--24. " TCMB1EZDIS ,TCMB1 EZ disable" "No,No,No,No,No,No,No,Yes"
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bitfld.long 0x18 19.--21. " TCMB0EZDIS ,TCMB0 EZ disable" "No,No,No,No,No,No,No,Yes"
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bitfld.long 0x18 16.--18. " TCMAEZDIS ,TCMA EZ disable" "No,No,No,No,No,No,No,Yes"
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hexmask.long.byte 0x18 8.--15. 1. " SPIBSYNC2SEN ,SPIB latching of baud clock enable"
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hexmask.long.byte 0x18 0.--7. 1. " SPIASYNC2SEN ,SPIA latching of baud clock enable"
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line.long 0x1C "ATCMERRCAPTCTL,A TCM Error CAPTCTL Register"
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hexmask.long.tbyte 0x1C 8.--27. 0x01 " ERRATCADDR ,TCM address for which parity error happened"
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bitfld.long 0x1C 3.--5. " ATCFORCEERR ,ATC error force" ",Not forced,Not forced,Not forced,Not forced,Not forced,Not forced,Forced"
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bitfld.long 0x1C 0.--2. " ERRATCADDRCLR ,Re-enable latching" "0,1,2,3,4,5,6,7"
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line.long 0x20 "B0TCMERRCAPTCTL,B0 TCM Error CAPTCTL Register"
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hexmask.long.tbyte 0x20 8.--27. 0x01 " ERRB0TCADDR ,TCM address for which parity error happened"
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bitfld.long 0x20 3.--5. " B0TCFORCEERR ,B0TC error force" ",Not forced,Not forced,Not forced,Not forced,Not forced,Not forced,Forced"
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bitfld.long 0x20 0.--2. " ERRB0TCADDRCLR ,Re-enable the latching" "0,1,2,3,4,5,6,7"
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line.long 0x24 "B1TCMERRCAPTCTL,B1 TCM Error CAPTCTL Register"
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hexmask.long.tbyte 0x24 8.--27. 0x01 " ERRB1TCADDR ,TCM address for which parity error happened"
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bitfld.long 0x24 3.--5. " B1TCFORCEERR ,B1TC error force" ",Not forced,Not forced,Not forced,Not forced,Not forced,Not forced,Forced"
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bitfld.long 0x24 0.--2. " ERRB1TCADDRCLR ,Re-enable latching" "0,1,2,3,4,5,6,7"
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line.long 0x28 "SOFTCORERST,Software CORE Reset Register"
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hexmask.long.byte 0x28 24.--31. 1. " RST_WFICHECKEN ,Reset WFI check enable"
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hexmask.long.byte 0x28 16.--23. 1. " RSTASSRTDLY ,RST assert for programmed number of clock cycles"
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hexmask.long.byte 0x28 8.--15. 1. " RSTTOASSRTDLY ,Programmed number of clock cycle before reset is asserted"
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line.long 0x2C "WDOGRSTEN,Watchdog Reset Enable Register"
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bitfld.long 0x2C 7. " SYSWDOGRSTEN[7] ,MSS WDOG expiry to cause only MSS subsystem reset enable 7" "Disabled,Enabled"
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bitfld.long 0x2C 6. " [6] ,MSS WDOG expiry to cause only MSS subsystem reset enable 6" "Disabled,Enabled"
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bitfld.long 0x2C 5. " [5] ,MSS WDOG expiry to cause only MSS subsystem reset enable 5" "Disabled,Enabled"
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bitfld.long 0x2C 4. " [4] ,MSS WDOG expiry to cause only MSS subsystem reset enable 4" "Disabled,Enabled"
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bitfld.long 0x2C 3. " [3] ,MSS WDOG expiry to cause only MSS subsystem reset enable 3" "Disabled,Enabled"
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bitfld.long 0x2C 2. " [2] ,MSS WDOG expiry to cause only MSS subsystem reset enable 2" "Disabled,Enabled"
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bitfld.long 0x2C 1. " [1] ,MSS WDOG expiry to cause only MSS subsystem reset enable 1" "Disabled,Enabled"
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bitfld.long 0x2C 0. " [0] ,MSS WDOG expiry to cause only MSS subsystem reset enable 0" "Disabled,Enabled"
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rgroup.long 0xD8++0x07
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line.long 0x00 "RSTCAUSE,MSS RST Cause Register"
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hexmask.long.byte 0x00 0.--7. 1. " MSS_RCM ,RST cause"
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line.long 0x04 "RSTCAUSECLR,MSS RST Cause Clear Register"
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hexmask.long.byte 0x04 0.--7. 1. " RSTCAUSECLR ,RST cause clear"
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group.long 0xE0++0x03
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line.long 0x00 "SPITRIGSRC,SPI Trigger Source Register"
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hexmask.long.word 0x00 16.--26. 1. " SPIBTRIG ,Trigger sources for MIBSPIB"
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bitfld.long 0x00 8. " SPIATRIG1 ,1st bit of trigger source input of SPIA" "Disabled,Enabled"
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bitfld.long 0x00 0. " SPIATRIG0 ,0th bit of trigger source input of SPIA" "Disabled,Enabled"
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rgroup.long 0xE4++0x03
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line.long 0x00 "CLKINUSE,MSS Clock In Use Register"
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bitfld.long 0x00 24.--27. " FRCCLKINUSE ,Current clock source select MUX value for FRC clock" "VCLK,RCCLK,600Mhz PLL,240Mhz PLL,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
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bitfld.long 0x00 20.--23. " RTIDCLKINUSE ,Current clock source select MUX value for RTID clock" "VCLK,RCCLK,600Mhz PLL,240Mhz PLL,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
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bitfld.long 0x00 16.--19. " RTICCLKINUSE ,Current clock source select MUX value for RTIC clock" "VCLK,RCCLK,600Mhz PLL,240Mhz PLL,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
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bitfld.long 0x00 12.--15. " QSPICLKINUSE ,Current clock source select MUX value for QSPI clock" "VCLK,RCCLK,600Mhz PLL,240Mhz PLL,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
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bitfld.long 0x00 8.--11. " DCANCLKINUSE ,Current clock source select MUX value for DCAN clock" "VCLK,RCCLK,600Mhz PLL,240Mhz PLL,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
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bitfld.long 0x00 4.--7. " FRAYCLKINUSE ,Current clock source select MUX value for fray clock" "VCLK,RCCLK,600Mhz PLL,240Mhz PLL,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
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bitfld.long 0x00 0.--3. " VCLKINUSE ,Current clock source select MUX value for VCLK" "VCLK,RCCLK,600Mhz PLL,240Mhz PLL,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
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group.long 0xE8++0x03
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line.long 0x00 "ECCEN,MSS ECC Enable Register"
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bitfld.long 0x00 19.--21. " BSS_MSS_ADDR_CLR ,Write 3'b111 to clear address captured due to ECC error in BSS mbox for MSS" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16.--18. " MSS_BSS_ADDR_CLR ,Write 3'b111 to clear address captured due to ECC error in MSS mbox for BSS" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x00 8.--15. 1. " ECC_MSS_BSS_EN1 ,Enable ECC for MSS-BSS mailbox"
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hexmask.long.byte 0x00 0.--7. 1. " ECC_MSS_BSS_EN0 ,Enable ECC for MSS-BSS mailbox"
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rgroup.long 0xEC++0x03
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line.long 0x00 "ECCCAPT,MSS ECC Capture Register"
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hexmask.long.byte 0x00 24.--30. 1. " BSS_MBOX4MSS_REPAIRED_BIT ,BSS mailbox for MSS repaired bit"
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hexmask.long.byte 0x00 16.--23. 0x01 " BSS_MBOX4MSS_ECC_FAULT_ADDRESS ,BSS mailbox for MSS repaired bit"
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hexmask.long.byte 0x00 8.--14. 1. " MSS_MBOX4BSS_REPAIRED_BIT ,MSS mailbox for BSS repaired bit"
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hexmask.long.byte 0x00 0.--7. 0x01 " MSS_MBOX4BSS_ECC_FAULT_ADDRESS ,MSS mailbox for BSS repaired bit"
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group.long 0xF0++0x03
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line.long 0x00 "CLKDIVCTL2,Clock Divide Control 2 Register"
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hexmask.long.byte 0x00 0.--7. 1. " QSPICLKDIV ,Divide value for QSPI baud clock selected by field QSPICLKSRCSEL"
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group.long 0xFC++0x03
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line.long 0x00 "SWIRQC,SW IRQ2 Register"
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hexmask.long.byte 0x00 24.--31. 1. " SWIRQ[5] ,Trigger interrupt 5"
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hexmask.long.byte 0x00 8.--15. 1. " [4] ,Trigger interrupt 4"
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width 0x0B
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tree.end
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tree "MSS GPCFG Registers"
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base ad:0xFFFFF800
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width 17.
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group.long 0x00++0x13
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line.long 0x00 "GPCFG0,General Purpose Config Register 0"
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line.long 0x04 "GPCFG1,General Purpose Config Register 1"
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line.long 0x08 "GPCFG2,General Purpose Config Register 2"
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line.long 0x0C "GPCFG3,General Purpose Config Register 3"
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line.long 0x10 "GPCFG4,General Purpose Config Register 4"
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group.long 0x2C++0x03
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line.long 0x00 "GPCFG11,General Purpose Config Register 11"
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bitfld.long 0x00 17. " BSS2DSSSWIRQ2 ,Self clearing register bit to generate interrupt to DSP from BSS" "No interrupt,Interrupt"
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bitfld.long 0x00 16. " BSS2DSSSWIRQ1 ,Self clearing register bit to generate interrupt to DSP from BSS" "No interrupt,Interrupt"
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bitfld.long 0x00 9. " DSS2BSSSWIRQ2 ,Self clearing register bit to generate interrupt to BSS from DSP" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " DSS2BSSSWIRQ1 ,Self clearing register bit to generate interrupt to BSS from DSP" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " MSS2BSSSWIRQ2 ,Self clearing register bit to generate interrupt to BSS from MSS" "No interrupt,Interrupt"
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newline
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bitfld.long 0x00 0. " MSS2BSSSWIRQ1 ,Self clearing register bit to generate interrupt to BSS from MSS" "No interrupt,Interrupt"
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group.long 0xD0++0x1F
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line.long 0x00 "CCCACFG0,CCC A Configuration 0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " MARGIN_COUNT ,Margin value for clock comparison"
|
|
bitfld.long 0x00 8. " SINGLE_SHOT_MODE ,Single shot mode" "Continuous,Single shot"
|
|
bitfld.long 0x00 7. " ENABLE_MODULE ,CCC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DISABLE_CLOCKS ,Clock disable" "No,Yes"
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|
bitfld.long 0x00 3.--5. " CLOCK[1]_SEL ,Clock 1 select" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0.--2. " [0] ,Clock 0 select" "0,1,2,3,4,5,6,7"
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|
line.long 0x04 "CCCACFG1,CCC A Configuration 1 Register"
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line.long 0x08 "CCCACFG2,CCC A Configuration 2 Register"
|
|
line.long 0x0C "CCCACFG3,CCC A Configuration 3 Register"
|
|
line.long 0x10 "CCCBCFG0,CCC B Configuration 0 Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " MARGIN_COUNT ,Margin value for clock comparison"
|
|
bitfld.long 0x10 8. " SINGLE_SHOT_MODE ,Single shot mode" "Continuous,Single shot"
|
|
bitfld.long 0x10 7. " ENABLE_MODULE ,CCC enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " DISABLE_CLOCKS ,Clock disables" "No,Yes"
|
|
bitfld.long 0x10 3.--5. " CLOCK[1]_SEL ,Clock 1 select" "0,1,2,3,4,5,6,7"
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|
newline
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bitfld.long 0x10 0.--2. " [0] ,Clock 0 select" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "CCCBCFG1,CCC B Configuration 1 Register"
|
|
line.long 0x18 "CCCBCFG2,CCC B Configuration 2 Register"
|
|
line.long 0x1C "CCCBCFG3,CCC B Configuration 3 Register"
|
|
rgroup.long 0xF0++0x0B
|
|
line.long 0x00 "CCCACNTVAL,CCC A Count Value Register"
|
|
line.long 0x04 "CCCBCNTVAL,CCC B Count Value Register"
|
|
line.long 0x08 "CCCABERRSTAT,CCC AB Error Status Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " CCCB_ERR_STS ,CCCB error status"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CCCA_ERR_STS ,CCCA error status"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "USERMODEEN,User Mode Access Enable Register"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "EPWMCFG,EPWM Configuration Register"
|
|
bitfld.long 0x00 4.--5. " EPWM[3]_SYNCIN ,SYNCIN to EPWM3 select" "Rampgen,FRC,External,External"
|
|
bitfld.long 0x00 2.--3. " [2] ,SYNCIN to EPWM2 select" "Rampgen,FRC,External,External"
|
|
bitfld.long 0x00 0.--1. " [1] ,SYNCIN to EPWM1 select" "Rampgen,FRC,External,External"
|
|
group.long 0x148++0x17
|
|
line.long 0x00 "DMMSWINT0,DMM SW Interrupt 0 Register"
|
|
line.long 0x04 "DMMSWINT1,DMM SW Interrupt 1 Register"
|
|
line.long 0x08 "DMMSWINTSEL0,DMM SW Interrupt Select 0 Register"
|
|
line.long 0x0C "DMMSWINTSEL1,DMM SW Interrupt Select 1 Register"
|
|
line.long 0x10 "CCCBWDEN,CCC BWD Enable Register"
|
|
bitfld.long 0x10 16. " ENABLECCBERRRSTN ,Enable CCCB error to generate WD rest" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " ENABLECCBERRNMI ,Enable CCCB error to generate NMI" "Disabled,Enabled"
|
|
line.long 0x14 "GPIOINTREDGESEL,GPIO Interrupt Edge Select Register"
|
|
bitfld.long 0x14 2. " GPIO[2]EDGESEL ,GPIO2 edge select" "Positive,Negative"
|
|
bitfld.long 0x14 1. " [1] ,GPIO1 edge select" "Positive,Negative"
|
|
bitfld.long 0x14 0. " [0] ,GPIO0 edge select" "Positive,Negative"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "PWMDMATRIGEN,PWM DMA Trigger Enable Register"
|
|
bitfld.long 0x00 0.--3. " PWMDMATRIGEN ,PWM DMA trigger enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x168++0x07
|
|
line.long 0x00 "JTAGTXDATA,JTAG TX Data Register"
|
|
line.long 0x04 "JTAGTXCONTROL,JTAG TX Control Register"
|
|
hexmask.long 0x04 1.--31. 1. " JTAGTXCONTROL ,JTAG TX control"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "JTAGRXDATA,JTAG RX Data Register"
|
|
group.long 0x178++0x0F
|
|
line.long 0x00 "JTAGTXRXACK,JTAG TX RX ACK Register"
|
|
bitfld.long 0x00 8. " JTAGRXDATAWR ,Indication from system security logic that JTAGRXDATA is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 0. " JTAGTXDATARD ,Indication from the system security logic that JTAGTXDATA has been accepted" "Not accepted,Accepted"
|
|
line.long 0x04 "JTAGRXCONTROL,JTAG RX Control Register"
|
|
hexmask.long 0x04 1.--31. 1. " JTAGTXCONTROL ,JTAG TX control"
|
|
line.long 0x08 "MSS2GEMSWIRQ,MSS 2 GEM SWIRQ Register"
|
|
bitfld.long 0x08 1. " MSS2GEMSWIRQ[2] ,Self clearing register bit to generate interrupt to DSP from MSS" "Not generated,Generated"
|
|
bitfld.long 0x08 0. " [1] ,Self clearing register bit to generate interrupt to DSP from MSS" "Not generated,Generated"
|
|
line.long 0x0C "CSETBFLUSH,C SETB FLUSH Register"
|
|
rbitfld.long 0x0C 10. " CSETBFULL ,Indicates that the ETB RAM has overflowed or wrapped around to address zero" "No overflow,Overflow"
|
|
rbitfld.long 0x0C 9. " CSETBACQ_OMPLETE ,Indicates that trace acquisition is complete by ETB" "Not completed,Completed"
|
|
rbitfld.long 0x0C 8. " CSETBFLUSHINACK ,Return acknowledgment to CSETBFLUSHIN" "Not returned,Returned"
|
|
bitfld.long 0x0C 0. " CSETBFLUSHIN ,External control used to assert the ATB signal AFVALIDS and drain any historical FIFO information on the bus" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DSS REG Registers"
|
|
base ad:0x50000400
|
|
width 22.
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "RTIEVENTCAPTURESEL,RTI1 Event Capture Select Register"
|
|
bitfld.long 0x00 16.--19. " EVT[1] ,Source of interrupt for Counter value capture for RTI1 Event 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " [0] ,Source of interrupt for Counter value capture for RTI1 Event 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CQCFG1,CQ0 Configuration 1 Register"
|
|
hexmask.long.word 0x00 22.--30. 0x40 " CQ2BASEADDR ,Address to be added to be internal address pointer for CQ2"
|
|
hexmask.long.word 0x00 13.--21. 0x20 " CQ1BASEADDR ,Address to be added to be internal address pointer for CQ1"
|
|
hexmask.long.word 0x00 4.--12. 0x10 " CQ0BASEADDR ,Address to be added to be internal address pointer for CQ0"
|
|
newline
|
|
bitfld.long 0x00 3. " CQ96BITPACKEN ,This is used to pack the CQ data into only the LSB 96 bits of each row of the CQ memory" "0,1"
|
|
newline
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x00 0.--1. " CQDATAWIDTH ,This is used to appropriately pack the valid CQ data bits in appropriate bits in the CQ memory" "Raw 16,Raw 16,Raw 12,Raw 14"
|
|
else
|
|
bitfld.long 0x00 0.--1. " CQDATAWIDTH ,This is used to appropriately pack the valid CQ data bits in appropriate bits in the CQ memory" "0,Raw 16,Raw 12,Raw 14"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TPCCPARSTATCFG,TPCCPARSTATCFG"
|
|
bitfld.long 0x00 10. " TPCCPARITYTSTEN ,Enable bit for the self test of the parity logic in TPCC" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TPCCPARITYEN ,Enable bit for the parity computation in TPCC" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TPCCPARITYCLR ,Clear bit for the parity error from TPCC" "Not cleared,Cleared"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " TPCCPARITYSTAT ,Parity address from TPCC"
|
|
group.long 0x104++0x17
|
|
line.long 0x00 "TPTC0WRMPUSTADD0,TPTC0 Write MPU Start Address 0 Register"
|
|
line.long 0x04 "TPTC0WRMPUSTADD1,TPTC0 Write MPU Start Address 1 Register"
|
|
line.long 0x08 "TPTC0WRMPUSTADD2,TPTC0 Write MPU Start Address 2 Register"
|
|
line.long 0x0C "TPTC0WRMPUSTADD3,TPTC0 Write MPU Start Address 3 Register"
|
|
line.long 0x10 "TPTC0WRMPUSTADD4,TPTC0 Write MPU Start Address 4 Register"
|
|
line.long 0x14 "TPTC0WRMPUSTADD5,TPTC0 Write MPU Start Address 5 Register"
|
|
group.long 0x124++0x17
|
|
line.long 0x00 "TPTC0WRMPUENDADD0,TPTC0 Write MPU End Address 0 Register"
|
|
line.long 0x04 "TPTC0WRMPUENDADD1,TPTC0 Write MPU End Address 1 Register"
|
|
line.long 0x08 "TPTC0WRMPUENDADD2,TPTC0 Write MPU End Address 2 Register"
|
|
line.long 0x0C "TPTC0WRMPUENDADD3,TPTC0 Write MPU End Address 3 Register"
|
|
line.long 0x10 "TPTC0WRMPUENDADD4,TPTC0 Write MPU End Address 4 Register"
|
|
line.long 0x14 "TPTC0WRMPUENDADD5,TPTC0 Write MPU End Address 5 Register"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "TPTC0WRMPUERRADD,TPTC0 Write MPU Error Address Register"
|
|
group.long 0x148++0x17
|
|
line.long 0x00 "TPTC0RDMPUSTADD0,TPTC0 Read MPU Start Address 0 Register"
|
|
line.long 0x04 "TPTC0RDMPUSTADD1,TPTC0 Read MPU Start Address 1 Register"
|
|
line.long 0x08 "TPTC0RDMPUSTADD2,TPTC0 Read MPU Start Address 2 Register"
|
|
line.long 0x0C "TPTC0RDMPUSTADD3,TPTC0 Read MPU Start Address 3 Register"
|
|
line.long 0x10 "TPTC0RDMPUSTADD4,TPTC0 Read MPU Start Address 4 Register"
|
|
line.long 0x14 "TPTC0RDMPUSTADD5,TPTC0 Read MPU Start Address 5 Register"
|
|
group.long 0x168++0x17
|
|
line.long 0x00 "TPTC0RDMPUENDADD0,TPTC0 Read MPU End Address 0 Register"
|
|
line.long 0x04 "TPTC0RDMPUENDADD1,TPTC0 Read MPU End Address 1 Register"
|
|
line.long 0x08 "TPTC0RDMPUENDADD2,TPTC0 Read MPU End Address 2 Register"
|
|
line.long 0x0C "TPTC0RDMPUENDADD3,TPTC0 Read MPU End Address 3 Register"
|
|
line.long 0x10 "TPTC0RDMPUENDADD4,TPTC0 Read MPU End Address 4 Register"
|
|
line.long 0x14 "TPTC0RDMPUENDADD5,TPTC0 Read MPU End Address 5 Register"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "TPTC0RDMPUERRADD,TPTC0 Read MPU Error Address Register"
|
|
group.long 0x18C++0x17
|
|
line.long 0x00 "TPTC1WRMPUSTADD0,TPTC1 Write MPU Start Address 0 Register"
|
|
line.long 0x04 "TPTC1WRMPUSTADD1,TPTC1 Write MPU Start Address 1 Register"
|
|
line.long 0x08 "TPTC1WRMPUSTADD2,TPTC1 Write MPU Start Address 2 Register"
|
|
line.long 0x0C "TPTC1WRMPUSTADD3,TPTC1 Write MPU Start Address 3 Register"
|
|
line.long 0x10 "TPTC1WRMPUSTADD4,TPTC1 Write MPU Start Address 4 Register"
|
|
line.long 0x14 "TPTC1WRMPUSTADD5,TPTC1 Write MPU Start Address 5 Register"
|
|
group.long 0x1AC++0x17
|
|
line.long 0x00 "TPTC1WRMPUENDADD0,TPTC1 Write MPU End Address 0 Register"
|
|
line.long 0x04 "TPTC1WRMPUENDADD1,TPTC1 Write MPU End Address 1 Register"
|
|
line.long 0x08 "TPTC1WRMPUENDADD2,TPTC1 Write MPU End Address 2 Register"
|
|
line.long 0x0C "TPTC1WRMPUENDADD3,TPTC1 Write MPU End Address 3 Register"
|
|
line.long 0x10 "TPTC1WRMPUENDADD4,TPTC1 Write MPU End Address 4 Register"
|
|
line.long 0x14 "TPTC1WRMPUENDADD5,TPTC1 Write MPU End Address 5 Register"
|
|
rgroup.long 0x1CC++0x03
|
|
line.long 0x00 "TPTC1WRMPUERRADD,TPTC1 Write MPU Error Address Register"
|
|
group.long 0x1D0++0x17
|
|
line.long 0x00 "TPTC1RDMPUSTADD0,TPTC1 Read MPU Start Address 0 Register"
|
|
line.long 0x04 "TPTC1RDMPUSTADD1,TPTC1 Read MPU Start Address 1 Register"
|
|
line.long 0x08 "TPTC1RDMPUSTADD2,TPTC1 Read MPU Start Address 2 Register"
|
|
line.long 0x0C "TPTC1RDMPUSTADD3,TPTC1 Read MPU Start Address 3 Register"
|
|
line.long 0x10 "TPTC1RDMPUSTADD4,TPTC1 Read MPU Start Address 4 Register"
|
|
line.long 0x14 "TPTC1RDMPUSTADD5,TPTC1 Read MPU Start Address 5 Register"
|
|
group.long 0x1F0++0x17
|
|
line.long 0x00 "TPTC1RDMPUENDADD0,TPTC1 Read MPU End Address 0 Register"
|
|
line.long 0x04 "TPTC1RDMPUENDADD1,TPTC1 Read MPU End Address 1 Register"
|
|
line.long 0x08 "TPTC1RDMPUENDADD2,TPTC1 Read MPU End Address 2 Register"
|
|
line.long 0x0C "TPTC1RDMPUENDADD3,TPTC1 Read MPU End Address 3 Register"
|
|
line.long 0x10 "TPTC1RDMPUENDADD4,TPTC1 Read MPU End Address 4 Register"
|
|
line.long 0x14 "TPTC1RDMPUENDADD5,TPTC1 Read MPU End Address 5 Register"
|
|
rgroup.long 0x210++0x03
|
|
line.long 0x00 "TPTC1RDMPUERRADD,TPTC1 Read MPU Error Address Register"
|
|
group.long 0x214++0x07
|
|
line.long 0x00 "TPTCMPUVALIDCFG,TPTC MPU Valid Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TPTC1RDMPURNGVLD ,Valid bit for each address range for the MPU in the read port of TPTC1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TPTC1WRMPURNGVLD ,Valid bit for each address range for the MPU in the read port of TPTC1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TPTC0RDMPURNGVLD ,Valid bit for each address range for the MPU in the read port of TPTC1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " TPTC0WRMPURNGVLD ,Valid bit for each address range for the MPU in the read port of TPTC1"
|
|
line.long 0x04 "TPTCMPUENCFG,TPTC MPU Enable Configuration Register"
|
|
bitfld.long 0x04 7. " TPTC1RDMPUERRCLR ,Clear flag for error from the MPU in the read port of TPTC1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " TPTC1WRMPUERRCLR ,Clear flag for error from the MPU in the write port of TPTC1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " TPTC0RDMPUERRCLR ,Clear flag for error from the MPU in the read port of TPTC0" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 4. " TPTC0WRMPUERRCLR ,Clear flag for error from the MPU in the write port of TPTC0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " TPTC1RDMPUEN ,Enable bit for the MPU in the read port of TPTC1" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " TPTC1WRMPUEN ,Enable bit for the MPU in the write port of TPTC1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " TPTC0RDMPUEN ,Enable bit for the MPU in the read port of TPTC0" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TPTC0WRMPUEN ,Enable bit for the MPU in the write port of TPTC0" "Disabled,Enabled"
|
|
group.long 0x21C++0x0F
|
|
line.long 0x00 "TESTPATTERNRX1ICFG,Test Pattern RX1 I Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TSTPATRX1IINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 0"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " TSTPATRX1IOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 0"
|
|
line.long 0x04 "TESTPATTERNRX2ICFG,TEST Pattern RX2 I Configuration Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " TSTPATRX2IINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 1"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " TSTPATRX2IOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 1"
|
|
line.long 0x08 "TESTPATTERNRX3ICFG,Test Pattern RX3 I Configuration Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " TSTPATRX3IINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 2"
|
|
hexmask.long.word 0x08 0.--15. 0x01 " TSTPATRX3IOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 2"
|
|
line.long 0x0C "TESTPATTERNRX4ICFG,Test Pattern RX4 I Configuration Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " TSTPATRX4IINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 3"
|
|
hexmask.long.word 0x0C 0.--15. 0x01 " TSTPATRX4IOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 3"
|
|
group.long 0x22C++0x0F
|
|
line.long 0x00 "TESTPATTERNRX1QCFG,Test Pattern RX1 Q Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TSTPATRX1QINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 0"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " TSTPATRX1QOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 0"
|
|
line.long 0x04 "TESTPATTERNRX2QCFG,Test Pattern RX2 Q Configuration Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " TSTPATRX2QINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 1"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " TSTPATRX2QOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 1"
|
|
line.long 0x08 "TESTPATTERNRX3QCFG,Test Pattern RX3 Q Configuration Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " TSTPATRX3QINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 2"
|
|
hexmask.long.word 0x08 0.--15. 0x01 " TSTPATRX3QOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 2"
|
|
line.long 0x0C "TESTPATTERNRX4QCFG,Test Pattern RX4 Q Configuration Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " TSTPATRX4QINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 3"
|
|
hexmask.long.word 0x0C 0.--15. 0x01 " TSTPATRX4QOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 3"
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "TESTPATTERNVLDCFG,Test Pattern VLD Configuration"
|
|
bitfld.long 0x00 8.--10. " TSTPATGENEN ,Enable for test pattern generator" "Disabled,,,,,,,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TSTPATVLDCNT ,Number of DSS Interconnect clocks 200 MHz between successive samples for the test pattern gen"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "DSSMISC,DSS Miscellaneous Register"
|
|
bitfld.long 0x00 6.--8. " FFTACCSLVEN ,Enable HW accelerator" "Disabled,,,,,,,Enabled"
|
|
endif
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "TPCC1PARSTATCFG,TPCC1 Parity Stat Configuration Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " NU ,Number"
|
|
bitfld.long 0x00 11. " TPCC1PARITYTSTEN ,Enable bit for the self test of the parity logic in TPCC" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TPCC1PARITYEN ,Enable bit for the parity computation in TPCC" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " TPCC1PARITYCLR ,Clear bit for the parity error from TPCC write 0x1 to clear the status" "Not cleared,Cleared"
|
|
hexmask.long.word 0x00 0.--8. 0x01 " TPCC1PARITYSTAT ,Parity address from TPCC"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "DMMSWINT1,DMM Switch Interrupt 1 Register"
|
|
bitfld.long 0x00 22. " DMMCQWREN ,CQ write enable from DMM" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " DMMCQPINPONSEL ,CQ ping pong select for HIL mode" "0,1"
|
|
bitfld.long 0x00 20. " DMMCPBPMMEMSEL ,Select signal for muxing between HW registers/memory for CPBPM data" "HW registers,Memory"
|
|
newline
|
|
bitfld.long 0x00 19. " DMMCPBPMWREN ,CPBPM write enable from DMM" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DMMCPBPMPINPONSEL ,CP BPM ping pong select for HIL mode" "0,1"
|
|
bitfld.long 0x00 17. " DMMADCBUFWREN ,ADC buffer write enable from DMM" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " DMMADCBUFPINPONSEL ,ADC Buffer ping pong select for HIL mode" "0,1"
|
|
group.long 0x270++0x13
|
|
line.long 0x00 "DSSINTRCFG,DSS Interrupt Configuration"
|
|
bitfld.long 0x00 7. " LGFRAMESTRTINTMUXSEL[1] ,Logical frame start select" "DFE,DMM global CFG bit"
|
|
bitfld.long 0x00 6. " [0] ,Interrupt select" "MUX,DMM SW interrupt 3"
|
|
bitfld.long 0x00 5. " PINPONINTMUXSEL[1] ,Ping pong switch select" "VIN/DFE,DMM global CFG bit"
|
|
newline
|
|
bitfld.long 0x00 4. " [0] ,Interrupt select" "MUX,DMM SW interrupt 2"
|
|
bitfld.long 0x00 3. " CHIRPAVLINTMUXSEL[1] ,Chirp available select" "VIN/DFE,DMM global CFG bit"
|
|
bitfld.long 0x00 2. " [0] ,Interrupt select" "MUX,DMM SW interrupt 1"
|
|
newline
|
|
bitfld.long 0x00 1. " FRAMESTRTINTMUXSEL[1] ,Frame start select" "VIN/DFE,DMM global CFG bit"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt select" "MUX,DMM SW interrupt 0"
|
|
line.long 0x04 "MPUMSTIDCFG1,MPU Master ID Configuration 1 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " MPUMSTID[3] ,MPU master ID 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,MPU master ID 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,MPU master ID 1"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,MPU maser ID 0"
|
|
line.long 0x08 "MPUMSTIDCFG2,MPU Master ID Configuration 2 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " MPUMSTID[7] ,MPU master ID 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,MPU master ID 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,MPU master ID 5"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,MPU master ID 4"
|
|
line.long 0x0C "MPUMSTIDCFG3,MPU Master ID Configuration 3 Register"
|
|
bitfld.long 0x0C 19. " MPUMSTIDEN ,Enable control for master ID based MPU" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " MPUERRCLR ,Error clear pulse for master ID based MPU" "Not cleared,Cleared"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " MPUERRMSTID ,Error status field"
|
|
newline
|
|
bitfld.long 0x0C 7. " MPUMSTIDVLD[7] ,Master ID 7 valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 6. " [6] ,Master ID 6 valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 5. " [5] ,Master ID 5 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x0C 4. " [4] ,Master ID 4 valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 3. " [3] ,Master ID 3 valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 2. " [2] ,Master ID 2 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x0C 1. " [1] ,Master ID 1 valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 0. " [0] ,Master ID 0 valid" "Not valid,Valid"
|
|
line.long 0x10 "HSRAM1ECCCFG,HSRAM1 ECC Configuration Register"
|
|
hexmask.long.word 0x10 15.--22. 1. " HSRAM1ECCREPAIREDBIT ,Bit position of the repaired bit in HSRAM1"
|
|
hexmask.long.word 0x10 4.--14. 0x10 " HSRAM1ECCFAULTADDRESS ,ECC fault address in HSRAM1"
|
|
bitfld.long 0x10 3. " HSRAM1ECCERRCLR ,Clear bit for ECC error indication in HSRAM1" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x10 2. " HSRAM1ECCEN ,Enable for ECC in HSRAM1" "Disabled,Enabled"
|
|
rbitfld.long 0x10 1. " HSRAM1ECCINITDONE ,Done status for ECC initialization for HSRAM1" "Not done,Done"
|
|
bitfld.long 0x10 0. " HSRAM1ECCINIT ,ECC initialization For HSRAM1" "Disabled,Enabled"
|
|
group.long 0x288++0x0B
|
|
line.long 0x00 "DATATRRAMECCCFG,DATATRRAM ECC Configuration Register"
|
|
hexmask.long.word 0x00 13.--20. 1. " DATATRRAMECCREPAIREDBIT ,Bit position of the repaired bit in DATATRRAM"
|
|
hexmask.long.word 0x00 4.--12. 0x10 " DATATRRAMECCFAULTADDRESS ,ECC fault address in DATATRRAM"
|
|
bitfld.long 0x00 3. " DATATRRAMECCERRCLR ,Clear bit for ECC error indication in DATATRRAM" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 2. " DATATRRAMECCEN ,Enable for ECC in DATATRRAM" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " DATATRRAMECCINITDONE ,Done status for ECC initialization for data transfer RAM" "Not done,Done"
|
|
bitfld.long 0x00 0. " DATATRRAMECCINIT ,ECC initialization for data transfer RAM" "Disabled,Enabled"
|
|
line.long 0x04 "ADCBUFPINGECCCFG,ADC Buffer Ping ECC Configuration Register"
|
|
hexmask.long.word 0x04 15.--22. 1. " ADCBUFPINGECCREPAIREDBIT ,Bit position of the repaired bit in ADC buffer ping memory"
|
|
hexmask.long.word 0x04 4.--14. 0x10 " ADCBUFPINGECCFAULTADDRESS ,ECC fault address in ADC buffer ping memory"
|
|
bitfld.long 0x04 3. " ADCBUFPINGECCERRCLR ,Clear bit for ECC error indication in ADC buffer ping memory" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " ADCBUFPINGECCEN ,Enable for ECC in ADC buffer ping memory" "Disabled,Enabled"
|
|
rbitfld.long 0x04 1. " ADCBUFPINGECCINITDONE ,Done status for ECC initialization for ADC buffer ping memory" "Not done,Done"
|
|
bitfld.long 0x04 0. " ADCBUFPINGECCINIT ,ECC initialization For ADC buffer ping memory" "Disabled,Enabled"
|
|
line.long 0x08 "ADCBUFPONGECCCFG,ADC Buffer Pong ECC Configuration Register"
|
|
hexmask.long.word 0x08 15.--22. 1. " ADCBUFPONGECCREPAIREDBIT ,Bit position of the repaired bit in ADC buffer pong memory"
|
|
hexmask.long.word 0x08 4.--14. 0x10 " ADCBUFPONGECCFAULTADDRESS ,ECC fault address in ADC buffer pong memory"
|
|
bitfld.long 0x08 3. " ADCBUFPONGECCERRCLR ,Clear bit for ECC error indication in ADC buffer pong memory" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 2. " ADCBUFPONGECCEN ,Enable for ECC in ADC buffer pong memory" "Disabled,Enabled"
|
|
rbitfld.long 0x08 1. " ADCBUFPONGECCINITDONE ,Done status for ECC initialization for ADC buffer pong memory" "Not done,Done"
|
|
bitfld.long 0x08 0. " ADCBUFPONGECCINIT ,ECC initialization for ADC buffer pong memory" "Disabled,Enabled"
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "UMAP0PARITYCFG1,UMAP0 Parity Configuration 1 Register"
|
|
hexmask.long.word 0x00 15.--25. 0x80 " UMAP0BANK23ADDOUT ,Address corresponding to the parity error in bank 2 or bank 3 of UMAP0"
|
|
hexmask.long.word 0x00 4.--14. 0x10 " UMAP0BANK01ADDOUT ,Address corresponding to the parity error in bank 0 or bank 1 of UMAP0"
|
|
rbitfld.long 0x00 3. " UMAP0BANK23ERROUT ,Parity error indication from either bank 2 or bank 3 of UMAP0" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 2. " UMAP0BANK01ERROUT ,Parity error indication from either bank 0 or bank 1 of UMAP0" "No error,Error"
|
|
bitfld.long 0x00 1. " UMAP0PARERRCLR ,Clear pulse for all the error status from UMAP0 parity check logic" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " UMAP0PAREN ,Enable for UMAP0 parity check logic" "Disabled,Enabled"
|
|
rgroup.long 0x2A0++0x07
|
|
line.long 0x00 "UMAP0PARITYCFG2,UMAP1 Parity Configuration 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " UMAP0BANK1BITOUT ,Bit level indication corresponding to parity error from UMAP0 bank 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " UMAP0BANK0BITOUT ,Bit level indication corresponding to parity error from UMAP0 bank 0"
|
|
line.long 0x04 "UMAP0PARITYCFG3,UMAP0PARITYCFG3"
|
|
hexmask.long.word 0x04 16.--31. 1. " UMAP0BANK3BITOUT ,Bit level indication corresponding to parity error from UMAP0 bank 3"
|
|
hexmask.long.word 0x04 0.--15. 1. " UMAP0BANK2BITOUT ,Bit level indication corresponding to parity error from UMAP0 bank 2"
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "UMAP1PARITYCFG1,UMAP1 Parity Configuration 1 Register"
|
|
hexmask.long.word 0x00 15.--25. 0x80 " UMAP1BANK23ADDOUT ,Address corresponding to the parity error in bank 2 or bank 3 of UMAP1"
|
|
hexmask.long.word 0x00 4.--14. 0x10 " UMAP1BANK01ADDOUT ,Address corresponding to the parity error in bank 0 or bank 1 of UMAP1"
|
|
rbitfld.long 0x00 3. " UMAP1BANK23ERROUT ,Parity error indication from either bank 2 or bank 3 of UMAP1" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 2. " UMAP1BANK01ERROUT ,Parity error indication from either bank 0 or bank 1 of UMAP1" "No error,Error"
|
|
bitfld.long 0x00 1. " UMAP1PARERRCLR ,Clear pulse for all the error status from UMAP1 parity check logic" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " UMAP1PAREN ,Enable for UMAP1 parity check logic" "Disabled,Enabled"
|
|
rgroup.long 0x2AC++0x07
|
|
line.long 0x00 "UMAP1PARITYCFG2,UMAP1 Parity Configuration 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " UMAP1BANK1BITOUT ,Bit level indication corresponding to parity error from UMAP1 bank 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " UMAP1BANK0BITOUT ,Bit level indication corresponding to parity error from UMAP1 bank 0"
|
|
line.long 0x04 "UMAP1PARITYCFG3,UMAP1 Parity Configuration 3 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " UMAP1BANK3BITOUT ,Bit level indication corresponding to parity error from UMAP1 bank 3"
|
|
hexmask.long.word 0x04 0.--15. 1. " UMAP1BANK2BITOUT ,Bit level indication corresponding to parity error from UMAP1 bank 2"
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "ESMGRP2MASKCFG,ESM Group2 Mask Configuration Register"
|
|
bitfld.long 0x00 31. " ESMGRP2MASK[31] ,Bit level mask for error signal 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " [30] ,Bit level mask for error signal 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " [29] ,Bit level mask for error signal 29" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Bit level mask for error signal 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " [27] ,Bit level mask for error signal 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " [26] ,Bit level mask for error signal 26" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Bit level mask for error signal 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " [24] ,Bit level mask for error signal 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " [23] ,Bit level mask for error signal 23" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Bit level mask for error signal 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " [21] ,Bit level mask for error signal 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " [20] ,Bit level mask for error signal 20" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Bit level mask for error signal 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " [18] ,Bit level mask for error signal 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " [17] ,Bit level mask for error signal 17" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Bit level mask for error signal 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " [15] ,Bit level mask for error signal 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " [14] ,Bit level mask for error signal 14" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Bit level mask for error signal 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " [12] ,Bit level mask for error signal 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " [11] ,Bit level mask for error signal 11" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Bit level mask for error signal 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " [9] ,Bit level mask for error signal 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Bit level mask for error signal 8" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Bit level mask for error signal 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " [6] ,Bit level mask for error signal 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Bit level mask for error signal 5" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Bit level mask for error signal 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " [3] ,Bit level mask for error signal 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,Bit level mask for error signal 2" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Bit level mask for error signal 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Bit level mask for error signal 0" "Not masked,Masked"
|
|
rgroup.long 0x2B8++0x0B
|
|
line.long 0x00 "L2MEMINITCFG1,L2 Memory Initialization Configuration 1 Register"
|
|
bitfld.long 0x00 31. " UMAP1BANK3PARINITDONE ,Initialization done status from UMAP1 bank 3 parity memory" "Not done,Done"
|
|
bitfld.long 0x00 30. " UMAP1BANK2PARINITDONE ,Initialization done status from UMAP1 bank 2 parity memory" "Not done,Done"
|
|
bitfld.long 0x00 29. " UMAP1BANK1PARINITDONE ,Initialization done status from UMAP1 bank 1 parity memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 28. " UMAP1BANK0PARINITDONE ,Initialization done status from UMAP1 bank 0 parity memory" "Not done,Done"
|
|
bitfld.long 0x00 27. " UMAP0BANK3PARINITDONE ,Initialization done status from UMAP0 bank 3 parity memory" "Not done,Done"
|
|
bitfld.long 0x00 26. " UMAP0BANK2PARINITDONE ,Initialization done status from UMAP0 bank 2 parity memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 25. " UMAP0BANK1PARINITDONE ,Initialization done status from UMAP0 bank 1 parity memory" "Not done,Done"
|
|
bitfld.long 0x00 24. " UMAP0BANK0PARINITDONE ,Initialization done status from UMAP0 bank 0 parity memory" "Not done,Done"
|
|
bitfld.long 0x00 23. " UMAP0BANK3DATAINITDONE ,Initialization done status from UMAP0 bank 3 data memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 22. " UMAP0BANK2DATAINITDONE ,Initialization done status from UMAP0 bank 2 data memory" "Not done,Done"
|
|
bitfld.long 0x00 21. " UMAP0BANK1DATAINITDONE ,Initialization done status from UMAP0 bank 1 data memory" "Not done,Done"
|
|
bitfld.long 0x00 20. " UMAP0BANK0DATAINITDONE ,Initialization done status from UMAP0 bank 0 data memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 19. " UMAP0BANK3DATAINITDONE ,Initialization done status from UMAP0 bank 3 data memory" "Not done,Done"
|
|
bitfld.long 0x00 18. " UMAP0BANK2DATAINITDONE ,Initialization done status from UMAP0 bank 2 data memory" "Not done,Done"
|
|
bitfld.long 0x00 17. " UMAP0BANK1DATAINITDONE ,Initialization done status from UMAP0 bank 1 data memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 16. " UMAP0BANK0DATAINITDONE ,Initialization done status from UMAP0 bank 0 data memory" "Not done,Done"
|
|
bitfld.long 0x00 15. " UMAP1BANK3PARINIT ,Initialization trigger for UMAP1 bank 3 parity memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 14. " UMAP1BANK2PARINIT ,Initialization trigger for UMAP1 bank 2 parity memory" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 13. " UMAP1BANK1PARINIT ,Initialization trigger for UMAP1 bank 1 parity memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 12. " UMAP1BANK0PARINIT ,Initialization trigger for UMAP1 bank 0 parity memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 11. " UMAP0BANK3PARINIT ,Initialization trigger for UMAP0 bank 3 parity memory" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 10. " UMAP0BANK2PARINIT ,Initialization trigger for UMAP0 bank 2 parity memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 9. " UMAP0BANK1PARINIT ,Initialization trigger for UMAP0 bank 1 parity memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 8. " UMAP0BANK0PARINIT ,Initialization trigger for UMAP0 bank 0 parity memory" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 7. " UMAP1BANK3DATAINIT ,Initialization trigger for UMAP1 bank 3 data memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 6. " UMAP1BANK2DATAINIT ,Initialization trigger for UMAP1 bank 2 data memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 5. " UMAP1BANK1DATAINIT ,Initialization trigger for UMAP1 bank 1 data memory" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 4. " UMAP1BANK0DATAINIT ,Initialization trigger for UMAP1 bank 0 data memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 3. " UMAP0BANK3DATAINIT ,Initialization trigger for UMAP0 bank 3 data memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 2. " UMAP0BANK2DATAINIT ,Initialization trigger for UMAP0 bank 2 data memory" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 1. " UMAP0BANK1DATAINIT ,Initialization trigger for UMAP0 bank 1 data memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " UMAP0BANK0DATAINIT ,Initialization trigger for UMAP0 bank 0 data memory" "Not triggered,Triggered"
|
|
line.long 0x04 "L2MEMINITCFG2,L2M Memory Initialization Configuration 2 Register"
|
|
bitfld.long 0x04 7. " UMAP1BANK1PARINITDONE ,Initialization done status for UMAP1 bank1 PRAM memory" "Not done,Done"
|
|
bitfld.long 0x04 6. " UMAP1BANK0PARINITDONE ,Initialization done status for UMAP1 bank 0 PRAM memory" "Not done,Done"
|
|
bitfld.long 0x04 5. " UMAP0BANK1PARINITDONE ,Initialization done status for UMAP0 bank 1 PRAM memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x04 4. " UMAP0BANK0PARINITDONE ,Initialization done status for UMAP0 bank 0 PRAM memory" "Not done,Done"
|
|
bitfld.long 0x04 3. " UMAP1BANK1PRAMINIT ,Initialization trigger for UMAP1 bank 1 PRAM memory" "Not triggered,Triggered"
|
|
bitfld.long 0x04 2. " UMAP1BANK0PRAMINIT ,Initialization trigger for UMAP1 bank0 PRAM memory" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x04 1. " UMAP0BANK1PRAMINIT ,Initialization trigger for UMAP0 bank 1 PRAM memory" "Not triggered,Triggered"
|
|
bitfld.long 0x04 0. " UMAP0BANK0PRAMINIT ,Initialization trigger for UMAP0 bank 0 PRAM memory" "Not triggered,Triggered"
|
|
line.long 0x08 "GEMRSTCAUSE,GEM Reset Cause Register"
|
|
bitfld.long 0x08 24. " GEMRSTCAUSECLR ,GEM reset cause clear" "Not cleared,Cleared"
|
|
hexmask.long.byte 0x08 16.--23. 1. " GEMPORCAUSE ,DSP POR reset bitwise indication"
|
|
hexmask.long.byte 0x08 8.--15. 1. " GEMGRSTCAUSE ,DSP reset bitwise indication"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. " GEMLRSTCAUSE ,DSP reset bitwise indication"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "GEMPWRSMCFG4,GEM Power SM Configuration 4 Register"
|
|
bitfld.long 0x00 18. " GEMEVENTMASK ,Mask bit for events going to DSP" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " PWRSMLRSTHALT ,Signal to halt DSP power cycle state machine before de-asserting LRST of DSP" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " PWRSMSLEEPTRIG ,Sleep mode trigger for DSP power down state machine" "Disabled,Enabled"
|
|
group.long 0x2D4++0x17
|
|
line.long 0x00 "PWRSMWAKEMASK0,Power SM Wake Mask 0 Register"
|
|
bitfld.long 0x00 31. " PWRSMWAKEMASK0[31] ,Bit level mask for wakeup source bit 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " [30] ,Bit level mask for wakeup source bit 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " [29] ,Bit level mask for wakeup source bit 29" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Bit level mask for wakeup source bit 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " [27] ,Bit level mask for wakeup source bit 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " [26] ,Bit level mask for wakeup source bit 26" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Bit level mask for wakeup source bit 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " [24] ,Bit level mask for wakeup source bit 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " [23] ,Bit level mask for wakeup source bit 23" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Bit level mask for wakeup source bit 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " [21] ,Bit level mask for wakeup source bit 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " [20] ,Bit level mask for wakeup source bit 20" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Bit level mask for wakeup source bit 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " [18] ,Bit level mask for wakeup source bit 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " [17] ,Bit level mask for wakeup source bit 17" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Bit level mask for wakeup source bit 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " [15] ,Bit level mask for wakeup source bit 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " [14] ,Bit level mask for wakeup source bit 14" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Bit level mask for wakeup source bit 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " [12] ,Bit level mask for wakeup source bit 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " [11] ,Bit level mask for wakeup source bit 11" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Bit level mask for wakeup source bit 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " [9] ,Bit level mask for wakeup source bit 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Bit level mask for wakeup source bit 8" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Bit level mask for wakeup source bit 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " [6] ,Bit level mask for wakeup source bit 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Bit level mask for wakeup source bit 5" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Bit level mask for wakeup source bit 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " [3] ,Bit level mask for wakeup source bit 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,Bit level mask for wakeup source bit 2" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Bit level mask for wakeup source bit 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Bit level mask for wakeup source bit 0" "Not masked,Masked"
|
|
line.long 0x04 "PWRSMWAKEMASK1,Power SM Wake Mask 1 Register"
|
|
bitfld.long 0x04 31. " PWRSMWAKEMASK1[63] ,Bit level mask for wakeup source bit 63" "Not masked,Masked"
|
|
bitfld.long 0x04 30. " [62] ,Bit level mask for wakeup source bit 62" "Not masked,Masked"
|
|
bitfld.long 0x04 29. " [61] ,Bit level mask for wakeup source bit 61" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 28. " [60] ,Bit level mask for wakeup source bit 60" "Not masked,Masked"
|
|
bitfld.long 0x04 27. " [59] ,Bit level mask for wakeup source bit 59" "Not masked,Masked"
|
|
bitfld.long 0x04 26. " [58] ,Bit level mask for wakeup source bit 58" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 25. " [57] ,Bit level mask for wakeup source bit 57" "Not masked,Masked"
|
|
bitfld.long 0x04 24. " [56] ,Bit level mask for wakeup source bit 56" "Not masked,Masked"
|
|
bitfld.long 0x04 23. " [55] ,Bit level mask for wakeup source bit 55" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 22. " [54] ,Bit level mask for wakeup source bit 54" "Not masked,Masked"
|
|
bitfld.long 0x04 21. " [53] ,Bit level mask for wakeup source bit 53" "Not masked,Masked"
|
|
bitfld.long 0x04 20. " [52] ,Bit level mask for wakeup source bit 52" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 19. " [51] ,Bit level mask for wakeup source bit 51" "Not masked,Masked"
|
|
bitfld.long 0x04 18. " [50] ,Bit level mask for wakeup source bit 50" "Not masked,Masked"
|
|
bitfld.long 0x04 17. " [49] ,Bit level mask for wakeup source bit 49" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 16. " [48] ,Bit level mask for wakeup source bit 48" "Not masked,Masked"
|
|
bitfld.long 0x04 15. " [47] ,Bit level mask for wakeup source bit 47" "Not masked,Masked"
|
|
bitfld.long 0x04 14. " [46] ,Bit level mask for wakeup source bit 46" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 13. " [45] ,Bit level mask for wakeup source bit 45" "Not masked,Masked"
|
|
bitfld.long 0x04 12. " [44] ,Bit level mask for wakeup source bit 44" "Not masked,Masked"
|
|
bitfld.long 0x04 11. " [43] ,Bit level mask for wakeup source bit 43" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 10. " [42] ,Bit level mask for wakeup source bit 42" "Not masked,Masked"
|
|
bitfld.long 0x04 9. " [41] ,Bit level mask for wakeup source bit 41" "Not masked,Masked"
|
|
bitfld.long 0x04 8. " [40] ,Bit level mask for wakeup source bit 40" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 7. " [39] ,Bit level mask for wakeup source bit 39" "Not masked,Masked"
|
|
bitfld.long 0x04 6. " [38] ,Bit level mask for wakeup source bit 38" "Not masked,Masked"
|
|
bitfld.long 0x04 5. " [37] ,Bit level mask for wakeup source bit 37" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 4. " [36] ,Bit level mask for wakeup source bit 36" "Not masked,Masked"
|
|
bitfld.long 0x04 3. " [35] ,Bit level mask for wakeup source bit 35" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " [34] ,Bit level mask for wakeup source bit 34" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,Bit level mask for wakeup source bit 33" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " [32] ,Bit level mask for wakeup source bit 32" "Not masked,Masked"
|
|
line.long 0x08 "PWRSMWAKEMASK2,Power SM Wake Mask 2 Register"
|
|
bitfld.long 0x08 31. " PWRSMWAKEMASK2[95] ,Bit level mask for wakeup source bit 95" "Not masked,Masked"
|
|
bitfld.long 0x08 30. " [94] ,Bit level mask for wakeup source bit 94" "Not masked,Masked"
|
|
bitfld.long 0x08 29. " [93] ,Bit level mask for wakeup source bit 93" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 28. " [92] ,Bit level mask for wakeup source bit 92" "Not masked,Masked"
|
|
bitfld.long 0x08 27. " [91] ,Bit level mask for wakeup source bit 91" "Not masked,Masked"
|
|
bitfld.long 0x08 26. " [90] ,Bit level mask for wakeup source bit 90" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 25. " [89] ,Bit level mask for wakeup source bit 89" "Not masked,Masked"
|
|
bitfld.long 0x08 24. " [88] ,Bit level mask for wakeup source bit 88" "Not masked,Masked"
|
|
bitfld.long 0x08 23. " [87] ,Bit level mask for wakeup source bit 87" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 22. " [86] ,Bit level mask for wakeup source bit 86" "Not masked,Masked"
|
|
bitfld.long 0x08 21. " [85] ,Bit level mask for wakeup source bit 85" "Not masked,Masked"
|
|
bitfld.long 0x08 20. " [84] ,Bit level mask for wakeup source bit 84" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 19. " [83] ,Bit level mask for wakeup source bit 83" "Not masked,Masked"
|
|
bitfld.long 0x08 18. " [82] ,Bit level mask for wakeup source bit 82" "Not masked,Masked"
|
|
bitfld.long 0x08 17. " [81] ,Bit level mask for wakeup source bit 81" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 16. " [80] ,Bit level mask for wakeup source bit 80" "Not masked,Masked"
|
|
bitfld.long 0x08 15. " [79] ,Bit level mask for wakeup source bit 79" "Not masked,Masked"
|
|
bitfld.long 0x08 14. " [78] ,Bit level mask for wakeup source bit 78" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 13. " [77] ,Bit level mask for wakeup source bit 77" "Not masked,Masked"
|
|
bitfld.long 0x08 12. " [76] ,Bit level mask for wakeup source bit 76" "Not masked,Masked"
|
|
bitfld.long 0x08 11. " [75] ,Bit level mask for wakeup source bit 75" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 10. " [74] ,Bit level mask for wakeup source bit 74" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " [73] ,Bit level mask for wakeup source bit 73" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " [72] ,Bit level mask for wakeup source bit 72" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 7. " [71] ,Bit level mask for wakeup source bit 71" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " [70] ,Bit level mask for wakeup source bit 70" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " [69] ,Bit level mask for wakeup source bit 69" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 4. " [68] ,Bit level mask for wakeup source bit 68" "Not masked,Masked"
|
|
bitfld.long 0x08 3. " [67] ,Bit level mask for wakeup source bit 67" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " [66] ,Bit level mask for wakeup source bit 66" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 1. " [65] ,Bit level mask for wakeup source bit 65" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " [64] ,Bit level mask for wakeup source bit 64" "Not masked,Masked"
|
|
line.long 0x0C "PWRSMMISEVTMASK0,Power SM Missed Event Mask 0 Register"
|
|
bitfld.long 0x0C 31. " PWRSMMISEVTMASK0[31] ,Bit level mask for missed event 31" "Not masked,Masked"
|
|
bitfld.long 0x0C 30. " [30] ,Bit level mask for missed event 30" "Not masked,Masked"
|
|
bitfld.long 0x0C 29. " [29] ,Bit level mask for missed event 29" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 28. " [28] ,Bit level mask for missed event 28" "Not masked,Masked"
|
|
bitfld.long 0x0C 27. " [27] ,Bit level mask for missed event 27" "Not masked,Masked"
|
|
bitfld.long 0x0C 26. " [26] ,Bit level mask for missed event 26" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 25. " [25] ,Bit level mask for missed event 25" "Not masked,Masked"
|
|
bitfld.long 0x0C 24. " [24] ,Bit level mask for missed event 24" "Not masked,Masked"
|
|
bitfld.long 0x0C 23. " [23] ,Bit level mask for missed event 23" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 22. " [22] ,Bit level mask for missed event 22" "Not masked,Masked"
|
|
bitfld.long 0x0C 21. " [21] ,Bit level mask for missed event 21" "Not masked,Masked"
|
|
bitfld.long 0x0C 20. " [20] ,Bit level mask for missed event 20" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 19. " [19] ,Bit level mask for missed event 19" "Not masked,Masked"
|
|
bitfld.long 0x0C 18. " [18] ,Bit level mask for missed event 18" "Not masked,Masked"
|
|
bitfld.long 0x0C 17. " [17] ,Bit level mask for missed event 17" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 16. " [16] ,Bit level mask for missed event 16" "Not masked,Masked"
|
|
bitfld.long 0x0C 15. " [15] ,Bit level mask for missed event 15" "Not masked,Masked"
|
|
bitfld.long 0x0C 14. " [14] ,Bit level mask for missed event 14" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 13. " [13] ,Bit level mask for missed event 13" "Not masked,Masked"
|
|
bitfld.long 0x0C 12. " [12] ,Bit level mask for missed event 12" "Not masked,Masked"
|
|
bitfld.long 0x0C 11. " [11] ,Bit level mask for missed event 11" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 10. " [10] ,Bit level mask for missed event 10" "Not masked,Masked"
|
|
bitfld.long 0x0C 9. " [9] ,Bit level mask for missed event 9" "Not masked,Masked"
|
|
bitfld.long 0x0C 8. " [8] ,Bit level mask for missed event 8" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 7. " [7] ,Bit level mask for missed event 7" "Not masked,Masked"
|
|
bitfld.long 0x0C 6. " [6] ,Bit level mask for missed event 6" "Not masked,Masked"
|
|
bitfld.long 0x0C 5. " [5] ,Bit level mask for missed event 5" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 4. " [4] ,Bit level mask for missed event 4" "Not masked,Masked"
|
|
bitfld.long 0x0C 3. " [3] ,Bit level mask for missed event 3" "Not masked,Masked"
|
|
bitfld.long 0x0C 2. " [2] ,Bit level mask for missed event 2" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 1. " [1] ,Bit level mask for missed event 1" "Not masked,Masked"
|
|
bitfld.long 0x0C 0. " [0] ,Bit level mask for missed event 0" "Not masked,Masked"
|
|
line.long 0x10 "PWRSMMISEVTMASK1,Power SM Missed Event Mask 1 Register"
|
|
bitfld.long 0x10 31. " PWRSMMISEVTMASK1[63] ,Bit level mask for missed event 63" "Not masked,Masked"
|
|
bitfld.long 0x10 30. " [62] ,Bit level mask for missed event 62" "Not masked,Masked"
|
|
bitfld.long 0x10 29. " [61] ,Bit level mask for missed event 61" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 28. " [60] ,Bit level mask for missed event 60" "Not masked,Masked"
|
|
bitfld.long 0x10 27. " [59] ,Bit level mask for missed event 59" "Not masked,Masked"
|
|
bitfld.long 0x10 26. " [58] ,Bit level mask for missed event 58" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 25. " [57] ,Bit level mask for missed event 57" "Not masked,Masked"
|
|
bitfld.long 0x10 24. " [56] ,Bit level mask for missed event 56" "Not masked,Masked"
|
|
bitfld.long 0x10 23. " [55] ,Bit level mask for missed event 55" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 22. " [54] ,Bit level mask for missed event 54" "Not masked,Masked"
|
|
bitfld.long 0x10 21. " [53] ,Bit level mask for missed event 53" "Not masked,Masked"
|
|
bitfld.long 0x10 20. " [52] ,Bit level mask for missed event 52" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 19. " [51] ,Bit level mask for missed event 51" "Not masked,Masked"
|
|
bitfld.long 0x10 18. " [50] ,Bit level mask for missed event 50" "Not masked,Masked"
|
|
bitfld.long 0x10 17. " [49] ,Bit level mask for missed event 49" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 16. " [48] ,Bit level mask for missed event 48" "Not masked,Masked"
|
|
bitfld.long 0x10 15. " [47] ,Bit level mask for missed event 47" "Not masked,Masked"
|
|
bitfld.long 0x10 14. " [46] ,Bit level mask for missed event 46" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 13. " [45] ,Bit level mask for missed event 45" "Not masked,Masked"
|
|
bitfld.long 0x10 12. " [44] ,Bit level mask for missed event 44" "Not masked,Masked"
|
|
bitfld.long 0x10 11. " [43] ,Bit level mask for missed event 43" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 10. " [42] ,Bit level mask for missed event 42" "Not masked,Masked"
|
|
bitfld.long 0x10 9. " [41] ,Bit level mask for missed event 41" "Not masked,Masked"
|
|
bitfld.long 0x10 8. " [40] ,Bit level mask for missed event 40" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 7. " [39] ,Bit level mask for missed event 39" "Not masked,Masked"
|
|
bitfld.long 0x10 6. " [38] ,Bit level mask for missed event 38" "Not masked,Masked"
|
|
bitfld.long 0x10 5. " [37] ,Bit level mask for missed event 37" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 4. " [36] ,Bit level mask for missed event 36" "Not masked,Masked"
|
|
bitfld.long 0x10 3. " [35] ,Bit level mask for missed event 35" "Not masked,Masked"
|
|
bitfld.long 0x10 2. " [34] ,Bit level mask for missed event 34" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 1. " [33] ,Bit level mask for missed event 33" "Not masked,Masked"
|
|
bitfld.long 0x10 0. " [32] ,Bit level mask for missed event 32" "Not masked,Masked"
|
|
line.long 0x14 "PWRSMMISEVTMASK2,Power SM Missed Event Mask 2 Register"
|
|
bitfld.long 0x14 31. " PWRSMMISEVTMASK2[95] ,Bit level mask for missed event 95" "Not masked,Masked"
|
|
bitfld.long 0x14 30. " [94] ,Bit level mask for missed event 94" "Not masked,Masked"
|
|
bitfld.long 0x14 29. " [93] ,Bit level mask for missed event 93" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 28. " [92] ,Bit level mask for missed event 92" "Not masked,Masked"
|
|
bitfld.long 0x14 27. " [91] ,Bit level mask for missed event 91" "Not masked,Masked"
|
|
bitfld.long 0x14 26. " [90] ,Bit level mask for missed event 90" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 25. " [89] ,Bit level mask for missed event 89" "Not masked,Masked"
|
|
bitfld.long 0x14 24. " [88] ,Bit level mask for missed event 88" "Not masked,Masked"
|
|
bitfld.long 0x14 23. " [87] ,Bit level mask for missed event 87" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 22. " [86] ,Bit level mask for missed event 86" "Not masked,Masked"
|
|
bitfld.long 0x14 21. " [85] ,Bit level mask for missed event 85" "Not masked,Masked"
|
|
bitfld.long 0x14 20. " [84] ,Bit level mask for missed event 84" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 19. " [83] ,Bit level mask for missed event 83" "Not masked,Masked"
|
|
bitfld.long 0x14 18. " [82] ,Bit level mask for missed event 82" "Not masked,Masked"
|
|
bitfld.long 0x14 17. " [81] ,Bit level mask for missed event 81" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 16. " [80] ,Bit level mask for missed event 80" "Not masked,Masked"
|
|
bitfld.long 0x14 15. " [79] ,Bit level mask for missed event 79" "Not masked,Masked"
|
|
bitfld.long 0x14 14. " [78] ,Bit level mask for missed event 78" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 13. " [77] ,Bit level mask for missed event 77" "Not masked,Masked"
|
|
bitfld.long 0x14 12. " [76] ,Bit level mask for missed event 76" "Not masked,Masked"
|
|
bitfld.long 0x14 11. " [75] ,Bit level mask for missed event 75" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 10. " [74] ,Bit level mask for missed event 74" "Not masked,Masked"
|
|
bitfld.long 0x14 9. " [73] ,Bit level mask for missed event 73" "Not masked,Masked"
|
|
bitfld.long 0x14 8. " [72] ,Bit level mask for missed event 72" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 7. " [71] ,Bit level mask for missed event 71" "Not masked,Masked"
|
|
bitfld.long 0x14 6. " [70] ,Bit level mask for missed event 70" "Not masked,Masked"
|
|
bitfld.long 0x14 5. " [69] ,Bit level mask for missed event 69" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 4. " [68] ,Bit level mask for missed event 68" "Not masked,Masked"
|
|
bitfld.long 0x14 3. " [67] ,Bit level mask for missed event 67" "Not masked,Masked"
|
|
bitfld.long 0x14 2. " [66] ,Bit level mask for missed event 66" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 1. " [65] ,Bit level mask for missed event 65" "Not masked,Masked"
|
|
bitfld.long 0x14 0. " [64] ,Bit level mask for missed event 64" "Not masked,Masked"
|
|
rgroup.long 0x2EC++0x07
|
|
line.long 0x00 "PWRSMWAKESRCSTAT0,Power SM Wake Source Status 0 Register"
|
|
bitfld.long 0x00 31. " PWRSMWAKESRCSTAT0[31] ,Wakeup source status bit 31" "0,1"
|
|
bitfld.long 0x00 30. " [30] ,Wakeup source status bit 30" "0,1"
|
|
bitfld.long 0x00 29. " [29] ,Wakeup source status bit 29" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Wakeup source status bit 28" "0,1"
|
|
bitfld.long 0x00 27. " [27] ,Wakeup source status bit 27" "0,1"
|
|
bitfld.long 0x00 26. " [26] ,Wakeup source status bit 26" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Wakeup source status bit 25" "0,1"
|
|
bitfld.long 0x00 24. " [24] ,Wakeup source status bit 24" "0,1"
|
|
bitfld.long 0x00 23. " [23] ,Wakeup source status bit 23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Wakeup source status bit 22" "0,1"
|
|
bitfld.long 0x00 21. " [21] ,Wakeup source status bit 21" "0,1"
|
|
bitfld.long 0x00 20. " [20] ,Wakeup source status bit 20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Wakeup source status bit 19" "0,1"
|
|
bitfld.long 0x00 18. " [18] ,Wakeup source status bit 18" "0,1"
|
|
bitfld.long 0x00 17. " [17] ,Wakeup source status bit 17" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Wakeup source status bit 16" "0,1"
|
|
bitfld.long 0x00 15. " [15] ,Wakeup source status bit 15" "0,1"
|
|
bitfld.long 0x00 14. " [14] ,Wakeup source status bit 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Wakeup source status bit 13" "0,1"
|
|
bitfld.long 0x00 12. " [12] ,Wakeup source status bit 12" "0,1"
|
|
bitfld.long 0x00 11. " [11] ,Wakeup source status bit 11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Wakeup source status bit 10" "0,1"
|
|
bitfld.long 0x00 9. " [9] ,Wakeup source status bit 9" "0,1"
|
|
bitfld.long 0x00 8. " [8] ,Wakeup source status bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Wakeup source status bit 7" "0,1"
|
|
bitfld.long 0x00 6. " [6] ,Wakeup source status bit 6" "0,1"
|
|
bitfld.long 0x00 5. " [5] ,Wakeup source status bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Wakeup source status bit 4" "0,1"
|
|
bitfld.long 0x00 3. " [3] ,Wakeup source status bit 3" "0,1"
|
|
bitfld.long 0x00 2. " [2] ,Wakeup source status bit 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Wakeup source status bit 1" "0,1"
|
|
bitfld.long 0x00 0. " [0] ,Wakeup source status bit 0" "0,1"
|
|
line.long 0x04 "PWRSMWAKESRCSTAT1,Power SM Wake Source Status 1 Register"
|
|
bitfld.long 0x04 31. " PWRSMWAKESRCSTAT1[63] ,Wakeup source status bit 63" "0,1"
|
|
bitfld.long 0x04 30. " [62] ,Wakeup source status bit 62" "0,1"
|
|
bitfld.long 0x04 29. " [61] ,Wakeup source status bit 61" "0,1"
|
|
newline
|
|
bitfld.long 0x04 28. " [60] ,Wakeup source status bit 60" "0,1"
|
|
bitfld.long 0x04 27. " [59] ,Wakeup source status bit 59" "0,1"
|
|
bitfld.long 0x04 26. " [58] ,Wakeup source status bit 58" "0,1"
|
|
newline
|
|
bitfld.long 0x04 25. " [57] ,Wakeup source status bit 57" "0,1"
|
|
bitfld.long 0x04 24. " [56] ,Wakeup source status bit 56" "0,1"
|
|
bitfld.long 0x04 23. " [55] ,Wakeup source status bit 55" "0,1"
|
|
newline
|
|
bitfld.long 0x04 22. " [54] ,Wakeup source status bit 54" "0,1"
|
|
bitfld.long 0x04 21. " [53] ,Wakeup source status bit 53" "0,1"
|
|
bitfld.long 0x04 20. " [52] ,Wakeup source status bit 52" "0,1"
|
|
newline
|
|
bitfld.long 0x04 19. " [51] ,Wakeup source status bit 51" "0,1"
|
|
bitfld.long 0x04 18. " [50] ,Wakeup source status bit 50" "0,1"
|
|
bitfld.long 0x04 17. " [49] ,Wakeup source status bit 49" "0,1"
|
|
newline
|
|
bitfld.long 0x04 16. " [48] ,Wakeup source status bit 48" "0,1"
|
|
bitfld.long 0x04 15. " [47] ,Wakeup source status bit 47" "0,1"
|
|
bitfld.long 0x04 14. " [46] ,Wakeup source status bit 46" "0,1"
|
|
newline
|
|
bitfld.long 0x04 13. " [45] ,Wakeup source status bit 45" "0,1"
|
|
bitfld.long 0x04 12. " [44] ,Wakeup source status bit 44" "0,1"
|
|
bitfld.long 0x04 11. " [43] ,Wakeup source status bit 43" "0,1"
|
|
newline
|
|
bitfld.long 0x04 10. " [42] ,Wakeup source status bit 42" "0,1"
|
|
bitfld.long 0x04 9. " [41] ,Wakeup source status bit 41" "0,1"
|
|
bitfld.long 0x04 8. " [40] ,Wakeup source status bit 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. " [39] ,Wakeup source status bit 39" "0,1"
|
|
bitfld.long 0x04 6. " [38] ,Wakeup source status bit 38" "0,1"
|
|
bitfld.long 0x04 5. " [37] ,Wakeup source status bit 37" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. " [36] ,Wakeup source status bit 36" "0,1"
|
|
bitfld.long 0x04 3. " [35] ,Wakeup source status bit 35" "0,1"
|
|
bitfld.long 0x04 2. " [34] ,Wakeup source status bit 34" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,Wakeup source status bit 33" "0,1"
|
|
bitfld.long 0x04 0. " [32] ,Wakeup source status bit 32" "0,1"
|
|
rgroup.long 0x320++0x0F
|
|
line.long 0x00 "PWRSMWAKESRCSTAT2,Power SM Wake Source Status 2 Register"
|
|
bitfld.long 0x00 31. " PWRSMWAKESRCSTAT2[95] ,Wakeup source status bit 95" "0,1"
|
|
bitfld.long 0x00 30. " [94] ,Wakeup source status bit 94" "0,1"
|
|
bitfld.long 0x00 29. " [93] ,Wakeup source status bit 93" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. " [92] ,Wakeup source status bit 92" "0,1"
|
|
bitfld.long 0x00 27. " [91] ,Wakeup source status bit 91" "0,1"
|
|
bitfld.long 0x00 26. " [90] ,Wakeup source status bit 90" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " [89] ,Wakeup source status bit 89" "0,1"
|
|
bitfld.long 0x00 24. " [88] ,Wakeup source status bit 88" "0,1"
|
|
bitfld.long 0x00 23. " [87] ,Wakeup source status bit 87" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. " [86] ,Wakeup source status bit 86" "0,1"
|
|
bitfld.long 0x00 21. " [85] ,Wakeup source status bit 85" "0,1"
|
|
bitfld.long 0x00 20. " [84] ,Wakeup source status bit 84" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " [83] ,Wakeup source status bit 83" "0,1"
|
|
bitfld.long 0x00 18. " [82] ,Wakeup source status bit 82" "0,1"
|
|
bitfld.long 0x00 17. " [81] ,Wakeup source status bit 81" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " [80] ,Wakeup source status bit 80" "0,1"
|
|
bitfld.long 0x00 15. " [79] ,Wakeup source status bit 79" "0,1"
|
|
bitfld.long 0x00 14. " [78] ,Wakeup source status bit 78" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. " [77] ,Wakeup source status bit 77" "0,1"
|
|
bitfld.long 0x00 12. " [76] ,Wakeup source status bit 76" "0,1"
|
|
bitfld.long 0x00 11. " [75] ,Wakeup source status bit 75" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. " [74] ,Wakeup source status bit 74" "0,1"
|
|
bitfld.long 0x00 9. " [73] ,Wakeup source status bit 73" "0,1"
|
|
bitfld.long 0x00 8. " [72] ,Wakeup source status bit 72" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " [71] ,Wakeup source status bit 71" "0,1"
|
|
bitfld.long 0x00 6. " [70] ,Wakeup source status bit 70" "0,1"
|
|
bitfld.long 0x00 5. " [69] ,Wakeup source status bit 69" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " [68] ,Wakeup source status bit 68" "0,1"
|
|
bitfld.long 0x00 3. " [67] ,Wakeup source status bit 67" "0,1"
|
|
bitfld.long 0x00 2. " [66] ,Wakeup source status bit 66" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " [65] ,Wakeup source status bit 65" "0,1"
|
|
bitfld.long 0x00 0. " [64] ,Wakeup source status bit 64" "0,1"
|
|
line.long 0x04 "PWRSMEVNTMONSTAT0,Power SM Event Monitor Status 0 Register"
|
|
bitfld.long 0x04 31. " PWRSMEVNTMONSTAT0[31] ,Missed event monitor status bit 31" "Not missed,Missed"
|
|
bitfld.long 0x04 30. " [30] ,Missed event monitor status bit 30" "Not missed,Missed"
|
|
bitfld.long 0x04 29. " [29] ,Missed event monitor status bit 29" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 28. " [28] ,Missed event monitor status bit 28" "Not missed,Missed"
|
|
bitfld.long 0x04 27. " [27] ,Missed event monitor status bit 27" "Not missed,Missed"
|
|
bitfld.long 0x04 26. " [26] ,Missed event monitor status bit 26" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,Missed event monitor status bit 25" "Not missed,Missed"
|
|
bitfld.long 0x04 24. " [24] ,Missed event monitor status bit 24" "Not missed,Missed"
|
|
bitfld.long 0x04 23. " [23] ,Missed event monitor status bit 23" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,Missed event monitor status bit 22" "Not missed,Missed"
|
|
bitfld.long 0x04 21. " [21] ,Missed event monitor status bit 21" "Not missed,Missed"
|
|
bitfld.long 0x04 20. " [20] ,Missed event monitor status bit 20" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Missed event monitor status bit 19" "Not missed,Missed"
|
|
bitfld.long 0x04 18. " [18] ,Missed event monitor status bit 18" "Not missed,Missed"
|
|
bitfld.long 0x04 17. " [17] ,Missed event monitor status bit 17" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,Missed event monitor status bit 16" "Not missed,Missed"
|
|
bitfld.long 0x04 15. " [15] ,Missed event monitor status bit 15" "Not missed,Missed"
|
|
bitfld.long 0x04 14. " [14] ,Missed event monitor status bit 14" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,Missed event monitor status bit 13" "Not missed,Missed"
|
|
bitfld.long 0x04 12. " [12] ,Missed event monitor status bit 12" "Not missed,Missed"
|
|
bitfld.long 0x04 11. " [11] ,Missed event monitor status bit 11" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 10. " [10] ,Missed event monitor status bit 10" "Not missed,Missed"
|
|
bitfld.long 0x04 9. " [9] ,Missed event monitor status bit 9" "Not missed,Missed"
|
|
bitfld.long 0x04 8. " [8] ,Missed event monitor status bit 8" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Missed event monitor status bit 7" "Not missed,Missed"
|
|
bitfld.long 0x04 6. " [6] ,Missed event monitor status bit 6" "Not missed,Missed"
|
|
bitfld.long 0x04 5. " [5] ,Missed event monitor status bit 5" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Missed event monitor status bit 4" "Not missed,Missed"
|
|
bitfld.long 0x04 3. " [3] ,Missed event monitor status bit 3" "Not missed,Missed"
|
|
bitfld.long 0x04 2. " [2] ,Missed event monitor status bit 2" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Missed event monitor status bit 1" "Not missed,Missed"
|
|
bitfld.long 0x04 0. " [0] ,Missed event monitor status bit 0" "Not missed,Missed"
|
|
line.long 0x08 "PWRSMEVNTMONSTAT1,Power SM Event Monitor Status 1 Register"
|
|
bitfld.long 0x08 31. " PWRSMEVNTMONSTAT1[63] ,Missed event monitor status bit 63" "Not missed,Missed"
|
|
bitfld.long 0x08 30. " [62] ,Missed event monitor status bit 62" "Not missed,Missed"
|
|
bitfld.long 0x08 29. " [61] ,Missed event monitor status bit 61" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 28. " [60] ,Missed event monitor status bit 60" "Not missed,Missed"
|
|
bitfld.long 0x08 27. " [59] ,Missed event monitor status bit 59" "Not missed,Missed"
|
|
bitfld.long 0x08 26. " [58] ,Missed event monitor status bit 58" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 25. " [57] ,Missed event monitor status bit 57" "Not missed,Missed"
|
|
bitfld.long 0x08 24. " [56] ,Missed event monitor status bit 56" "Not missed,Missed"
|
|
bitfld.long 0x08 23. " [55] ,Missed event monitor status bit 55" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 22. " [54] ,Missed event monitor status bit 54" "Not missed,Missed"
|
|
bitfld.long 0x08 21. " [53] ,Missed event monitor status bit 53" "Not missed,Missed"
|
|
bitfld.long 0x08 20. " [52] ,Missed event monitor status bit 52" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 19. " [51] ,Missed event monitor status bit 51" "Not missed,Missed"
|
|
bitfld.long 0x08 18. " [50] ,Missed event monitor status bit 50" "Not missed,Missed"
|
|
bitfld.long 0x08 17. " [49] ,Missed event monitor status bit 49" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 16. " [48] ,Missed event monitor status bit 48" "Not missed,Missed"
|
|
bitfld.long 0x08 15. " [47] ,Missed event monitor status bit 47" "Not missed,Missed"
|
|
bitfld.long 0x08 14. " [46] ,Missed event monitor status bit 46" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 13. " [45] ,Missed event monitor status bit 45" "Not missed,Missed"
|
|
bitfld.long 0x08 12. " [44] ,Missed event monitor status bit 44" "Not missed,Missed"
|
|
bitfld.long 0x08 11. " [43] ,Missed event monitor status bit 43" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 10. " [42] ,Missed event monitor status bit 42" "Not missed,Missed"
|
|
bitfld.long 0x08 9. " [41] ,Missed event monitor status bit 41" "Not missed,Missed"
|
|
bitfld.long 0x08 8. " [40] ,Missed event monitor status bit 40" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 7. " [39] ,Missed event monitor status bit 39" "Not missed,Missed"
|
|
bitfld.long 0x08 6. " [38] ,Missed event monitor status bit 38" "Not missed,Missed"
|
|
bitfld.long 0x08 5. " [37] ,Missed event monitor status bit 37" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 4. " [36] ,Missed event monitor status bit 36" "Not missed,Missed"
|
|
bitfld.long 0x08 3. " [35] ,Missed event monitor status bit 35" "Not missed,Missed"
|
|
bitfld.long 0x08 2. " [34] ,Missed event monitor status bit 34" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 1. " [33] ,Missed event monitor status bit 33" "Not missed,Missed"
|
|
bitfld.long 0x08 0. " [32] ,Missed event monitor status bit 32" "Not missed,Missed"
|
|
line.long 0x0C "PWRSMEVNTMONSTAT2,Power SM Event Monitor Status 2 Register"
|
|
bitfld.long 0x0C 31. " PWRSMEVNTMONSTAT2[95] ,Missed event monitor status bit 95" "Not missed,Missed"
|
|
bitfld.long 0x0C 30. " [94] ,Missed event monitor status bit 94" "Not missed,Missed"
|
|
bitfld.long 0x0C 29. " [93] ,Missed event monitor status bit 93" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 28. " [92] ,Missed event monitor status bit 92" "Not missed,Missed"
|
|
bitfld.long 0x0C 27. " [91] ,Missed event monitor status bit 91" "Not missed,Missed"
|
|
bitfld.long 0x0C 26. " [90] ,Missed event monitor status bit 90" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 25. " [89] ,Missed event monitor status bit 89" "Not missed,Missed"
|
|
bitfld.long 0x0C 24. " [88] ,Missed event monitor status bit 88" "Not missed,Missed"
|
|
bitfld.long 0x0C 23. " [87] ,Missed event monitor status bit 87" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 22. " [86] ,Missed event monitor status bit 86" "Not missed,Missed"
|
|
bitfld.long 0x0C 21. " [85] ,Missed event monitor status bit 85" "Not missed,Missed"
|
|
bitfld.long 0x0C 20. " [84] ,Missed event monitor status bit 84" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 19. " [83] ,Missed event monitor status bit 83" "Not missed,Missed"
|
|
bitfld.long 0x0C 18. " [82] ,Missed event monitor status bit 82" "Not missed,Missed"
|
|
bitfld.long 0x0C 17. " [81] ,Missed event monitor status bit 81" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 16. " [80] ,Missed event monitor status bit 80" "Not missed,Missed"
|
|
bitfld.long 0x0C 15. " [79] ,Missed event monitor status bit 79" "Not missed,Missed"
|
|
bitfld.long 0x0C 14. " [78] ,Missed event monitor status bit 78" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 13. " [77] ,Missed event monitor status bit 77" "Not missed,Missed"
|
|
bitfld.long 0x0C 12. " [76] ,Missed event monitor status bit 76" "Not missed,Missed"
|
|
bitfld.long 0x0C 11. " [75] ,Missed event monitor status bit 75" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 10. " [74] ,Missed event monitor status bit 74" "Not missed,Missed"
|
|
bitfld.long 0x0C 9. " [73] ,Missed event monitor status bit 73" "Not missed,Missed"
|
|
bitfld.long 0x0C 8. " [72] ,Missed event monitor status bit 72" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 7. " [71] ,Missed event monitor status bit 71" "Not missed,Missed"
|
|
bitfld.long 0x0C 6. " [70] ,Missed event monitor status bit 70" "Not missed,Missed"
|
|
bitfld.long 0x0C 5. " [69] ,Missed event monitor status bit 69" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 4. " [68] ,Missed event monitor status bit 68" "Not missed,Missed"
|
|
bitfld.long 0x0C 3. " [67] ,Missed event monitor status bit 67" "Not missed,Missed"
|
|
bitfld.long 0x0C 2. " [66] ,Missed event monitor status bit 66" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 1. " [65] ,Missed event monitor status bit 65" "Not missed,Missed"
|
|
bitfld.long 0x0C 0. " [64] ,Missed event monitor status bit 64" "Not missed,Missed"
|
|
group.long 0x330++0x23
|
|
line.long 0x00 "PWRSMWAKESRCSTATCLR0,Power SM Wake Source Status Clear 0 Register"
|
|
bitfld.long 0x00 31. " PWRSMWAKESRCSTATCLR0[31] ,Clear wakeup source status bit 31" "Not cleared,Cleared"
|
|
bitfld.long 0x00 30. " [30] ,Clear wakeup source status bit 30" "Not cleared,Cleared"
|
|
bitfld.long 0x00 29. " [29] ,Clear wakeup source status bit 29" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Clear wakeup source status bit 28" "Not cleared,Cleared"
|
|
bitfld.long 0x00 27. " [27] ,Clear wakeup source status bit 27" "Not cleared,Cleared"
|
|
bitfld.long 0x00 26. " [26] ,Clear wakeup source status bit 26" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Clear wakeup source status bit 25" "Not cleared,Cleared"
|
|
bitfld.long 0x00 24. " [24] ,Clear wakeup source status bit 24" "Not cleared,Cleared"
|
|
bitfld.long 0x00 23. " [23] ,Clear wakeup source status bit 23" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Clear wakeup source status bit 22" "Not cleared,Cleared"
|
|
bitfld.long 0x00 21. " [21] ,Clear wakeup source status bit 21" "Not cleared,Cleared"
|
|
bitfld.long 0x00 20. " [20] ,Clear wakeup source status bit 20" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Clear wakeup source status bit 19" "Not cleared,Cleared"
|
|
bitfld.long 0x00 18. " [18] ,Clear wakeup source status bit 18" "Not cleared,Cleared"
|
|
bitfld.long 0x00 17. " [17] ,Clear wakeup source status bit 17" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Clear wakeup source status bit 16" "Not cleared,Cleared"
|
|
bitfld.long 0x00 15. " [15] ,Clear wakeup source status bit 15" "Not cleared,Cleared"
|
|
bitfld.long 0x00 14. " [14] ,Clear wakeup source status bit 14" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Clear wakeup source status bit 13" "Not cleared,Cleared"
|
|
bitfld.long 0x00 12. " [12] ,Clear wakeup source status bit 12" "Not cleared,Cleared"
|
|
bitfld.long 0x00 11. " [11] ,Clear wakeup source status bit 11" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Clear wakeup source status bit 10" "Not cleared,Cleared"
|
|
bitfld.long 0x00 9. " [9] ,Clear wakeup source status bit 9" "Not cleared,Cleared"
|
|
bitfld.long 0x00 8. " [8] ,Clear wakeup source status bit 8" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Clear wakeup source status bit 7" "Not cleared,Cleared"
|
|
bitfld.long 0x00 6. " [6] ,Clear wakeup source status bit 6" "Not cleared,Cleared"
|
|
bitfld.long 0x00 5. " [5] ,Clear wakeup source status bit 5" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Clear wakeup source status bit 4" "Not cleared,Cleared"
|
|
bitfld.long 0x00 3. " [3] ,Clear wakeup source status bit 3" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " [2] ,Clear wakeup source status bit 2" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Clear wakeup source status bit 1" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " [0] ,Clear wakeup source status bit 0" "Not cleared,Cleared"
|
|
line.long 0x04 "PWRSMWAKESRCSTATCLR1,Power SM Wake Source Status Clear 1 Register"
|
|
bitfld.long 0x04 31. " PWRSMWAKESRCSTATCLR1[63] ,Clear wakeup source status bit 63" "Not cleared,Cleared"
|
|
bitfld.long 0x04 30. " [62] ,Clear wakeup source status bit 62" "Not cleared,Cleared"
|
|
bitfld.long 0x04 29. " [61] ,Clear wakeup source status bit 61" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 28. " [60] ,Clear wakeup source status bit 60" "Not cleared,Cleared"
|
|
bitfld.long 0x04 27. " [59] ,Clear wakeup source status bit 59" "Not cleared,Cleared"
|
|
bitfld.long 0x04 26. " [58] ,Clear wakeup source status bit 58" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 25. " [57] ,Clear wakeup source status bit 57" "Not cleared,Cleared"
|
|
bitfld.long 0x04 24. " [56] ,Clear wakeup source status bit 56" "Not cleared,Cleared"
|
|
bitfld.long 0x04 23. " [55] ,Clear wakeup source status bit 55" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 22. " [54] ,Clear wakeup source status bit 54" "Not cleared,Cleared"
|
|
bitfld.long 0x04 21. " [53] ,Clear wakeup source status bit 53" "Not cleared,Cleared"
|
|
bitfld.long 0x04 20. " [52] ,Clear wakeup source status bit 52" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 19. " [51] ,Clear wakeup source status bit 51" "Not cleared,Cleared"
|
|
bitfld.long 0x04 18. " [50] ,Clear wakeup source status bit 50" "Not cleared,Cleared"
|
|
bitfld.long 0x04 17. " [49] ,Clear wakeup source status bit 49" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 16. " [48] ,Clear wakeup source status bit 48" "Not cleared,Cleared"
|
|
bitfld.long 0x04 15. " [47] ,Clear wakeup source status bit 47" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [46] ,Clear wakeup source status bit 46" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 13. " [45] ,Clear wakeup source status bit 45" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [44] ,Clear wakeup source status bit 44" "Not cleared,Cleared"
|
|
bitfld.long 0x04 11. " [43] ,Clear wakeup source status bit 43" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 10. " [42] ,Clear wakeup source status bit 42" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [41] ,Clear wakeup source status bit 41" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [40] ,Clear wakeup source status bit 40" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [39] ,Clear wakeup source status bit 39" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [38] ,Clear wakeup source status bit 38" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [37] ,Clear wakeup source status bit 37" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 4. " [36] ,Clear wakeup source status bit 36" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " [35] ,Clear wakeup source status bit 35" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [34] ,Clear wakeup source status bit 34" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,Clear wakeup source status bit 33" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [32] ,Clear wakeup source status bit 32" "Not cleared,Cleared"
|
|
line.long 0x08 "PWRSMWAKESRCSTATCLR2,Power SM Wake Source Status Clear 2 Register"
|
|
bitfld.long 0x08 31. " PWRSMWAKESRCSTATCLR2[95] ,Clear wakeup source status bit 95" "Not cleared,Cleared"
|
|
bitfld.long 0x08 30. " [94] ,Clear wakeup source status bit 94" "Not cleared,Cleared"
|
|
bitfld.long 0x08 29. " [93] ,Clear wakeup source status bit 93" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 28. " [92] ,Clear wakeup source status bit 92" "Not cleared,Cleared"
|
|
bitfld.long 0x08 27. " [91] ,Clear wakeup source status bit 91" "Not cleared,Cleared"
|
|
bitfld.long 0x08 26. " [90] ,Clear wakeup source status bit 90" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 25. " [89] ,Clear wakeup source status bit 89" "Not cleared,Cleared"
|
|
bitfld.long 0x08 24. " [88] ,Clear wakeup source status bit 88" "Not cleared,Cleared"
|
|
bitfld.long 0x08 23. " [87] ,Clear wakeup source status bit 87" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 22. " [86] ,Clear wakeup source status bit 86" "Not cleared,Cleared"
|
|
bitfld.long 0x08 21. " [85] ,Clear wakeup source status bit 85" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " [84] ,Clear wakeup source status bit 84" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 19. " [83] ,Clear wakeup source status bit 83" "Not cleared,Cleared"
|
|
bitfld.long 0x08 18. " [82] ,Clear wakeup source status bit 82" "Not cleared,Cleared"
|
|
bitfld.long 0x08 17. " [81] ,Clear wakeup source status bit 81" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 16. " [80] ,Clear wakeup source status bit 80" "Not cleared,Cleared"
|
|
bitfld.long 0x08 15. " [79] ,Clear wakeup source status bit 79" "Not cleared,Cleared"
|
|
bitfld.long 0x08 14. " [78] ,Clear wakeup source status bit 78" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 13. " [77] ,Clear wakeup source status bit 77" "Not cleared,Cleared"
|
|
bitfld.long 0x08 12. " [76] ,Clear wakeup source status bit 76" "Not cleared,Cleared"
|
|
bitfld.long 0x08 11. " [75] ,Clear wakeup source status bit 75" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 10. " [74] ,Clear wakeup source status bit 74" "Not cleared,Cleared"
|
|
bitfld.long 0x08 9. " [73] ,Clear wakeup source status bit 73" "Not cleared,Cleared"
|
|
bitfld.long 0x08 8. " [72] ,Clear wakeup source status bit 72" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 7. " [71] ,Clear wakeup source status bit 71" "Not cleared,Cleared"
|
|
bitfld.long 0x08 6. " [70] ,Clear wakeup source status bit 70" "Not cleared,Cleared"
|
|
bitfld.long 0x08 5. " [69] ,Clear wakeup source status bit 69" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 4. " [68] ,Clear wakeup source status bit 68" "Not cleared,Cleared"
|
|
bitfld.long 0x08 3. " [67] ,Clear wakeup source status bit 67" "Not cleared,Cleared"
|
|
bitfld.long 0x08 2. " [66] ,Clear wakeup source status bit 66" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 1. " [65] ,Clear wakeup source status bit 65" "Not cleared,Cleared"
|
|
bitfld.long 0x08 0. " [64] ,Clear wakeup source status bit 64" "Not cleared,Cleared"
|
|
line.long 0x0C "ADCBUFCFG1,ADC Buffer Configuration 1 Register"
|
|
bitfld.long 0x0C 15. " ADCBUFCONTSTOPPL ,Enable stop pulse for continuous mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " ADCBUFCONTSTRTPL ,Enable start pulse for continuous mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " ADCBUFCONTMODEEN ,Continuous mode enable for ADC buffer" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 12. " ADCBUFWRITEMODE ,ADC buffer write mode" "Interleaved,Non-interleaved"
|
|
bitfld.long 0x0C 9. " RX3EN ,Enable for Rx3 write" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " RX2EN ,Enable for Rx2 write" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 7. " RX1EN ,Enable for Rx1 write" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " RX0EN ,Enable for Rx0 write" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " ADCBUFIQSWAP ,ADC buffer I/Q swap" "I LSB / Q MSB,I MSB / Q LSB"
|
|
newline
|
|
bitfld.long 0x0C 2. " ADCBUFREALONLYMODE ,ADC buffer mode select" "Complex,Real"
|
|
line.long 0x10 "ADCBUFCFG2,ADC Buffer Configuration 2 Register"
|
|
hexmask.long.word 0x10 16.--26. 0x01 " ADCBUFADDRX1 ,128 bit address offset 1"
|
|
hexmask.long.word 0x10 0.--10. 0x01 " ADCBUFADDRX0 ,128 bit address offset 0"
|
|
line.long 0x14 "ADCBUFCFG3,ADC Buffer Configuration 3 Register"
|
|
hexmask.long.word 0x14 16.--26. 0x01 " ADCBUFADDRX3 ,128 bit address offset 3"
|
|
hexmask.long.word 0x14 0.--10. 0x01 " ADCBUFADDRX2 ,128 bit address offset 2"
|
|
line.long 0x18 "ADCBUFCFG4,ADC Buffer Configuration 4 Register"
|
|
bitfld.long 0x18 21.--25. " ADCBUFNUMCHRPPONG ,Number of chirps to be stored in pong buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x18 16.--20. " ADCBUFNUMCHRPPING ,Number of chirps to be stored in ping buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x18 0.--15. 1. " ADCBUFSAMPCNT ,ADC buffer samples counter"
|
|
line.long 0x1C "STCPBISTSMCFG1,STC PBIST SM Configuration 1 Register"
|
|
rbitfld.long 0x1C 20. " PBISTTESTSTATCLR ,Clear bit for PBIST status" "Not cleared,Cleared"
|
|
rbitfld.long 0x1C 19. " PBISTTESTSTAT[1] ,PBIST fail indication from GEM" "Not failed,Failed"
|
|
rbitfld.long 0x1C 18. " PBISTTESTSTAT[0] ,PBIST done indication from GEM" "Not done,Done"
|
|
newline
|
|
rbitfld.long 0x1C 12.--17. " STCPBISTSMSTATE ,Current state of STC PBIST state machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x1C 4. " STCPBISTCKSTPACKMASK ,Mask bit for ignoring the clock stop ACK from GEM" "Not masked,Masked"
|
|
bitfld.long 0x1C 3. " STCPBISTLRSTDASRTHALT ,Configuration to halt the state machine before the final de-assertion of LRST" "Proceeded,Halt"
|
|
newline
|
|
bitfld.long 0x1C 2. " STCPBISTSMTRIG ,Trigger pulse for the STC PBIST state machine" "Not triggered,Triggered"
|
|
bitfld.long 0x1C 0.--1. " STCPBISTEN ,Enable for PBIST and STC" ",STC,PBIST,Both"
|
|
line.long 0x20 "STCPBISTSMCFG2,STC PBIST SM Configuration 2 Register"
|
|
bitfld.long 0x20 16. " BCK2BCKSTCEN ,Enables back to back STC" "Disabled,Enabled"
|
|
bitfld.long 0x20 12.--13. " GEMPBISTROMCLKSEL ,GEM PBIST ROM clock frequency" "600 Mhz,300 Mhz,200 Mhz,150 Mhz"
|
|
bitfld.long 0x20 6.--11. " GEMTMODEVLCTASRTCNT ,No of clocks after asserting GEM TMODE VLCT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
|
|
newline
|
|
bitfld.long 0x20 0.--5. " GEMTMODEVLCTDASRTCNT ,No of clocks after de-asserting GEM TMODE VLCT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
|
|
group.long 0x358++0x07
|
|
line.long 0x00 "RTI2EVENTCAPTURESEL,RTI2 Event Captured Select Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " RTI2EVT1 ,Used to select the event to be captured for RTI2 event 1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RTI2EVT0 ,Used to select the event to be captured for RTI2 event 0"
|
|
line.long 0x04 "DSSMISC5,DSS Miscellaneous 5 Register"
|
|
rbitfld.long 0x04 7. " TPCC1PARMEMINITDONE ,Memory initialization done status for the TPCC1 parity memory" "Disabled,Enabled"
|
|
rbitfld.long 0x04 6. " TPCC0PARMEMINITDONE ,Memory initialization done status for the TPCC0 parity memory" "Disabled,Enabled"
|
|
rbitfld.long 0x04 5. " TPCC1PARMEMINIT ,Memory initialization for the TPCC1 parity memory" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x04 4. " TPCC0PARMEMINIT ,Memory initialization for the TPCC0 parity memory" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CPBPMPIPOSELVAL ,Ping pong select override value for CPBPM (Read/Write)" "Pong/Ping,Ping/Pong"
|
|
bitfld.long 0x04 2. " CPBPMPIPOSELCNT ,Ping pong select override control for CPBPM memory" "SW register,HW FSM"
|
|
newline
|
|
bitfld.long 0x04 1. " CQPIPOSELVAL ,Ping pong select override value for CQ memory (Read/Write)" "Pong/Ping,Ping/Pong"
|
|
bitfld.long 0x04 0. " CQPIPOSELCNT ,Ping pong select override control for CQ memory" "SW register,HW FSM"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DSS REG2 Registers"
|
|
base ad:0x50000C00
|
|
width 19.
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "TPTC2WRMPUSTADD0,TPTC2 Start Address Write For Region 0 Register"
|
|
line.long 0x04 "TPTC2WRMPUSTADD1,TPTC2 Start Address Write For Region 1 Register"
|
|
line.long 0x08 "TPTC2WRMPUSTADD2,TPTC2 Start Address Write For Region 2 Register"
|
|
line.long 0x0C "TPTC2WRMPUSTADD3,TPTC2 Start Address Write For Region 3 Register"
|
|
line.long 0x10 "TPTC2WRMPUSTADD4,TPTC2 Start Address Write For Region 4 Register"
|
|
line.long 0x14 "TPTC2WRMPUSTADD5,TPTC2 Start Address Write For Region 5 Register"
|
|
group.long 0x120++0x17
|
|
line.long 0x00 "TPTC2WRMPUENDADD0,TPTC2 End Address Write For Region 0 Register"
|
|
line.long 0x04 "TPTC2WRMPUENDADD1,TPTC2 End Address Write For Region 1 Register"
|
|
line.long 0x08 "TPTC2WRMPUENDADD2,TPTC2 End Address Write For Region 2 Register"
|
|
line.long 0x0C "TPTC2WRMPUENDADD3,TPTC2 End Address Write For Region 3 Register"
|
|
line.long 0x10 "TPTC2WRMPUENDADD4,TPTC2 End Address Write For Region 4 Register"
|
|
line.long 0x14 "TPTC2WRMPUENDADD5,TPTC2 End Address Write For Region 5 Register"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "TPTC2WRMPUERRADD,TPTC2 Write Address Status Register"
|
|
group.long 0x148++0x17
|
|
line.long 0x00 "TPTC2RDMPUSTADD0,TPTC2 Start Address Read For Region 0 Register"
|
|
line.long 0x04 "TPTC2RDMPUSTADD1,TPTC2 Start Address Read For Region 1 Register"
|
|
line.long 0x08 "TPTC2RDMPUSTADD2,TPTC2 Start Address Read For Region 2 Register"
|
|
line.long 0x0C "TPTC2RDMPUSTADD3,TPTC2 Start Address Read For Region 3 Register"
|
|
line.long 0x10 "TPTC2RDMPUSTADD4,TPTC2 Start Address Read For Region 4 Register"
|
|
line.long 0x14 "TPTC2RDMPUSTADD5,TPTC2 Start Address Read For Region 5 Register"
|
|
group.long 0x168++0x17
|
|
line.long 0x00 "TPTC2RDMPUENDADD0,TPTC2 End Address Read For Region 0 Register"
|
|
line.long 0x04 "TPTC2RDMPUENDADD1,TPTC2 End Address Read For Region 1 Register"
|
|
line.long 0x08 "TPTC2RDMPUENDADD2,TPTC2 End Address Read For Region 2 Register"
|
|
line.long 0x0C "TPTC2RDMPUENDADD3,TPTC2 End Address Read For Region 3 Register"
|
|
line.long 0x10 "TPTC2RDMPUENDADD4,TPTC2 End Address Read For Region 4 Register"
|
|
line.long 0x14 "TPTC2RDMPUENDADD5,TPTC2 End Address Read For Region 5 Register"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "TPTC2RDMPUERRADD,TPTC2 Read Address Status Register"
|
|
group.long 0x18C++0x17
|
|
line.long 0x00 "TPTC3WRMPUSTADD0,TPTC3 Start Address Write For Region 0 Register"
|
|
line.long 0x04 "TPTC3WRMPUSTADD1,TPTC3 Start Address Write For Region 1 Register"
|
|
line.long 0x08 "TPTC3WRMPUSTADD2,TPTC3 Start Address Write For Region 2 Register"
|
|
line.long 0x0C "TPTC3WRMPUSTADD3,TPTC3 Start Address Write For Region 3 Register"
|
|
line.long 0x10 "TPTC3WRMPUSTADD4,TPTC3 Start Address Write For Region 4 Register"
|
|
line.long 0x14 "TPTC3WRMPUSTADD5,TPTC3 Start Address Write For Region 5 Register"
|
|
group.long 0x1AC++0x17
|
|
line.long 0x00 "TPTC3WRMPUENDADD0,TPTC3 End Address Write For Region 0 Register"
|
|
line.long 0x04 "TPTC3WRMPUENDADD1,TPTC3 End Address Write For Region 1 Register"
|
|
line.long 0x08 "TPTC3WRMPUENDADD2,TPTC3 End Address Write For Region 2 Register"
|
|
line.long 0x0C "TPTC3WRMPUENDADD3,TPTC3 End Address Write For Region 3 Register"
|
|
line.long 0x10 "TPTC3WRMPUENDADD4,TPTC3 End Address Write For Region 4 Register"
|
|
line.long 0x14 "TPTC3WRMPUENDADD5,TPTC3 End Address Write For Region 5 Register"
|
|
rgroup.long 0x1CC++0x03
|
|
line.long 0x00 "TPTC3WRMPUERRADD,TPTC3 Write Address Status Register"
|
|
group.long 0x1D0++0x17
|
|
line.long 0x00 "TPTC3RDMPUSTADD0,TPTC3 Start Address Read For Region 0 Register"
|
|
line.long 0x04 "TPTC3RDMPUSTADD1,TPTC3 Start Address Read For Region 1 Register"
|
|
line.long 0x08 "TPTC3RDMPUSTADD2,TPTC3 Start Address Read For Region 2 Register"
|
|
line.long 0x0C "TPTC3RDMPUSTADD3,TPTC3 Start Address Read For Region 3 Register"
|
|
line.long 0x10 "TPTC3RDMPUSTADD4,TPTC3 Start Address Read For Region 4 Register"
|
|
line.long 0x14 "TPTC3RDMPUSTADD5,TPTC3 Start Address Read For Region 5 Register"
|
|
group.long 0x1F0++0x17
|
|
line.long 0x00 "TPTC3RDMPUENDADD0,TPTC3 End Address Read For Region 0 Register"
|
|
line.long 0x04 "TPTC3RDMPUENDADD1,TPTC3 End Address Read For Region 1 Register"
|
|
line.long 0x08 "TPTC3RDMPUENDADD2,TPTC3 End Address Read For Region 2 Register"
|
|
line.long 0x0C "TPTC3RDMPUENDADD3,TPTC3 End Address Read For Region 3 Register"
|
|
line.long 0x10 "TPTC3RDMPUENDADD4,TPTC3 End Address Read For Region 4 Register"
|
|
line.long 0x14 "TPTC3RDMPUENDADD5,TPTC3 End Address Read For Region 5 Register"
|
|
rgroup.long 0x210++0x03
|
|
line.long 0x00 "TPTC3RDMPUERRADD,TPTC3 Read Address Status Register"
|
|
group.long 0x214++0x07
|
|
line.long 0x00 "TPTCMPUVALIDCFG2,TPTCMPUVALIDCFG2 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TPTC3RDMPURNGVLD ,TPTC3 read valid bit for each address range for the MPU"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TPTC3WRMPURNGVLD ,TPTC3 write valid bit for each address range for the MPU"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " TPTC2RDMPURNGVLD ,TPTC2 read valid bit for each address range for the MPU"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TPTC2WRMPURNGVLD ,TPTC2 write valid bit for each address range for the MPU"
|
|
line.long 0x04 "TPTCMPUENCFG2,TPTCMPUENCFG2 Register"
|
|
eventfld.long 0x04 7. " TPTC3RDMPUERRCLR ,Clear flag for error from the MPU in the read port of TPTC3" "Not occurred,Occurred"
|
|
eventfld.long 0x04 6. " TPTC3WRMPUERRCLR ,Clear flag for error from the MPU in the write port of TPTC3" "Not occurred,Occurred"
|
|
eventfld.long 0x04 5. " TPTC2RDMPUERRCLR ,Clear flag for error from the MPU in the read port of TPTC2" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 4. " TPTC2WRMPUERRCLR ,Clear flag for error from the MPU in the write port of TPTC2" "Not occurred,Occurred"
|
|
bitfld.long 0x04 3. " TPTC3RDMPUEN ,MPU in the read port of TPTC3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " TPTC3WRMPUEN ,MPU in the write port of TPTC3 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " TPTC2RDMPUEN ,MPU in the read port of TPTC2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TPTC2WRMPUEN ,MPU in the write port of TPTC2 enable" "Disabled,Enabled"
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "L3ECCCFG1,L3ECCCFG1 Register"
|
|
hexmask.long.tbyte 0x00 3.--26. 1. " L3ECCREPAIREDBIT ,Bit position of repaired bit in L3 ECC memory"
|
|
rbitfld.long 0x00 2. " L3ECCERRSTAT ,L3 ECC error latched status" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 1. " L3ECCERRCLR ,L3 ECC clear bit" "No clear,Clear"
|
|
bitfld.long 0x00 0. " L3ECCEN ,L3 ECC logic enable" "Disabled,Enabled"
|
|
rgroup.long 0x26C++0x03
|
|
line.long 0x00 "L3ECCCFG2,L3ECCCFG2 Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 0x01 " L3ECCFAULTADDR ,Fault address of L3 ECC memory"
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "DSS2MSSSWIRQ,DSS2MSSSWIRQ Register"
|
|
bitfld.long 0x00 1. " MSSSWIRQ2 ,Generate a pulse from DSS to MSS VIM line 61" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MSSSWIRQ1 ,Generate a pulse from DSS to MSS VIM line 52" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree.open "AWR (Power, Reset, Clock Management and Control Registers)"
|
|
base ad:0xFFFFE100
|
|
width 22.
|
|
tree "MSS TOPRCM Registers"
|
|
group.long 0x08++0x23
|
|
line.long 0x00 "BSSCTL,Control Signals To BSS Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BSSCPUHALT ,Halt BSS CR4 to halt"
|
|
line.long 0x04 "DSSCTL,DSSCTL Register"
|
|
bitfld.long 0x04 26. " GEMLRSTN ,DSP local reset value that will be propagated to the DSP when the DSP power FSM has switched the DSP on" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " GEMGRSTN ,DSP global reset value that will be propagated to the DSP when the DSP power FSM has switched the DSP on" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " GEMPORZ ,DSP reset value that will be propagated to the DSP when the DSP power FSM has switched the DSP on" "Disabled,Enabled"
|
|
line.long 0x08 "EXTCLKDIV,Clock Divide Value For MCU_CLKOUT and PMIC_CLKOUT Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " EXTCLK2DIV ,Divide value for PMIC_CLKOUT source clock"
|
|
hexmask.long.byte 0x08 0.--7. 1. " EXTCLK1DIV ,Divide value for MCU_CLKOUT"
|
|
line.long 0x0C "EXTCLKSRCSEL,Clock Source Select Value For MCU_CLKOUT and PMIC_CLKOUT Register"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x0C 8.--11. " EXTCLK2SRCSEL ,Select clock source for PMIC_CLKOUT" "CPUCLK,RCCLK,600-mHz PLL,240-mHz PLL,RCCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTCLK1SRCSEL ,Select clock source for MCU_CLKOUT" "CPUCLK,RCCLK,600-mHz PLL,240-mHz PLL,RCCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
else
|
|
bitfld.long 0x0C 8.--11. " EXTCLK2SRCSEL ,Select clock source for PMIC_CLKOUT" "CPUCLK,RCCLK,600-mHz PLL,,RCCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTCLK1SRCSEL ,Select clock source for MCU_CLKOUT" "CPUCLK,RCCLK,600-mHz PLL,,RCCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
endif
|
|
line.long 0x10 "EXTCLKCTL,Clock Gate Control For MCU_CLKOUT and PMIC_CLKOUT Register"
|
|
hexmask.long.byte 0x10 8.--15. 1. " EXTCLK2GATE ,Pre clock divider gate for PMIC_CLKOUT"
|
|
hexmask.long.byte 0x10 0.--7. 1. " EXTCLK1GATE ,Pre clock divider gate for MCU_CLKOUT"
|
|
line.long 0x14 "SOFTSYSRST,Software Triggered Warm Reset Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " SOFTSYSRST ,Software trigger warm reset"
|
|
line.long 0x18 "WDRSTEN,Issue Warm Reset Upon MSS Watch Dog Reset Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " WDRSTEN ,Watchdog trigger warm reset"
|
|
line.long 0x1C "SYSRSTCAUSE,Reset Cause Register"
|
|
bitfld.long 0x1C 0.--3. " SYSRSTCAUSE ,System reset cause" ",,,,,,,,Ext. warm reset,NRESET,Warm reset,,SOFTSYSRST,?..."
|
|
line.long 0x20 "SYSRSTCAUSECLR,Clear Reset Cause Register"
|
|
hexmask.long.byte 0x20 0.--7. 1. " SYSRSTCAUSECLR ,System reset clear cause"
|
|
newline
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "MISCCAPT,Capture Required Status Values Across The Chip Register"
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "DCDCCTL0,PMIC_CLKOUT Dethering Control Register"
|
|
line.long 0x04 "DCDCCTL1,PMIC_CLKOUT Dethering Control Register"
|
|
hexmask.long 0x04 2.--31. 1. " DCDCCTL1 ,PMIC_CLKOUT dethering control"
|
|
bitfld.long 0x04 1. " DCDCLKEN ,PMIC_CLKOUT dethering control block Enable Multi Bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " DCDCRST ,PMI clock out dethering control block reset Multi Bit" "No reset,Reset"
|
|
group.long 0x48++0x0B
|
|
line.long 0x00 "USERMODEEN,User Mode Access Enable Register"
|
|
line.long 0x04 "LVDSPADCTL0,LVDS Pad Control 0 Register"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x04 22. " EXT_RES_EN_TX1 ,External reset enable for i_LVDS_tx1_io_cell" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " HIZ_DISABLE_TX1 ,HIZ disable for i_LVDS_tx1_io_cell" "No,Yes"
|
|
bitfld.long 0x04 20. " SUB_LVDS_EN_TX1 ,SUB_LVDS enable for i_LVDS_tx1_io_cell" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " LPSEL_TX1 ,LPSEL for i_LVDS_tx1_io_cell" "0,1"
|
|
newline
|
|
bitfld.long 0x04 18. " LOPWRB_TX1 ,LOPWRB for i_LVDS_tx1_io_cell" "0,1"
|
|
bitfld.long 0x04 17. " LOPWRA_TX1 ,LOPWRA for i_LVDS_tx1_io_cell" "0,1"
|
|
bitfld.long 0x04 16. " PWRDN_TX1 ,Power down for i_LVDS_tx1_io_cell" "Powered up,Powered down"
|
|
newline
|
|
bitfld.long 0x04 14. " EXT_RES_EN_TX0 ,External reset enable for i_LVDS_tx0_io_cell" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " HIZ_DISABLE_TX0 ,HIZ disable for i_LVDS_tx0_io_cell" "No,Yes"
|
|
bitfld.long 0x04 12. " SUB_LVDS_EN_TX0 ,SUB_LVDS enable for i_LVDS_tx0_io_cell" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " LPSEL_TX0 ,LPSEL for i_LVDS_tx0_io_cell" "0,1"
|
|
newline
|
|
bitfld.long 0x04 10. " LOPWRB_TX0 ,LOPWRB for i_LVDS_tx0_io_cell" "0,1"
|
|
bitfld.long 0x04 9. " LOPWRA_TX0 ,LOPWRA for i_LVDS_tx0_io_cell" "0,1"
|
|
bitfld.long 0x04 8. " PWRDN_TX0 ,Power down for i_LVDS_tx0_io_cell" "Powered up,Powered down"
|
|
newline
|
|
bitfld.long 0x04 6. " EXT_RES_EN_CLK ,External reset enable for i_LVDSclk_io_cell" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " HIZ_DISABLE_CLK ,HIZ disable for i_LVDSclk_io_cell" "No,Yes"
|
|
bitfld.long 0x04 4. " SUB_LVDS_EN_CLK ,SUB_LVDS enable for i_LVDSclk_io_cell" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " LPSEL_CLK ,LPSEL for i_LVDSclk_io_cell" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. " LOPWRB_CLK ,LOPWRB for i_LVDSclk_io_cell" "0,1"
|
|
bitfld.long 0x04 1. " LOPWRA_CLK ,LOPWRA for i_LVDSclk_io_cell" "0,1"
|
|
bitfld.long 0x04 0. " PWRDN_CLK ,Power down for i_LVDSclk_io_cell" "Powered up,Powered down"
|
|
endif
|
|
line.long 0x08 "LVDSPADCTL1,LVDS Pad Control 1 Register"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x08 25. " EFUSE_SET_BIAS ,Efuse set for lvds_bias_cell" "Not set,Set"
|
|
bitfld.long 0x08 24. " PWRDN_BIAS ,Power down for i_LVDSfrclk_io_cell" "Powered up,Powered down"
|
|
newline
|
|
bitfld.long 0x08 14. " EXT_RES_EN_FRCLK ,External reset enable for i_LVDSfrclk_io_cell" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " HIZ_DISABLE_FRCLK ,HIZ disable for i_LVDSfrclk_io_cell" "No,Yes"
|
|
bitfld.long 0x08 12. " SUB_LVDS_EN_FRCLK ,SUB_LVDS enable for i_LVDSfrclk_io_cell" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " LPSEL_FRCLK ,LPSEL for i_LVDSfrclk_io_cell" "0,1"
|
|
newline
|
|
bitfld.long 0x08 10. " LOPWRB_FRCLK ,LOPWRB for i_LVDSfrclk_io_cell" "0,1"
|
|
bitfld.long 0x08 9. " LOPWRA_FRCLK ,LOPWRA for i_LVDSfrclk_io_cell" "0,1"
|
|
bitfld.long 0x08 8. " PWRDN_FRCLK ,Power down for i_LVDSfrclk_io_cell" "Powered up,Powered down"
|
|
endif
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "DFTREG0,DFT Register 0"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x00 31. " SELFTEST_EN[25] ,Memory group [25] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [24] ,Memory group [24] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [23] ,Memory group [23] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [22] ,Memory group [22] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [21] ,Memory group [21] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [20] ,Memory group [20] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [19] ,Memory group [19] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [18] ,Memory group [18] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [17] ,Memory group [17] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [16] ,Memory group [16] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [15] ,Memory group [15] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [14] ,Memory group [14] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [13] ,Memory group [13] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [12] ,Memory group [12] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [11] ,Memory group [11] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [10] ,Memory group [10] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [9] ,Memory group [9] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [8] ,Memory group [8] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [7] ,Memory group [7] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [6] ,Memory group [6] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [5] ,Memory group [5] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [4] ,Memory group [4] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [3] ,Memory group [3] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " [2] ,Memory group [2] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [1] ,Memory group [1] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [0] ,Memory group [0] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " PBIST_RST ,PBIST IP reset control" "No reset,Reset"
|
|
bitfld.long 0x00 0.--3. " SELFTEST_KEY ,MSS PBIST self-test key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x04 "DFTREG1,DFT Register 1"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x04 31. " SELFTEST_DIS[31] ,Memory group [31] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [30] ,Memory group [30] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [29] ,Memory group [29] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [28] ,Memory group [28] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 27. " [27] ,Memory group [27] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [26] ,Memory group [26] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [25] ,Memory group [25] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [24] ,Memory group [24] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 23. " [23] ,Memory group [23] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [22] ,Memory group [22] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [21] ,Memory group [21] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [20] ,Memory group [20] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Memory group [19] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [18] ,Memory group [18] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [17] ,Memory group [17] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [16] ,Memory group [16] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " [15] ,Memory group [15] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [14] ,Memory group [14] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [13] ,Memory group [13] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [12] ,Memory group [12] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Memory group [11] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [10] ,Memory group [10] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [9] ,Memory group [9] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [8] ,Memory group [8] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Memory group [7] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [6] ,Memory group [6] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [5] ,Memory group [5] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [4] ,Memory group [4] self-test enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Memory group [3] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,Memory group [2] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [1] ,Memory group [1] self-test enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [0] ,Memory group [0] self-test enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "DFTREG5,DFT Register 5"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x00 5.--8. " MEM_SELFTEST_EN ,Subsystem level memory self-test power clock gate enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " PBIST_SELFTEST_KEY ,DSP PBIST self-test key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "MEMINITDONE,Memory Initialization Done Status Register"
|
|
sif !cpuis("AWR1843*")
|
|
bitfld.long 0x00 16. " SHMEM ,Memory initialization done status for shared memory" "Not done,Done"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 9. " BSSVIMMEM ,Memory initialization done status for BSS VIM memory" "Not done,Done"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "MSS_SIGNATURE,Spare Register"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "GEMBOOTSTCEN,GEM BOOT STC Enable Register"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x00 0. " GEMBOOTSTCEN ,Enable GEM STC during GEM power UP" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 16. " GEMBOOTSTCEN ,Enable GEM STC during GEM power UP" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "MISCCTL1,Miscellaneous Control Register"
|
|
sif cpuis("AWR1843*")
|
|
hexmask.long.word 0x00 16.--24. 1. " EXT_CLK_EN ,External clock as QSPI baud clock source enable"
|
|
hexmask.long.byte 0x00 8.--15. 1. " LVL_LB_CLK ,Board level loop back clock for QSPI enable"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WARM_RESET_EN ,Enable warm_resetn from external device in addition to internally generated warm reset"
|
|
endif
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "USERMODEEN2,User Mode Access Enable 2 Register"
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "SYSTICK,SYSTICK Register"
|
|
group.long 0x1C4++0x13
|
|
line.long 0x00 "SECURECFGREG1,Secure CFG Register 1"
|
|
bitfld.long 0x00 28.--30. " JTAGFIREWALLEN ,JTAG firewall" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled"
|
|
bitfld.long 0x00 20.--22. " SECURERAMFIREWALLEN ,Secure RAM firewall" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled"
|
|
bitfld.long 0x00 16.--18. " LOGGERFIREWALLEN ,Logger firewall" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " TRACEFIREWALLEN ,Trace firewall" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled"
|
|
bitfld.long 0x00 8.--10. " CRYPTOFIREWALLEN ,Crypto firewall" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled"
|
|
bitfld.long 0x00 4.--6. " CUSTCEKFIREWALLEN ,CEK[1/2] firewall" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled"
|
|
line.long 0x04 "SECURECFGREG2,Secure CFG Register 2"
|
|
bitfld.long 0x04 8.--10. " CUSTKEYERASE ,Erase CEK1" "0,1,2,3,4,5,6,Erased"
|
|
bitfld.long 0x04 0.--2. " DMMFIREWALLEN ,DMM firewall" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled"
|
|
line.long 0x08 "SECURECFGREG3,Secure CFG Register 3"
|
|
bitfld.long 0x08 28.--30. " JTAGSTICKYBIT ,JTAG sticky" "0,1,2,3,4,5,6,Set"
|
|
bitfld.long 0x08 20.--22. " SECURERAMSTICKYBIT ,Secure RAM sticky" "0,1,2,3,4,5,6,Set"
|
|
bitfld.long 0x08 16.--18. " TRACESTICKYBIT ,Trace sticky" "0,1,2,3,4,5,6,Set"
|
|
newline
|
|
bitfld.long 0x08 12.--14. " CRYPTOSTICKYBIT ,Crypto sticky" "0,1,2,3,4,5,6,Set"
|
|
bitfld.long 0x08 8.--10. " CUSTCEKSTICKYBIT ,CEK[1/2] sticky for firewall" "0,1,2,3,4,5,6,Set"
|
|
bitfld.long 0x08 0.--2. " LOGGERSTICKYBIT ,Logger sticky" "0,1,2,3,4,5,6,Set"
|
|
line.long 0x0C "SECURECFGREG4,Secure CFG Register 4"
|
|
bitfld.long 0x0C 0.--2. " DMMSTICKYBIT ,DMM sticky" "0,1,2,3,4,5,6,Set"
|
|
line.long 0x10 "SECURERAMREG,Secure RAM Register"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x10 24. " SECURERAMKEY255 ,Secure RAM key bitwidth" "128,255"
|
|
else
|
|
bitfld.long 0x10 24. " SECURERAMKEY255 ,Secure RAM key bitwidth" "255,128"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x10 16.--23. 1. " SECURERAMKEYIDX ,Secure RAM index"
|
|
bitfld.long 0x10 8. " SECURERAMKEYRD ,Secure RAM load key" "Disabled,Enabled"
|
|
rbitfld.long 0x10 0. " SECURERAMRDDONE ,Secure RAM key loaded into register done" "Not done,Done"
|
|
sif cpuis("AWR1843*")
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "SPAREMULTIBIT,Spare Register"
|
|
bitfld.long 0x00 11. " SPAREMULTIBIT[11] ,MIBSPIB" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,SPIB trigger source polarity select" "Polarity 0,Polarity 1"
|
|
bitfld.long 0x00 9. " [9] ,SPIA trigger source polarity select" "Polarity 0,Polarity 1"
|
|
newline
|
|
bitfld.long 0x00 8. " [8] ,MIBSPIB external chip select is overridden with the value of MIBSPIB CS polarity-slave mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,MIBSPIA external chip select is overridden with the value of MIBSPIB CS polarity-slave mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,MIBSPIB CS trigger SRC enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,MIBSPIB CS polarity-slave mode" "High,Low"
|
|
bitfld.long 0x00 4. " [4] ,MIBSPIB MISO OE_N control based on chip select" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,MIBSPIA" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,MIBSPIA CS trigger SRC enable-slave mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,MIBSPIA CS polarity-slave mode" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,MIBSPIA MISO OE_N control based on chip" "Disabled,Enabled"
|
|
else
|
|
; group.long 0x1E4++0x03
|
|
; line.long 0x00 "SPAREMULTIBIT,Spare Register"
|
|
; bitfld.long 0x00 11. " SPAREMULTIBIT11 ,MIBSPIB" "Disabled,Enabled"
|
|
; bitfld.long 0x00 10. " SPAREMULTIBIT10 ,SPIB trigger source polarity select" "Polarity 0,Polarity 1"
|
|
; bitfld.long 0x00 9. " SPAREMULTIBIT9 ,SPIA trigger source polarity select" "Polarity 0,Polarity 1"
|
|
; newline
|
|
; bitfld.long 0x00 8. " SPAREMULTIBIT8 ,MIBSPIB external chip select is overridden with the value of MIBSPIB CS polarity-slave mode" "Disabled,Enabled"
|
|
; bitfld.long 0x00 7. " SPAREMULTIBIT7 ,MIBSPIA external chip select is overridden with the value of MIBSPIB CS polarity-slave mode" "Disabled,Enabled"
|
|
; bitfld.long 0x00 6. " SPAREMULTIBIT6 ,MIBSPIB CS trigger SRC enable" "Disabled,Enabled"
|
|
; newline
|
|
; bitfld.long 0x00 5. " SPAREMULTIBIT5 ,MIBSPIB CS polarity-slave mode" "High,Low"
|
|
; bitfld.long 0x00 4. " SPAREMULTIBIT4 ,MIBSPIB MISO OE_N control based on chip select" "Disabled,Enabled"
|
|
; bitfld.long 0x00 3. " SPAREMULTIBIT3 ,MIBSPIA" "Disabled,Enabled"
|
|
; newline
|
|
; bitfld.long 0x00 2. " SPAREMULTIBIT2 ,MIBSPIA CS trigger SRC enable-slave mode" "Disabled,Enabled"
|
|
; bitfld.long 0x00 1. " SPAREMULTIBIT1 ,MIBSPIA CS polarity-slave mode" "High,Low"
|
|
; bitfld.long 0x00 0. " SPAREMULTIBIT0 ,MIBSPIA MISO OE_N control based on chip" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x200++0x0F
|
|
line.long 0x00 "UID31TO0,Efuse Row Capture Register For FROM1"
|
|
line.long 0x04 "UID63TO32,Efuse Row Capture Register For FROM1"
|
|
line.long 0x08 "UID95TO64,Efuse Row Capture Register For FROM1"
|
|
line.long 0x0C "UID119TO96,Efuse Row Capture Register For FROM1"
|
|
newline
|
|
rgroup.long 0x2A8++0x07
|
|
line.long 0x00 "MEMINITSTARTSHMEM,Shared Memory Initialization Start Register"
|
|
bitfld.long 0x00 7. " MEMINITSTARTBANK[7] ,Trigger shared memory initialization for bank 7" "Not triggered,Triggered"
|
|
bitfld.long 0x00 6. " [6] ,Trigger shared memory initialization for bank 6" "Not triggered,Triggered"
|
|
bitfld.long 0x00 5. " [5] ,Trigger shared memory initialization for bank 5" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Trigger shared memory initialization for bank 4" "Not triggered,Triggered"
|
|
bitfld.long 0x00 3. " [3] ,Trigger shared memory initialization for bank 3" "Not triggered,Triggered"
|
|
bitfld.long 0x00 2. " [2] ,Trigger shared memory initialization for bank 2" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Trigger shared memory initialization for bank 1" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " [0] ,Writing '1' will trigger shared memory initialization for bank 0" "Not triggered,Triggered"
|
|
line.long 0x04 "MEMINITDONESHMEM,Shared Memory Initialization End Register"
|
|
bitfld.long 0x04 7. " MEMINITDONEBANK[7] ,Memory initialization done status for shared memory for bank 7" "Pending,Done"
|
|
bitfld.long 0x04 6. " [6] ,Memory initialization done status for shared memory for bank 6" "Pending,Done"
|
|
bitfld.long 0x04 5. " [5] ,Memory initialization done status for shared memory for bank 5" "Pending,Done"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Memory initialization done status for shared memory for bank 4" "Pending,Done"
|
|
bitfld.long 0x04 3. " [3] ,Memory initialization done status for shared memory for bank 3" "Pending,Done"
|
|
bitfld.long 0x04 2. " [2] ,Memory initialization done status for shared memory for bank 2" "Pending,Done"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Memory initialization done status for shared memory for bank 1" "Pending,Done"
|
|
bitfld.long 0x04 0. " [0] ,Memory initialization done status for shared memory for bank 0" "Pending,Done"
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "DSSMEMTAB0,Controls Ordering Of Banks In Shared Memory Associated With DSS Register"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x00 28.--31. " DSSMEMTAB0[7] ,DSS L3RAM shared memory bank number 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " [6] ,DSS L3RAM shared memory bank number 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " [5] ,DSS L3RAM shared memory bank number 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " [4] ,DSS L3RAM shared memory bank number 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " [3] ,DSS L3RAM shared memory bank number 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " [2] ,DSS L3RAM shared memory bank number 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " [1] ,DSS L3RAM shared memory bank number 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " [0] ,DSS L3RAM shared memory bank number 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x2BC++0x07
|
|
line.long 0x00 "TCMAMEMTAB,Controls Ordering Of Banks In Shared Memory Associated With MSS TCMA Register"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x00 12.--15. " TCMAMEMTAB[3] ,MSS TCMA shared memory bank number 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " [2] ,MSS TCMA shared memory bank number 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " [1] ,MSS TCMA shared memory bank number 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " [0] ,MSS TCMA shared memory bank number 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hexmask.long.word 0x00 0.--15. 1. " TCMAMEMTAB ,MSS TCMA memory table for shared memory"
|
|
endif
|
|
line.long 0x04 "TCMBMEMTAB,Controls Ordering of Banks in Shared Memory Associated with MSS TCMB Register"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x04 12.--15. " TCMBMEMTAB[3] ,MSS TCMB shared memory bank number 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " [2] ,MSS TCMB shared memory bank number 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " [1] ,MSS TCMB shared memory bank number 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " [0] ,MSS TCMB shared memory bank number 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
hexmask.long.word 0x04 0.--15. 1. " TCMBMEMTAB ,MSS TCMB memory table for shared memory"
|
|
endif
|
|
group.long 0x2C8++0x0B
|
|
line.long 0x00 "SHMEMBANKSEL3TO0,Shared Memory Master Allocation Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BANK3 ,Bank3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BANK2 ,Bank2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " BANK1 ,Bank1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " BANK0 ,Bank0"
|
|
line.long 0x04 "SHMEMBANKSEL7TO4,Shared Memory Master Allocation Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " BANK7 ,Bank7"
|
|
hexmask.long.byte 0x04 16.--23. 1. " BANK6 ,Bank6"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. " BANK5 ,Bank5"
|
|
hexmask.long.byte 0x04 0.--7. 1. " BANK4 ,Bank4"
|
|
line.long 0x08 "PBISTCLKCTL,PBIST Clock Control Register"
|
|
hexmask.long.byte 0x08 8.--15. 1. " PBIST300MCLKGATE ,Pre clock divider gate for PBIST300M clock"
|
|
bitfld.long 0x08 4.--7. " PBIST300MCLKSRCSEL ,DSP PBIST clock source select" "CPUCLK,RCCLK,600-MHz PLL,,RCCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
bitfld.long 0x08 0.--3. " PBIST300MCLKDIV ,Divide value for DSP PBIST source clock" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
tree.end
|
|
base ad:0xFFFFFF00
|
|
tree "MSS RCM Registers"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "SOFTRST1,Sys Soft Reset 1 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CR4SYSRST ,MSS CR4 only reset"
|
|
line.long 0x04 "SOFTRST2,System Software Reset 2 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " VIMRST ,VIM only reset"
|
|
group.long 0x18++0x0B
|
|
line.long 0x00 "CLKDIVCTL0,Clock Divider Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " FDCANCLKDIV ,Divide value for FDCAN source clock"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DCANCLKDIV ,Divide value for DCAN source clock"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VCLKCLKDIV ,Divide value for MSS subsystem source clock"
|
|
line.long 0x04 "CLKSRCSEL0,Clock Source Select Register"
|
|
bitfld.long 0x04 16.--19. " QSPICLKSRCSEL ,Select clock source for QSPI baud clock" "MSS_VCLK,RCCLK,600-mHz PLL,,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
bitfld.long 0x04 8.--11. " FRAYCLKSRCSEL ,Select clock source for FRAY" "MSS_VCLK,RCCLK,600-mHz PLL,,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
bitfld.long 0x04 0.--3. " DCANCLKSRCSEL ,Select clock source for DCAN" "MSS_VCLK,RCCLK,600-mHz PLL,,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
line.long 0x08 "CR4CTL,CR4CTL Register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " MEMSWAPWAIT ,MEMSWAPWAIT"
|
|
hexmask.long.byte 0x08 8.--15. 1. " CR4MEMSWAP ,CR4MEMSWAP"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CLKGATE,Clock Gate Register"
|
|
bitfld.long 0x00 5. " FDCANCLKGATE ,Pre clock divider gate for FDCAN clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DCANCLKGATE ,Pre clock divider gate for DCAN clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " QSPICLKGATE ,Pre clock divider gate for QSPI clock" "Disabled,Enabled"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CLKSRCSEL1,Clock Source Select Register"
|
|
bitfld.long 0x00 0.--3. " VCLKCLKSRCSEL ,Select clock source for MSS subsystem VCLK" "CPUCLK,RCCLK,600-mHz,,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "CURRCLKDIV0,Current Clock Divider 0 Register"
|
|
sif cpuis("AWR1843*")
|
|
hexmask.long.byte 0x00 24.--31. 1. " FDCANCURRCLKDIV ,Current divide value of FDCAN baud clock divider"
|
|
else
|
|
hexmask.long.byte 0x00 24.--31. 1. " FRAYCURRCLKDIV ,Current divide value of FRAY baud clock divider"
|
|
endif
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " DCANCURRCLKDIV ,Current divide value of DCAN baud clock divider"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VCLKCURRCLKDIV ,Current divide value of VCLK divider"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "MEMINITSTART,Memory Initialization Trigger Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MEMINITKEY ,Memory hardware initialization global enable key"
|
|
bitfld.long 0x00 17. " BSSMBOX4GEMMEM ,DSS-BSS mailbox initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 16. " MSSMBOX4GEMMEM ,DSS-MSS mailbox initialization" "Not initialized,Initialized"
|
|
newline
|
|
bitfld.long 0x00 15. " GEMMBOX4MSSMEM ,DSS-MSS mailbox initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 14. " GEMMBOX4BSSMEM ,DSS-BSS mailbox initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 9. " DMA2MEM ,DMA2 memory initialization" "Not initialized,Initialized"
|
|
newline
|
|
bitfld.long 0x00 8. " BSSMBOX4MSSMEM ,BSS mail box FO MSS memory initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 7. " MSSMBOX4BSSMEM ,MSS mail box FO BSS memory initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 6. " DCANMEM ,DCAN memory initialization" "Not initialized,Initialized"
|
|
newline
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x00 5. " SPIBMEM ,SPIB memory initialization" "Not initialized,Initialized"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 4. " SPIAMEM ,SPIA memory initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 3. " VIMMEM ,VIM memory initialization" "Not initialized,Initialized"
|
|
newline
|
|
bitfld.long 0x00 2. " DMAMEM ,DMA memory initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 1. " CR4TCMBMEM ,MSS TCMB memory initialization" "Not initialized,Initialized"
|
|
bitfld.long 0x00 0. " CR4TCMAMEM ,MSS TCMA memory initialization" "Not initialized,Initialized"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "CURRCLKDIV1,Current Clock Divider 1 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " QSPICURRCLKDIV ,Current divide value of QSPI_CLK divider"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "MEMINITDONE,Memory Initialization Done Register"
|
|
bitfld.long 0x00 17. " BSSMBOX4GEMMEM ,Memory Initialization done status for DSS- BSS mailbox" "Not done,Done"
|
|
bitfld.long 0x00 16. " MSSMBOX4GEMMEM ,Memory Initialization done status for DSS- MSS mailbox" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 15. " GEMMBOX4MSSMEM ,Memory Initialization done status for DSS- MSS mailbox" "Not done,Done"
|
|
bitfld.long 0x00 14. " GEMMBOX4BSSMEM ,Memory Initialization done status for DSS- BSS mailbox" "Not done,Done"
|
|
bitfld.long 0x00 9. " DMA2MEM ,Memory Initialization done status for MSS DMA2 memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 8. " BSSMBOX4MSSMEM ,Memory initialization done status for BSS mailbox MSS memory" "Not done,Done"
|
|
bitfld.long 0x00 7. " MSSMBOX4BSSMEM ,Memory initialization done status for MSS mailbox for BSS memory" "Not done,Done"
|
|
bitfld.long 0x00 6. " DCANMEM ,Memory initialization done status for DCAN memory" "Not done,Done"
|
|
newline
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x00 5. " SPIBMEM ,Memory initialization done status for MSS SPIB memory" "Not done,Done"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 4. " SPIAMEM ,Memory initialization done status for MSS SPIA memory" "Not done,Done"
|
|
bitfld.long 0x00 3. " VIMMEM ,Memory initialization done status for MSS VIM memory" "Not done,Done"
|
|
bitfld.long 0x00 2. " DMAMEM ,Memory initialization done status for MSS DMA memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 1. " CR4TCMBMEM ,Memory initialization done status for MSS TCMB memory" "Not done,Done"
|
|
bitfld.long 0x00 0. " CR4TCMAMEM ,Memory initialization done status for MSS TCMA memory" "Not done,Done"
|
|
newline
|
|
group.long 0x70++0x0F
|
|
line.long 0x00 "ECCENMSSGEM,ECC Enable MSSGEM Register"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x00 19.--21. " GEM_MSS_ADDR_CLR ,Write 3'b111 to clear address captured due to ECC error in GEM mbox for MSS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " MSS_GEM_ADDR_CLR ,Write 3'b111 to clear address captured due to ECC error in MSS mbox for GEM" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ECC_MSS_DSS_EN0 ,Enable ECC for MSS-DSS mailbox"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ECC_MSS_DSS_EN1 ,Enable ECC for MSS-DSS mailbox"
|
|
endif
|
|
line.long 0x04 "ECCCAPTMSSGEM,ECC CAPT MSSGEM Register"
|
|
sif cpuis("AWR1843*")
|
|
hexmask.long.byte 0x04 24.--30. 1. " GEM_MBOX4MSS_REPAIRED_BIT ,GEM mailbox for MSS repaired bit"
|
|
hexmask.long.byte 0x04 16.--23. 0x01 " GEM_MBOX4MSS_ECC_FAULT_ADDRESS ,GEM mailbox for MSS repaired bit"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--14. 1. " MSS_MBOX4GEM_REPAIRED_BIT ,MSS mailbox for GEM repaired bit"
|
|
hexmask.long.byte 0x04 0.--7. 0x01 " MSS_MBOX4GEM_ECC_FAULT_ADDRESS ,MSS mailbox for GEM repaired bit"
|
|
endif
|
|
line.long 0x08 "ECCENBSSGEM,ECC Enable BSSGEM Register"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x08 19.--21. " GEM_BSS_ADDR_CLR ,Write 3'b111 to clear address captured due to ECC error in GEM mbox for BSS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 16.--18. " BSS_GEM_ADDR_CLR ,Write 3'b111 to clear address captured due to ECC error in BSS mbox for GEM" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x08 8.--15. 1. " ECC_MSS_BSS_EN1 ,Enable ECC for MSS-BSS mailbox"
|
|
hexmask.long.byte 0x08 0.--7. 1. " ECC_MSS_BSS_EN0 ,Enable ECC for MSS-BSS mailbox"
|
|
endif
|
|
line.long 0x0C "ECCCAPTBSSGEM,ECC CAPT BSSGEM Register"
|
|
sif cpuis("AWR1843*")
|
|
hexmask.long.byte 0x0C 24.--30. 1. " GEM_MBOX4BSS_REPAIRED_BIT ,GEM mailbox for BSS repaired bit"
|
|
hexmask.long.byte 0x0C 16.--23. 0x01 " GEM_MBOX4BSS_ECC_FAULT_ADDRESS ,GEM mailbox for BSS repaired bit"
|
|
newline
|
|
hexmask.long.byte 0x0C 8.--14. 1. " BSS_MBOX4GEM_REPAIRED_BIT ,BSS mailbox for GEM repaired bit"
|
|
hexmask.long.byte 0x0C 0.--7. 0x01 " BSS_MBOX4GEM_ECC_FAULT_ADDRESS ,BSS mailbox for GEM repaired bit"
|
|
newline
|
|
endif
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "USERMODEEN,User Mode Access Enable Register"
|
|
line.long 0x04 "NSYSPERUSERMODEN,NSYSPER User Mode Enable Register"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x04 24.--26. " DCAN_UM_EN ,Enable user mode access to DCAN" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 19.--21. " SCIB_UM_EN ,Enable user mode access to SCIB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--18. " SCIA_UM_EN ,Enable user mode access to SCIA" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 11.--13. " QSPI_UM_EN ,Enable user mode access to QSPI" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 8.--10. " GIO_UM_EN ,Enable user mode access to GIO" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 3.--5. " SPIB_UM_EN ,Enable user mode access to SPIB" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " SPIA_UM_EN ,Enable user mode access to SPIA" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
line.long 0x08 "SECURERAMMMI,Secure RAM MMI Register"
|
|
rbitfld.long 0x08 16. " SECURERAMINITDONE ,Memory initialization done status for Secure Key RAM" "Not done,Done"
|
|
bitfld.long 0x08 0. " SECURERAMINIT ,Secure Key RAM memory initialization" "Not initialized,Initialized"
|
|
line.long 0x0C "SECURERAMECC,Secure RAM ECC Register"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " SECURERAMBIT ,Secure key RAM repaired bit"
|
|
hexmask.long.byte 0x0C 16.--23. 0x01 " SECURERAMADDR ,Secure key RAM ECC fault address"
|
|
newline
|
|
bitfld.long 0x0C 8.--10. " SECURERAMECCCLR ,Write 3'b111 to clear address captured due to ECC error" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " SECURERAMECCEN ,ECC for secure key RAM"
|
|
group.long 0x90++0x13
|
|
line.long 0x00 "ESMGATE0,ESM Gate 0 Register"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x00 28.--31. " LINE[7] ,Gate ESM group 2 line 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " [6] ,Gate ESM group 2 line 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " [5] ,Gate ESM group 2 line 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " [4] ,Gate ESM group 2 line 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " [3] ,Gate ESM group 2 line 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " [2] ,Gate ESM group 2 line 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " [1] ,Gate ESM group 2 line 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " [0] ,Gate ESM group 2 line 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x04 "ESMGATE1,ESM Gate 1 Register"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x04 28.--31. " LINE[15] ,Gate ESM group 2 line 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. " [14] ,Gate ESM group 2 line 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 20.--23. " [13] ,Gate ESM group 2 line 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 16.--19. " [12] ,Gate ESM group 2 line 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " [11] ,Gate ESM group 2 line 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " [10] ,Gate ESM group 2 line 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " [9] ,Gate ESM group 2 line 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " [8] ,Gate ESM group 2 line 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x08 "ESMGATE2,ESM Gate 2 Register"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x08 28.--31. " LINE[23] ,Gate ESM group 2 line 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 24.--27. " [22] ,Gate ESM group 2 line 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 20.--23. " [21] ,Gate ESM group 2 line 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 16.--19. " [20] ,Gate ESM group 2 line 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x08 12.--15. " [19] ,Gate ESM group 2 line 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--11. " [18] ,Gate ESM group 2 line 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 4.--7. " [17] ,Gate ESM group 2 line 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. " [16] ,Gate ESM group 2 line 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x0C "ESMGATE3,ESM Gate 3 Register"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x0C 28.--31. " LINE[23] ,Gate ESM group 2 line 23" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 24.--27. " [22] ,Gate ESM group 2 line 22" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 20.--23. " [21] ,Gate ESM group 2 line 21" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 16.--19. " [20] ,Gate ESM group 2 line 20" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x0C 12.--15. " [19] ,Gate ESM group 2 line 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 8.--11. " [18] ,Gate ESM group 2 line 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 4.--7. " [17] ,Gate ESM group 2 line 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. " [16] ,Gate ESM group 2 line 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
line.long 0x10 "ESMGATE4,ESM Gate 4 Register"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x10 28.--31. " LINE[7] ,Gate ESM group 3 line 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 24.--27. " [6] ,Gate ESM group 3 line 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 20.--23. " [5] ,Gate ESM group 3 line 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--19. " [4] ,Gate ESM group 3 line 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x10 12.--15. " [3] ,Gate ESM group 3 line 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8.--11. " [2] ,Gate ESM group 3 line 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 4.--7. " [1] ,Gate ESM group 3 line 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " [0] ,Gate ESM group 3 line 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "KEY,CFGREG Access Key Register"
|
|
group.long 0xB8++0x1B
|
|
line.long 0x00 "SWIRQA,SWIRQ 0 Register"
|
|
sif cpuis("AWR1843*")
|
|
hexmask.long.byte 0x00 24.--31. 1. " SWIRQ1 ,System software interrupt trigger 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SWIRQ0 ,System software interrupt trigger 0"
|
|
else
|
|
hexmask.long.byte 0x00 24.--31. 1. " SWIRQ1 ,System software interrupt trigger 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SWIRQ1DAT ,System software interrupt data"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SWIRQ0 ,System software interrupt trigger 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SWIRQ0DAT ,System software interrupt data"
|
|
endif
|
|
line.long 0x04 "SWIRQB,SWIRQ 1 Register"
|
|
sif cpuis("AWR1843*")
|
|
hexmask.long.byte 0x04 24.--31. 1. " SWIRQ3 ,System software interrupt trigger 3"
|
|
hexmask.long.byte 0x04 8.--15. 1. " SWIRQ2 ,System software interrupt trigger 2"
|
|
else
|
|
hexmask.long.byte 0x04 24.--31. 1. " SWIRQ3 ,System software interrupt trigger 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " SWIRQ3DAT ,System software interrupt data"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. " SWIRQ2 ,System software interrupt trigger 2"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SWIRQ2DAT ,System software interrupt data"
|
|
endif
|
|
line.long 0x08 "MISCCTL0,Miscellaneous Control Register"
|
|
bitfld.long 0x08 22.--24. " TCMB1EZDIS ,TCMB1 EZ disable" "EZ=0,EZ=0,EZ=0,EZ=0,EZ=0,EZ=0,EZ=0,EZ=1"
|
|
bitfld.long 0x08 19.--21. " TCMB0EZDIS ,TCMB0 EZ disable" "EZ=0,EZ=0,EZ=0,EZ=0,EZ=0,EZ=0,EZ=0,EZ=1"
|
|
bitfld.long 0x08 16.--18. " TCMAEZDIS ,TCMA EZ disable" "EZ=0,EZ=0,EZ=0,EZ=0,EZ=0,EZ=0,EZ=0,EZ=1"
|
|
line.long 0x0C "ATCMERRCAPTCTL,A TCM Error CAPTCTL Register"
|
|
hexmask.long.tbyte 0x0C 8.--27. 0x01 " ERRATCADDR ,TCM address for which parity error happened"
|
|
bitfld.long 0x0C 3.--5. " ATCFORCEERR ,ATC error force" ",Not forced,Not forced,Not forced,Not forced,Not forced,Not forced,Forced"
|
|
bitfld.long 0x0C 0.--2. " ERRATCADDRCLR ,Re-enable latching" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "B0TCMERRCAPTCTL,B0 TCM Error CAPTCTL Register"
|
|
hexmask.long.tbyte 0x10 8.--27. 0x01 " ERRB0TCADDR ,TCM address for which parity error happened"
|
|
bitfld.long 0x10 3.--5. " B0TCFORCEERR ,B0TC error force" ",Not forced,Not forced,Not forced,Not forced,Not forced,Not forced,Forced"
|
|
bitfld.long 0x10 0.--2. " ERRB0TCADDRCLR ,Re-enable the latching" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "B1TCMERRCAPTCTL,B1 TCM Error CAPTCTL Register"
|
|
hexmask.long.tbyte 0x14 8.--27. 0x01 " ERRB1TCADDR ,TCM address for which parity error happened"
|
|
bitfld.long 0x14 3.--5. " B1TCFORCEERR ,B1TC error force" ",Not forced,Not forced,Not forced,Not forced,Not forced,Not forced,Forced"
|
|
bitfld.long 0x14 0.--2. " ERRB1TCADDRCLR ,Re-enable latching" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "SOFTCORERST,Software CORE Reset Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " RST_WFICHECKEN ,Reset WFI check enable"
|
|
hexmask.long.byte 0x18 8.--15. 1. " RSTTOASSRTDLY ,Programmed number of clock cycle before reset is asserted"
|
|
rgroup.long 0xD8++0x07
|
|
line.long 0x00 "RSTCAUSE,MSS RST Cause Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MSS_RCM ,RST cause"
|
|
line.long 0x04 "RSTCAUSECLR,MSS RST Cause Clear Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RSTCAUSECLR ,RST cause clear"
|
|
newline
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "SPITRIGSRC,SPI Trigger Source Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " SPIBTRIG ,Trigger sources for MIBSPIB"
|
|
bitfld.long 0x00 8. " SPIATRIG1 ,1st bit of trigger source input of SPIA" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SPIATRIG0 ,0th bit of trigger source input of SPIA" "Disabled,Enabled"
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "CLKINUSE,MSS Clock In Use Register"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x00 12.--15. " QSPICLKINUSE ,Current clock source select MUX value for QSPI clock" "VCLK,RCCLK,600Mhz PLL,240Mhz PLL,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
bitfld.long 0x00 8.--11. " DCANCLKINUSE ,Current clock source select MUX value for DCAN clock" "VCLK,RCCLK,600Mhz PLL,240Mhz PLL,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
bitfld.long 0x00 4.--7. " FRAYCLKINUSE ,Current clock source select MUX value for fray clock" "VCLK,RCCLK,600Mhz PLL,240Mhz PLL,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
bitfld.long 0x00 0.--3. " VCLKINUSE ,Current clock source select MUX value for VCLK" "VCLK,RCCLK,600Mhz PLL,240Mhz PLL,CPUCLK,RCCLK,REFCLK,RCCLK,?..."
|
|
else
|
|
bitfld.long 0x00 12.--15. " QSPICLKINUSE ,Current clock source select MUX value for QSPI clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " DCANCLKINUSE ,Current clock source select MUX value for DCAN clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " FRAYCLKINUSE ,Current clock source select MUX value for fray clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " VCLKINUSE ,Current clock source select MUX value for VCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "ECCEN,MSS ECC Enable Register"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x00 19.--21. " BSS_MSS_ADDR_CLR ,Write 3'b111 to clear address captured due to ECC error in BSS mbox for MSS" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " MSS_BSS_ADDR_CLR ,Write 3'b111 to clear address captured due to ECC error in MSS mbox for BSS" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ECC_MSS_BSS_EN1 ,Enable ECC for MSS-BSS mailbox"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ECC_MSS_BSS_EN0 ,Enable ECC for MSS-BSS mailbox"
|
|
endif
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "ECCCAPT,MSS ECC Capture Register"
|
|
sif cpuis("AWR1843*")
|
|
hexmask.long.byte 0x00 24.--30. 1. " BSS_MBOX4MSS_REPAIRED_BIT ,BSS mailbox for MSS repaired bit"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " BSS_MBOX4MSS_ECC_FAULT_ADDRESS ,BSS mailbox for MSS repaired bit"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. " MSS_MBOX4BSS_REPAIRED_BIT ,MSS mailbox for BSS repaired bit"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " MSS_MBOX4BSS_ECC_FAULT_ADDRESS ,MSS mailbox for BSS repaired bit"
|
|
endif
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CLKDIVCTL2,Clock Divide Control 2 Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " QSPICLKDIV ,Divide value for QSPI baud clock selected by field QSPICLKSRCSEL"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "SWIRQC,SW IRQ2 Register"
|
|
sif cpuis("AWR1843*")
|
|
hexmask.long.byte 0x00 24.--31. 1. " SWIRQ5 ,Trigger interrupt 5"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SWIRQ4 ,Trigger interrupt 4"
|
|
else
|
|
hexmask.long.byte 0x00 24.--31. 1. " SWIRQ5 ,Trigger interrupt 5"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SWIRQ5DAT ,System software interrupt data 5"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " SWIRQ4 ,Trigger interrupt 4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SWIRQ4DAT ,System software interrupt data 4"
|
|
endif
|
|
tree.end
|
|
base ad:0xFFFFF800
|
|
tree "MSS GPCFG REG Registers"
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "GPCFG0,General Purpose Config Register 0"
|
|
line.long 0x04 "GPCFG1,General Purpose Config Register 1"
|
|
line.long 0x08 "GPCFG2,General Purpose Config Register 2"
|
|
line.long 0x0C "GPCFG3,General Purpose Config Register 3"
|
|
line.long 0x10 "GPCFG4,General Purpose Config Register 4"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "GPCFG11,General Purpose Config Register 11"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x00 17. " BSS2DSSSWIRQ2 ,Self clearing register bit to generate interrupt to DSP from BSS" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " BSS2DSSSWIRQ1 ,Self clearing register bit to generate interrupt to DSP from BSS" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " DSS2BSSSWIRQ2 ,Self clearing register bit to generate interrupt to BSS from DSP" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8. " DSS2BSSSWIRQ1 ,Self clearing register bit to generate interrupt to BSS from DSP" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " MSS2BSSSWIRQ2 ,Self clearing register bit to generate interrupt to BSS from MSS" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MSS2BSSSWIRQ1 ,Self clearing register bit to generate interrupt to BSS from MSS" "No interrupt,Interrupt"
|
|
else
|
|
eventfld.long 0x00 17. " BSS2DSSSWIRQ2 ,Self clearing register bit to generate interrupt to DSP from BSS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " BSS2DSSSWIRQ1 ,Self clearing register bit to generate interrupt to DSP from BSS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " DSS2BSSSWIRQ2 ,Self clearing register bit to generate interrupt to BSS from DSP" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " DSS2BSSSWIRQ1 ,Self clearing register bit to generate interrupt to BSS from DSP" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " MSS2BSSSWIRQ2 ,Self clearing register bit to generate interrupt to BSS from MSS" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " MSS2BSSSWIRQ1 ,Self clearing register bit to generate interrupt to BSS from MSS" "No interrupt,Interrupt"
|
|
endif
|
|
group.long 0xD0++0x1F
|
|
line.long 0x00 "CCCACFG0,CCC A Configuration 0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " MARGIN_COUNT ,Margin value for clock comparison"
|
|
newline
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x00 8. " SINGLE_SHOT_MODE ,Single shot mode" "Continuous,Single shot"
|
|
else
|
|
bitfld.long 0x00 8. " SINGLE_SHOT_MODE ,Single shot mode" "Single shot,Continuous"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 7. " ENABLE_MODULE ,CCC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DISABLE_CLOCKS ,Clock disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3.--5. " CLOCK1_SEL ,Clock 1 select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " CLOCK0_SEL ,Clock 0 select" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "CCCACFG1,CCC A Configuration 1 Register"
|
|
line.long 0x08 "CCCACFG2,CCC A Configuration 2 Register"
|
|
line.long 0x0C "CCCACFG3,CCC A Configuration 3 Register"
|
|
line.long 0x10 "CCCBCFG0,CCC B Configuration 0 Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " MARGIN_COUNT ,Margin value for clock comparison"
|
|
newline
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x10 8. " SINGLE_SHOT_MODE ,Single shot mode" "Continuous,Single shot"
|
|
else
|
|
bitfld.long 0x10 8. " SINGLE_SHOT_MODE ,Single shot mode" "Single shot,Continuous"
|
|
endif
|
|
newline
|
|
bitfld.long 0x10 7. " ENABLE_MODULE ,CCC enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " DISABLE_CLOCKS ,Clock disables" "No,Yes"
|
|
newline
|
|
bitfld.long 0x10 3.--5. " CLOCK1_SEL ,Clock 1 select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0.--2. " CLOCK0_SEL ,Clock 0 select" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "CCCBCFG1,CCC B Configuration 1 Register"
|
|
line.long 0x18 "CCCBCFG2,CCC B Configuration 2 Register"
|
|
line.long 0x1C "CCCBCFG3,CCC B Configuration 3 Register"
|
|
rgroup.long 0xF0++0x0B
|
|
line.long 0x00 "CCCACNTVAL,CCC A Count Value Register"
|
|
line.long 0x04 "CCCBCNTVAL,CCC B Count Value Register"
|
|
line.long 0x08 "CCCABERRSTAT,CCC AB Error Status Register"
|
|
sif cpuis("AWR1843*")
|
|
hexmask.long.byte 0x08 8.--15. 1. " CCCB_ERR_STS ,CCCB error status"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CCCA_ERR_STS ,CCCA error status"
|
|
endif
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "USERMODEEN,User Mode Access Enable Register"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "EPWMCFG,EPWM Configuration Register"
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x00 4.--5. " EPWM3_SYNCIN ,SYNCIN to EPWM3 select" "Rampgen,FRC,External,External"
|
|
bitfld.long 0x00 2.--3. " EPWM2_SYNCIN ,SYNCIN to EPWM2 select" "Rampgen,FRC,External,External"
|
|
bitfld.long 0x00 0.--1. " EPWM1_SYNCIN ,SYNCIN to EPWM1 select" "Rampgen,FRC,External,External"
|
|
endif
|
|
group.long 0x148++0x17
|
|
line.long 0x00 "DMMSWINT0,DMM SW Interrupt 0 Register"
|
|
line.long 0x04 "DMMSWINT1,DMM SW Interrupt 1 Register"
|
|
line.long 0x08 "DMMSWINTSEL0,DMM SW Interrupt Select 0 Register"
|
|
line.long 0x0C "DMMSWINTSEL1,DMM SW Interrupt Select 1 Register"
|
|
line.long 0x10 "CCCBWDEN,CCC BWD Enable Register"
|
|
bitfld.long 0x10 16. " ENABLECCBERRRSTN ,Enable CCCB error to generate WD rest" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " ENABLECCBERRNMI ,Enable CCCB error to generate NMI" "Disabled,Enabled"
|
|
line.long 0x14 "GPIOINTREDGESEL,GPIO Interrupt Edge Select Register"
|
|
bitfld.long 0x14 2. " GPIO2EDGESEL ,GPIO2 edge select" "Positive,Negative"
|
|
bitfld.long 0x14 1. " GPIO1EDGESEL ,GPIO1 edge select" "Positive,Negative"
|
|
bitfld.long 0x14 0. " GPIO0EDGESEL ,GPIO0 edge select" "Positive,Negative"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "PWMDMATRIGEN,PWM DMA Trigger Enable Register"
|
|
bitfld.long 0x00 0.--3. " PWMDMATRIGEN ,PWM DMA trigger enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x168++0x07
|
|
line.long 0x00 "JTAGTXDATA,JTAG TX Data Register"
|
|
line.long 0x04 "JTAGTXCONTROL,JTAG TX Control Register"
|
|
sif cpuis("AWR1843*")
|
|
hexmask.long 0x04 1.--31. 1. " JTAGTXCONTROL ,JTAG TX control"
|
|
endif
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "JTAGRXDATA,JTAG RX Data Register"
|
|
group.long 0x178++0x0F
|
|
line.long 0x00 "JTAGTXRXACK,JTAG TX RX ACK Register"
|
|
bitfld.long 0x00 8. " JTAGRXDATAWR ,Indication from system security logic that JTAGRXDATA is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 0. " JTAGTXDATARD ,Indication from the system security logic that JTAGTXDATA has been accepted" "Not accepted,Accepted"
|
|
line.long 0x04 "JTAGRXCONTROL,JTAG RX Control Register"
|
|
sif cpuis("AWR1843*")
|
|
hexmask.long 0x04 1.--31. 1. " JTAGTXCONTROL ,JTAG TX control"
|
|
endif
|
|
line.long 0x08 "MSS2GEMSWIRQ,MSS 2 GEM SWIRQ Register"
|
|
bitfld.long 0x08 1. " MSS2GEMSWIRQ2 ,Self clearing register bit to generate interrupt to DSP from MSS" "Not generated,Generated"
|
|
bitfld.long 0x08 0. " MSS2GEMSWIRQ1 ,Self clearing register bit to generate interrupt to DSP from MSS" "Not generated,Generated"
|
|
line.long 0x0C "CSETBFLUSH,C SETB FLUSH Register"
|
|
rbitfld.long 0x0C 10. " CSETBFULL ,Indicates that the ETB RAM has overflowed or wrapped around to address zero" "No overflow,Overflow"
|
|
rbitfld.long 0x0C 9. " CSETBACQ_OMPLETE ,Indicates that trace acquisition is complete by ETB" "Not completed,Completed"
|
|
newline
|
|
rbitfld.long 0x0C 8. " CSETBFLUSHINACK ,Return acknowledgment to CSETBFLUSHIN" "Not returned,Returned"
|
|
bitfld.long 0x0C 0. " CSETBFLUSHIN ,External control used to assert the ATB signal AFVALIDS and drain any historical FIFO information on the bus" "Disabled,Enabled"
|
|
tree.end
|
|
width 0x0B
|
|
tree "DSS REG Registers"
|
|
base ad:0x50000400
|
|
width 22.
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "RTIEVENTCAPTURESEL,RTI1 Event Capture Select Register"
|
|
bitfld.long 0x00 16.--19. " EVT[1] ,Source of interrupt for Counter value capture for RTI1 Event 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " [0] ,Source of interrupt for Counter value capture for RTI1 Event 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CQCFG1,CQ0 Configuration 1 Register"
|
|
hexmask.long.word 0x00 22.--30. 0x40 " CQ2BASEADDR ,Address to be added to be internal address pointer for CQ2"
|
|
hexmask.long.word 0x00 13.--21. 0x20 " CQ1BASEADDR ,Address to be added to be internal address pointer for CQ1"
|
|
hexmask.long.word 0x00 4.--12. 0x10 " CQ0BASEADDR ,Address to be added to be internal address pointer for CQ0"
|
|
newline
|
|
bitfld.long 0x00 3. " CQ96BITPACKEN ,This is used to pack the CQ data into only the LSB 96 bits of each row of the CQ memory" "0,1"
|
|
newline
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x00 0.--1. " CQDATAWIDTH ,This is used to appropriately pack the valid CQ data bits in appropriate bits in the CQ memory" "Raw 16,Raw 16,Raw 12,Raw 14"
|
|
else
|
|
bitfld.long 0x00 0.--1. " CQDATAWIDTH ,This is used to appropriately pack the valid CQ data bits in appropriate bits in the CQ memory" "0,Raw 16,Raw 12,Raw 14"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TPCCPARSTATCFG,TPCCPARSTATCFG"
|
|
bitfld.long 0x00 10. " TPCCPARITYTSTEN ,Enable bit for the self test of the parity logic in TPCC" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TPCCPARITYEN ,Enable bit for the parity computation in TPCC" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TPCCPARITYCLR ,Clear bit for the parity error from TPCC" "Not cleared,Cleared"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " TPCCPARITYSTAT ,Parity address from TPCC"
|
|
group.long 0x104++0x17
|
|
line.long 0x00 "TPTC0WRMPUSTADD0,TPTC0 Write MPU Start Address 0 Register"
|
|
line.long 0x04 "TPTC0WRMPUSTADD1,TPTC0 Write MPU Start Address 1 Register"
|
|
line.long 0x08 "TPTC0WRMPUSTADD2,TPTC0 Write MPU Start Address 2 Register"
|
|
line.long 0x0C "TPTC0WRMPUSTADD3,TPTC0 Write MPU Start Address 3 Register"
|
|
line.long 0x10 "TPTC0WRMPUSTADD4,TPTC0 Write MPU Start Address 4 Register"
|
|
line.long 0x14 "TPTC0WRMPUSTADD5,TPTC0 Write MPU Start Address 5 Register"
|
|
group.long 0x124++0x17
|
|
line.long 0x00 "TPTC0WRMPUENDADD0,TPTC0 Write MPU End Address 0 Register"
|
|
line.long 0x04 "TPTC0WRMPUENDADD1,TPTC0 Write MPU End Address 1 Register"
|
|
line.long 0x08 "TPTC0WRMPUENDADD2,TPTC0 Write MPU End Address 2 Register"
|
|
line.long 0x0C "TPTC0WRMPUENDADD3,TPTC0 Write MPU End Address 3 Register"
|
|
line.long 0x10 "TPTC0WRMPUENDADD4,TPTC0 Write MPU End Address 4 Register"
|
|
line.long 0x14 "TPTC0WRMPUENDADD5,TPTC0 Write MPU End Address 5 Register"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "TPTC0WRMPUERRADD,TPTC0 Write MPU Error Address Register"
|
|
group.long 0x148++0x17
|
|
line.long 0x00 "TPTC0RDMPUSTADD0,TPTC0 Read MPU Start Address 0 Register"
|
|
line.long 0x04 "TPTC0RDMPUSTADD1,TPTC0 Read MPU Start Address 1 Register"
|
|
line.long 0x08 "TPTC0RDMPUSTADD2,TPTC0 Read MPU Start Address 2 Register"
|
|
line.long 0x0C "TPTC0RDMPUSTADD3,TPTC0 Read MPU Start Address 3 Register"
|
|
line.long 0x10 "TPTC0RDMPUSTADD4,TPTC0 Read MPU Start Address 4 Register"
|
|
line.long 0x14 "TPTC0RDMPUSTADD5,TPTC0 Read MPU Start Address 5 Register"
|
|
group.long 0x168++0x17
|
|
line.long 0x00 "TPTC0RDMPUENDADD0,TPTC0 Read MPU End Address 0 Register"
|
|
line.long 0x04 "TPTC0RDMPUENDADD1,TPTC0 Read MPU End Address 1 Register"
|
|
line.long 0x08 "TPTC0RDMPUENDADD2,TPTC0 Read MPU End Address 2 Register"
|
|
line.long 0x0C "TPTC0RDMPUENDADD3,TPTC0 Read MPU End Address 3 Register"
|
|
line.long 0x10 "TPTC0RDMPUENDADD4,TPTC0 Read MPU End Address 4 Register"
|
|
line.long 0x14 "TPTC0RDMPUENDADD5,TPTC0 Read MPU End Address 5 Register"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "TPTC0RDMPUERRADD,TPTC0 Read MPU Error Address Register"
|
|
group.long 0x18C++0x17
|
|
line.long 0x00 "TPTC1WRMPUSTADD0,TPTC1 Write MPU Start Address 0 Register"
|
|
line.long 0x04 "TPTC1WRMPUSTADD1,TPTC1 Write MPU Start Address 1 Register"
|
|
line.long 0x08 "TPTC1WRMPUSTADD2,TPTC1 Write MPU Start Address 2 Register"
|
|
line.long 0x0C "TPTC1WRMPUSTADD3,TPTC1 Write MPU Start Address 3 Register"
|
|
line.long 0x10 "TPTC1WRMPUSTADD4,TPTC1 Write MPU Start Address 4 Register"
|
|
line.long 0x14 "TPTC1WRMPUSTADD5,TPTC1 Write MPU Start Address 5 Register"
|
|
group.long 0x1AC++0x17
|
|
line.long 0x00 "TPTC1WRMPUENDADD0,TPTC1 Write MPU End Address 0 Register"
|
|
line.long 0x04 "TPTC1WRMPUENDADD1,TPTC1 Write MPU End Address 1 Register"
|
|
line.long 0x08 "TPTC1WRMPUENDADD2,TPTC1 Write MPU End Address 2 Register"
|
|
line.long 0x0C "TPTC1WRMPUENDADD3,TPTC1 Write MPU End Address 3 Register"
|
|
line.long 0x10 "TPTC1WRMPUENDADD4,TPTC1 Write MPU End Address 4 Register"
|
|
line.long 0x14 "TPTC1WRMPUENDADD5,TPTC1 Write MPU End Address 5 Register"
|
|
rgroup.long 0x1CC++0x03
|
|
line.long 0x00 "TPTC1WRMPUERRADD,TPTC1 Write MPU Error Address Register"
|
|
group.long 0x1D0++0x17
|
|
line.long 0x00 "TPTC1RDMPUSTADD0,TPTC1 Read MPU Start Address 0 Register"
|
|
line.long 0x04 "TPTC1RDMPUSTADD1,TPTC1 Read MPU Start Address 1 Register"
|
|
line.long 0x08 "TPTC1RDMPUSTADD2,TPTC1 Read MPU Start Address 2 Register"
|
|
line.long 0x0C "TPTC1RDMPUSTADD3,TPTC1 Read MPU Start Address 3 Register"
|
|
line.long 0x10 "TPTC1RDMPUSTADD4,TPTC1 Read MPU Start Address 4 Register"
|
|
line.long 0x14 "TPTC1RDMPUSTADD5,TPTC1 Read MPU Start Address 5 Register"
|
|
group.long 0x1F0++0x17
|
|
line.long 0x00 "TPTC1RDMPUENDADD0,TPTC1 Read MPU End Address 0 Register"
|
|
line.long 0x04 "TPTC1RDMPUENDADD1,TPTC1 Read MPU End Address 1 Register"
|
|
line.long 0x08 "TPTC1RDMPUENDADD2,TPTC1 Read MPU End Address 2 Register"
|
|
line.long 0x0C "TPTC1RDMPUENDADD3,TPTC1 Read MPU End Address 3 Register"
|
|
line.long 0x10 "TPTC1RDMPUENDADD4,TPTC1 Read MPU End Address 4 Register"
|
|
line.long 0x14 "TPTC1RDMPUENDADD5,TPTC1 Read MPU End Address 5 Register"
|
|
rgroup.long 0x210++0x03
|
|
line.long 0x00 "TPTC1RDMPUERRADD,TPTC1 Read MPU Error Address Register"
|
|
group.long 0x214++0x07
|
|
line.long 0x00 "TPTCMPUVALIDCFG,TPTC MPU Valid Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TPTC1RDMPURNGVLD ,Valid bit for each address range for the MPU in the read port of TPTC1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TPTC1WRMPURNGVLD ,Valid bit for each address range for the MPU in the read port of TPTC1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TPTC0RDMPURNGVLD ,Valid bit for each address range for the MPU in the read port of TPTC1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " TPTC0WRMPURNGVLD ,Valid bit for each address range for the MPU in the read port of TPTC1"
|
|
line.long 0x04 "TPTCMPUENCFG,TPTC MPU Enable Configuration Register"
|
|
bitfld.long 0x04 7. " TPTC1RDMPUERRCLR ,Clear flag for error from the MPU in the read port of TPTC1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " TPTC1WRMPUERRCLR ,Clear flag for error from the MPU in the write port of TPTC1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " TPTC0RDMPUERRCLR ,Clear flag for error from the MPU in the read port of TPTC0" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 4. " TPTC0WRMPUERRCLR ,Clear flag for error from the MPU in the write port of TPTC0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " TPTC1RDMPUEN ,Enable bit for the MPU in the read port of TPTC1" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " TPTC1WRMPUEN ,Enable bit for the MPU in the write port of TPTC1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " TPTC0RDMPUEN ,Enable bit for the MPU in the read port of TPTC0" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TPTC0WRMPUEN ,Enable bit for the MPU in the write port of TPTC0" "Disabled,Enabled"
|
|
group.long 0x21C++0x0F
|
|
line.long 0x00 "TESTPATTERNRX1ICFG,Test Pattern RX1 I Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TSTPATRX1IINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 0"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " TSTPATRX1IOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 0"
|
|
line.long 0x04 "TESTPATTERNRX2ICFG,TEST Pattern RX2 I Configuration Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " TSTPATRX2IINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 1"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " TSTPATRX2IOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 1"
|
|
line.long 0x08 "TESTPATTERNRX3ICFG,Test Pattern RX3 I Configuration Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " TSTPATRX3IINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 2"
|
|
hexmask.long.word 0x08 0.--15. 0x01 " TSTPATRX3IOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 2"
|
|
line.long 0x0C "TESTPATTERNRX4ICFG,Test Pattern RX4 I Configuration Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " TSTPATRX4IINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 3"
|
|
hexmask.long.word 0x0C 0.--15. 0x01 " TSTPATRX4IOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 3"
|
|
group.long 0x22C++0x0F
|
|
line.long 0x00 "TESTPATTERNRX1QCFG,Test Pattern RX1 Q Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TSTPATRX1QINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 0"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " TSTPATRX1QOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 0"
|
|
line.long 0x04 "TESTPATTERNRX2QCFG,Test Pattern RX2 Q Configuration Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " TSTPATRX2QINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 1"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " TSTPATRX2QOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 1"
|
|
line.long 0x08 "TESTPATTERNRX3QCFG,Test Pattern RX3 Q Configuration Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " TSTPATRX3QINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 2"
|
|
hexmask.long.word 0x08 0.--15. 0x01 " TSTPATRX3QOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 2"
|
|
line.long 0x0C "TESTPATTERNRX4QCFG,Test Pattern RX4 Q Configuration Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " TSTPATRX4QINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 3"
|
|
hexmask.long.word 0x0C 0.--15. 0x01 " TSTPATRX4QOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 3"
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "TESTPATTERNVLDCFG,Test Pattern VLD Configuration"
|
|
bitfld.long 0x00 8.--10. " TSTPATGENEN ,Enable for test pattern generator" "Disabled,,,,,,,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TSTPATVLDCNT ,Number of DSS Interconnect clocks 200 MHz between successive samples for the test pattern gen"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "DSSMISC,DSS Miscellaneous Register"
|
|
bitfld.long 0x00 6.--8. " FFTACCSLVEN ,Enable HW accelerator" "Disabled,,,,,,,Enabled"
|
|
endif
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "TPCC1PARSTATCFG,TPCC1 Parity Stat Configuration Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " NU ,Number"
|
|
bitfld.long 0x00 11. " TPCC1PARITYTSTEN ,Enable bit for the self test of the parity logic in TPCC" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TPCC1PARITYEN ,Enable bit for the parity computation in TPCC" "Disabled,Enabled"
|
|
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|
|
bitfld.long 0x00 9. " TPCC1PARITYCLR ,Clear bit for the parity error from TPCC write 0x1 to clear the status" "Not cleared,Cleared"
|
|
hexmask.long.word 0x00 0.--8. 0x01 " TPCC1PARITYSTAT ,Parity address from TPCC"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "DMMSWINT1,DMM Switch Interrupt 1 Register"
|
|
bitfld.long 0x00 22. " DMMCQWREN ,CQ write enable from DMM" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " DMMCQPINPONSEL ,CQ ping pong select for HIL mode" "0,1"
|
|
bitfld.long 0x00 20. " DMMCPBPMMEMSEL ,Select signal for muxing between HW registers/memory for CPBPM data" "HW registers,Memory"
|
|
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|
|
bitfld.long 0x00 19. " DMMCPBPMWREN ,CPBPM write enable from DMM" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DMMCPBPMPINPONSEL ,CP BPM ping pong select for HIL mode" "0,1"
|
|
bitfld.long 0x00 17. " DMMADCBUFWREN ,ADC buffer write enable from DMM" "Disabled,Enabled"
|
|
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|
|
bitfld.long 0x00 16. " DMMADCBUFPINPONSEL ,ADC Buffer ping pong select for HIL mode" "0,1"
|
|
group.long 0x270++0x13
|
|
line.long 0x00 "DSSINTRCFG,DSS Interrupt Configuration"
|
|
bitfld.long 0x00 7. " LGFRAMESTRTINTMUXSEL[1] ,Logical frame start select" "DFE,DMM global CFG bit"
|
|
bitfld.long 0x00 6. " [0] ,Interrupt select" "MUX,DMM SW interrupt 3"
|
|
bitfld.long 0x00 5. " PINPONINTMUXSEL[1] ,Ping pong switch select" "VIN/DFE,DMM global CFG bit"
|
|
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|
|
bitfld.long 0x00 4. " [0] ,Interrupt select" "MUX,DMM SW interrupt 2"
|
|
bitfld.long 0x00 3. " CHIRPAVLINTMUXSEL[1] ,Chirp available select" "VIN/DFE,DMM global CFG bit"
|
|
bitfld.long 0x00 2. " [0] ,Interrupt select" "MUX,DMM SW interrupt 1"
|
|
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|
|
bitfld.long 0x00 1. " FRAMESTRTINTMUXSEL[1] ,Frame start select" "VIN/DFE,DMM global CFG bit"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt select" "MUX,DMM SW interrupt 0"
|
|
line.long 0x04 "MPUMSTIDCFG1,MPU Master ID Configuration 1 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " MPUMSTID[3] ,MPU master ID 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,MPU master ID 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,MPU master ID 1"
|
|
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|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,MPU maser ID 0"
|
|
line.long 0x08 "MPUMSTIDCFG2,MPU Master ID Configuration 2 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " MPUMSTID[7] ,MPU master ID 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,MPU master ID 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,MPU master ID 5"
|
|
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|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,MPU master ID 4"
|
|
line.long 0x0C "MPUMSTIDCFG3,MPU Master ID Configuration 3 Register"
|
|
bitfld.long 0x0C 19. " MPUMSTIDEN ,Enable control for master ID based MPU" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " MPUERRCLR ,Error clear pulse for master ID based MPU" "Not cleared,Cleared"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " MPUERRMSTID ,Error status field"
|
|
newline
|
|
bitfld.long 0x0C 7. " MPUMSTIDVLD[7] ,Master ID 7 valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 6. " [6] ,Master ID 6 valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 5. " [5] ,Master ID 5 valid" "Not valid,Valid"
|
|
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|
|
bitfld.long 0x0C 4. " [4] ,Master ID 4 valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 3. " [3] ,Master ID 3 valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 2. " [2] ,Master ID 2 valid" "Not valid,Valid"
|
|
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|
|
bitfld.long 0x0C 1. " [1] ,Master ID 1 valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 0. " [0] ,Master ID 0 valid" "Not valid,Valid"
|
|
line.long 0x10 "HSRAM1ECCCFG,HSRAM1 ECC Configuration Register"
|
|
hexmask.long.word 0x10 15.--22. 1. " HSRAM1ECCREPAIREDBIT ,Bit position of the repaired bit in HSRAM1"
|
|
hexmask.long.word 0x10 4.--14. 0x10 " HSRAM1ECCFAULTADDRESS ,ECC fault address in HSRAM1"
|
|
bitfld.long 0x10 3. " HSRAM1ECCERRCLR ,Clear bit for ECC error indication in HSRAM1" "Not cleared,Cleared"
|
|
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|
|
bitfld.long 0x10 2. " HSRAM1ECCEN ,Enable for ECC in HSRAM1" "Disabled,Enabled"
|
|
rbitfld.long 0x10 1. " HSRAM1ECCINITDONE ,Done status for ECC initialization for HSRAM1" "Not done,Done"
|
|
bitfld.long 0x10 0. " HSRAM1ECCINIT ,ECC initialization For HSRAM1" "Disabled,Enabled"
|
|
group.long 0x288++0x0B
|
|
line.long 0x00 "DATATRRAMECCCFG,DATATRRAM ECC Configuration Register"
|
|
hexmask.long.word 0x00 13.--20. 1. " DATATRRAMECCREPAIREDBIT ,Bit position of the repaired bit in DATATRRAM"
|
|
hexmask.long.word 0x00 4.--12. 0x10 " DATATRRAMECCFAULTADDRESS ,ECC fault address in DATATRRAM"
|
|
bitfld.long 0x00 3. " DATATRRAMECCERRCLR ,Clear bit for ECC error indication in DATATRRAM" "Not cleared,Cleared"
|
|
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|
|
bitfld.long 0x00 2. " DATATRRAMECCEN ,Enable for ECC in DATATRRAM" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " DATATRRAMECCINITDONE ,Done status for ECC initialization for data transfer RAM" "Not done,Done"
|
|
bitfld.long 0x00 0. " DATATRRAMECCINIT ,ECC initialization for data transfer RAM" "Disabled,Enabled"
|
|
line.long 0x04 "ADCBUFPINGECCCFG,ADC Buffer Ping ECC Configuration Register"
|
|
hexmask.long.word 0x04 15.--22. 1. " ADCBUFPINGECCREPAIREDBIT ,Bit position of the repaired bit in ADC buffer ping memory"
|
|
hexmask.long.word 0x04 4.--14. 0x10 " ADCBUFPINGECCFAULTADDRESS ,ECC fault address in ADC buffer ping memory"
|
|
bitfld.long 0x04 3. " ADCBUFPINGECCERRCLR ,Clear bit for ECC error indication in ADC buffer ping memory" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " ADCBUFPINGECCEN ,Enable for ECC in ADC buffer ping memory" "Disabled,Enabled"
|
|
rbitfld.long 0x04 1. " ADCBUFPINGECCINITDONE ,Done status for ECC initialization for ADC buffer ping memory" "Not done,Done"
|
|
bitfld.long 0x04 0. " ADCBUFPINGECCINIT ,ECC initialization For ADC buffer ping memory" "Disabled,Enabled"
|
|
line.long 0x08 "ADCBUFPONGECCCFG,ADC Buffer Pong ECC Configuration Register"
|
|
hexmask.long.word 0x08 15.--22. 1. " ADCBUFPONGECCREPAIREDBIT ,Bit position of the repaired bit in ADC buffer pong memory"
|
|
hexmask.long.word 0x08 4.--14. 0x10 " ADCBUFPONGECCFAULTADDRESS ,ECC fault address in ADC buffer pong memory"
|
|
bitfld.long 0x08 3. " ADCBUFPONGECCERRCLR ,Clear bit for ECC error indication in ADC buffer pong memory" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 2. " ADCBUFPONGECCEN ,Enable for ECC in ADC buffer pong memory" "Disabled,Enabled"
|
|
rbitfld.long 0x08 1. " ADCBUFPONGECCINITDONE ,Done status for ECC initialization for ADC buffer pong memory" "Not done,Done"
|
|
bitfld.long 0x08 0. " ADCBUFPONGECCINIT ,ECC initialization for ADC buffer pong memory" "Disabled,Enabled"
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "UMAP0PARITYCFG1,UMAP0 Parity Configuration 1 Register"
|
|
hexmask.long.word 0x00 15.--25. 0x80 " UMAP0BANK23ADDOUT ,Address corresponding to the parity error in bank 2 or bank 3 of UMAP0"
|
|
hexmask.long.word 0x00 4.--14. 0x10 " UMAP0BANK01ADDOUT ,Address corresponding to the parity error in bank 0 or bank 1 of UMAP0"
|
|
rbitfld.long 0x00 3. " UMAP0BANK23ERROUT ,Parity error indication from either bank 2 or bank 3 of UMAP0" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 2. " UMAP0BANK01ERROUT ,Parity error indication from either bank 0 or bank 1 of UMAP0" "No error,Error"
|
|
bitfld.long 0x00 1. " UMAP0PARERRCLR ,Clear pulse for all the error status from UMAP0 parity check logic" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " UMAP0PAREN ,Enable for UMAP0 parity check logic" "Disabled,Enabled"
|
|
rgroup.long 0x2A0++0x07
|
|
line.long 0x00 "UMAP0PARITYCFG2,UMAP1 Parity Configuration 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " UMAP0BANK1BITOUT ,Bit level indication corresponding to parity error from UMAP0 bank 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " UMAP0BANK0BITOUT ,Bit level indication corresponding to parity error from UMAP0 bank 0"
|
|
line.long 0x04 "UMAP0PARITYCFG3,UMAP0PARITYCFG3"
|
|
hexmask.long.word 0x04 16.--31. 1. " UMAP0BANK3BITOUT ,Bit level indication corresponding to parity error from UMAP0 bank 3"
|
|
hexmask.long.word 0x04 0.--15. 1. " UMAP0BANK2BITOUT ,Bit level indication corresponding to parity error from UMAP0 bank 2"
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "UMAP1PARITYCFG1,UMAP1 Parity Configuration 1 Register"
|
|
hexmask.long.word 0x00 15.--25. 0x80 " UMAP1BANK23ADDOUT ,Address corresponding to the parity error in bank 2 or bank 3 of UMAP1"
|
|
hexmask.long.word 0x00 4.--14. 0x10 " UMAP1BANK01ADDOUT ,Address corresponding to the parity error in bank 0 or bank 1 of UMAP1"
|
|
rbitfld.long 0x00 3. " UMAP1BANK23ERROUT ,Parity error indication from either bank 2 or bank 3 of UMAP1" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 2. " UMAP1BANK01ERROUT ,Parity error indication from either bank 0 or bank 1 of UMAP1" "No error,Error"
|
|
bitfld.long 0x00 1. " UMAP1PARERRCLR ,Clear pulse for all the error status from UMAP1 parity check logic" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " UMAP1PAREN ,Enable for UMAP1 parity check logic" "Disabled,Enabled"
|
|
rgroup.long 0x2AC++0x07
|
|
line.long 0x00 "UMAP1PARITYCFG2,UMAP1 Parity Configuration 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " UMAP1BANK1BITOUT ,Bit level indication corresponding to parity error from UMAP1 bank 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " UMAP1BANK0BITOUT ,Bit level indication corresponding to parity error from UMAP1 bank 0"
|
|
line.long 0x04 "UMAP1PARITYCFG3,UMAP1 Parity Configuration 3 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " UMAP1BANK3BITOUT ,Bit level indication corresponding to parity error from UMAP1 bank 3"
|
|
hexmask.long.word 0x04 0.--15. 1. " UMAP1BANK2BITOUT ,Bit level indication corresponding to parity error from UMAP1 bank 2"
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "ESMGRP2MASKCFG,ESM Group2 Mask Configuration Register"
|
|
bitfld.long 0x00 31. " ESMGRP2MASK[31] ,Bit level mask for error signal 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " [30] ,Bit level mask for error signal 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " [29] ,Bit level mask for error signal 29" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Bit level mask for error signal 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " [27] ,Bit level mask for error signal 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " [26] ,Bit level mask for error signal 26" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Bit level mask for error signal 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " [24] ,Bit level mask for error signal 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " [23] ,Bit level mask for error signal 23" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Bit level mask for error signal 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " [21] ,Bit level mask for error signal 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " [20] ,Bit level mask for error signal 20" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Bit level mask for error signal 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " [18] ,Bit level mask for error signal 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " [17] ,Bit level mask for error signal 17" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Bit level mask for error signal 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " [15] ,Bit level mask for error signal 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " [14] ,Bit level mask for error signal 14" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Bit level mask for error signal 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " [12] ,Bit level mask for error signal 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " [11] ,Bit level mask for error signal 11" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Bit level mask for error signal 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " [9] ,Bit level mask for error signal 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Bit level mask for error signal 8" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Bit level mask for error signal 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " [6] ,Bit level mask for error signal 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Bit level mask for error signal 5" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Bit level mask for error signal 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " [3] ,Bit level mask for error signal 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,Bit level mask for error signal 2" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Bit level mask for error signal 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Bit level mask for error signal 0" "Not masked,Masked"
|
|
rgroup.long 0x2B8++0x0B
|
|
line.long 0x00 "L2MEMINITCFG1,L2 Memory Initialization Configuration 1 Register"
|
|
bitfld.long 0x00 31. " UMAP1BANK3PARINITDONE ,Initialization done status from UMAP1 bank 3 parity memory" "Not done,Done"
|
|
bitfld.long 0x00 30. " UMAP1BANK2PARINITDONE ,Initialization done status from UMAP1 bank 2 parity memory" "Not done,Done"
|
|
bitfld.long 0x00 29. " UMAP1BANK1PARINITDONE ,Initialization done status from UMAP1 bank 1 parity memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 28. " UMAP1BANK0PARINITDONE ,Initialization done status from UMAP1 bank 0 parity memory" "Not done,Done"
|
|
bitfld.long 0x00 27. " UMAP0BANK3PARINITDONE ,Initialization done status from UMAP0 bank 3 parity memory" "Not done,Done"
|
|
bitfld.long 0x00 26. " UMAP0BANK2PARINITDONE ,Initialization done status from UMAP0 bank 2 parity memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 25. " UMAP0BANK1PARINITDONE ,Initialization done status from UMAP0 bank 1 parity memory" "Not done,Done"
|
|
bitfld.long 0x00 24. " UMAP0BANK0PARINITDONE ,Initialization done status from UMAP0 bank 0 parity memory" "Not done,Done"
|
|
bitfld.long 0x00 23. " UMAP0BANK3DATAINITDONE ,Initialization done status from UMAP0 bank 3 data memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 22. " UMAP0BANK2DATAINITDONE ,Initialization done status from UMAP0 bank 2 data memory" "Not done,Done"
|
|
bitfld.long 0x00 21. " UMAP0BANK1DATAINITDONE ,Initialization done status from UMAP0 bank 1 data memory" "Not done,Done"
|
|
bitfld.long 0x00 20. " UMAP0BANK0DATAINITDONE ,Initialization done status from UMAP0 bank 0 data memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 19. " UMAP0BANK3DATAINITDONE ,Initialization done status from UMAP0 bank 3 data memory" "Not done,Done"
|
|
bitfld.long 0x00 18. " UMAP0BANK2DATAINITDONE ,Initialization done status from UMAP0 bank 2 data memory" "Not done,Done"
|
|
bitfld.long 0x00 17. " UMAP0BANK1DATAINITDONE ,Initialization done status from UMAP0 bank 1 data memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 16. " UMAP0BANK0DATAINITDONE ,Initialization done status from UMAP0 bank 0 data memory" "Not done,Done"
|
|
bitfld.long 0x00 15. " UMAP1BANK3PARINIT ,Initialization trigger for UMAP1 bank 3 parity memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 14. " UMAP1BANK2PARINIT ,Initialization trigger for UMAP1 bank 2 parity memory" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 13. " UMAP1BANK1PARINIT ,Initialization trigger for UMAP1 bank 1 parity memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 12. " UMAP1BANK0PARINIT ,Initialization trigger for UMAP1 bank 0 parity memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 11. " UMAP0BANK3PARINIT ,Initialization trigger for UMAP0 bank 3 parity memory" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 10. " UMAP0BANK2PARINIT ,Initialization trigger for UMAP0 bank 2 parity memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 9. " UMAP0BANK1PARINIT ,Initialization trigger for UMAP0 bank 1 parity memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 8. " UMAP0BANK0PARINIT ,Initialization trigger for UMAP0 bank 0 parity memory" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 7. " UMAP1BANK3DATAINIT ,Initialization trigger for UMAP1 bank 3 data memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 6. " UMAP1BANK2DATAINIT ,Initialization trigger for UMAP1 bank 2 data memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 5. " UMAP1BANK1DATAINIT ,Initialization trigger for UMAP1 bank 1 data memory" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 4. " UMAP1BANK0DATAINIT ,Initialization trigger for UMAP1 bank 0 data memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 3. " UMAP0BANK3DATAINIT ,Initialization trigger for UMAP0 bank 3 data memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 2. " UMAP0BANK2DATAINIT ,Initialization trigger for UMAP0 bank 2 data memory" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 1. " UMAP0BANK1DATAINIT ,Initialization trigger for UMAP0 bank 1 data memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " UMAP0BANK0DATAINIT ,Initialization trigger for UMAP0 bank 0 data memory" "Not triggered,Triggered"
|
|
line.long 0x04 "L2MEMINITCFG2,L2M Memory Initialization Configuration 2 Register"
|
|
bitfld.long 0x04 7. " UMAP1BANK1PARINITDONE ,Initialization done status for UMAP1 bank1 PRAM memory" "Not done,Done"
|
|
bitfld.long 0x04 6. " UMAP1BANK0PARINITDONE ,Initialization done status for UMAP1 bank 0 PRAM memory" "Not done,Done"
|
|
bitfld.long 0x04 5. " UMAP0BANK1PARINITDONE ,Initialization done status for UMAP0 bank 1 PRAM memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x04 4. " UMAP0BANK0PARINITDONE ,Initialization done status for UMAP0 bank 0 PRAM memory" "Not done,Done"
|
|
bitfld.long 0x04 3. " UMAP1BANK1PRAMINIT ,Initialization trigger for UMAP1 bank 1 PRAM memory" "Not triggered,Triggered"
|
|
bitfld.long 0x04 2. " UMAP1BANK0PRAMINIT ,Initialization trigger for UMAP1 bank0 PRAM memory" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x04 1. " UMAP0BANK1PRAMINIT ,Initialization trigger for UMAP0 bank 1 PRAM memory" "Not triggered,Triggered"
|
|
bitfld.long 0x04 0. " UMAP0BANK0PRAMINIT ,Initialization trigger for UMAP0 bank 0 PRAM memory" "Not triggered,Triggered"
|
|
line.long 0x08 "GEMRSTCAUSE,GEM Reset Cause Register"
|
|
bitfld.long 0x08 24. " GEMRSTCAUSECLR ,GEM reset cause clear" "Not cleared,Cleared"
|
|
hexmask.long.byte 0x08 16.--23. 1. " GEMPORCAUSE ,DSP POR reset bitwise indication"
|
|
hexmask.long.byte 0x08 8.--15. 1. " GEMGRSTCAUSE ,DSP reset bitwise indication"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. " GEMLRSTCAUSE ,DSP reset bitwise indication"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "GEMPWRSMCFG4,GEM Power SM Configuration 4 Register"
|
|
bitfld.long 0x00 18. " GEMEVENTMASK ,Mask bit for events going to DSP" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " PWRSMLRSTHALT ,Signal to halt DSP power cycle state machine before de-asserting LRST of DSP" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " PWRSMSLEEPTRIG ,Sleep mode trigger for DSP power down state machine" "Disabled,Enabled"
|
|
group.long 0x2D4++0x17
|
|
line.long 0x00 "PWRSMWAKEMASK0,Power SM Wake Mask 0 Register"
|
|
bitfld.long 0x00 31. " PWRSMWAKEMASK0[31] ,Bit level mask for wakeup source bit 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " [30] ,Bit level mask for wakeup source bit 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " [29] ,Bit level mask for wakeup source bit 29" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Bit level mask for wakeup source bit 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " [27] ,Bit level mask for wakeup source bit 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " [26] ,Bit level mask for wakeup source bit 26" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Bit level mask for wakeup source bit 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " [24] ,Bit level mask for wakeup source bit 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " [23] ,Bit level mask for wakeup source bit 23" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Bit level mask for wakeup source bit 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " [21] ,Bit level mask for wakeup source bit 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " [20] ,Bit level mask for wakeup source bit 20" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Bit level mask for wakeup source bit 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " [18] ,Bit level mask for wakeup source bit 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " [17] ,Bit level mask for wakeup source bit 17" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Bit level mask for wakeup source bit 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " [15] ,Bit level mask for wakeup source bit 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " [14] ,Bit level mask for wakeup source bit 14" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Bit level mask for wakeup source bit 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " [12] ,Bit level mask for wakeup source bit 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " [11] ,Bit level mask for wakeup source bit 11" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Bit level mask for wakeup source bit 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " [9] ,Bit level mask for wakeup source bit 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Bit level mask for wakeup source bit 8" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Bit level mask for wakeup source bit 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " [6] ,Bit level mask for wakeup source bit 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Bit level mask for wakeup source bit 5" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Bit level mask for wakeup source bit 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " [3] ,Bit level mask for wakeup source bit 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,Bit level mask for wakeup source bit 2" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Bit level mask for wakeup source bit 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Bit level mask for wakeup source bit 0" "Not masked,Masked"
|
|
line.long 0x04 "PWRSMWAKEMASK1,Power SM Wake Mask 1 Register"
|
|
bitfld.long 0x04 31. " PWRSMWAKEMASK1[63] ,Bit level mask for wakeup source bit 63" "Not masked,Masked"
|
|
bitfld.long 0x04 30. " [62] ,Bit level mask for wakeup source bit 62" "Not masked,Masked"
|
|
bitfld.long 0x04 29. " [61] ,Bit level mask for wakeup source bit 61" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 28. " [60] ,Bit level mask for wakeup source bit 60" "Not masked,Masked"
|
|
bitfld.long 0x04 27. " [59] ,Bit level mask for wakeup source bit 59" "Not masked,Masked"
|
|
bitfld.long 0x04 26. " [58] ,Bit level mask for wakeup source bit 58" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 25. " [57] ,Bit level mask for wakeup source bit 57" "Not masked,Masked"
|
|
bitfld.long 0x04 24. " [56] ,Bit level mask for wakeup source bit 56" "Not masked,Masked"
|
|
bitfld.long 0x04 23. " [55] ,Bit level mask for wakeup source bit 55" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 22. " [54] ,Bit level mask for wakeup source bit 54" "Not masked,Masked"
|
|
bitfld.long 0x04 21. " [53] ,Bit level mask for wakeup source bit 53" "Not masked,Masked"
|
|
bitfld.long 0x04 20. " [52] ,Bit level mask for wakeup source bit 52" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 19. " [51] ,Bit level mask for wakeup source bit 51" "Not masked,Masked"
|
|
bitfld.long 0x04 18. " [50] ,Bit level mask for wakeup source bit 50" "Not masked,Masked"
|
|
bitfld.long 0x04 17. " [49] ,Bit level mask for wakeup source bit 49" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 16. " [48] ,Bit level mask for wakeup source bit 48" "Not masked,Masked"
|
|
bitfld.long 0x04 15. " [47] ,Bit level mask for wakeup source bit 47" "Not masked,Masked"
|
|
bitfld.long 0x04 14. " [46] ,Bit level mask for wakeup source bit 46" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 13. " [45] ,Bit level mask for wakeup source bit 45" "Not masked,Masked"
|
|
bitfld.long 0x04 12. " [44] ,Bit level mask for wakeup source bit 44" "Not masked,Masked"
|
|
bitfld.long 0x04 11. " [43] ,Bit level mask for wakeup source bit 43" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 10. " [42] ,Bit level mask for wakeup source bit 42" "Not masked,Masked"
|
|
bitfld.long 0x04 9. " [41] ,Bit level mask for wakeup source bit 41" "Not masked,Masked"
|
|
bitfld.long 0x04 8. " [40] ,Bit level mask for wakeup source bit 40" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 7. " [39] ,Bit level mask for wakeup source bit 39" "Not masked,Masked"
|
|
bitfld.long 0x04 6. " [38] ,Bit level mask for wakeup source bit 38" "Not masked,Masked"
|
|
bitfld.long 0x04 5. " [37] ,Bit level mask for wakeup source bit 37" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 4. " [36] ,Bit level mask for wakeup source bit 36" "Not masked,Masked"
|
|
bitfld.long 0x04 3. " [35] ,Bit level mask for wakeup source bit 35" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " [34] ,Bit level mask for wakeup source bit 34" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,Bit level mask for wakeup source bit 33" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " [32] ,Bit level mask for wakeup source bit 32" "Not masked,Masked"
|
|
line.long 0x08 "PWRSMWAKEMASK2,Power SM Wake Mask 2 Register"
|
|
bitfld.long 0x08 31. " PWRSMWAKEMASK2[95] ,Bit level mask for wakeup source bit 95" "Not masked,Masked"
|
|
bitfld.long 0x08 30. " [94] ,Bit level mask for wakeup source bit 94" "Not masked,Masked"
|
|
bitfld.long 0x08 29. " [93] ,Bit level mask for wakeup source bit 93" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 28. " [92] ,Bit level mask for wakeup source bit 92" "Not masked,Masked"
|
|
bitfld.long 0x08 27. " [91] ,Bit level mask for wakeup source bit 91" "Not masked,Masked"
|
|
bitfld.long 0x08 26. " [90] ,Bit level mask for wakeup source bit 90" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 25. " [89] ,Bit level mask for wakeup source bit 89" "Not masked,Masked"
|
|
bitfld.long 0x08 24. " [88] ,Bit level mask for wakeup source bit 88" "Not masked,Masked"
|
|
bitfld.long 0x08 23. " [87] ,Bit level mask for wakeup source bit 87" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 22. " [86] ,Bit level mask for wakeup source bit 86" "Not masked,Masked"
|
|
bitfld.long 0x08 21. " [85] ,Bit level mask for wakeup source bit 85" "Not masked,Masked"
|
|
bitfld.long 0x08 20. " [84] ,Bit level mask for wakeup source bit 84" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 19. " [83] ,Bit level mask for wakeup source bit 83" "Not masked,Masked"
|
|
bitfld.long 0x08 18. " [82] ,Bit level mask for wakeup source bit 82" "Not masked,Masked"
|
|
bitfld.long 0x08 17. " [81] ,Bit level mask for wakeup source bit 81" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 16. " [80] ,Bit level mask for wakeup source bit 80" "Not masked,Masked"
|
|
bitfld.long 0x08 15. " [79] ,Bit level mask for wakeup source bit 79" "Not masked,Masked"
|
|
bitfld.long 0x08 14. " [78] ,Bit level mask for wakeup source bit 78" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 13. " [77] ,Bit level mask for wakeup source bit 77" "Not masked,Masked"
|
|
bitfld.long 0x08 12. " [76] ,Bit level mask for wakeup source bit 76" "Not masked,Masked"
|
|
bitfld.long 0x08 11. " [75] ,Bit level mask for wakeup source bit 75" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 10. " [74] ,Bit level mask for wakeup source bit 74" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " [73] ,Bit level mask for wakeup source bit 73" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " [72] ,Bit level mask for wakeup source bit 72" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 7. " [71] ,Bit level mask for wakeup source bit 71" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " [70] ,Bit level mask for wakeup source bit 70" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " [69] ,Bit level mask for wakeup source bit 69" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 4. " [68] ,Bit level mask for wakeup source bit 68" "Not masked,Masked"
|
|
bitfld.long 0x08 3. " [67] ,Bit level mask for wakeup source bit 67" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " [66] ,Bit level mask for wakeup source bit 66" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 1. " [65] ,Bit level mask for wakeup source bit 65" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " [64] ,Bit level mask for wakeup source bit 64" "Not masked,Masked"
|
|
line.long 0x0C "PWRSMMISEVTMASK0,Power SM Missed Event Mask 0 Register"
|
|
bitfld.long 0x0C 31. " PWRSMMISEVTMASK0[31] ,Bit level mask for missed event 31" "Not masked,Masked"
|
|
bitfld.long 0x0C 30. " [30] ,Bit level mask for missed event 30" "Not masked,Masked"
|
|
bitfld.long 0x0C 29. " [29] ,Bit level mask for missed event 29" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 28. " [28] ,Bit level mask for missed event 28" "Not masked,Masked"
|
|
bitfld.long 0x0C 27. " [27] ,Bit level mask for missed event 27" "Not masked,Masked"
|
|
bitfld.long 0x0C 26. " [26] ,Bit level mask for missed event 26" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 25. " [25] ,Bit level mask for missed event 25" "Not masked,Masked"
|
|
bitfld.long 0x0C 24. " [24] ,Bit level mask for missed event 24" "Not masked,Masked"
|
|
bitfld.long 0x0C 23. " [23] ,Bit level mask for missed event 23" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 22. " [22] ,Bit level mask for missed event 22" "Not masked,Masked"
|
|
bitfld.long 0x0C 21. " [21] ,Bit level mask for missed event 21" "Not masked,Masked"
|
|
bitfld.long 0x0C 20. " [20] ,Bit level mask for missed event 20" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 19. " [19] ,Bit level mask for missed event 19" "Not masked,Masked"
|
|
bitfld.long 0x0C 18. " [18] ,Bit level mask for missed event 18" "Not masked,Masked"
|
|
bitfld.long 0x0C 17. " [17] ,Bit level mask for missed event 17" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 16. " [16] ,Bit level mask for missed event 16" "Not masked,Masked"
|
|
bitfld.long 0x0C 15. " [15] ,Bit level mask for missed event 15" "Not masked,Masked"
|
|
bitfld.long 0x0C 14. " [14] ,Bit level mask for missed event 14" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 13. " [13] ,Bit level mask for missed event 13" "Not masked,Masked"
|
|
bitfld.long 0x0C 12. " [12] ,Bit level mask for missed event 12" "Not masked,Masked"
|
|
bitfld.long 0x0C 11. " [11] ,Bit level mask for missed event 11" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 10. " [10] ,Bit level mask for missed event 10" "Not masked,Masked"
|
|
bitfld.long 0x0C 9. " [9] ,Bit level mask for missed event 9" "Not masked,Masked"
|
|
bitfld.long 0x0C 8. " [8] ,Bit level mask for missed event 8" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 7. " [7] ,Bit level mask for missed event 7" "Not masked,Masked"
|
|
bitfld.long 0x0C 6. " [6] ,Bit level mask for missed event 6" "Not masked,Masked"
|
|
bitfld.long 0x0C 5. " [5] ,Bit level mask for missed event 5" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 4. " [4] ,Bit level mask for missed event 4" "Not masked,Masked"
|
|
bitfld.long 0x0C 3. " [3] ,Bit level mask for missed event 3" "Not masked,Masked"
|
|
bitfld.long 0x0C 2. " [2] ,Bit level mask for missed event 2" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 1. " [1] ,Bit level mask for missed event 1" "Not masked,Masked"
|
|
bitfld.long 0x0C 0. " [0] ,Bit level mask for missed event 0" "Not masked,Masked"
|
|
line.long 0x10 "PWRSMMISEVTMASK1,Power SM Missed Event Mask 1 Register"
|
|
bitfld.long 0x10 31. " PWRSMMISEVTMASK1[63] ,Bit level mask for missed event 63" "Not masked,Masked"
|
|
bitfld.long 0x10 30. " [62] ,Bit level mask for missed event 62" "Not masked,Masked"
|
|
bitfld.long 0x10 29. " [61] ,Bit level mask for missed event 61" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 28. " [60] ,Bit level mask for missed event 60" "Not masked,Masked"
|
|
bitfld.long 0x10 27. " [59] ,Bit level mask for missed event 59" "Not masked,Masked"
|
|
bitfld.long 0x10 26. " [58] ,Bit level mask for missed event 58" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 25. " [57] ,Bit level mask for missed event 57" "Not masked,Masked"
|
|
bitfld.long 0x10 24. " [56] ,Bit level mask for missed event 56" "Not masked,Masked"
|
|
bitfld.long 0x10 23. " [55] ,Bit level mask for missed event 55" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 22. " [54] ,Bit level mask for missed event 54" "Not masked,Masked"
|
|
bitfld.long 0x10 21. " [53] ,Bit level mask for missed event 53" "Not masked,Masked"
|
|
bitfld.long 0x10 20. " [52] ,Bit level mask for missed event 52" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 19. " [51] ,Bit level mask for missed event 51" "Not masked,Masked"
|
|
bitfld.long 0x10 18. " [50] ,Bit level mask for missed event 50" "Not masked,Masked"
|
|
bitfld.long 0x10 17. " [49] ,Bit level mask for missed event 49" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 16. " [48] ,Bit level mask for missed event 48" "Not masked,Masked"
|
|
bitfld.long 0x10 15. " [47] ,Bit level mask for missed event 47" "Not masked,Masked"
|
|
bitfld.long 0x10 14. " [46] ,Bit level mask for missed event 46" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 13. " [45] ,Bit level mask for missed event 45" "Not masked,Masked"
|
|
bitfld.long 0x10 12. " [44] ,Bit level mask for missed event 44" "Not masked,Masked"
|
|
bitfld.long 0x10 11. " [43] ,Bit level mask for missed event 43" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 10. " [42] ,Bit level mask for missed event 42" "Not masked,Masked"
|
|
bitfld.long 0x10 9. " [41] ,Bit level mask for missed event 41" "Not masked,Masked"
|
|
bitfld.long 0x10 8. " [40] ,Bit level mask for missed event 40" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 7. " [39] ,Bit level mask for missed event 39" "Not masked,Masked"
|
|
bitfld.long 0x10 6. " [38] ,Bit level mask for missed event 38" "Not masked,Masked"
|
|
bitfld.long 0x10 5. " [37] ,Bit level mask for missed event 37" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 4. " [36] ,Bit level mask for missed event 36" "Not masked,Masked"
|
|
bitfld.long 0x10 3. " [35] ,Bit level mask for missed event 35" "Not masked,Masked"
|
|
bitfld.long 0x10 2. " [34] ,Bit level mask for missed event 34" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 1. " [33] ,Bit level mask for missed event 33" "Not masked,Masked"
|
|
bitfld.long 0x10 0. " [32] ,Bit level mask for missed event 32" "Not masked,Masked"
|
|
line.long 0x14 "PWRSMMISEVTMASK2,Power SM Missed Event Mask 2 Register"
|
|
bitfld.long 0x14 31. " PWRSMMISEVTMASK2[95] ,Bit level mask for missed event 95" "Not masked,Masked"
|
|
bitfld.long 0x14 30. " [94] ,Bit level mask for missed event 94" "Not masked,Masked"
|
|
bitfld.long 0x14 29. " [93] ,Bit level mask for missed event 93" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 28. " [92] ,Bit level mask for missed event 92" "Not masked,Masked"
|
|
bitfld.long 0x14 27. " [91] ,Bit level mask for missed event 91" "Not masked,Masked"
|
|
bitfld.long 0x14 26. " [90] ,Bit level mask for missed event 90" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 25. " [89] ,Bit level mask for missed event 89" "Not masked,Masked"
|
|
bitfld.long 0x14 24. " [88] ,Bit level mask for missed event 88" "Not masked,Masked"
|
|
bitfld.long 0x14 23. " [87] ,Bit level mask for missed event 87" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 22. " [86] ,Bit level mask for missed event 86" "Not masked,Masked"
|
|
bitfld.long 0x14 21. " [85] ,Bit level mask for missed event 85" "Not masked,Masked"
|
|
bitfld.long 0x14 20. " [84] ,Bit level mask for missed event 84" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 19. " [83] ,Bit level mask for missed event 83" "Not masked,Masked"
|
|
bitfld.long 0x14 18. " [82] ,Bit level mask for missed event 82" "Not masked,Masked"
|
|
bitfld.long 0x14 17. " [81] ,Bit level mask for missed event 81" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 16. " [80] ,Bit level mask for missed event 80" "Not masked,Masked"
|
|
bitfld.long 0x14 15. " [79] ,Bit level mask for missed event 79" "Not masked,Masked"
|
|
bitfld.long 0x14 14. " [78] ,Bit level mask for missed event 78" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 13. " [77] ,Bit level mask for missed event 77" "Not masked,Masked"
|
|
bitfld.long 0x14 12. " [76] ,Bit level mask for missed event 76" "Not masked,Masked"
|
|
bitfld.long 0x14 11. " [75] ,Bit level mask for missed event 75" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 10. " [74] ,Bit level mask for missed event 74" "Not masked,Masked"
|
|
bitfld.long 0x14 9. " [73] ,Bit level mask for missed event 73" "Not masked,Masked"
|
|
bitfld.long 0x14 8. " [72] ,Bit level mask for missed event 72" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 7. " [71] ,Bit level mask for missed event 71" "Not masked,Masked"
|
|
bitfld.long 0x14 6. " [70] ,Bit level mask for missed event 70" "Not masked,Masked"
|
|
bitfld.long 0x14 5. " [69] ,Bit level mask for missed event 69" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 4. " [68] ,Bit level mask for missed event 68" "Not masked,Masked"
|
|
bitfld.long 0x14 3. " [67] ,Bit level mask for missed event 67" "Not masked,Masked"
|
|
bitfld.long 0x14 2. " [66] ,Bit level mask for missed event 66" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 1. " [65] ,Bit level mask for missed event 65" "Not masked,Masked"
|
|
bitfld.long 0x14 0. " [64] ,Bit level mask for missed event 64" "Not masked,Masked"
|
|
rgroup.long 0x2EC++0x07
|
|
line.long 0x00 "PWRSMWAKESRCSTAT0,Power SM Wake Source Status 0 Register"
|
|
bitfld.long 0x00 31. " PWRSMWAKESRCSTAT0[31] ,Wakeup source status bit 31" "0,1"
|
|
bitfld.long 0x00 30. " [30] ,Wakeup source status bit 30" "0,1"
|
|
bitfld.long 0x00 29. " [29] ,Wakeup source status bit 29" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Wakeup source status bit 28" "0,1"
|
|
bitfld.long 0x00 27. " [27] ,Wakeup source status bit 27" "0,1"
|
|
bitfld.long 0x00 26. " [26] ,Wakeup source status bit 26" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Wakeup source status bit 25" "0,1"
|
|
bitfld.long 0x00 24. " [24] ,Wakeup source status bit 24" "0,1"
|
|
bitfld.long 0x00 23. " [23] ,Wakeup source status bit 23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Wakeup source status bit 22" "0,1"
|
|
bitfld.long 0x00 21. " [21] ,Wakeup source status bit 21" "0,1"
|
|
bitfld.long 0x00 20. " [20] ,Wakeup source status bit 20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Wakeup source status bit 19" "0,1"
|
|
bitfld.long 0x00 18. " [18] ,Wakeup source status bit 18" "0,1"
|
|
bitfld.long 0x00 17. " [17] ,Wakeup source status bit 17" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Wakeup source status bit 16" "0,1"
|
|
bitfld.long 0x00 15. " [15] ,Wakeup source status bit 15" "0,1"
|
|
bitfld.long 0x00 14. " [14] ,Wakeup source status bit 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Wakeup source status bit 13" "0,1"
|
|
bitfld.long 0x00 12. " [12] ,Wakeup source status bit 12" "0,1"
|
|
bitfld.long 0x00 11. " [11] ,Wakeup source status bit 11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Wakeup source status bit 10" "0,1"
|
|
bitfld.long 0x00 9. " [9] ,Wakeup source status bit 9" "0,1"
|
|
bitfld.long 0x00 8. " [8] ,Wakeup source status bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Wakeup source status bit 7" "0,1"
|
|
bitfld.long 0x00 6. " [6] ,Wakeup source status bit 6" "0,1"
|
|
bitfld.long 0x00 5. " [5] ,Wakeup source status bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Wakeup source status bit 4" "0,1"
|
|
bitfld.long 0x00 3. " [3] ,Wakeup source status bit 3" "0,1"
|
|
bitfld.long 0x00 2. " [2] ,Wakeup source status bit 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Wakeup source status bit 1" "0,1"
|
|
bitfld.long 0x00 0. " [0] ,Wakeup source status bit 0" "0,1"
|
|
line.long 0x04 "PWRSMWAKESRCSTAT1,Power SM Wake Source Status 1 Register"
|
|
bitfld.long 0x04 31. " PWRSMWAKESRCSTAT1[63] ,Wakeup source status bit 63" "0,1"
|
|
bitfld.long 0x04 30. " [62] ,Wakeup source status bit 62" "0,1"
|
|
bitfld.long 0x04 29. " [61] ,Wakeup source status bit 61" "0,1"
|
|
newline
|
|
bitfld.long 0x04 28. " [60] ,Wakeup source status bit 60" "0,1"
|
|
bitfld.long 0x04 27. " [59] ,Wakeup source status bit 59" "0,1"
|
|
bitfld.long 0x04 26. " [58] ,Wakeup source status bit 58" "0,1"
|
|
newline
|
|
bitfld.long 0x04 25. " [57] ,Wakeup source status bit 57" "0,1"
|
|
bitfld.long 0x04 24. " [56] ,Wakeup source status bit 56" "0,1"
|
|
bitfld.long 0x04 23. " [55] ,Wakeup source status bit 55" "0,1"
|
|
newline
|
|
bitfld.long 0x04 22. " [54] ,Wakeup source status bit 54" "0,1"
|
|
bitfld.long 0x04 21. " [53] ,Wakeup source status bit 53" "0,1"
|
|
bitfld.long 0x04 20. " [52] ,Wakeup source status bit 52" "0,1"
|
|
newline
|
|
bitfld.long 0x04 19. " [51] ,Wakeup source status bit 51" "0,1"
|
|
bitfld.long 0x04 18. " [50] ,Wakeup source status bit 50" "0,1"
|
|
bitfld.long 0x04 17. " [49] ,Wakeup source status bit 49" "0,1"
|
|
newline
|
|
bitfld.long 0x04 16. " [48] ,Wakeup source status bit 48" "0,1"
|
|
bitfld.long 0x04 15. " [47] ,Wakeup source status bit 47" "0,1"
|
|
bitfld.long 0x04 14. " [46] ,Wakeup source status bit 46" "0,1"
|
|
newline
|
|
bitfld.long 0x04 13. " [45] ,Wakeup source status bit 45" "0,1"
|
|
bitfld.long 0x04 12. " [44] ,Wakeup source status bit 44" "0,1"
|
|
bitfld.long 0x04 11. " [43] ,Wakeup source status bit 43" "0,1"
|
|
newline
|
|
bitfld.long 0x04 10. " [42] ,Wakeup source status bit 42" "0,1"
|
|
bitfld.long 0x04 9. " [41] ,Wakeup source status bit 41" "0,1"
|
|
bitfld.long 0x04 8. " [40] ,Wakeup source status bit 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. " [39] ,Wakeup source status bit 39" "0,1"
|
|
bitfld.long 0x04 6. " [38] ,Wakeup source status bit 38" "0,1"
|
|
bitfld.long 0x04 5. " [37] ,Wakeup source status bit 37" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. " [36] ,Wakeup source status bit 36" "0,1"
|
|
bitfld.long 0x04 3. " [35] ,Wakeup source status bit 35" "0,1"
|
|
bitfld.long 0x04 2. " [34] ,Wakeup source status bit 34" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,Wakeup source status bit 33" "0,1"
|
|
bitfld.long 0x04 0. " [32] ,Wakeup source status bit 32" "0,1"
|
|
rgroup.long 0x320++0x0F
|
|
line.long 0x00 "PWRSMWAKESRCSTAT2,Power SM Wake Source Status 2 Register"
|
|
bitfld.long 0x00 31. " PWRSMWAKESRCSTAT2[95] ,Wakeup source status bit 95" "0,1"
|
|
bitfld.long 0x00 30. " [94] ,Wakeup source status bit 94" "0,1"
|
|
bitfld.long 0x00 29. " [93] ,Wakeup source status bit 93" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. " [92] ,Wakeup source status bit 92" "0,1"
|
|
bitfld.long 0x00 27. " [91] ,Wakeup source status bit 91" "0,1"
|
|
bitfld.long 0x00 26. " [90] ,Wakeup source status bit 90" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " [89] ,Wakeup source status bit 89" "0,1"
|
|
bitfld.long 0x00 24. " [88] ,Wakeup source status bit 88" "0,1"
|
|
bitfld.long 0x00 23. " [87] ,Wakeup source status bit 87" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. " [86] ,Wakeup source status bit 86" "0,1"
|
|
bitfld.long 0x00 21. " [85] ,Wakeup source status bit 85" "0,1"
|
|
bitfld.long 0x00 20. " [84] ,Wakeup source status bit 84" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " [83] ,Wakeup source status bit 83" "0,1"
|
|
bitfld.long 0x00 18. " [82] ,Wakeup source status bit 82" "0,1"
|
|
bitfld.long 0x00 17. " [81] ,Wakeup source status bit 81" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " [80] ,Wakeup source status bit 80" "0,1"
|
|
bitfld.long 0x00 15. " [79] ,Wakeup source status bit 79" "0,1"
|
|
bitfld.long 0x00 14. " [78] ,Wakeup source status bit 78" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. " [77] ,Wakeup source status bit 77" "0,1"
|
|
bitfld.long 0x00 12. " [76] ,Wakeup source status bit 76" "0,1"
|
|
bitfld.long 0x00 11. " [75] ,Wakeup source status bit 75" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. " [74] ,Wakeup source status bit 74" "0,1"
|
|
bitfld.long 0x00 9. " [73] ,Wakeup source status bit 73" "0,1"
|
|
bitfld.long 0x00 8. " [72] ,Wakeup source status bit 72" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " [71] ,Wakeup source status bit 71" "0,1"
|
|
bitfld.long 0x00 6. " [70] ,Wakeup source status bit 70" "0,1"
|
|
bitfld.long 0x00 5. " [69] ,Wakeup source status bit 69" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " [68] ,Wakeup source status bit 68" "0,1"
|
|
bitfld.long 0x00 3. " [67] ,Wakeup source status bit 67" "0,1"
|
|
bitfld.long 0x00 2. " [66] ,Wakeup source status bit 66" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " [65] ,Wakeup source status bit 65" "0,1"
|
|
bitfld.long 0x00 0. " [64] ,Wakeup source status bit 64" "0,1"
|
|
line.long 0x04 "PWRSMEVNTMONSTAT0,Power SM Event Monitor Status 0 Register"
|
|
bitfld.long 0x04 31. " PWRSMEVNTMONSTAT0[31] ,Missed event monitor status bit 31" "Not missed,Missed"
|
|
bitfld.long 0x04 30. " [30] ,Missed event monitor status bit 30" "Not missed,Missed"
|
|
bitfld.long 0x04 29. " [29] ,Missed event monitor status bit 29" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 28. " [28] ,Missed event monitor status bit 28" "Not missed,Missed"
|
|
bitfld.long 0x04 27. " [27] ,Missed event monitor status bit 27" "Not missed,Missed"
|
|
bitfld.long 0x04 26. " [26] ,Missed event monitor status bit 26" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,Missed event monitor status bit 25" "Not missed,Missed"
|
|
bitfld.long 0x04 24. " [24] ,Missed event monitor status bit 24" "Not missed,Missed"
|
|
bitfld.long 0x04 23. " [23] ,Missed event monitor status bit 23" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,Missed event monitor status bit 22" "Not missed,Missed"
|
|
bitfld.long 0x04 21. " [21] ,Missed event monitor status bit 21" "Not missed,Missed"
|
|
bitfld.long 0x04 20. " [20] ,Missed event monitor status bit 20" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Missed event monitor status bit 19" "Not missed,Missed"
|
|
bitfld.long 0x04 18. " [18] ,Missed event monitor status bit 18" "Not missed,Missed"
|
|
bitfld.long 0x04 17. " [17] ,Missed event monitor status bit 17" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,Missed event monitor status bit 16" "Not missed,Missed"
|
|
bitfld.long 0x04 15. " [15] ,Missed event monitor status bit 15" "Not missed,Missed"
|
|
bitfld.long 0x04 14. " [14] ,Missed event monitor status bit 14" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,Missed event monitor status bit 13" "Not missed,Missed"
|
|
bitfld.long 0x04 12. " [12] ,Missed event monitor status bit 12" "Not missed,Missed"
|
|
bitfld.long 0x04 11. " [11] ,Missed event monitor status bit 11" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 10. " [10] ,Missed event monitor status bit 10" "Not missed,Missed"
|
|
bitfld.long 0x04 9. " [9] ,Missed event monitor status bit 9" "Not missed,Missed"
|
|
bitfld.long 0x04 8. " [8] ,Missed event monitor status bit 8" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Missed event monitor status bit 7" "Not missed,Missed"
|
|
bitfld.long 0x04 6. " [6] ,Missed event monitor status bit 6" "Not missed,Missed"
|
|
bitfld.long 0x04 5. " [5] ,Missed event monitor status bit 5" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Missed event monitor status bit 4" "Not missed,Missed"
|
|
bitfld.long 0x04 3. " [3] ,Missed event monitor status bit 3" "Not missed,Missed"
|
|
bitfld.long 0x04 2. " [2] ,Missed event monitor status bit 2" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Missed event monitor status bit 1" "Not missed,Missed"
|
|
bitfld.long 0x04 0. " [0] ,Missed event monitor status bit 0" "Not missed,Missed"
|
|
line.long 0x08 "PWRSMEVNTMONSTAT1,Power SM Event Monitor Status 1 Register"
|
|
bitfld.long 0x08 31. " PWRSMEVNTMONSTAT1[63] ,Missed event monitor status bit 63" "Not missed,Missed"
|
|
bitfld.long 0x08 30. " [62] ,Missed event monitor status bit 62" "Not missed,Missed"
|
|
bitfld.long 0x08 29. " [61] ,Missed event monitor status bit 61" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 28. " [60] ,Missed event monitor status bit 60" "Not missed,Missed"
|
|
bitfld.long 0x08 27. " [59] ,Missed event monitor status bit 59" "Not missed,Missed"
|
|
bitfld.long 0x08 26. " [58] ,Missed event monitor status bit 58" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 25. " [57] ,Missed event monitor status bit 57" "Not missed,Missed"
|
|
bitfld.long 0x08 24. " [56] ,Missed event monitor status bit 56" "Not missed,Missed"
|
|
bitfld.long 0x08 23. " [55] ,Missed event monitor status bit 55" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 22. " [54] ,Missed event monitor status bit 54" "Not missed,Missed"
|
|
bitfld.long 0x08 21. " [53] ,Missed event monitor status bit 53" "Not missed,Missed"
|
|
bitfld.long 0x08 20. " [52] ,Missed event monitor status bit 52" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 19. " [51] ,Missed event monitor status bit 51" "Not missed,Missed"
|
|
bitfld.long 0x08 18. " [50] ,Missed event monitor status bit 50" "Not missed,Missed"
|
|
bitfld.long 0x08 17. " [49] ,Missed event monitor status bit 49" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 16. " [48] ,Missed event monitor status bit 48" "Not missed,Missed"
|
|
bitfld.long 0x08 15. " [47] ,Missed event monitor status bit 47" "Not missed,Missed"
|
|
bitfld.long 0x08 14. " [46] ,Missed event monitor status bit 46" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 13. " [45] ,Missed event monitor status bit 45" "Not missed,Missed"
|
|
bitfld.long 0x08 12. " [44] ,Missed event monitor status bit 44" "Not missed,Missed"
|
|
bitfld.long 0x08 11. " [43] ,Missed event monitor status bit 43" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 10. " [42] ,Missed event monitor status bit 42" "Not missed,Missed"
|
|
bitfld.long 0x08 9. " [41] ,Missed event monitor status bit 41" "Not missed,Missed"
|
|
bitfld.long 0x08 8. " [40] ,Missed event monitor status bit 40" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 7. " [39] ,Missed event monitor status bit 39" "Not missed,Missed"
|
|
bitfld.long 0x08 6. " [38] ,Missed event monitor status bit 38" "Not missed,Missed"
|
|
bitfld.long 0x08 5. " [37] ,Missed event monitor status bit 37" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 4. " [36] ,Missed event monitor status bit 36" "Not missed,Missed"
|
|
bitfld.long 0x08 3. " [35] ,Missed event monitor status bit 35" "Not missed,Missed"
|
|
bitfld.long 0x08 2. " [34] ,Missed event monitor status bit 34" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 1. " [33] ,Missed event monitor status bit 33" "Not missed,Missed"
|
|
bitfld.long 0x08 0. " [32] ,Missed event monitor status bit 32" "Not missed,Missed"
|
|
line.long 0x0C "PWRSMEVNTMONSTAT2,Power SM Event Monitor Status 2 Register"
|
|
bitfld.long 0x0C 31. " PWRSMEVNTMONSTAT2[95] ,Missed event monitor status bit 95" "Not missed,Missed"
|
|
bitfld.long 0x0C 30. " [94] ,Missed event monitor status bit 94" "Not missed,Missed"
|
|
bitfld.long 0x0C 29. " [93] ,Missed event monitor status bit 93" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 28. " [92] ,Missed event monitor status bit 92" "Not missed,Missed"
|
|
bitfld.long 0x0C 27. " [91] ,Missed event monitor status bit 91" "Not missed,Missed"
|
|
bitfld.long 0x0C 26. " [90] ,Missed event monitor status bit 90" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 25. " [89] ,Missed event monitor status bit 89" "Not missed,Missed"
|
|
bitfld.long 0x0C 24. " [88] ,Missed event monitor status bit 88" "Not missed,Missed"
|
|
bitfld.long 0x0C 23. " [87] ,Missed event monitor status bit 87" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 22. " [86] ,Missed event monitor status bit 86" "Not missed,Missed"
|
|
bitfld.long 0x0C 21. " [85] ,Missed event monitor status bit 85" "Not missed,Missed"
|
|
bitfld.long 0x0C 20. " [84] ,Missed event monitor status bit 84" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 19. " [83] ,Missed event monitor status bit 83" "Not missed,Missed"
|
|
bitfld.long 0x0C 18. " [82] ,Missed event monitor status bit 82" "Not missed,Missed"
|
|
bitfld.long 0x0C 17. " [81] ,Missed event monitor status bit 81" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 16. " [80] ,Missed event monitor status bit 80" "Not missed,Missed"
|
|
bitfld.long 0x0C 15. " [79] ,Missed event monitor status bit 79" "Not missed,Missed"
|
|
bitfld.long 0x0C 14. " [78] ,Missed event monitor status bit 78" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 13. " [77] ,Missed event monitor status bit 77" "Not missed,Missed"
|
|
bitfld.long 0x0C 12. " [76] ,Missed event monitor status bit 76" "Not missed,Missed"
|
|
bitfld.long 0x0C 11. " [75] ,Missed event monitor status bit 75" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 10. " [74] ,Missed event monitor status bit 74" "Not missed,Missed"
|
|
bitfld.long 0x0C 9. " [73] ,Missed event monitor status bit 73" "Not missed,Missed"
|
|
bitfld.long 0x0C 8. " [72] ,Missed event monitor status bit 72" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 7. " [71] ,Missed event monitor status bit 71" "Not missed,Missed"
|
|
bitfld.long 0x0C 6. " [70] ,Missed event monitor status bit 70" "Not missed,Missed"
|
|
bitfld.long 0x0C 5. " [69] ,Missed event monitor status bit 69" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 4. " [68] ,Missed event monitor status bit 68" "Not missed,Missed"
|
|
bitfld.long 0x0C 3. " [67] ,Missed event monitor status bit 67" "Not missed,Missed"
|
|
bitfld.long 0x0C 2. " [66] ,Missed event monitor status bit 66" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 1. " [65] ,Missed event monitor status bit 65" "Not missed,Missed"
|
|
bitfld.long 0x0C 0. " [64] ,Missed event monitor status bit 64" "Not missed,Missed"
|
|
group.long 0x330++0x23
|
|
line.long 0x00 "PWRSMWAKESRCSTATCLR0,Power SM Wake Source Status Clear 0 Register"
|
|
bitfld.long 0x00 31. " PWRSMWAKESRCSTATCLR0[31] ,Clear wakeup source status bit 31" "Not cleared,Cleared"
|
|
bitfld.long 0x00 30. " [30] ,Clear wakeup source status bit 30" "Not cleared,Cleared"
|
|
bitfld.long 0x00 29. " [29] ,Clear wakeup source status bit 29" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Clear wakeup source status bit 28" "Not cleared,Cleared"
|
|
bitfld.long 0x00 27. " [27] ,Clear wakeup source status bit 27" "Not cleared,Cleared"
|
|
bitfld.long 0x00 26. " [26] ,Clear wakeup source status bit 26" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Clear wakeup source status bit 25" "Not cleared,Cleared"
|
|
bitfld.long 0x00 24. " [24] ,Clear wakeup source status bit 24" "Not cleared,Cleared"
|
|
bitfld.long 0x00 23. " [23] ,Clear wakeup source status bit 23" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Clear wakeup source status bit 22" "Not cleared,Cleared"
|
|
bitfld.long 0x00 21. " [21] ,Clear wakeup source status bit 21" "Not cleared,Cleared"
|
|
bitfld.long 0x00 20. " [20] ,Clear wakeup source status bit 20" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Clear wakeup source status bit 19" "Not cleared,Cleared"
|
|
bitfld.long 0x00 18. " [18] ,Clear wakeup source status bit 18" "Not cleared,Cleared"
|
|
bitfld.long 0x00 17. " [17] ,Clear wakeup source status bit 17" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Clear wakeup source status bit 16" "Not cleared,Cleared"
|
|
bitfld.long 0x00 15. " [15] ,Clear wakeup source status bit 15" "Not cleared,Cleared"
|
|
bitfld.long 0x00 14. " [14] ,Clear wakeup source status bit 14" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Clear wakeup source status bit 13" "Not cleared,Cleared"
|
|
bitfld.long 0x00 12. " [12] ,Clear wakeup source status bit 12" "Not cleared,Cleared"
|
|
bitfld.long 0x00 11. " [11] ,Clear wakeup source status bit 11" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Clear wakeup source status bit 10" "Not cleared,Cleared"
|
|
bitfld.long 0x00 9. " [9] ,Clear wakeup source status bit 9" "Not cleared,Cleared"
|
|
bitfld.long 0x00 8. " [8] ,Clear wakeup source status bit 8" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Clear wakeup source status bit 7" "Not cleared,Cleared"
|
|
bitfld.long 0x00 6. " [6] ,Clear wakeup source status bit 6" "Not cleared,Cleared"
|
|
bitfld.long 0x00 5. " [5] ,Clear wakeup source status bit 5" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Clear wakeup source status bit 4" "Not cleared,Cleared"
|
|
bitfld.long 0x00 3. " [3] ,Clear wakeup source status bit 3" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " [2] ,Clear wakeup source status bit 2" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Clear wakeup source status bit 1" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " [0] ,Clear wakeup source status bit 0" "Not cleared,Cleared"
|
|
line.long 0x04 "PWRSMWAKESRCSTATCLR1,Power SM Wake Source Status Clear 1 Register"
|
|
bitfld.long 0x04 31. " PWRSMWAKESRCSTATCLR1[63] ,Clear wakeup source status bit 63" "Not cleared,Cleared"
|
|
bitfld.long 0x04 30. " [62] ,Clear wakeup source status bit 62" "Not cleared,Cleared"
|
|
bitfld.long 0x04 29. " [61] ,Clear wakeup source status bit 61" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 28. " [60] ,Clear wakeup source status bit 60" "Not cleared,Cleared"
|
|
bitfld.long 0x04 27. " [59] ,Clear wakeup source status bit 59" "Not cleared,Cleared"
|
|
bitfld.long 0x04 26. " [58] ,Clear wakeup source status bit 58" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 25. " [57] ,Clear wakeup source status bit 57" "Not cleared,Cleared"
|
|
bitfld.long 0x04 24. " [56] ,Clear wakeup source status bit 56" "Not cleared,Cleared"
|
|
bitfld.long 0x04 23. " [55] ,Clear wakeup source status bit 55" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 22. " [54] ,Clear wakeup source status bit 54" "Not cleared,Cleared"
|
|
bitfld.long 0x04 21. " [53] ,Clear wakeup source status bit 53" "Not cleared,Cleared"
|
|
bitfld.long 0x04 20. " [52] ,Clear wakeup source status bit 52" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 19. " [51] ,Clear wakeup source status bit 51" "Not cleared,Cleared"
|
|
bitfld.long 0x04 18. " [50] ,Clear wakeup source status bit 50" "Not cleared,Cleared"
|
|
bitfld.long 0x04 17. " [49] ,Clear wakeup source status bit 49" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 16. " [48] ,Clear wakeup source status bit 48" "Not cleared,Cleared"
|
|
bitfld.long 0x04 15. " [47] ,Clear wakeup source status bit 47" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [46] ,Clear wakeup source status bit 46" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 13. " [45] ,Clear wakeup source status bit 45" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [44] ,Clear wakeup source status bit 44" "Not cleared,Cleared"
|
|
bitfld.long 0x04 11. " [43] ,Clear wakeup source status bit 43" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 10. " [42] ,Clear wakeup source status bit 42" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [41] ,Clear wakeup source status bit 41" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [40] ,Clear wakeup source status bit 40" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [39] ,Clear wakeup source status bit 39" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [38] ,Clear wakeup source status bit 38" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [37] ,Clear wakeup source status bit 37" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 4. " [36] ,Clear wakeup source status bit 36" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " [35] ,Clear wakeup source status bit 35" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [34] ,Clear wakeup source status bit 34" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,Clear wakeup source status bit 33" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [32] ,Clear wakeup source status bit 32" "Not cleared,Cleared"
|
|
line.long 0x08 "PWRSMWAKESRCSTATCLR2,Power SM Wake Source Status Clear 2 Register"
|
|
bitfld.long 0x08 31. " PWRSMWAKESRCSTATCLR2[95] ,Clear wakeup source status bit 95" "Not cleared,Cleared"
|
|
bitfld.long 0x08 30. " [94] ,Clear wakeup source status bit 94" "Not cleared,Cleared"
|
|
bitfld.long 0x08 29. " [93] ,Clear wakeup source status bit 93" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 28. " [92] ,Clear wakeup source status bit 92" "Not cleared,Cleared"
|
|
bitfld.long 0x08 27. " [91] ,Clear wakeup source status bit 91" "Not cleared,Cleared"
|
|
bitfld.long 0x08 26. " [90] ,Clear wakeup source status bit 90" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 25. " [89] ,Clear wakeup source status bit 89" "Not cleared,Cleared"
|
|
bitfld.long 0x08 24. " [88] ,Clear wakeup source status bit 88" "Not cleared,Cleared"
|
|
bitfld.long 0x08 23. " [87] ,Clear wakeup source status bit 87" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 22. " [86] ,Clear wakeup source status bit 86" "Not cleared,Cleared"
|
|
bitfld.long 0x08 21. " [85] ,Clear wakeup source status bit 85" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " [84] ,Clear wakeup source status bit 84" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 19. " [83] ,Clear wakeup source status bit 83" "Not cleared,Cleared"
|
|
bitfld.long 0x08 18. " [82] ,Clear wakeup source status bit 82" "Not cleared,Cleared"
|
|
bitfld.long 0x08 17. " [81] ,Clear wakeup source status bit 81" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 16. " [80] ,Clear wakeup source status bit 80" "Not cleared,Cleared"
|
|
bitfld.long 0x08 15. " [79] ,Clear wakeup source status bit 79" "Not cleared,Cleared"
|
|
bitfld.long 0x08 14. " [78] ,Clear wakeup source status bit 78" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 13. " [77] ,Clear wakeup source status bit 77" "Not cleared,Cleared"
|
|
bitfld.long 0x08 12. " [76] ,Clear wakeup source status bit 76" "Not cleared,Cleared"
|
|
bitfld.long 0x08 11. " [75] ,Clear wakeup source status bit 75" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 10. " [74] ,Clear wakeup source status bit 74" "Not cleared,Cleared"
|
|
bitfld.long 0x08 9. " [73] ,Clear wakeup source status bit 73" "Not cleared,Cleared"
|
|
bitfld.long 0x08 8. " [72] ,Clear wakeup source status bit 72" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 7. " [71] ,Clear wakeup source status bit 71" "Not cleared,Cleared"
|
|
bitfld.long 0x08 6. " [70] ,Clear wakeup source status bit 70" "Not cleared,Cleared"
|
|
bitfld.long 0x08 5. " [69] ,Clear wakeup source status bit 69" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 4. " [68] ,Clear wakeup source status bit 68" "Not cleared,Cleared"
|
|
bitfld.long 0x08 3. " [67] ,Clear wakeup source status bit 67" "Not cleared,Cleared"
|
|
bitfld.long 0x08 2. " [66] ,Clear wakeup source status bit 66" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 1. " [65] ,Clear wakeup source status bit 65" "Not cleared,Cleared"
|
|
bitfld.long 0x08 0. " [64] ,Clear wakeup source status bit 64" "Not cleared,Cleared"
|
|
line.long 0x0C "ADCBUFCFG1,ADC Buffer Configuration 1 Register"
|
|
bitfld.long 0x0C 15. " ADCBUFCONTSTOPPL ,Enable stop pulse for continuous mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " ADCBUFCONTSTRTPL ,Enable start pulse for continuous mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " ADCBUFCONTMODEEN ,Continuous mode enable for ADC buffer" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 12. " ADCBUFWRITEMODE ,ADC buffer write mode" "Interleaved,Non-interleaved"
|
|
bitfld.long 0x0C 9. " RX3EN ,Enable for Rx3 write" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " RX2EN ,Enable for Rx2 write" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 7. " RX1EN ,Enable for Rx1 write" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " RX0EN ,Enable for Rx0 write" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " ADCBUFIQSWAP ,ADC buffer I/Q swap" "I LSB / Q MSB,I MSB / Q LSB"
|
|
newline
|
|
bitfld.long 0x0C 2. " ADCBUFREALONLYMODE ,ADC buffer mode select" "Complex,Real"
|
|
line.long 0x10 "ADCBUFCFG2,ADC Buffer Configuration 2 Register"
|
|
hexmask.long.word 0x10 16.--26. 0x01 " ADCBUFADDRX1 ,128 bit address offset 1"
|
|
hexmask.long.word 0x10 0.--10. 0x01 " ADCBUFADDRX0 ,128 bit address offset 0"
|
|
line.long 0x14 "ADCBUFCFG3,ADC Buffer Configuration 3 Register"
|
|
hexmask.long.word 0x14 16.--26. 0x01 " ADCBUFADDRX3 ,128 bit address offset 3"
|
|
hexmask.long.word 0x14 0.--10. 0x01 " ADCBUFADDRX2 ,128 bit address offset 2"
|
|
line.long 0x18 "ADCBUFCFG4,ADC Buffer Configuration 4 Register"
|
|
bitfld.long 0x18 21.--25. " ADCBUFNUMCHRPPONG ,Number of chirps to be stored in pong buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x18 16.--20. " ADCBUFNUMCHRPPING ,Number of chirps to be stored in ping buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x18 0.--15. 1. " ADCBUFSAMPCNT ,ADC buffer samples counter"
|
|
line.long 0x1C "STCPBISTSMCFG1,STC PBIST SM Configuration 1 Register"
|
|
rbitfld.long 0x1C 20. " PBISTTESTSTATCLR ,Clear bit for PBIST status" "Not cleared,Cleared"
|
|
rbitfld.long 0x1C 19. " PBISTTESTSTAT[1] ,PBIST fail indication from GEM" "Not failed,Failed"
|
|
rbitfld.long 0x1C 18. " PBISTTESTSTAT[0] ,PBIST done indication from GEM" "Not done,Done"
|
|
newline
|
|
rbitfld.long 0x1C 12.--17. " STCPBISTSMSTATE ,Current state of STC PBIST state machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x1C 4. " STCPBISTCKSTPACKMASK ,Mask bit for ignoring the clock stop ACK from GEM" "Not masked,Masked"
|
|
bitfld.long 0x1C 3. " STCPBISTLRSTDASRTHALT ,Configuration to halt the state machine before the final de-assertion of LRST" "Proceeded,Halt"
|
|
newline
|
|
bitfld.long 0x1C 2. " STCPBISTSMTRIG ,Trigger pulse for the STC PBIST state machine" "Not triggered,Triggered"
|
|
bitfld.long 0x1C 0.--1. " STCPBISTEN ,Enable for PBIST and STC" ",STC,PBIST,Both"
|
|
line.long 0x20 "STCPBISTSMCFG2,STC PBIST SM Configuration 2 Register"
|
|
bitfld.long 0x20 16. " BCK2BCKSTCEN ,Enables back to back STC" "Disabled,Enabled"
|
|
bitfld.long 0x20 12.--13. " GEMPBISTROMCLKSEL ,GEM PBIST ROM clock frequency" "600 Mhz,300 Mhz,200 Mhz,150 Mhz"
|
|
bitfld.long 0x20 6.--11. " GEMTMODEVLCTASRTCNT ,No of clocks after asserting GEM TMODE VLCT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
|
|
newline
|
|
bitfld.long 0x20 0.--5. " GEMTMODEVLCTDASRTCNT ,No of clocks after de-asserting GEM TMODE VLCT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
|
|
group.long 0x358++0x07
|
|
line.long 0x00 "RTI2EVENTCAPTURESEL,RTI2 Event Captured Select Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " RTI2EVT1 ,Used to select the event to be captured for RTI2 event 1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RTI2EVT0 ,Used to select the event to be captured for RTI2 event 0"
|
|
line.long 0x04 "DSSMISC5,DSS Miscellaneous 5 Register"
|
|
rbitfld.long 0x04 7. " TPCC1PARMEMINITDONE ,Memory initialization done status for the TPCC1 parity memory" "Disabled,Enabled"
|
|
rbitfld.long 0x04 6. " TPCC0PARMEMINITDONE ,Memory initialization done status for the TPCC0 parity memory" "Disabled,Enabled"
|
|
rbitfld.long 0x04 5. " TPCC1PARMEMINIT ,Memory initialization for the TPCC1 parity memory" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x04 4. " TPCC0PARMEMINIT ,Memory initialization for the TPCC0 parity memory" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CPBPMPIPOSELVAL ,Ping pong select override value for CPBPM (Read/Write)" "Pong/Ping,Ping/Pong"
|
|
bitfld.long 0x04 2. " CPBPMPIPOSELCNT ,Ping pong select override control for CPBPM memory" "SW register,HW FSM"
|
|
newline
|
|
bitfld.long 0x04 1. " CQPIPOSELVAL ,Ping pong select override value for CQ memory (Read/Write)" "Pong/Ping,Ping/Pong"
|
|
bitfld.long 0x04 0. " CQPIPOSELCNT ,Ping pong select override control for CQ memory" "SW register,HW FSM"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DSS REG2 Registers"
|
|
base ad:0x50000C00
|
|
width 19.
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "TPTC2WRMPUSTADD0,TPTC2 Start Address Write For Region 0 Register"
|
|
line.long 0x04 "TPTC2WRMPUSTADD1,TPTC2 Start Address Write For Region 1 Register"
|
|
line.long 0x08 "TPTC2WRMPUSTADD2,TPTC2 Start Address Write For Region 2 Register"
|
|
line.long 0x0C "TPTC2WRMPUSTADD3,TPTC2 Start Address Write For Region 3 Register"
|
|
line.long 0x10 "TPTC2WRMPUSTADD4,TPTC2 Start Address Write For Region 4 Register"
|
|
line.long 0x14 "TPTC2WRMPUSTADD5,TPTC2 Start Address Write For Region 5 Register"
|
|
group.long 0x120++0x17
|
|
line.long 0x00 "TPTC2WRMPUENDADD0,TPTC2 End Address Write For Region 0 Register"
|
|
line.long 0x04 "TPTC2WRMPUENDADD1,TPTC2 End Address Write For Region 1 Register"
|
|
line.long 0x08 "TPTC2WRMPUENDADD2,TPTC2 End Address Write For Region 2 Register"
|
|
line.long 0x0C "TPTC2WRMPUENDADD3,TPTC2 End Address Write For Region 3 Register"
|
|
line.long 0x10 "TPTC2WRMPUENDADD4,TPTC2 End Address Write For Region 4 Register"
|
|
line.long 0x14 "TPTC2WRMPUENDADD5,TPTC2 End Address Write For Region 5 Register"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "TPTC2WRMPUERRADD,TPTC2 Write Address Status Register"
|
|
group.long 0x148++0x17
|
|
line.long 0x00 "TPTC2RDMPUSTADD0,TPTC2 Start Address Read For Region 0 Register"
|
|
line.long 0x04 "TPTC2RDMPUSTADD1,TPTC2 Start Address Read For Region 1 Register"
|
|
line.long 0x08 "TPTC2RDMPUSTADD2,TPTC2 Start Address Read For Region 2 Register"
|
|
line.long 0x0C "TPTC2RDMPUSTADD3,TPTC2 Start Address Read For Region 3 Register"
|
|
line.long 0x10 "TPTC2RDMPUSTADD4,TPTC2 Start Address Read For Region 4 Register"
|
|
line.long 0x14 "TPTC2RDMPUSTADD5,TPTC2 Start Address Read For Region 5 Register"
|
|
group.long 0x168++0x17
|
|
line.long 0x00 "TPTC2RDMPUENDADD0,TPTC2 End Address Read For Region 0 Register"
|
|
line.long 0x04 "TPTC2RDMPUENDADD1,TPTC2 End Address Read For Region 1 Register"
|
|
line.long 0x08 "TPTC2RDMPUENDADD2,TPTC2 End Address Read For Region 2 Register"
|
|
line.long 0x0C "TPTC2RDMPUENDADD3,TPTC2 End Address Read For Region 3 Register"
|
|
line.long 0x10 "TPTC2RDMPUENDADD4,TPTC2 End Address Read For Region 4 Register"
|
|
line.long 0x14 "TPTC2RDMPUENDADD5,TPTC2 End Address Read For Region 5 Register"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "TPTC2RDMPUERRADD,TPTC2 Read Address Status Register"
|
|
group.long 0x18C++0x17
|
|
line.long 0x00 "TPTC3WRMPUSTADD0,TPTC3 Start Address Write For Region 0 Register"
|
|
line.long 0x04 "TPTC3WRMPUSTADD1,TPTC3 Start Address Write For Region 1 Register"
|
|
line.long 0x08 "TPTC3WRMPUSTADD2,TPTC3 Start Address Write For Region 2 Register"
|
|
line.long 0x0C "TPTC3WRMPUSTADD3,TPTC3 Start Address Write For Region 3 Register"
|
|
line.long 0x10 "TPTC3WRMPUSTADD4,TPTC3 Start Address Write For Region 4 Register"
|
|
line.long 0x14 "TPTC3WRMPUSTADD5,TPTC3 Start Address Write For Region 5 Register"
|
|
group.long 0x1AC++0x17
|
|
line.long 0x00 "TPTC3WRMPUENDADD0,TPTC3 End Address Write For Region 0 Register"
|
|
line.long 0x04 "TPTC3WRMPUENDADD1,TPTC3 End Address Write For Region 1 Register"
|
|
line.long 0x08 "TPTC3WRMPUENDADD2,TPTC3 End Address Write For Region 2 Register"
|
|
line.long 0x0C "TPTC3WRMPUENDADD3,TPTC3 End Address Write For Region 3 Register"
|
|
line.long 0x10 "TPTC3WRMPUENDADD4,TPTC3 End Address Write For Region 4 Register"
|
|
line.long 0x14 "TPTC3WRMPUENDADD5,TPTC3 End Address Write For Region 5 Register"
|
|
rgroup.long 0x1CC++0x03
|
|
line.long 0x00 "TPTC3WRMPUERRADD,TPTC3 Write Address Status Register"
|
|
group.long 0x1D0++0x17
|
|
line.long 0x00 "TPTC3RDMPUSTADD0,TPTC3 Start Address Read For Region 0 Register"
|
|
line.long 0x04 "TPTC3RDMPUSTADD1,TPTC3 Start Address Read For Region 1 Register"
|
|
line.long 0x08 "TPTC3RDMPUSTADD2,TPTC3 Start Address Read For Region 2 Register"
|
|
line.long 0x0C "TPTC3RDMPUSTADD3,TPTC3 Start Address Read For Region 3 Register"
|
|
line.long 0x10 "TPTC3RDMPUSTADD4,TPTC3 Start Address Read For Region 4 Register"
|
|
line.long 0x14 "TPTC3RDMPUSTADD5,TPTC3 Start Address Read For Region 5 Register"
|
|
group.long 0x1F0++0x17
|
|
line.long 0x00 "TPTC3RDMPUENDADD0,TPTC3 End Address Read For Region 0 Register"
|
|
line.long 0x04 "TPTC3RDMPUENDADD1,TPTC3 End Address Read For Region 1 Register"
|
|
line.long 0x08 "TPTC3RDMPUENDADD2,TPTC3 End Address Read For Region 2 Register"
|
|
line.long 0x0C "TPTC3RDMPUENDADD3,TPTC3 End Address Read For Region 3 Register"
|
|
line.long 0x10 "TPTC3RDMPUENDADD4,TPTC3 End Address Read For Region 4 Register"
|
|
line.long 0x14 "TPTC3RDMPUENDADD5,TPTC3 End Address Read For Region 5 Register"
|
|
rgroup.long 0x210++0x03
|
|
line.long 0x00 "TPTC3RDMPUERRADD,TPTC3 Read Address Status Register"
|
|
group.long 0x214++0x07
|
|
line.long 0x00 "TPTCMPUVALIDCFG2,TPTCMPUVALIDCFG2 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TPTC3RDMPURNGVLD ,TPTC3 read valid bit for each address range for the MPU"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TPTC3WRMPURNGVLD ,TPTC3 write valid bit for each address range for the MPU"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " TPTC2RDMPURNGVLD ,TPTC2 read valid bit for each address range for the MPU"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TPTC2WRMPURNGVLD ,TPTC2 write valid bit for each address range for the MPU"
|
|
line.long 0x04 "TPTCMPUENCFG2,TPTCMPUENCFG2 Register"
|
|
eventfld.long 0x04 7. " TPTC3RDMPUERRCLR ,Clear flag for error from the MPU in the read port of TPTC3" "Not occurred,Occurred"
|
|
eventfld.long 0x04 6. " TPTC3WRMPUERRCLR ,Clear flag for error from the MPU in the write port of TPTC3" "Not occurred,Occurred"
|
|
eventfld.long 0x04 5. " TPTC2RDMPUERRCLR ,Clear flag for error from the MPU in the read port of TPTC2" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 4. " TPTC2WRMPUERRCLR ,Clear flag for error from the MPU in the write port of TPTC2" "Not occurred,Occurred"
|
|
bitfld.long 0x04 3. " TPTC3RDMPUEN ,MPU in the read port of TPTC3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " TPTC3WRMPUEN ,MPU in the write port of TPTC3 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " TPTC2RDMPUEN ,MPU in the read port of TPTC2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TPTC2WRMPUEN ,MPU in the write port of TPTC2 enable" "Disabled,Enabled"
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "L3ECCCFG1,L3ECCCFG1 Register"
|
|
hexmask.long.tbyte 0x00 3.--26. 1. " L3ECCREPAIREDBIT ,Bit position of repaired bit in L3 ECC memory"
|
|
rbitfld.long 0x00 2. " L3ECCERRSTAT ,L3 ECC error latched status" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 1. " L3ECCERRCLR ,L3 ECC clear bit" "No clear,Clear"
|
|
bitfld.long 0x00 0. " L3ECCEN ,L3 ECC logic enable" "Disabled,Enabled"
|
|
rgroup.long 0x26C++0x03
|
|
line.long 0x00 "L3ECCCFG2,L3ECCCFG2 Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 0x01 " L3ECCFAULTADDR ,Fault address of L3 ECC memory"
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "DSS2MSSSWIRQ,DSS2MSSSWIRQ Register"
|
|
bitfld.long 0x00 1. " MSSSWIRQ2 ,Generate a pulse from DSS to MSS VIM line 61" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MSSSWIRQ1 ,Generate a pulse from DSS to MSS VIM line 52" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.open "DMA (Direct Memory Access Controller)"
|
|
tree "DMA1"
|
|
base ad:0xFFFFF000
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCTRL,Global Control Register"
|
|
bitfld.long 0x00 16. " DMA_EN ,DMA enable" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS3137-EP")||cpuis("AWR1843")||cpuis("AWR1843-CORE1")||cpuis("AWR1843DSP")||cpuis("AWR6843*")
|
|
rbitfld.long 0x00 14. " BUS_BUSY ,DMA external AHB bus status" "Not busy,Busy"
|
|
else
|
|
bitfld.long 0x00 14. " BUS_BUSY ,DMA external AHB bus status" "Not busy,Busy"
|
|
endif
|
|
bitfld.long 0x00 8.--9. " DEBUG_MODE ,Debug mode" "Suspend ignored,Block finished,Frame finished,Immediate stop"
|
|
newline
|
|
bitfld.long 0x00 0. " DMA_RES ,DMA software reset" "No reset,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PEND,Channel Pending Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " PEND[31] ,Channel 31 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 30. " [30] ,Channel 30 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 29. " [29] ,Channel 29 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 28. " [28] ,Channel 28 pending register" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Channel 27 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 26. " [26] ,Channel 26 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 25. " [25] ,Channel 25 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 24. " [24] ,Channel 24 pending register" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Channel 23 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 22. " [22] ,Channel 22 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 21. " [21] ,Channel 21 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 20. " [20] ,Channel 20 pending register" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel 19 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 18. " [18] ,Channel 18 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 17. " [17] ,Channel 17 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 16. " [16] ,Channel 16 pending register" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel 15 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 pending register" "Inactive,Pending"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " PEND[15] ,Channel 15 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 pending register" "Inactive,Pending"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Channel 11 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Channel 10 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Channel 9 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 8. " [8] ,Channel 8 pending register" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel 7 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 pending register" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 pending register" "Inactive,Pending"
|
|
sif cpuis("AWR1443")||cpuis("AWR1443-CORE0")||cpuis("AWR1443-CORE1")||cpuis("AWR1642")||cpuis("AWR1642-CORE1")||cpuis("AWR1843")||cpuis("AWR1843-CORE1")||cpuis("AWR1843DSP")||cpuis("AWR6843*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FBREG,Fall Back Register For EMC"
|
|
bitfld.long 0x00 8.--11. " FSMFB ,Switch off RTL clock gating for all FSM logics used for saving power" ",,,,,Enabled,,,,,Disabled,?..."
|
|
bitfld.long 0x00 0.--3. " VBUSPFB ,Switch off RTL clock gating for all VBUSP logics used for saving power" ",,,,,Enabled,,,,,Disabled,?..."
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DMASTAT,DMA Status Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " STCH[31] ,Status of DMA channel 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " [30] ,Status of DMA channel 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " [29] ,Status of DMA channel 29" "Inactive,Active"
|
|
bitfld.long 0x00 28. " [28] ,Status of DMA channel 28" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Status of DMA channel 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " [26] ,Status of DMA channel 26" "Inactive,Active"
|
|
bitfld.long 0x00 25. " [25] ,Status of DMA channel 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " [24] ,Status of DMA channel 24" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Status of DMA channel 23" "Inactive,Active"
|
|
bitfld.long 0x00 22. " [22] ,Status of DMA channel 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " [21] ,Status of DMA channel 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " [20] ,Status of DMA channel 20" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Status of DMA channel 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " [18] ,Status of DMA channel 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " [17] ,Status of DMA channel 17" "Inactive,Active"
|
|
bitfld.long 0x00 16. " [16] ,Status of DMA channel 16" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Status of DMA channel 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " [14] ,Status of DMA channel 14" "Inactive,Active"
|
|
bitfld.long 0x00 13. " [13] ,Status of DMA channel 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " [12] ,Status of DMA channel 12" "Inactive,Active"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " STCH[15] ,Status of DMA channel 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " [14] ,Status of DMA channel 14" "Inactive,Active"
|
|
bitfld.long 0x00 13. " [13] ,Status of DMA channel 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " [12] ,Status of DMA channel 12" "Inactive,Active"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Status of DMA channel 11" "Inactive,Active"
|
|
bitfld.long 0x00 10. " [10] ,Status of DMA channel 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " [9] ,Status of DMA channel 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " [8] ,Status of DMA channel 8" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Status of DMA channel 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " [6] ,Status of DMA channel 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " [5] ,Status of DMA channel 5" "Inactive,Active"
|
|
bitfld.long 0x00 4. " [4] ,Status of DMA channel 4" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Status of DMA channel 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " [2] ,Status of DMA channel 2" "Inactive,Active"
|
|
bitfld.long 0x00 1. " [1] ,Status of DMA channel 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " [0] ,Status of DMA channel 0" "Inactive,Active"
|
|
width 10.
|
|
tree "Channel Enable Status Registers"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "HWCHENAS,HWCHANNEL Enable Set And Status Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " HWCHENA[31] ,HW channel 31 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,HW channel 30 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,HW channel 29 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,HW channel 28 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,HW channel 27 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,HW channel 26 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,HW channel 25 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,HW channel 24 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,HW channel 23 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,HW channel 22 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,HW channel 21 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,HW channel 20 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,HW channel 19 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,HW channel 18 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,HW channel 17 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,HW channel 16 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,HW channel 15 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,HW channel 14 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,HW channel 13 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,HW channel 12 enable status" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " HWCHENA[15] ,HW channel 15 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,HW channel 14 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,HW channel 13 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,HW channel 12 enable status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,HW channel 11 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,HW channel 10 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,HW channel 9 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,HW channel 8 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,HW channel 7 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,HW channel 6 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,HW channel 5 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,HW channel 4 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,HW channel 3 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,HW channel 2 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,HW channel 1 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,HW channel 0 enable status" "Disabled,Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "HWCHENAR,HWCHANNEL Enable Reset And Status Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " HWCHDIS[31] ,HW channel 31 disable" "No effect,Reset"
|
|
bitfld.long 0x00 30. " [30] ,HW channel 30 disable" "No effect,Reset"
|
|
bitfld.long 0x00 29. " [29] ,HW channel 29 disable" "No effect,Reset"
|
|
bitfld.long 0x00 28. " [28] ,HW channel 28 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,HW channel 27 disable" "No effect,Reset"
|
|
bitfld.long 0x00 26. " [26] ,HW channel 26 disable" "No effect,Reset"
|
|
bitfld.long 0x00 25. " [25] ,HW channel 25 disable" "No effect,Reset"
|
|
bitfld.long 0x00 24. " [24] ,HW channel 24 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,HW channel 23 disable" "No effect,Reset"
|
|
bitfld.long 0x00 22. " [22] ,HW channel 22 disable" "No effect,Reset"
|
|
bitfld.long 0x00 21. " [21] ,HW channel 21 disable" "No effect,Reset"
|
|
bitfld.long 0x00 20. " [20] ,HW channel 20 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,HW channel 19 disable" "No effect,Reset"
|
|
bitfld.long 0x00 18. " [18] ,HW channel 18 disable" "No effect,Reset"
|
|
bitfld.long 0x00 17. " [17] ,HW channel 17 disable" "No effect,Reset"
|
|
bitfld.long 0x00 16. " [16] ,HW channel 16 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,HW channel 15 disable" "No effect,Reset"
|
|
bitfld.long 0x00 14. " [14] ,HW channel 14 disable" "No effect,Reset"
|
|
bitfld.long 0x00 13. " [13] ,HW channel 13 disable" "No effect,Reset"
|
|
bitfld.long 0x00 12. " [12] ,HW channel 12 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,HW channel 11 disable" "No effect,Reset"
|
|
bitfld.long 0x00 10. " [10] ,HW channel 10 disable" "No effect,Reset"
|
|
bitfld.long 0x00 9. " [9] ,HW channel 9 disable" "No effect,Reset"
|
|
bitfld.long 0x00 8. " [8] ,HW channel 8 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,HW channel 7 disable" "No effect,Reset"
|
|
bitfld.long 0x00 6. " [6] ,HW channel 6 disable" "No effect,Reset"
|
|
bitfld.long 0x00 5. " [5] ,HW channel 5 disable" "No effect,Reset"
|
|
bitfld.long 0x00 4. " [4] ,HW channel 4 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,HW channel 3 disable" "No effect,Reset"
|
|
bitfld.long 0x00 2. " [2] ,HW channel 2 disable" "No effect,Reset"
|
|
bitfld.long 0x00 1. " [1] ,HW channel 1 disable" "No effect,Reset"
|
|
bitfld.long 0x00 0. " [0] ,HW channel 0 disable" "No effect,Reset"
|
|
else
|
|
eventfld.long 0x00 15. " HWCHDIS[15] ,HW channel 15 disable" "No effect,Reset"
|
|
eventfld.long 0x00 14. " [14] ,HW channel 14 disable" "No effect,Reset"
|
|
eventfld.long 0x00 13. " [13] ,HW channel 13 disable" "No effect,Reset"
|
|
eventfld.long 0x00 12. " [12] ,HW channel 12 disable" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,HW channel 11 disable" "No effect,Reset"
|
|
eventfld.long 0x00 10. " [10] ,HW channel 10 disable" "No effect,Reset"
|
|
eventfld.long 0x00 9. " [9] ,HW channel 9 disable" "No effect,Reset"
|
|
eventfld.long 0x00 8. " [8] ,HW channel 8 disable" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,HW channel 7 disable" "No effect,Reset"
|
|
eventfld.long 0x00 6. " [6] ,HW channel 6 disable" "No effect,Reset"
|
|
eventfld.long 0x00 5. " [5] ,HW channel 5 disable" "No effect,Reset"
|
|
eventfld.long 0x00 4. " [4] ,HW channel 4 disable" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,HW channel 3 disable" "No effect,Reset"
|
|
eventfld.long 0x00 2. " [2] ,HW channel 2 disable" "No effect,Reset"
|
|
eventfld.long 0x00 1. " [1] ,HW channel 1 disable" "No effect,Reset"
|
|
eventfld.long 0x00 0. " [0] ,HW channel 0 disable" "No effect,Reset"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SWCHENAS,SWCHANNEL Enable Set And Status Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " SWCHENA[31] ,SW channel 31 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 30. " [30] ,SW channel 30 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 29. " [29] ,SW channel 29 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 28. " [28] ,SW channel 28 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SW channel 27 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 26. " [26] ,SW channel 26 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 25. " [25] ,SW channel 25 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 24. " [24] ,SW channel 24 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SW channel 23 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 22. " [22] ,SW channel 22 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 21. " [21] ,SW channel 21 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20. " [20] ,SW channel 20 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SW channel 19 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 18. " [18] ,SW channel 18 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 17. " [17] ,SW channel 17 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 16. " [16] ,SW channel 16 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SW channel 15 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 14. " [14] ,SW channel 14 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 13. " [13] ,SW channel 13 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 12. " [12] ,SW channel 12 enable status" "Not triggered,Triggered"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " SWCHENA[15] ,SW channel 15 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 14. " [14] ,SW channel 14 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 13. " [13] ,SW channel 13 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 12. " [12] ,SW channel 12 enable status" "Not triggered,Triggered"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,SW channel 11 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 10. " [10] ,SW channel 10 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 9. " [9] ,SW channel 9 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 8. " [8] ,SW channel 8 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SW channel 7 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 6. " [6] ,SW channel 6 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 5. " [5] ,SW channel 5 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 4. " [4] ,SW channel 4 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SW channel 3 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 2. " [2] ,SW channel 2 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 1. " [1] ,SW channel 1 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " [0] ,SW channel 0 enable status" "Not triggered,Triggered"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SWCHENAR,SWCHANNEL Enable Reset And Status Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " SWCHDIS[31] ,SW channel 31 disable" "No effect,Reset"
|
|
bitfld.long 0x00 30. " [30] ,SW channel 30 disable" "No effect,Reset"
|
|
bitfld.long 0x00 29. " [29] ,SW channel 29 disable" "No effect,Reset"
|
|
bitfld.long 0x00 28. " [28] ,SW channel 28 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SW channel 27 disable" "No effect,Reset"
|
|
bitfld.long 0x00 26. " [26] ,SW channel 26 disable" "No effect,Reset"
|
|
bitfld.long 0x00 25. " [25] ,SW channel 25 disable" "No effect,Reset"
|
|
bitfld.long 0x00 24. " [24] ,SW channel 24 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SW channel 23 disable" "No effect,Reset"
|
|
bitfld.long 0x00 22. " [22] ,SW channel 22 disable" "No effect,Reset"
|
|
bitfld.long 0x00 21. " [21] ,SW channel 21 disable" "No effect,Reset"
|
|
bitfld.long 0x00 20. " [20] ,SW channel 20 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SW channel 19 disable" "No effect,Reset"
|
|
bitfld.long 0x00 18. " [18] ,SW channel 18 disable" "No effect,Reset"
|
|
bitfld.long 0x00 17. " [17] ,SW channel 17 disable" "No effect,Reset"
|
|
bitfld.long 0x00 16. " [16] ,SW channel 16 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SW channel 15 disable" "No effect,Reset"
|
|
bitfld.long 0x00 14. " [14] ,SW channel 14 disable" "No effect,Reset"
|
|
bitfld.long 0x00 13. " [13] ,SW channel 13 disable" "No effect,Reset"
|
|
bitfld.long 0x00 12. " [12] ,SW channel 12 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SW channel 11 disable" "No effect,Reset"
|
|
bitfld.long 0x00 10. " [10] ,SW channel 10 disable" "No effect,Reset"
|
|
bitfld.long 0x00 9. " [9] ,SW channel 9 disable" "No effect,Reset"
|
|
bitfld.long 0x00 8. " [8] ,SW channel 8 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SW channel 7 disable" "No effect,Reset"
|
|
bitfld.long 0x00 6. " [6] ,SW channel 6 disable" "No effect,Reset"
|
|
bitfld.long 0x00 5. " [5] ,SW channel 5 disable" "No effect,Reset"
|
|
bitfld.long 0x00 4. " [4] ,SW channel 4 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SW channel 3 disable" "No effect,Reset"
|
|
bitfld.long 0x00 2. " [2] ,SW channel 2 disable" "No effect,Reset"
|
|
bitfld.long 0x00 1. " [1] ,SW channel 1 disable" "No effect,Reset"
|
|
bitfld.long 0x00 0. " [0] ,SW channel 0 disable" "No effect,Reset"
|
|
else
|
|
eventfld.long 0x00 15. " SWCHDIS[15] ,SW channel 15 disable" "No effect,Reset"
|
|
eventfld.long 0x00 14. " [14] ,SW channel 14 disable" "No effect,Reset"
|
|
eventfld.long 0x00 13. " [13] ,SW channel 13 disable" "No effect,Reset"
|
|
eventfld.long 0x00 12. " [12] ,SW channel 12 disable" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,SW channel 11 disable" "No effect,Reset"
|
|
eventfld.long 0x00 10. " [10] ,SW channel 10 disable" "No effect,Reset"
|
|
eventfld.long 0x00 9. " [9] ,SW channel 9 disable" "No effect,Reset"
|
|
eventfld.long 0x00 8. " [8] ,SW channel 8 disable" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,SW channel 7 disable" "No effect,Reset"
|
|
eventfld.long 0x00 6. " [6] ,SW channel 6 disable" "No effect,Reset"
|
|
eventfld.long 0x00 5. " [5] ,SW channel 5 disable" "No effect,Reset"
|
|
eventfld.long 0x00 4. " [4] ,SW channel 4 disable" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,SW channel 3 disable" "No effect,Reset"
|
|
eventfld.long 0x00 2. " [2] ,SW channel 2 disable" "No effect,Reset"
|
|
eventfld.long 0x00 1. " [1] ,SW channel 1 disable" "No effect,Reset"
|
|
eventfld.long 0x00 0. " [0] ,SW channel 0 disable" "No effect,Reset"
|
|
endif
|
|
tree.end
|
|
newline
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CHPRIOS,Channel Priority Set Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " CPS[31] ,Channel priority 31 set" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,Channel priority 30 set" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,Channel priority 29 set" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,Channel priority 28 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Channel priority 27 set" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,Channel priority 26 set" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,Channel priority 25 set" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Channel priority 24 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Channel priority 23 set" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,Channel priority 22 set" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Channel priority 21 set" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Channel priority 20 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel priority 19 set" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Channel priority 18 set" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,Channel priority 17 set" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Channel priority 16 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel priority 15 set" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Channel priority 14 set" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Channel priority 13 set" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Channel priority 12 set" "Low,High"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " CPS[15] ,Channel priority 15 set" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Channel priority 14 set" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Channel priority 13 set" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Channel priority 12 set" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Channel priority 11 set" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Channel priority 10 set" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Channel priority 9 set" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Channel priority 8 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel priority 7 set" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Channel priority 6 set" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Channel priority 5 set" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Channel priority 4 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel priority 3 set" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Channel priority 2 set" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Channel priority 1 set" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Channel priority 0 set" "Low,High"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CHPRIOR,Channel Priority Reset Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " CPL[31] ,Channel priority 31" "No effect,Reset"
|
|
bitfld.long 0x00 30. " [30] ,Channel priority 30" "No effect,Reset"
|
|
bitfld.long 0x00 29. " [29] ,Channel priority 29" "No effect,Reset"
|
|
bitfld.long 0x00 28. " [28] ,Channel priority 28" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Channel priority 27" "No effect,Reset"
|
|
bitfld.long 0x00 26. " [26] ,Channel priority 26" "No effect,Reset"
|
|
bitfld.long 0x00 25. " [25] ,Channel priority 25" "No effect,Reset"
|
|
bitfld.long 0x00 24. " [24] ,Channel priority 24" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Channel priority 23" "No effect,Reset"
|
|
bitfld.long 0x00 22. " [22] ,Channel priority 22" "No effect,Reset"
|
|
bitfld.long 0x00 21. " [21] ,Channel priority 21" "No effect,Reset"
|
|
bitfld.long 0x00 20. " [20] ,Channel priority 20" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel priority 19" "No effect,Reset"
|
|
bitfld.long 0x00 18. " [18] ,Channel priority 18" "No effect,Reset"
|
|
bitfld.long 0x00 17. " [17] ,Channel priority 17" "No effect,Reset"
|
|
bitfld.long 0x00 16. " [16] ,Channel priority 16" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel priority 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " [14] ,Channel priority 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " [13] ,Channel priority 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " [12] ,Channel priority 12" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel priority 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " [10] ,Channel priority 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " [9] ,Channel priority 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " [8] ,Channel priority 8" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel priority 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " [6] ,Channel priority 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " [5] ,Channel priority 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " [4] ,Channel priority 4" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel priority 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " [2] ,Channel priority 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " [1] ,Channel priority 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " [0] ,Channel priority 0" "No effect,Reset"
|
|
else
|
|
eventfld.long 0x00 15. " CPL[15] ,Channel priority 15" "No effect,Reset"
|
|
eventfld.long 0x00 14. " [14] ,Channel priority 14" "No effect,Reset"
|
|
eventfld.long 0x00 13. " [13] ,Channel priority 13" "No effect,Reset"
|
|
eventfld.long 0x00 12. " [12] ,Channel priority 12" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Channel priority 11" "No effect,Reset"
|
|
eventfld.long 0x00 10. " [10] ,Channel priority 10" "No effect,Reset"
|
|
eventfld.long 0x00 9. " [9] ,Channel priority 9" "No effect,Reset"
|
|
eventfld.long 0x00 8. " [8] ,Channel priority 8" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Channel priority 7" "No effect,Reset"
|
|
eventfld.long 0x00 6. " [6] ,Channel priority 6" "No effect,Reset"
|
|
eventfld.long 0x00 5. " [5] ,Channel priority 5" "No effect,Reset"
|
|
eventfld.long 0x00 4. " [4] ,Channel priority 4" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Channel priority 3" "No effect,Reset"
|
|
eventfld.long 0x00 2. " [2] ,Channel priority 2" "No effect,Reset"
|
|
eventfld.long 0x00 1. " [1] ,Channel priority 1" "No effect,Reset"
|
|
eventfld.long 0x00 0. " [0] ,Channel priority 0" "No effect,Reset"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "GCHIENAS,Global Channel Interrupt Enable Set Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " GCHIE[31] ,Global channel interrupt enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Global channel interrupt enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Global channel interrupt enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Global channel interrupt enable 28" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Global channel interrupt enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Global channel interrupt enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Global channel interrupt enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Global channel interrupt enable 24" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Global channel interrupt enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Global channel interrupt enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Global channel interrupt enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Global channel interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Global channel interrupt enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Global channel interrupt enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Global channel interrupt enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Global channel interrupt enable 16" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Global channel interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Global channel interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Global channel interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Global channel interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " GCHIE[15] ,Global channel interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Global channel interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Global channel interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Global channel interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Global channel interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Global channel interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Global channel interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Global channel interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Global channel interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Global channel interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Global channel interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Global channel interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Global channel interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Global channel interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Global channel interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Global channel interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GCHIENAR,Global Channel Interrupt Enable Reset Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " GCHID[31] ,Global channel interrupt disable 31" "No effect,Reset"
|
|
bitfld.long 0x00 30. " [30] ,Global channel interrupt disable 30" "No effect,Reset"
|
|
bitfld.long 0x00 29. " [29] ,Global channel interrupt disable 29" "No effect,Reset"
|
|
bitfld.long 0x00 28. " [28] ,Global channel interrupt disable 28" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Global channel interrupt disable 27" "No effect,Reset"
|
|
bitfld.long 0x00 26. " [26] ,Global channel interrupt disable 26" "No effect,Reset"
|
|
bitfld.long 0x00 25. " [25] ,Global channel interrupt disable 25" "No effect,Reset"
|
|
bitfld.long 0x00 24. " [24] ,Global channel interrupt disable 24" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Global channel interrupt disable 23" "No effect,Reset"
|
|
bitfld.long 0x00 22. " [22] ,Global channel interrupt disable 22" "No effect,Reset"
|
|
bitfld.long 0x00 21. " [21] ,Global channel interrupt disable 21" "No effect,Reset"
|
|
bitfld.long 0x00 20. " [20] ,Global channel interrupt disable 20" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Global channel interrupt disable 19" "No effect,Reset"
|
|
bitfld.long 0x00 18. " [18] ,Global channel interrupt disable 18" "No effect,Reset"
|
|
bitfld.long 0x00 17. " [17] ,Global channel interrupt disable 17" "No effect,Reset"
|
|
bitfld.long 0x00 16. " [16] ,Global channel interrupt disable 16" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Global channel interrupt disable 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " [14] ,Global channel interrupt disable 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " [13] ,Global channel interrupt disable 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " [12] ,Global channel interrupt disable 12" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Global channel interrupt disable 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " [10] ,Global channel interrupt disable 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " [9] ,Global channel interrupt disable 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " [8] ,Global channel interrupt disable 8" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Global channel interrupt disable 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " [6] ,Global channel interrupt disable 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " [5] ,Global channel interrupt disable 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " [4] ,Global channel interrupt disable 4" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Global channel interrupt disable 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " [2] ,Global channel interrupt disable 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " [1] ,Global channel interrupt disable 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " [0] ,Global channel interrupt disable 0" "No effect,Reset"
|
|
else
|
|
eventfld.long 0x00 15. " GCHID[15] ,Global channel interrupt disable 15" "No effect,Reset"
|
|
eventfld.long 0x00 14. " [14] ,Global channel interrupt disable 14" "No effect,Reset"
|
|
eventfld.long 0x00 13. " [13] ,Global channel interrupt disable 13" "No effect,Reset"
|
|
eventfld.long 0x00 12. " [12] ,Global channel interrupt disable 12" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Global channel interrupt disable 11" "No effect,Reset"
|
|
eventfld.long 0x00 10. " [10] ,Global channel interrupt disable 10" "No effect,Reset"
|
|
eventfld.long 0x00 9. " [9] ,Global channel interrupt disable 9" "No effect,Reset"
|
|
eventfld.long 0x00 8. " [8] ,Global channel interrupt disable 8" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Global channel interrupt disable 7" "No effect,Reset"
|
|
eventfld.long 0x00 6. " [6] ,Global channel interrupt disable 6" "No effect,Reset"
|
|
eventfld.long 0x00 5. " [5] ,Global channel interrupt disable 5" "No effect,Reset"
|
|
eventfld.long 0x00 4. " [4] ,Global channel interrupt disable 4" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Global channel interrupt disable 3" "No effect,Reset"
|
|
eventfld.long 0x00 2. " [2] ,Global channel interrupt disable 2" "No effect,Reset"
|
|
eventfld.long 0x00 1. " [1] ,Global channel interrupt disable 1" "No effect,Reset"
|
|
eventfld.long 0x00 0. " [0] ,Global channel interrupt disable 0" "No effect,Reset"
|
|
endif
|
|
tree "DMA Request Assignment Registers"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DREQASI0,DMA Request Assignment Register 0"
|
|
bitfld.long 0x00 24.--29. " CH0 ASI ,Channel 0 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH1 ASI ,Channel 1 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH2 ASI ,Channel 2 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH3 ASI ,Channel 3 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DREQASI1,DMA Request Assignment Register 1"
|
|
bitfld.long 0x00 24.--29. " CH4 ASI ,Channel 4 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH5 ASI ,Channel 5 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH6 ASI ,Channel 6 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH7 ASI ,Channel 7 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "DREQASI2,DMA Request Assignment Register 2"
|
|
bitfld.long 0x00 24.--29. " CH8 ASI ,Channel 8 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH9 ASI ,Channel 9 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH10ASI ,Channel 10 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH11ASI ,Channel 11 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DREQASI3,DMA Request Assignment Register 3"
|
|
bitfld.long 0x00 24.--29. " CH12ASI ,Channel 12 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH13ASI ,Channel 13 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH14ASI ,Channel 14 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH15ASI ,Channel 15 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "DREQASI4,DMA Request Assignment Register 4"
|
|
bitfld.long 0x00 24.--29. " CH16ASI ,Channel 16 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH17ASI ,Channel 17 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH18ASI ,Channel 18 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH19ASI ,Channel 19 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "DREQASI5,DMA Request Assignment Register 5"
|
|
bitfld.long 0x00 24.--29. " CH20ASI ,Channel 20 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH21ASI ,Channel 21 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH22ASI ,Channel 22 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH23ASI ,Channel 23 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "DREQASI6,DMA Request Assignment Register 6"
|
|
bitfld.long 0x00 24.--29. " CH24ASI ,Channel 24 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH25ASI ,Channel 25 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH26ASI ,Channel 26 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH27ASI ,Channel 27 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DREQASI7,DMA Request Assignment Register 7"
|
|
bitfld.long 0x00 24.--29. " CH28ASI ,Channel 28 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH29ASI ,Channel 29 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH30ASI ,Channel 30 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH31ASI ,Channel 31 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DREQASI0,DMA Request Assignment Register 0"
|
|
bitfld.long 0x00 24.--29. " CH0ASI ,Channel CH0ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH1ASI ,Channel CH1ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH2ASI ,Channel CH2ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH3ASI ,Channel CH3ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DREQASI1,DMA Request Assignment Register 1"
|
|
bitfld.long 0x00 24.--29. " CH4ASI ,Channel CH4ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH5ASI ,Channel CH5ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH6ASI ,Channel CH6ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH7ASI ,Channel CH7ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "DREQASI2,DMA Request Assignment Register 2"
|
|
bitfld.long 0x00 24.--29. " CH8ASI ,Channel CH8ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH9ASI ,Channel CH9ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH10ASI ,Channel CH10ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH11ASI ,Channel CH11ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DREQASI3,DMA Request Assignment Register 3"
|
|
bitfld.long 0x00 24.--29. " CH12ASI ,Channel CH12ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH13ASI ,Channel CH13ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH14ASI ,Channel CH14ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH15ASI ,Channel CH15ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
endif
|
|
tree.end
|
|
width 6.
|
|
tree "Port Assignment Registers"
|
|
sif cpuis("AWR*")
|
|
group.long 0x94++0x0F
|
|
line.long 0x00 "PAR0,Port Assignment Register 0"
|
|
sif cpuis("AWR1642")||cpuis("AWR1642-CORE1")
|
|
bitfld.long 0x00 28.--30. " CH0PA ,Port channel 0 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 24.--26. " CH1PA ,Port channel 1 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 20.--22. " CH2PA ,Port channel 2 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CH3PA ,Port channel 3 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 12.--14. " CH4PA ,Port channel 4 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 8.--10. " CH5PA ,Port channel 5 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CH6PA ,Port channel 6 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 0.--2. " CH7PA ,Port channel 7 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
else
|
|
bitfld.long 0x00 28.--30. " CH0PA ,Port channel 0 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x00 24.--26. " CH1PA ,Port channel 1 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x00 20.--22. " CH2PA ,Port channel 2 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CH3PA ,Port channel 3 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x00 12.--14. " CH4PA ,Port channel 4 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x00 8.--10. " CH5PA ,Port channel 5 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CH6PA ,Port channel 6 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x00 0.--2. " CH7PA ,Port channel 7 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
endif
|
|
line.long 0x04 "PAR1,Port Assignment Register 1"
|
|
sif cpuis("AWR1642")||cpuis("AWR1642-CORE1")
|
|
bitfld.long 0x04 28.--30. " CH8PA ,Port channel 8 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 24.--26. " CH9PA ,Port channel 9 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 20.--22. " CH10PA ,Port channel 10 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " CH11PA ,Port channel 11 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 12.--14. " CH12PA ,Port channel 12 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 8.--10. " CH13PA ,Port channel 13 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x04 4.--6. " CH14PA ,Port channel 14 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 0.--2. " CH15PA ,Port channel 15 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
else
|
|
bitfld.long 0x04 28.--30. " CH8PA ,Port channel 8 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x04 24.--26. " CH9PA ,Port channel 9 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x04 20.--22. " CH10PA ,Port channel 10 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " CH11PA ,Port channel 11 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x04 12.--14. " CH12PA ,Port channel 12 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x04 8.--10. " CH13PA ,Port channel 13 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x04 4.--6. " CH14PA ,Port channel 14 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x04 0.--2. " CH15PA ,Port channel 15 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
endif
|
|
line.long 0x08 "PAR2,Port Assignment Register 2"
|
|
sif cpuis("AWR1642")||cpuis("AWR1642-CORE1")
|
|
bitfld.long 0x08 28.--30. " CH16PA ,Port channel 16 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x08 24.--26. " CH17PA ,Port channel 17 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x08 20.--22. " CH18PA ,Port channel 18 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x08 16.--18. " CH19PA ,Port channel 19 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x08 12.--14. " CH20PA ,Port channel 20 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x08 8.--10. " CH21PA ,Port channel 21 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x08 4.--6. " CH22PA ,Port channel 22 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x08 0.--2. " CH23PA ,Port channel 23 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
else
|
|
bitfld.long 0x08 28.--30. " CH16PA ,Port channel 16 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x08 24.--26. " CH17PA ,Port channel 17 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x08 20.--22. " CH18PA ,Port channel 18 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x08 16.--18. " CH19PA ,Port channel 19 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x08 12.--14. " CH20PA ,Port channel 20 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x08 8.--10. " CH21PA ,Port channel 21 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x08 4.--6. " CH22PA ,Port channel 22 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x08 0.--2. " CH23PA ,Port channel 23 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
endif
|
|
line.long 0x0C "PAR3,Port Assignment Register 3"
|
|
sif cpuis("AWR1642")||cpuis("AWR1642-CORE1")
|
|
bitfld.long 0x0C 28.--30. " CH24PA ,Port channel 24 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x0C 24.--26. " CH25PA ,Port channel 25 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x0C 20.--22. " CH26PA ,Port channel 26 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x0C 16.--18. " CH27PA ,Port channel 27 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x0C 12.--14. " CH28PA ,Port channel 28 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x0C 8.--10. " CH29PA ,Port channel 29 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x0C 4.--6. " CH30PA ,Port channel 30 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x0C 0.--2. " CH31PA ,Port channel 31 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
else
|
|
bitfld.long 0x0C 28.--30. " CH24PA ,Port channel 24 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x0C 24.--26. " CH25PA ,Port channel 25 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x0C 20.--22. " CH26PA ,Port channel 26 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x0C 16.--18. " CH27PA ,Port channel 27 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x0C 12.--14. " CH28PA ,Port channel 28 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x0C 8.--10. " CH29PA ,Port channel 29 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x0C 4.--6. " CH30PA ,Port channel 30 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x0C 0.--2. " CH31PA ,Port channel 31 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
endif
|
|
elif cpuis("TMS570LS21*")||cpuis("TMS570LS31*")
|
|
group.long 0x94++0x07
|
|
line.long 0x00 "PAR0,Port Assignment Register 0"
|
|
bitfld.long 0x00 28.--30. " CH0PA ,Port channel 0 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 24.--26. " CH1PA ,Port channel 1 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 20.--22. " CH2PA ,Port channel 2 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CH3PA ,Port channel 3 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 12.--14. " CH4PA ,Port channel 4 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 8.--10. " CH5PA ,Port channel 5 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CH6PA ,Port channel 6 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 0.--2. " CH7PA ,Port channel 7 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
line.long 0x04 "PAR1,Port Assignment Register 1"
|
|
bitfld.long 0x04 28.--30. " CH8PA ,Port channel 8 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 24.--26. " CH9PA ,Port channel 9 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 20.--22. " CH10PA ,Port channel 10 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " CH11PA ,Port channel 11 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 12.--14. " CH12PA ,Port channel 12 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 8.--10. " CH13PA ,Port channel 13 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x04 4.--6. " CH14PA ,Port channel 14 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 0.--2. " CH15PA ,Port channel 15 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
else
|
|
group.long 0x94++0x07
|
|
line.long 0x00 "PAR0,Port Assignment Register 0"
|
|
bitfld.long 0x00 28.--30. " CH0PA ,Port channel 0 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 24.--26. " CH1PA ,Port channel 1 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 20.--22. " CH2PA ,Port channel 2 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CH3PA ,Port channel 3 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 12.--14. " CH4PA ,Port channel 4 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 8.--10. " CH5PA ,Port channel 5 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CH6PA ,Port channel 6 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 0.--2. " CH7PA ,Port channel 7 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
line.long 0x04 "PAR1,Port Assignment Register 1"
|
|
bitfld.long 0x04 28.--30. " CH8PA ,Port channel 8 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 24.--26. " CH9PA ,Port channel 9 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 20.--22. " CH10PA ,Port channel 10 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " CH11PA ,Port channel 11 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 12.--14. " CH12PA ,Port channel 12 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 8.--10. " CH13PA ,Port channel 13 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x04 4.--6. " CH14PA ,Port channel 14 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 0.--2. " CH15PA ,Port channel 15 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
endif
|
|
tree.end
|
|
width 8.
|
|
tree "Interrupt Mapping Registers"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "FTCMAP,FTC Interrupt Mapping Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " FTCAB[31] ,Frame transfer complete interrupt of channel 31 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 30. " [30] ,Frame transfer complete interrupt of channel 30 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 29. " [29] ,Frame transfer complete interrupt of channel 29 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 28. " [28] ,Frame transfer complete interrupt of channel 28 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Frame transfer complete interrupt of channel 27 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 26. " [26] ,Frame transfer complete interrupt of channel 26 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 25. " [25] ,Frame transfer complete interrupt of channel 25 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 24. " [24] ,Frame transfer complete interrupt of channel 24 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Frame transfer complete interrupt of channel 23 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 22. " [22] ,Frame transfer complete interrupt of channel 22 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 21. " [21] ,Frame transfer complete interrupt of channel 21 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 20. " [20] ,Frame transfer complete interrupt of channel 20 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Frame transfer complete interrupt of channel 19 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 18. " [18] ,Frame transfer complete interrupt of channel 18 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 17. " [17] ,Frame transfer complete interrupt of channel 17 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 16. " [16] ,Frame transfer complete interrupt of channel 16 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Frame transfer complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Frame transfer complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Frame transfer complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Frame transfer complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " FTCAB[15] ,Frame transfer complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Frame transfer complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Frame transfer complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Frame transfer complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Frame transfer complete interrupt of channel 11 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 10. " [10] ,Frame transfer complete interrupt of channel 10 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 9. " [9] ,Frame transfer complete interrupt of channel 9 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 8. " [8] ,Frame transfer complete interrupt of channel 8 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Frame transfer complete interrupt of channel 7 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 6. " [6] ,Frame transfer complete interrupt of channel 6 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 5. " [5] ,Frame transfer complete interrupt of channel 5 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 4. " [4] ,Frame transfer complete interrupt of channel 4 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Frame transfer complete interrupt of channel 3 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 2. " [2] ,Frame transfer complete interrupt of channel 2 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 1. " [1] ,Frame transfer complete interrupt of channel 1 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 0. " [0] ,Frame transfer complete interrupt of channel 0 to group A/B" "Group A,Group B"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "LFSMAP,LFS Interrupt Mapping Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " LFSAB[31] ,Last frame started interrupt of channel 31 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 30. " [30] ,Last frame started interrupt of channel 30 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 29. " [29] ,Last frame started interrupt of channel 29 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 28. " [28] ,Last frame started interrupt of channel 28 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Last frame started interrupt of channel 27 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 26. " [26] ,Last frame started interrupt of channel 26 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 25. " [25] ,Last frame started interrupt of channel 25 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 24. " [24] ,Last frame started interrupt of channel 24 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Last frame started interrupt of channel 23 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 22. " [22] ,Last frame started interrupt of channel 22 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 21. " [21] ,Last frame started interrupt of channel 21 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 20. " [20] ,Last frame started interrupt of channel 20 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Last frame started interrupt of channel 19 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 18. " [18] ,Last frame started interrupt of channel 18 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 17. " [17] ,Last frame started interrupt of channel 17 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 16. " [16] ,Last frame started interrupt of channel 16 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Last frame started interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Last frame started interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Last frame started interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Last frame started interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " LFSAB[15] ,Last frame started interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Last frame started interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Last frame started interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Last frame started interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Last frame started interrupt of channel 11 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 10. " [10] ,Last frame started interrupt of channel 10 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 9. " [9] ,Last frame started interrupt of channel 9 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 8. " [8] ,Last frame started interrupt of channel 8 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Last frame started interrupt of channel 7 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 6. " [6] ,Last frame started interrupt of channel 6 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 5. " [5] ,Last frame started interrupt of channel 5 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 4. " [4] ,Last frame started interrupt of channel 4 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Last frame started interrupt of channel 3 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 2. " [2] ,Last frame started interrupt of channel 2 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 1. " [1] ,Last frame started interrupt of channel 1 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 0. " [0] ,Last frame started interrupt of channel 0 to group A/B" "Group A,Group B"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "HBCMAP,HBC Interrupt Mapping Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " HBCAB[31] ,Half block complete interrupt of channel 31 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 30. " [30] ,Half block complete interrupt of channel 30 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 29. " [29] ,Half block complete interrupt of channel 29 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 28. " [28] ,Half block complete interrupt of channel 28 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Half block complete interrupt of channel 27 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 26. " [26] ,Half block complete interrupt of channel 26 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 25. " [25] ,Half block complete interrupt of channel 25 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 24. " [24] ,Half block complete interrupt of channel 24 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Half block complete interrupt of channel 23 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 22. " [22] ,Half block complete interrupt of channel 22 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 21. " [21] ,Half block complete interrupt of channel 21 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 20. " [20] ,Half block complete interrupt of channel 20 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Half block complete interrupt of channel 19 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 18. " [18] ,Half block complete interrupt of channel 18 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 17. " [17] ,Half block complete interrupt of channel 17 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 16. " [16] ,Half block complete interrupt of channel 16 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Half block complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Half block complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Half block complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Half block complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " HBCAB[15] ,Half block complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Half block complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Half block complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Half block complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Half block complete interrupt of channel 11 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 10. " [10] ,Half block complete interrupt of channel 10 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 9. " [9] ,Half block complete interrupt of channel 9 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 8. " [8] ,Half block complete interrupt of channel 8 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Half block complete interrupt of channel 7 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 6. " [6] ,Half block complete interrupt of channel 6 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 5. " [5] ,Half block complete interrupt of channel 5 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 4. " [4] ,Half block complete interrupt of channel 4 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Half block complete interrupt of channel 3 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 2. " [2] ,Half block complete interrupt of channel 2 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 1. " [1] ,Half block complete interrupt of channel 1 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 0. " [0] ,Half block complete interrupt of channel 0 to group A/B" "Group A,Group B"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "BTCMAP,BTC Interrupt Mapping Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " BTCAB[31] ,Block transfer complete interrupt of channel 31 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 30. " [30] ,Block transfer complete interrupt of channel 30 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 29. " [29] ,Block transfer complete interrupt of channel 29 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 28. " [28] ,Block transfer complete interrupt of channel 28 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Block transfer complete interrupt of channel 27 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 26. " [26] ,Block transfer complete interrupt of channel 26 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 25. " [25] ,Block transfer complete interrupt of channel 25 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 24. " [24] ,Block transfer complete interrupt of channel 24 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Block transfer complete interrupt of channel 23 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 22. " [22] ,Block transfer complete interrupt of channel 22 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 21. " [21] ,Block transfer complete interrupt of channel 21 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 20. " [20] ,Block transfer complete interrupt of channel 20 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Block transfer complete interrupt of channel 19 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 18. " [18] ,Block transfer complete interrupt of channel 18 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 17. " [17] ,Block transfer complete interrupt of channel 17 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 16. " [16] ,Block transfer complete interrupt of channel 16 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Block transfer complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Block transfer complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Block transfer complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Block transfer complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " BTCAB[15] ,Block transfer complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Block transfer complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Block transfer complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Block transfer complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Block transfer complete interrupt of channel 11 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 10. " [10] ,Block transfer complete interrupt of channel 10 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 9. " [9] ,Block transfer complete interrupt of channel 9 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 8. " [8] ,Block transfer complete interrupt of channel 8 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Block transfer complete interrupt of channel 7 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 6. " [6] ,Block transfer complete interrupt of channel 6 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 5. " [5] ,Block transfer complete interrupt of channel 5 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 4. " [4] ,Block transfer complete interrupt of channel 4 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Block transfer complete interrupt of channel 3 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 2. " [2] ,Block transfer complete interrupt of channel 2 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 1. " [1] ,Block transfer complete interrupt of channel 1 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 0. " [0] ,Block transfer complete interrupt of channel 0 to group A/B" "Group A,Group B"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "BERMAP,BER Interrupt Mapping Register"
|
|
bitfld.long 0x00 31. " BERAB[31] ,Bus error interrupt of channel 31 to group A/B" "A,B"
|
|
bitfld.long 0x00 30. " [30] ,Bus error interrupt of channel 30 to group A/B" "A,B"
|
|
bitfld.long 0x00 29. " [29] ,Bus error interrupt of channel 29 to group A/B" "A,B"
|
|
bitfld.long 0x00 28. " [28] ,Bus error interrupt of channel 28 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Bus error interrupt of channel 27 to group A/B" "A,B"
|
|
bitfld.long 0x00 26. " [26] ,Bus error interrupt of channel 26 to group A/B" "A,B"
|
|
bitfld.long 0x00 25. " [25] ,Bus error interrupt of channel 25 to group A/B" "A,B"
|
|
bitfld.long 0x00 24. " [24] ,Bus error interrupt of channel 24 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Bus error interrupt of channel 23 to group A/B" "A,B"
|
|
bitfld.long 0x00 22. " [22] ,Bus error interrupt of channel 22 to group A/B" "A,B"
|
|
bitfld.long 0x00 21. " [21] ,Bus error interrupt of channel 21 to group A/B" "A,B"
|
|
bitfld.long 0x00 20. " [20] ,Bus error interrupt of channel 20 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Bus error interrupt of channel 19 to group A/B" "A,B"
|
|
bitfld.long 0x00 18. " [18] ,Bus error interrupt of channel 18 to group A/B" "A,B"
|
|
bitfld.long 0x00 17. " [17] ,Bus error interrupt of channel 17 to group A/B" "A,B"
|
|
bitfld.long 0x00 16. " [16] ,Bus error interrupt of channel 16 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Bus error interrupt of channel 15 to group A/B" "A,B"
|
|
bitfld.long 0x00 14. " [14] ,Bus error interrupt of channel 14 to group A/B" "A,B"
|
|
bitfld.long 0x00 13. " [13] ,Bus error interrupt of channel 13 to group A/B" "A,B"
|
|
bitfld.long 0x00 12. " [12] ,Bus error interrupt of channel 12 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Bus error interrupt of channel 11 to group A/B" "A,B"
|
|
bitfld.long 0x00 10. " [10] ,Bus error interrupt of channel 10 to group A/B" "A,B"
|
|
bitfld.long 0x00 9. " [9] ,Bus error interrupt of channel 9 to group A/B" "A,B"
|
|
bitfld.long 0x00 8. " [8] ,Bus error interrupt of channel 8 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Bus error interrupt of channel 7 to group A/B" "A,B"
|
|
bitfld.long 0x00 6. " [6] ,Bus error interrupt of channel 6 to group A/B" "A,B"
|
|
bitfld.long 0x00 5. " [5] ,Bus error interrupt of channel 5 to group A/B" "A,B"
|
|
bitfld.long 0x00 4. " [4] ,Bus error interrupt of channel 4 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Bus error interrupt of channel 3 to group A/B" "A,B"
|
|
bitfld.long 0x00 2. " [2] ,Bus error interrupt of channel 2 to group A/B" "A,B"
|
|
bitfld.long 0x00 1. " [1] ,Bus error interrupt of channel 1 to group A/B" "A,B"
|
|
bitfld.long 0x00 0. " [0] ,Bus error interrupt of channel 0 to group A/B" "A,B"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "FTCINTENAS,FTC Interrupt Enable Set Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " FTCINTENA[31] ,FTC (frame transfer complete) interrupt enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,FTC (frame transfer complete) interrupt enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,FTC (frame transfer complete) interrupt enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,FTC (frame transfer complete) interrupt enable 28" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,FTC (frame transfer complete) interrupt enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,FTC (frame transfer complete) interrupt enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,FTC (frame transfer complete) interrupt enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,FTC (frame transfer complete) interrupt enable 24" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,FTC (frame transfer complete) interrupt enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,FTC (frame transfer complete) interrupt enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,FTC (frame transfer complete) interrupt enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,FTC (frame transfer complete) interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,FTC (frame transfer complete) interrupt enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,FTC (frame transfer complete) interrupt enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,FTC (frame transfer complete) interrupt enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,FTC (frame transfer complete) interrupt enable 16" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,FTC (frame transfer complete) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,FTC (frame transfer complete) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,FTC (frame transfer complete) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,FTC (frame transfer complete) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " FTCINTENA[15] ,FTC (frame transfer complete) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,FTC (frame transfer complete) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,FTC (frame transfer complete) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,FTC (frame transfer complete) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,FTC (frame transfer complete) interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,FTC (frame transfer complete) interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,FTC (frame transfer complete) interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,FTC (frame transfer complete) interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,FTC (frame transfer complete) interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,FTC (frame transfer complete) interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,FTC (frame transfer complete) interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,FTC (frame transfer complete) interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,FTC (frame transfer complete) interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,FTC (frame transfer complete) interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,FTC (frame transfer complete) interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,FTC (frame transfer complete) interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "FTCINTENAR,FTC Interrupt Enable Reset Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " FTCINTDIS[31] ,FTC (frame transfer complete) interrupt disable 31" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,FTC (frame transfer complete) interrupt disable 30" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,FTC (frame transfer complete) interrupt disable 29" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,FTC (frame transfer complete) interrupt disable 28" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,FTC (frame transfer complete) interrupt disable 27" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,FTC (frame transfer complete) interrupt disable 26" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,FTC (frame transfer complete) interrupt disable 25" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,FTC (frame transfer complete) interrupt disable 24" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,FTC (frame transfer complete) interrupt disable 23" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,FTC (frame transfer complete) interrupt disable 22" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,FTC (frame transfer complete) interrupt disable 21" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,FTC (frame transfer complete) interrupt disable 20" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,FTC (frame transfer complete) interrupt disable 19" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,FTC (frame transfer complete) interrupt disable 18" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,FTC (frame transfer complete) interrupt disable 17" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,FTC (frame transfer complete) interrupt disable 16" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,FTC (frame transfer complete) interrupt disable 15" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,FTC (frame transfer complete) interrupt disable 14" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,FTC (frame transfer complete) interrupt disable 13" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,FTC (frame transfer complete) interrupt disable 12" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,FTC (frame transfer complete) interrupt disable 11" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,FTC (frame transfer complete) interrupt disable 10" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,FTC (frame transfer complete) interrupt disable 9" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,FTC (frame transfer complete) interrupt disable 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,FTC (frame transfer complete) interrupt disable 7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,FTC (frame transfer complete) interrupt disable 6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,FTC (frame transfer complete) interrupt disable 5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,FTC (frame transfer complete) interrupt disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,FTC (frame transfer complete) interrupt disable 3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,FTC (frame transfer complete) interrupt disable 2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,FTC (frame transfer complete) interrupt disable 1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,FTC (frame transfer complete) interrupt disable 0" "No,Yes"
|
|
else
|
|
eventfld.long 0x00 15. " FTCINTDIS[15] ,FTC (frame transfer complete) interrupt disable 15" "No,Yes"
|
|
eventfld.long 0x00 14. " [14] ,FTC (frame transfer complete) interrupt disable 14" "No,Yes"
|
|
eventfld.long 0x00 13. " [13] ,FTC (frame transfer complete) interrupt disable 13" "No,Yes"
|
|
eventfld.long 0x00 12. " [12] ,FTC (frame transfer complete) interrupt disable 12" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,FTC (frame transfer complete) interrupt disable 11" "No,Yes"
|
|
eventfld.long 0x00 10. " [10] ,FTC (frame transfer complete) interrupt disable 10" "No,Yes"
|
|
eventfld.long 0x00 9. " [9] ,FTC (frame transfer complete) interrupt disable 9" "No,Yes"
|
|
eventfld.long 0x00 8. " [8] ,FTC (frame transfer complete) interrupt disable 8" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,FTC (frame transfer complete) interrupt disable 7" "No,Yes"
|
|
eventfld.long 0x00 6. " [6] ,FTC (frame transfer complete) interrupt disable 6" "No,Yes"
|
|
eventfld.long 0x00 5. " [5] ,FTC (frame transfer complete) interrupt disable 5" "No,Yes"
|
|
eventfld.long 0x00 4. " [4] ,FTC (frame transfer complete) interrupt disable 4" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,FTC (frame transfer complete) interrupt disable 3" "No,Yes"
|
|
eventfld.long 0x00 2. " [2] ,FTC (frame transfer complete) interrupt disable 2" "No,Yes"
|
|
eventfld.long 0x00 1. " [1] ,FTC (frame transfer complete) interrupt disable 1" "No,Yes"
|
|
eventfld.long 0x00 0. " [0] ,FTC (frame transfer complete) interrupt disable 0" "No,Yes"
|
|
endif
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "LFSINTENAS,LFS Interrupt Enable Set Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " LFSINTENA[31] ,LFS (last frame started) interrupt enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,LFS (last frame started) interrupt enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,LFS (last frame started) interrupt enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,LFS (last frame started) interrupt enable 28" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,LFS (last frame started) interrupt enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,LFS (last frame started) interrupt enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,LFS (last frame started) interrupt enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,LFS (last frame started) interrupt enable 24" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,LFS (last frame started) interrupt enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,LFS (last frame started) interrupt enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,LFS (last frame started) interrupt enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,LFS (last frame started) interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,LFS (last frame started) interrupt enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,LFS (last frame started) interrupt enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,LFS (last frame started) interrupt enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,LFS (last frame started) interrupt enable 16" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,LFS (last frame started) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,LFS (last frame started) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,LFS (last frame started) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,LFS (last frame started) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " LFSINTENA[15] ,LFS (last frame started) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,LFS (last frame started) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,LFS (last frame started) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,LFS (last frame started) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,LFS (last frame started) interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,LFS (last frame started) interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,LFS (last frame started) interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,LFS (last frame started) interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,LFS (last frame started) interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,LFS (last frame started) interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,LFS (last frame started) interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,LFS (last frame started) interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,LFS (last frame started) interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,LFS (last frame started) interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,LFS (last frame started) interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,LFS (last frame started) interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "LFSINTENAR,LFS Interrupt Enable Reset Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " LFSINTDIS[31] ,LFS (last frame started) interrupt disable 31" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,LFS (last frame started) interrupt disable 30" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,LFS (last frame started) interrupt disable 29" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,LFS (last frame started) interrupt disable 28" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,LFS (last frame started) interrupt disable 27" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,LFS (last frame started) interrupt disable 26" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,LFS (last frame started) interrupt disable 25" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,LFS (last frame started) interrupt disable 24" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,LFS (last frame started) interrupt disable 23" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,LFS (last frame started) interrupt disable 22" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,LFS (last frame started) interrupt disable 21" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,LFS (last frame started) interrupt disable 20" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,LFS (last frame started) interrupt disable 19" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,LFS (last frame started) interrupt disable 18" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,LFS (last frame started) interrupt disable 17" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,LFS (last frame started) interrupt disable 16" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,LFS (last frame started) interrupt disable 15" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,LFS (last frame started) interrupt disable 14" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,LFS (last frame started) interrupt disable 13" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,LFS (last frame started) interrupt disable 12" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,LFS (last frame started) interrupt disable 11" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,LFS (last frame started) interrupt disable 10" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,LFS (last frame started) interrupt disable 9" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,LFS (last frame started) interrupt disable 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,LFS (last frame started) interrupt disable 7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,LFS (last frame started) interrupt disable 6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,LFS (last frame started) interrupt disable 5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,LFS (last frame started) interrupt disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,LFS (last frame started) interrupt disable 3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,LFS (last frame started) interrupt disable 2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,LFS (last frame started) interrupt disable 1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,LFS (last frame started) interrupt disable 0" "No,Yes"
|
|
else
|
|
eventfld.long 0x00 15. " LFSINTDIS[15] ,LFS (last frame started) interrupt disable 15" "No,Yes"
|
|
eventfld.long 0x00 14. " [14] ,LFS (last frame started) interrupt disable 14" "No,Yes"
|
|
eventfld.long 0x00 13. " [13] ,LFS (last frame started) interrupt disable 13" "No,Yes"
|
|
eventfld.long 0x00 12. " [12] ,LFS (last frame started) interrupt disable 12" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,LFS (last frame started) interrupt disable 11" "No,Yes"
|
|
eventfld.long 0x00 10. " [10] ,LFS (last frame started) interrupt disable 10" "No,Yes"
|
|
eventfld.long 0x00 9. " [9] ,LFS (last frame started) interrupt disable 9" "No,Yes"
|
|
eventfld.long 0x00 8. " [8] ,LFS (last frame started) interrupt disable 8" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,LFS (last frame started) interrupt disable 7" "No,Yes"
|
|
eventfld.long 0x00 6. " [6] ,LFS (last frame started) interrupt disable 6" "No,Yes"
|
|
eventfld.long 0x00 5. " [5] ,LFS (last frame started) interrupt disable 5" "No,Yes"
|
|
eventfld.long 0x00 4. " [4] ,LFS (last frame started) interrupt disable 4" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,LFS (last frame started) interrupt disable 3" "No,Yes"
|
|
eventfld.long 0x00 2. " [2] ,LFS (last frame started) interrupt disable 2" "No,Yes"
|
|
eventfld.long 0x00 1. " [1] ,LFS (last frame started) interrupt disable 1" "No,Yes"
|
|
eventfld.long 0x00 0. " [0] ,LFS (last frame started) interrupt disable 0" "No,Yes"
|
|
endif
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "HBCINTENAS,HBC Interrupt Enable Set Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " HBCINTENA[31] ,HBC (half block complete) interrupt enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,HBC (half block complete) interrupt enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,HBC (half block complete) interrupt enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,HBC (half block complete) interrupt enable 28" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,HBC (half block complete) interrupt enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,HBC (half block complete) interrupt enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,HBC (half block complete) interrupt enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,HBC (half block complete) interrupt enable 24" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,HBC (half block complete) interrupt enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,HBC (half block complete) interrupt enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,HBC (half block complete) interrupt enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,HBC (half block complete) interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,HBC (half block complete) interrupt enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,HBC (half block complete) interrupt enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,HBC (half block complete) interrupt enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,HBC (half block complete) interrupt enable 16" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,HBC (half block complete) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,HBC (half block complete) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,HBC (half block complete) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,HBC (half block complete) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " HBCINTENA[15] ,HBC (half block complete) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,HBC (half block complete) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,HBC (half block complete) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,HBC (half block complete) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,HBC (half block complete) interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,HBC (half block complete) interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,HBC (half block complete) interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,HBC (half block complete) interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,HBC (half block complete) interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,HBC (half block complete) interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,HBC (half block complete) interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,HBC (half block complete) interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,HBC (half block complete) interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,HBC (half block complete) interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,HBC (half block complete) interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,HBC (half block complete) interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "HBCINTENAR,HBC Interrupt Enable Reset Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " HBCINTENA[31] ,HBC (half block complete) interrupt disable 31" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,HBC (half block complete) interrupt disable 30" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,HBC (half block complete) interrupt disable 29" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,HBC (half block complete) interrupt disable 28" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,HBC (half block complete) interrupt disable 27" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,HBC (half block complete) interrupt disable 26" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,HBC (half block complete) interrupt disable 25" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,HBC (half block complete) interrupt disable 24" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,HBC (half block complete) interrupt disable 23" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,HBC (half block complete) interrupt disable 22" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,HBC (half block complete) interrupt disable 21" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,HBC (half block complete) interrupt disable 20" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,HBC (half block complete) interrupt disable 19" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,HBC (half block complete) interrupt disable 18" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,HBC (half block complete) interrupt disable 17" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,HBC (half block complete) interrupt disable 16" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,HBC (half block complete) interrupt disable 15" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,HBC (half block complete) interrupt disable 14" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,HBC (half block complete) interrupt disable 13" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,HBC (half block complete) interrupt disable 12" "No,Yes"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " HBCINTENA[15] ,HBC (half block complete) interrupt disable 15" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,HBC (half block complete) interrupt disable 14" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,HBC (half block complete) interrupt disable 13" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,HBC (half block complete) interrupt disable 12" "No,Yes"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,HBC (half block complete) interrupt disable 11" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,HBC (half block complete) interrupt disable 10" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,HBC (half block complete) interrupt disable 9" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,HBC (half block complete) interrupt disable 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,HBC (half block complete) interrupt disable 7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,HBC (half block complete) interrupt disable 6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,HBC (half block complete) interrupt disable 5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,HBC (half block complete) interrupt disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,HBC (half block complete) interrupt disable 3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,HBC (half block complete) interrupt disable 2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,HBC (half block complete) interrupt disable 1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,HBC (half block complete) interrupt disable 0" "No,Yes"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "BTCINTENAS,BTC Interrupt Enable Set Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " BTCINTENA[31] ,BTC (block transfer complete) interrupt enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,BTC (block transfer complete) interrupt enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,BTC (block transfer complete) interrupt enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,BTC (block transfer complete) interrupt enable 28" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,BTC (block transfer complete) interrupt enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,BTC (block transfer complete) interrupt enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,BTC (block transfer complete) interrupt enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,BTC (block transfer complete) interrupt enable 24" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,BTC (block transfer complete) interrupt enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,BTC (block transfer complete) interrupt enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,BTC (block transfer complete) interrupt enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,BTC (block transfer complete) interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,BTC (block transfer complete) interrupt enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,BTC (block transfer complete) interrupt enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,BTC (block transfer complete) interrupt enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,BTC (block transfer complete) interrupt enable 16" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,BTC (block transfer complete) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,BTC (block transfer complete) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,BTC (block transfer complete) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,BTC (block transfer complete) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " BTCINTENA[15] ,BTC (block transfer complete) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,BTC (block transfer complete) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,BTC (block transfer complete) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,BTC (block transfer complete) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,BTC (block transfer complete) interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,BTC (block transfer complete) interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,BTC (block transfer complete) interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,BTC (block transfer complete) interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,BTC (block transfer complete) interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,BTC (block transfer complete) interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,BTC (block transfer complete) interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,BTC (block transfer complete) interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,BTC (block transfer complete) interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,BTC (block transfer complete) interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,BTC (block transfer complete) interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,BTC (block transfer complete) interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "BTCINTENAR,BTC Interrupt Enable Reset Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " BTCINTENA[31] ,BTC (block transfer complete) interrupt disable 31" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,BTC (block transfer complete) interrupt disable 30" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,BTC (block transfer complete) interrupt disable 29" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,BTC (block transfer complete) interrupt disable 28" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,BTC (block transfer complete) interrupt disable 27" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,BTC (block transfer complete) interrupt disable 26" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,BTC (block transfer complete) interrupt disable 25" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,BTC (block transfer complete) interrupt disable 24" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,BTC (block transfer complete) interrupt disable 23" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,BTC (block transfer complete) interrupt disable 22" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,BTC (block transfer complete) interrupt disable 21" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,BTC (block transfer complete) interrupt disable 20" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,BTC (block transfer complete) interrupt disable 19" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,BTC (block transfer complete) interrupt disable 18" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,BTC (block transfer complete) interrupt disable 17" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,BTC (block transfer complete) interrupt disable 16" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,BTC (block transfer complete) interrupt disable 15" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,BTC (block transfer complete) interrupt disable 14" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,BTC (block transfer complete) interrupt disable 13" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,BTC (block transfer complete) interrupt disable 12" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,BTC (block transfer complete) interrupt disable 11" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,BTC (block transfer complete) interrupt disable 10" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,BTC (block transfer complete) interrupt disable 9" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,BTC (block transfer complete) interrupt disable 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,BTC (block transfer complete) interrupt disable 7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,BTC (block transfer complete) interrupt disable 6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,BTC (block transfer complete) interrupt disable 5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,BTC (block transfer complete) interrupt disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,BTC (block transfer complete) interrupt disable 3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,BTC (block transfer complete) interrupt disable 2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,BTC (block transfer complete) interrupt disable 1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,BTC (block transfer complete) interrupt disable 0" "No,Yes"
|
|
else
|
|
eventfld.long 0x00 15. " BTCINTENA[15] ,BTC (block transfer complete) interrupt disable 15" "No,Yes"
|
|
eventfld.long 0x00 14. " [14] ,BTC (block transfer complete) interrupt disable 14" "No,Yes"
|
|
eventfld.long 0x00 13. " [13] ,BTC (block transfer complete) interrupt disable 13" "No,Yes"
|
|
eventfld.long 0x00 12. " [12] ,BTC (block transfer complete) interrupt disable 12" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,BTC (block transfer complete) interrupt disable 11" "No,Yes"
|
|
eventfld.long 0x00 10. " [10] ,BTC (block transfer complete) interrupt disable 10" "No,Yes"
|
|
eventfld.long 0x00 9. " [9] ,BTC (block transfer complete) interrupt disable 9" "No,Yes"
|
|
eventfld.long 0x00 8. " [8] ,BTC (block transfer complete) interrupt disable 8" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,BTC (block transfer complete) interrupt disable 7" "No,Yes"
|
|
eventfld.long 0x00 6. " [6] ,BTC (block transfer complete) interrupt disable 6" "No,Yes"
|
|
eventfld.long 0x00 5. " [5] ,BTC (block transfer complete) interrupt disable 5" "No,Yes"
|
|
eventfld.long 0x00 4. " [4] ,BTC (block transfer complete) interrupt disable 4" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,BTC (block transfer complete) interrupt disable 3" "No,Yes"
|
|
eventfld.long 0x00 2. " [2] ,BTC (block transfer complete) interrupt disable 2" "No,Yes"
|
|
eventfld.long 0x00 1. " [1] ,BTC (block transfer complete) interrupt disable 1" "No,Yes"
|
|
eventfld.long 0x00 0. " [0] ,BTC (block transfer complete) interrupt disable 0" "No,Yes"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Flag Registers"
|
|
width 10.
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "GINTFLAG,Global Interrupt Flag Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " GINT[31] ,Global interrupt flag for channel 31" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " [30] ,Global interrupt flag for channel 30" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " [29] ,Global interrupt flag for channel 29" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " [28] ,Global interrupt flag for channel 28" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Global interrupt flag for channel 27" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " [26] ,Global interrupt flag for channel 26" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " [25] ,Global interrupt flag for channel 25" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " [24] ,Global interrupt flag for channel 24" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Global interrupt flag for channel 23" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " [22] ,Global interrupt flag for channel 22" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " [21] ,Global interrupt flag for channel 21" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " [20] ,Global interrupt flag for channel 20" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Global interrupt flag for channel 19" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " [18] ,Global interrupt flag for channel 18" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " [17] ,Global interrupt flag for channel 17" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " [16] ,Global interrupt flag for channel 16" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Global interrupt flag for channel 15" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Global interrupt flag for channel 14" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Global interrupt flag for channel 13" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Global interrupt flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " GINT[15] ,Global interrupt flag for channel 15" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Global interrupt flag for channel 14" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Global interrupt flag for channel 13" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Global interrupt flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Global interrupt flag for channel 11" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Global interrupt flag for channel 10" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Global interrupt flag for channel 9" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " [8] ,Global interrupt flag for channel 8" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Global interrupt flag for channel 7" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " [6] ,Global interrupt flag for channel 6" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " [5] ,Global interrupt flag for channel 5" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Global interrupt flag for channel 4" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Global interrupt flag for channel 3" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " [2] ,Global interrupt flag for channel 2" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " [1] ,Global interrupt flag for channel 1" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Global interrupt flag for channel 0" "Not pending,Pending"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "FTCFLAG,FTC Interrupt Flag Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
eventfld.long 0x00 31. " FTCI[31] ,Frame transfer complete flag for channel 31" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " [30] ,Frame transfer complete flag for channel 30" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " [29] ,Frame transfer complete flag for channel 29" "Not pending,Pending"
|
|
eventfld.long 0x00 28. " [28] ,Frame transfer complete flag for channel 28" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Frame transfer complete flag for channel 27" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " [26] ,Frame transfer complete flag for channel 26" "Not pending,Pending"
|
|
eventfld.long 0x00 25. " [25] ,Frame transfer complete flag for channel 25" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " [24] ,Frame transfer complete flag for channel 24" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Frame transfer complete flag for channel 23" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " [22] ,Frame transfer complete flag for channel 22" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " [21] ,Frame transfer complete flag for channel 21" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " [20] ,Frame transfer complete flag for channel 20" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Frame transfer complete flag for channel 19" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " [18] ,Frame transfer complete flag for channel 18" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " [17] ,Frame transfer complete flag for channel 17" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " [16] ,Frame transfer complete flag for channel 16" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Frame transfer complete flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Frame transfer complete flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Frame transfer complete flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Frame transfer complete flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
else
|
|
eventfld.long 0x00 15. " FTCI[15] ,Frame transfer complete flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Frame transfer complete flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Frame transfer complete flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Frame transfer complete flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 11. " [11] ,Frame transfer complete flag for channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " [10] ,Frame transfer complete flag for channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " [9] ,Frame transfer complete flag for channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " [8] ,Frame transfer complete flag for channel 8" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Frame transfer complete flag for channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Frame transfer complete flag for channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Frame transfer complete flag for channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " [4] ,Frame transfer complete flag for channel 4" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Frame transfer complete flag for channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Frame transfer complete flag for channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " [1] ,Frame transfer complete flag for channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Frame transfer complete flag for channel 0" "Not pending,Pending"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "LFSFLAG,LFS Interrupt Flag Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
eventfld.long 0x00 31. " LFSI[31] ,Last frame transfer started flag for channel 31" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " [30] ,Last frame transfer started flag for channel 30" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " [29] ,Last frame transfer started flag for channel 29" "Not pending,Pending"
|
|
eventfld.long 0x00 28. " [28] ,Last frame transfer started flag for channel 28" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Last frame transfer started flag for channel 27" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " [26] ,Last frame transfer started flag for channel 26" "Not pending,Pending"
|
|
eventfld.long 0x00 25. " [25] ,Last frame transfer started flag for channel 25" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " [24] ,Last frame transfer started flag for channel 24" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Last frame transfer started flag for channel 23" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " [22] ,Last frame transfer started flag for channel 22" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " [21] ,Last frame transfer started flag for channel 21" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " [20] ,Last frame transfer started flag for channel 20" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Last frame transfer started flag for channel 19" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " [18] ,Last frame transfer started flag for channel 18" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " [17] ,Last frame transfer started flag for channel 17" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " [16] ,Last frame transfer started flag for channel 16" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Last frame transfer started flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Last frame transfer started flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Last frame transfer started flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Last frame transfer started flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
else
|
|
eventfld.long 0x00 15. " LFSI[15] ,Last frame transfer started flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Last frame transfer started flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Last frame transfer started flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Last frame transfer started flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 11. " [11] ,Last frame transfer started flag for channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " [10] ,Last frame transfer started flag for channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " [9] ,Last frame transfer started flag for channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " [8] ,Last frame transfer started flag for channel 8" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Last frame transfer started flag for channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Last frame transfer started flag for channel for channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Last frame transfer started flag for channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " [4] ,Last frame transfer started flag for channel 4" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Last frame transfer started flag for channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Last frame transfer started flag for channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " [1] ,Last frame transfer started flag for channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Last frame transfer started flag for channel 0" "Not pending,Pending"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "HBCFLAG,HBC Interrupt Flag Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
eventfld.long 0x00 31. " HBCI[31] ,Half of block transfer complete flag for channel 31" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " [30] ,Half of block transfer complete flag for channel 30" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " [29] ,Half of block transfer complete flag for channel 29" "Not pending,Pending"
|
|
eventfld.long 0x00 28. " [28] ,Half of block transfer complete flag for channel 28" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Half of block transfer complete flag for channel 27" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " [26] ,Half of block transfer complete flag for channel 26" "Not pending,Pending"
|
|
eventfld.long 0x00 25. " [25] ,Half of block transfer complete flag for channel 25" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " [24] ,Half of block transfer complete flag for channel 24" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Half of block transfer complete flag for channel 23" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " [22] ,Half of block transfer complete flag for channel 22" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " [21] ,Half of block transfer complete flag for channel 21" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " [20] ,Half of block transfer complete flag for channel 20" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Half of block transfer complete flag for channel 19" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " [18] ,Half of block transfer complete flag for channel 18" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " [17] ,Half of block transfer complete flag for channel 17" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " [16] ,Half of block transfer complete flag for channel 16" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Half of block transfer complete flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Half of block transfer complete flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Half of block transfer complete flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Half of block transfer complete flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
else
|
|
eventfld.long 0x00 15. " HBCI[15] ,Half of block transfer complete flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Half of block transfer complete flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Half of block transfer complete flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Half of block transfer complete flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 11. " [11] ,Half of block transfer complete flag for channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " [10] ,Half of block transfer complete flag for channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " [9] ,Half of block transfer complete flag for channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " [8] ,Half of block transfer complete flag for channel 8" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Half of block transfer complete flag for channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Half of block transfer complete flag for channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Half of block transfer complete flag for channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " [4] ,Half of block transfer complete flag for channel 4" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Half of block transfer complete flag for channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Half of block transfer complete flag for channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " [1] ,Half of block transfer complete flag for channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Half of block transfer complete flag for channel 0" "Not pending,Pending"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "BTCFLAG,BER Interrupt Flag Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
eventfld.long 0x00 31. " BTCI[31] ,Block transfer complete flag for channel 31" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " [30] ,Block transfer complete flag for channel 30" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " [29] ,Block transfer complete flag for channel 29" "Not pending,Pending"
|
|
eventfld.long 0x00 28. " [28] ,Block transfer complete flag for channel 28" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Block transfer complete flag for channel 27" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " [26] ,Block transfer complete flag for channel 26" "Not pending,Pending"
|
|
eventfld.long 0x00 25. " [25] ,Block transfer complete flag for channel 25" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " [24] ,Block transfer complete flag for channel 24" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Block transfer complete flag for channel 23" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " [22] ,Block transfer complete flag for channel 22" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " [21] ,Block transfer complete flag for channel 21" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " [20] ,Block transfer complete flag for channel 20" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Block transfer complete flag for channel 19" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " [18] ,Block transfer complete flag for channel 18" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " [17] ,Block transfer complete flag for channel 17" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " [16] ,Block transfer complete flag for channel 16" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Block transfer complete flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Block transfer complete flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Block transfer complete flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Block transfer complete flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
else
|
|
eventfld.long 0x00 15. " BTCI[15] ,Block transfer complete flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Block transfer complete flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Block transfer complete flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Block transfer complete flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 11. " [11] ,Block transfer complete flag for channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " [10] ,Block transfer complete flag for channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " [9] ,Block transfer complete flag for channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " [8] ,Block transfer complete flag for channel 8" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Block transfer complete flag for channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Block transfer complete flag for channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Block transfer complete flag for channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " [4] ,Block transfer complete flag for channel 4" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Block transfer complete flag for channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Block transfer complete flag for channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " [1] ,Block transfer complete flag for channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Block transfer complete flag for channel 0" "Not pending,Pending"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "BERFLAG,BER Interrupt Flag Register"
|
|
eventfld.long 0x00 31. " BERI[31] ,Bus error flag for channel 31" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " [30] ,Bus error flag for channel 30" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " [29] ,Bus error flag for channel 29" "Not pending,Pending"
|
|
eventfld.long 0x00 28. " [28] ,Bus error flag for channel 28" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Bus error flag for channel 27" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " [26] ,Bus error flag for channel 26" "Not pending,Pending"
|
|
eventfld.long 0x00 25. " [25] ,Bus error flag for channel 25" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " [24] ,Bus error flag for channel 24" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Bus error flag for channel 23" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " [22] ,Bus error flag for channel 22" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " [21] ,Bus error flag for channel 21" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " [20] ,Bus error flag for channel 20" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Bus error flag for channel 19" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " [18] ,Bus error flag for channel 18" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " [17] ,Bus error flag for channel 17" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " [16] ,Bus error flag for channel 16" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Bus error flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Bus error flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Bus error flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Bus error flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Bus error flag for channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " [10] ,Bus error flag for channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " [9] ,Bus error flag for channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " [8] ,Bus error flag for channel 8" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Bus error flag for channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Bus error flag for channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Bus error flag for channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " [4] ,Bus error flag for channel 4" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Bus error flag for channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Bus error flag for channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " [1] ,Bus error flag for channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Bus error flag for channel 0" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "BERFLAG,BER Interrupt Flag Register"
|
|
endif
|
|
tree.end
|
|
newline
|
|
width 12.
|
|
tree "Interrupt Channel Offset Registers"
|
|
hgroup.long 0x14C++0x03
|
|
hide.long 0x00 "FTCAOFFSET,FTCA Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x150++0x03
|
|
hide.long 0x00 "LFSAOFFSET,LFSA Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x154++0x03
|
|
hide.long 0x00 "HBCAOFFSET,HBCA Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x158++0x03
|
|
hide.long 0x00 "BTCAOFFSET,BTCA Interrupt Channel Offset Register"
|
|
in
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
hgroup.long 0x15C++0x03
|
|
hide.long 0x00 "BERAOFFSET,BERA Interrupt Channel Offset Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "FTCBOFFSET,FTCB Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x164++0x03
|
|
hide.long 0x00 "LFSBOFFSET,LFSB Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x168++0x03
|
|
hide.long 0x00 "HBCBOFFSET,HBCB Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x16C++0x03
|
|
hide.long 0x00 "BTCBOFFSET,BTCB Interrupt Channel Offset Register"
|
|
in
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
hgroup.long 0x170++0x03
|
|
hide.long 0x00 "BERBOFFSET,BERB Interrupt Channel Offset Register"
|
|
in
|
|
endif
|
|
tree.end
|
|
newline
|
|
width 8.
|
|
group.long 0x178++0x13
|
|
line.long 0x00 "PTCRL,Port Control Register"
|
|
rbitfld.long 0x00 24. " PENDB ,Port B transactions pending" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " BYB ,Bypass FIFO B" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 17. " PSFRHQPB ,Port B high priority queue priority scheme" "Fixed,Rotated"
|
|
bitfld.long 0x00 16. " PSFRLQPB ,Port B low priority queue priority scheme" "Fixed,Rotated"
|
|
sif cpuis("AWR1443")||cpuis("AWR1443-CORE0")||cpuis("AWR1443-CORE1")||cpuis("AWR1843")||cpuis("AWR6843*")
|
|
newline
|
|
bitfld.long 0x00 8. " PENDA ,Port A transactions pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " BYA ,Bypass FIFO A" "Not limited,Limited"
|
|
bitfld.long 0x00 1. " PSFRHQPA ,Port A high priority queue priority scheme" "Fixed,Rotated"
|
|
bitfld.long 0x00 0. " PSFRLQPA ,Port A low priority queue priority scheme" "Fixed,Rotated"
|
|
endif
|
|
line.long 0x04 "RTCTRL,RAM Test Control Register"
|
|
bitfld.long 0x04 0. " RTC ,RAM test control" "Disabled,Enabled"
|
|
line.long 0x08 "DCTRL,Debug Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x08 24.--28. " CHNUM ,Channel number" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rbitfld.long 0x08 24.--28. " CHNUM ,Channel number" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
eventfld.long 0x08 16. " DMADBGS ,DMA debug status" "Not detected,Detected"
|
|
bitfld.long 0x08 0. " DBGEN ,Debug enable" "Disabled,Enabled"
|
|
line.long 0x0C "WPR,Watch Point Register"
|
|
newline
|
|
line.long 0x10 "WMR,Watch Point Mask Register"
|
|
bitfld.long 0x10 31. " WM[31:0] ,Watch point bit 31 mask" "0,1"
|
|
bitfld.long 0x10 30. ",Watch point bit 30 mask" "0,1"
|
|
bitfld.long 0x10 29. ",Watch point bit 29 mask" "0,1"
|
|
bitfld.long 0x10 28. ",Watch point bit 28 mask" "0,1"
|
|
bitfld.long 0x10 27. ",Watch point bit 27 mask" "0,1"
|
|
bitfld.long 0x10 26. ",Watch point bit 26 mask" "0,1"
|
|
bitfld.long 0x10 25. ",Watch point bit 25 mask" "0,1"
|
|
bitfld.long 0x10 24. ",Watch point bit 24 mask" "0,1"
|
|
bitfld.long 0x10 23. ",Watch point bit 23 mask" "0,1"
|
|
bitfld.long 0x10 22. ",Watch point bit 22 mask" "0,1"
|
|
bitfld.long 0x10 21. ",Watch point bit 21 mask" "0,1"
|
|
bitfld.long 0x10 20. ",Watch point bit 20 mask" "0,1"
|
|
bitfld.long 0x10 19. ",Watch point bit 19 mask" "0,1"
|
|
bitfld.long 0x10 18. ",Watch point bit 18 mask" "0,1"
|
|
bitfld.long 0x10 17. ",Watch point bit 17 mask" "0,1"
|
|
bitfld.long 0x10 16. ",Watch point bit 16 mask" "0,1"
|
|
bitfld.long 0x10 15. ",Watch point bit 15 mask" "0,1"
|
|
bitfld.long 0x10 14. ",Watch point bit 14 mask" "0,1"
|
|
bitfld.long 0x10 13. ",Watch point bit 13 mask" "0,1"
|
|
bitfld.long 0x10 12. ",Watch point bit 12 mask" "0,1"
|
|
bitfld.long 0x10 11. ",Watch point bit 11 mask" "0,1"
|
|
bitfld.long 0x10 10. ",Watch point bit 10 mask" "0,1"
|
|
bitfld.long 0x10 9. ",Watch point bit 9 mask" "0,1"
|
|
bitfld.long 0x10 8. ",Watch point bit 8 mask" "0,1"
|
|
bitfld.long 0x10 7. ",Watch point bit 7 mask" "0,1"
|
|
bitfld.long 0x10 6. ",Watch point bit 6 mask" "0,1"
|
|
bitfld.long 0x10 5. ",Watch point bit 5 mask" "0,1"
|
|
bitfld.long 0x10 4. ",Watch point bit 4 mask" "0,1"
|
|
bitfld.long 0x10 3. ",Watch point bit 3 mask" "0,1"
|
|
bitfld.long 0x10 2. ",Watch point bit 2 mask" "0,1"
|
|
bitfld.long 0x10 1. ",Watch point bit 1 mask" "0,1"
|
|
bitfld.long 0x10 0. ",Watch point bit 0 mask" "0,1"
|
|
width 11.
|
|
tree "Active Channel Registers"
|
|
sif cpuis("AWR1443")||cpuis("AWR1443-CORE0")||cpuis("AWR1443-CORE1")||cpuis("AWR1843")||cpuis("AWR6843*")
|
|
group.long 0x18C++0x0B
|
|
line.long 0x00 "PAACSADDR,Port A Active Channel Source Address Register"
|
|
line.long 0x04 "PAACDADDR,Port A Active Channel Destination Address Register"
|
|
line.long 0x08 "PAACTC,Port A Active Channel Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " PAFTCOUNT ,Port A active channel frame count"
|
|
hexmask.long.word 0x08 0.--12. 1. " PAETCOUNT ,Port A active channel element count"
|
|
endif
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long 0x198++0x0B
|
|
line.long 0x00 "PBACSADDR,Port B Active Channel Source Address Register"
|
|
line.long 0x04 "PBACDADDR,Port B Active Channel Destination Address Register"
|
|
line.long 0x08 "PBACTC,PortB Active Channel Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " PBFTCOUNT ,Port B active channel frame count"
|
|
hexmask.long.word 0x08 0.--12. 1. " PBETCOUNT ,Port B active channel element count"
|
|
else
|
|
rgroup.long 0x198++0x0B
|
|
line.long 0x00 "PBACSADDR,Port B Active Channel Source Address Register"
|
|
line.long 0x04 "PBACDADDR,Port B Active Channel Destination Address Register"
|
|
line.long 0x08 "PBACTC,PortB Active Channel Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " PBFTCOUNT ,Port B active channel frame count"
|
|
hexmask.long.word 0x08 0.--12. 1. " PBETCOUNT ,Port B active channel element count"
|
|
endif
|
|
tree.end
|
|
newline
|
|
width 8.
|
|
group.long 0x1A8++0x07
|
|
line.long 0x00 "DMAPCR,Parity Control Register"
|
|
bitfld.long 0x00 16. " ERRA ,Error action" "Unchanged,Disabled"
|
|
bitfld.long 0x00 8. " TEST ,Parity bits memory mapping" "Not mapped,Mapped"
|
|
bitfld.long 0x00 0.--3. " PARITY_ENA ,Parity error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x04 "DMAPAR,Parity Error Address Register"
|
|
eventfld.long 0x04 24. " EDFLG ,Parity error detection flag" "No error,Error"
|
|
hexmask.long.word 0x04 0.--11. 0x01 " ERROR_ADDRESS ,Error address"
|
|
tree "DMA Memory Protection Registers"
|
|
width 11.
|
|
group.long 0x1B0++0x27
|
|
line.long 0x00 "DMAMPCTRL,DMA Memory Protection Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 28. " INT3AB ,Interrupt assignment of region 3 to group A/B" "VIM,DSP"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 28. " INT3AB ,Interrupt assignment of region 3 to group A/B" "VIM,2nd CPU"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 27. " INT3ENA ,Interrupt enable of region 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " REG3AP ,Region 3 access permission" "R/W,Read,Write,Not allowed"
|
|
bitfld.long 0x00 24. " REG3ENA ,Region 3 enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 20. " INT2AB ,Interrupt assignment of region 2 to group A/B" "VIM,DSP"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 20. " INT2AB ,Interrupt assignment of region 2 to group A/B" "VIM,2nd CPU"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 19. " INT2ENA ,Interrupt enable of region 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17.--18. " REG2AP ,Region 2 access permission" "R/W,Read,Write,Not allowed"
|
|
bitfld.long 0x00 16. " REG2ENA ,Region 2 enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 12. " INT1AB ,Interrupt assignment of region 1 to group A/B" "VIM,DSP"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 12. " INT1AB ,Interrupt assignment of region 1 to group A/B" "VIM,2nd CPU"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " INT1ENA ,Interrupt enable of region 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " REG1AP ,Region 1 access permission" "R/W,Read,Write,Not allowed"
|
|
bitfld.long 0x00 8. " REG1ENA ,Region 1 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " INT0AB ,Interrupt assignment of region 0 to group A/B" "VIM,DSP"
|
|
bitfld.long 0x00 3. " INT0ENA ,Interrupt enable of region 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--2. " REG0AP ,Region 0 access permission" "R/W,Read,Write,Not allowed"
|
|
bitfld.long 0x00 0. " REG0ENA ,Region 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMAMPST,Memory Protection Status Register"
|
|
eventfld.long 0x04 24. " REG3FT ,Region 3 fault" "Not detected,Detected"
|
|
eventfld.long 0x04 16. " REG2FT ,Region 2 fault" "Not detected,Detected"
|
|
eventfld.long 0x04 8. " REG1FT ,Region 1 fault" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 0. " REG0FT ,Region 0 fault" "Not detected,Detected"
|
|
line.long 0x08 "DMAMPR0S,DMA Protection Region Starting Address 0 Register"
|
|
line.long 0x0C "DMAMPR0E,DMA Protection Region End Address 0 Register"
|
|
line.long 0x10 "DMAMPR1S,DMA Protection Region Starting Address 1 Register"
|
|
line.long 0x14 "DMAMPR1E,DMA Protection Region End Address 1 Register"
|
|
line.long 0x18 "DMAMPR2S,DMA Protection Region Starting Address 2 Register"
|
|
line.long 0x1C "DMAMPR2E,DMA Protection Region End Address 2 Register"
|
|
line.long 0x20 "DMAMPR3S,DMA Protection Region Starting Address 3 Register"
|
|
line.long 0x24 "DMAMPR3E,DMA Protection Region End Address 3 Register"
|
|
tree.end
|
|
base ad:0xFFF80000
|
|
tree "Control Packet Registers"
|
|
width 9.
|
|
tree.open "Primary Control Packet Registers"
|
|
tree "Primary Control Packet 0"
|
|
group.long (0x0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 1"
|
|
group.long (0x20)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x20+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 2"
|
|
group.long (0x40)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x40+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 3"
|
|
group.long (0x60)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x60+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 4"
|
|
group.long (0x80)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x80+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 5"
|
|
group.long (0xA0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0xA0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 6"
|
|
group.long (0xC0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0xC0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 7"
|
|
group.long (0xE0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0xE0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 8"
|
|
group.long (0x100)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x100+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 9"
|
|
group.long (0x120)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x120+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 10"
|
|
group.long (0x140)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x140+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 11"
|
|
group.long (0x160)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x160+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 12"
|
|
group.long (0x180)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x180+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 13"
|
|
group.long (0x1A0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x1A0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 14"
|
|
group.long (0x1C0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x1C0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 15"
|
|
group.long (0x1E0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x1E0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 16"
|
|
group.long (0x200)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x200+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 17"
|
|
group.long (0x220)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x220+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 18"
|
|
group.long (0x240)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x240+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 19"
|
|
group.long (0x260)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x260+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 20"
|
|
group.long (0x280)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x280+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 21"
|
|
group.long (0x2A0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x2A0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 22"
|
|
group.long (0x2C0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x2C0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 23"
|
|
group.long (0x2E0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x2E0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 24"
|
|
group.long (0x300)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x300+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 25"
|
|
group.long (0x320)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x320+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 26"
|
|
group.long (0x340)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x340+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 27"
|
|
group.long (0x360)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x360+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 28"
|
|
group.long (0x380)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x380+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 29"
|
|
group.long (0x3A0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x3A0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 30"
|
|
group.long (0x3C0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x3C0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 31"
|
|
group.long (0x3E0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x3E0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree.end
|
|
tree.open "Working Control Packet Registers"
|
|
tree "Working Control Packet 0"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 1"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x10+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x10+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x10+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 2"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x20+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x20+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x20+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 3"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x30+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x30+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x30+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 4"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x40+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x40+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x40+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 5"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x50+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x50+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x50+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 6"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x60+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x60+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x60+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 7"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x70+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x70+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x70+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 8"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x80+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x80+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x80+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 9"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x90+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x90+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x90+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 10"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0xA0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0xA0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0xA0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 11"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0xB0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0xB0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0xB0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 12"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0xC0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0xC0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0xC0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 13"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0xD0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0xD0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0xD0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 14"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0xE0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0xE0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0xE0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 15"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0xF0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0xF0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0xF0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 16"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x100+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x100+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x100+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 17"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x110+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x110+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x110+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 18"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x120+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x120+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x120+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 19"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x130+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x130+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x130+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 20"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x140+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x140+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x140+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 21"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x150+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x150+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x150+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 22"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x160+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x160+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x160+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 23"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x170+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x170+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x170+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 24"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x180+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x180+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x180+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 25"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x190+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x190+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x190+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 26"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x1A0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x1A0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x1A0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 27"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x1B0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x1B0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x1B0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 28"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x1C0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x1C0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x1C0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 29"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x1D0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x1D0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x1D0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 30"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x1E0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x1E0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x1E0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 31"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x1F0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x1F0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x1F0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA2"
|
|
base ad:0xFCFFF800
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCTRL,Global Control Register"
|
|
bitfld.long 0x00 16. " DMA_EN ,DMA enable" "Disabled,Enabled"
|
|
sif cpuis("TMS570LS3137-EP")||cpuis("AWR1843")||cpuis("AWR1843-CORE1")||cpuis("AWR1843DSP")||cpuis("AWR6843*")
|
|
rbitfld.long 0x00 14. " BUS_BUSY ,DMA external AHB bus status" "Not busy,Busy"
|
|
else
|
|
bitfld.long 0x00 14. " BUS_BUSY ,DMA external AHB bus status" "Not busy,Busy"
|
|
endif
|
|
bitfld.long 0x00 8.--9. " DEBUG_MODE ,Debug mode" "Suspend ignored,Block finished,Frame finished,Immediate stop"
|
|
newline
|
|
bitfld.long 0x00 0. " DMA_RES ,DMA software reset" "No reset,Reset"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PEND,Channel Pending Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " PEND[31] ,Channel 31 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 30. " [30] ,Channel 30 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 29. " [29] ,Channel 29 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 28. " [28] ,Channel 28 pending register" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Channel 27 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 26. " [26] ,Channel 26 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 25. " [25] ,Channel 25 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 24. " [24] ,Channel 24 pending register" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Channel 23 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 22. " [22] ,Channel 22 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 21. " [21] ,Channel 21 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 20. " [20] ,Channel 20 pending register" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel 19 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 18. " [18] ,Channel 18 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 17. " [17] ,Channel 17 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 16. " [16] ,Channel 16 pending register" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel 15 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 pending register" "Inactive,Pending"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " PEND[15] ,Channel 15 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Channel 14 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Channel 13 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Channel 12 pending register" "Inactive,Pending"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Channel 11 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Channel 10 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Channel 9 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 8. " [8] ,Channel 8 pending register" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel 7 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 pending register" "Inactive,Pending"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 pending register" "Inactive,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 pending register" "Inactive,Pending"
|
|
sif cpuis("AWR1443")||cpuis("AWR1443-CORE0")||cpuis("AWR1443-CORE1")||cpuis("AWR1642")||cpuis("AWR1642-CORE1")||cpuis("AWR1843")||cpuis("AWR1843-CORE1")||cpuis("AWR1843DSP")||cpuis("AWR6843*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FBREG,Fall Back Register For EMC"
|
|
bitfld.long 0x00 8.--11. " FSMFB ,Switch off RTL clock gating for all FSM logics used for saving power" ",,,,,Enabled,,,,,Disabled,?..."
|
|
bitfld.long 0x00 0.--3. " VBUSPFB ,Switch off RTL clock gating for all VBUSP logics used for saving power" ",,,,,Enabled,,,,,Disabled,?..."
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DMASTAT,DMA Status Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " STCH[31] ,Status of DMA channel 31" "Inactive,Active"
|
|
bitfld.long 0x00 30. " [30] ,Status of DMA channel 30" "Inactive,Active"
|
|
bitfld.long 0x00 29. " [29] ,Status of DMA channel 29" "Inactive,Active"
|
|
bitfld.long 0x00 28. " [28] ,Status of DMA channel 28" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Status of DMA channel 27" "Inactive,Active"
|
|
bitfld.long 0x00 26. " [26] ,Status of DMA channel 26" "Inactive,Active"
|
|
bitfld.long 0x00 25. " [25] ,Status of DMA channel 25" "Inactive,Active"
|
|
bitfld.long 0x00 24. " [24] ,Status of DMA channel 24" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Status of DMA channel 23" "Inactive,Active"
|
|
bitfld.long 0x00 22. " [22] ,Status of DMA channel 22" "Inactive,Active"
|
|
bitfld.long 0x00 21. " [21] ,Status of DMA channel 21" "Inactive,Active"
|
|
bitfld.long 0x00 20. " [20] ,Status of DMA channel 20" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Status of DMA channel 19" "Inactive,Active"
|
|
bitfld.long 0x00 18. " [18] ,Status of DMA channel 18" "Inactive,Active"
|
|
bitfld.long 0x00 17. " [17] ,Status of DMA channel 17" "Inactive,Active"
|
|
bitfld.long 0x00 16. " [16] ,Status of DMA channel 16" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Status of DMA channel 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " [14] ,Status of DMA channel 14" "Inactive,Active"
|
|
bitfld.long 0x00 13. " [13] ,Status of DMA channel 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " [12] ,Status of DMA channel 12" "Inactive,Active"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " STCH[15] ,Status of DMA channel 15" "Inactive,Active"
|
|
bitfld.long 0x00 14. " [14] ,Status of DMA channel 14" "Inactive,Active"
|
|
bitfld.long 0x00 13. " [13] ,Status of DMA channel 13" "Inactive,Active"
|
|
bitfld.long 0x00 12. " [12] ,Status of DMA channel 12" "Inactive,Active"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Status of DMA channel 11" "Inactive,Active"
|
|
bitfld.long 0x00 10. " [10] ,Status of DMA channel 10" "Inactive,Active"
|
|
bitfld.long 0x00 9. " [9] ,Status of DMA channel 9" "Inactive,Active"
|
|
bitfld.long 0x00 8. " [8] ,Status of DMA channel 8" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Status of DMA channel 7" "Inactive,Active"
|
|
bitfld.long 0x00 6. " [6] ,Status of DMA channel 6" "Inactive,Active"
|
|
bitfld.long 0x00 5. " [5] ,Status of DMA channel 5" "Inactive,Active"
|
|
bitfld.long 0x00 4. " [4] ,Status of DMA channel 4" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Status of DMA channel 3" "Inactive,Active"
|
|
bitfld.long 0x00 2. " [2] ,Status of DMA channel 2" "Inactive,Active"
|
|
bitfld.long 0x00 1. " [1] ,Status of DMA channel 1" "Inactive,Active"
|
|
bitfld.long 0x00 0. " [0] ,Status of DMA channel 0" "Inactive,Active"
|
|
width 10.
|
|
tree "Channel Enable Status Registers"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "HWCHENAS,HWCHANNEL Enable Set And Status Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " HWCHENA[31] ,HW channel 31 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,HW channel 30 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,HW channel 29 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,HW channel 28 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,HW channel 27 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,HW channel 26 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,HW channel 25 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,HW channel 24 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,HW channel 23 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,HW channel 22 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,HW channel 21 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,HW channel 20 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,HW channel 19 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,HW channel 18 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,HW channel 17 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,HW channel 16 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,HW channel 15 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,HW channel 14 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,HW channel 13 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,HW channel 12 enable status" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " HWCHENA[15] ,HW channel 15 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,HW channel 14 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,HW channel 13 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,HW channel 12 enable status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,HW channel 11 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,HW channel 10 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,HW channel 9 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,HW channel 8 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,HW channel 7 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,HW channel 6 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,HW channel 5 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,HW channel 4 enable status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,HW channel 3 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,HW channel 2 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,HW channel 1 enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,HW channel 0 enable status" "Disabled,Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "HWCHENAR,HWCHANNEL Enable Reset And Status Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " HWCHDIS[31] ,HW channel 31 disable" "No effect,Reset"
|
|
bitfld.long 0x00 30. " [30] ,HW channel 30 disable" "No effect,Reset"
|
|
bitfld.long 0x00 29. " [29] ,HW channel 29 disable" "No effect,Reset"
|
|
bitfld.long 0x00 28. " [28] ,HW channel 28 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,HW channel 27 disable" "No effect,Reset"
|
|
bitfld.long 0x00 26. " [26] ,HW channel 26 disable" "No effect,Reset"
|
|
bitfld.long 0x00 25. " [25] ,HW channel 25 disable" "No effect,Reset"
|
|
bitfld.long 0x00 24. " [24] ,HW channel 24 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,HW channel 23 disable" "No effect,Reset"
|
|
bitfld.long 0x00 22. " [22] ,HW channel 22 disable" "No effect,Reset"
|
|
bitfld.long 0x00 21. " [21] ,HW channel 21 disable" "No effect,Reset"
|
|
bitfld.long 0x00 20. " [20] ,HW channel 20 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,HW channel 19 disable" "No effect,Reset"
|
|
bitfld.long 0x00 18. " [18] ,HW channel 18 disable" "No effect,Reset"
|
|
bitfld.long 0x00 17. " [17] ,HW channel 17 disable" "No effect,Reset"
|
|
bitfld.long 0x00 16. " [16] ,HW channel 16 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,HW channel 15 disable" "No effect,Reset"
|
|
bitfld.long 0x00 14. " [14] ,HW channel 14 disable" "No effect,Reset"
|
|
bitfld.long 0x00 13. " [13] ,HW channel 13 disable" "No effect,Reset"
|
|
bitfld.long 0x00 12. " [12] ,HW channel 12 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,HW channel 11 disable" "No effect,Reset"
|
|
bitfld.long 0x00 10. " [10] ,HW channel 10 disable" "No effect,Reset"
|
|
bitfld.long 0x00 9. " [9] ,HW channel 9 disable" "No effect,Reset"
|
|
bitfld.long 0x00 8. " [8] ,HW channel 8 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,HW channel 7 disable" "No effect,Reset"
|
|
bitfld.long 0x00 6. " [6] ,HW channel 6 disable" "No effect,Reset"
|
|
bitfld.long 0x00 5. " [5] ,HW channel 5 disable" "No effect,Reset"
|
|
bitfld.long 0x00 4. " [4] ,HW channel 4 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,HW channel 3 disable" "No effect,Reset"
|
|
bitfld.long 0x00 2. " [2] ,HW channel 2 disable" "No effect,Reset"
|
|
bitfld.long 0x00 1. " [1] ,HW channel 1 disable" "No effect,Reset"
|
|
bitfld.long 0x00 0. " [0] ,HW channel 0 disable" "No effect,Reset"
|
|
else
|
|
eventfld.long 0x00 15. " HWCHDIS[15] ,HW channel 15 disable" "No effect,Reset"
|
|
eventfld.long 0x00 14. " [14] ,HW channel 14 disable" "No effect,Reset"
|
|
eventfld.long 0x00 13. " [13] ,HW channel 13 disable" "No effect,Reset"
|
|
eventfld.long 0x00 12. " [12] ,HW channel 12 disable" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,HW channel 11 disable" "No effect,Reset"
|
|
eventfld.long 0x00 10. " [10] ,HW channel 10 disable" "No effect,Reset"
|
|
eventfld.long 0x00 9. " [9] ,HW channel 9 disable" "No effect,Reset"
|
|
eventfld.long 0x00 8. " [8] ,HW channel 8 disable" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,HW channel 7 disable" "No effect,Reset"
|
|
eventfld.long 0x00 6. " [6] ,HW channel 6 disable" "No effect,Reset"
|
|
eventfld.long 0x00 5. " [5] ,HW channel 5 disable" "No effect,Reset"
|
|
eventfld.long 0x00 4. " [4] ,HW channel 4 disable" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,HW channel 3 disable" "No effect,Reset"
|
|
eventfld.long 0x00 2. " [2] ,HW channel 2 disable" "No effect,Reset"
|
|
eventfld.long 0x00 1. " [1] ,HW channel 1 disable" "No effect,Reset"
|
|
eventfld.long 0x00 0. " [0] ,HW channel 0 disable" "No effect,Reset"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SWCHENAS,SWCHANNEL Enable Set And Status Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " SWCHENA[31] ,SW channel 31 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 30. " [30] ,SW channel 30 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 29. " [29] ,SW channel 29 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 28. " [28] ,SW channel 28 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SW channel 27 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 26. " [26] ,SW channel 26 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 25. " [25] ,SW channel 25 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 24. " [24] ,SW channel 24 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SW channel 23 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 22. " [22] ,SW channel 22 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 21. " [21] ,SW channel 21 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20. " [20] ,SW channel 20 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SW channel 19 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 18. " [18] ,SW channel 18 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 17. " [17] ,SW channel 17 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 16. " [16] ,SW channel 16 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SW channel 15 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 14. " [14] ,SW channel 14 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 13. " [13] ,SW channel 13 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 12. " [12] ,SW channel 12 enable status" "Not triggered,Triggered"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " SWCHENA[15] ,SW channel 15 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 14. " [14] ,SW channel 14 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 13. " [13] ,SW channel 13 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 12. " [12] ,SW channel 12 enable status" "Not triggered,Triggered"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,SW channel 11 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 10. " [10] ,SW channel 10 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 9. " [9] ,SW channel 9 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 8. " [8] ,SW channel 8 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SW channel 7 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 6. " [6] ,SW channel 6 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 5. " [5] ,SW channel 5 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 4. " [4] ,SW channel 4 enable status" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SW channel 3 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 2. " [2] ,SW channel 2 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 1. " [1] ,SW channel 1 enable status" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " [0] ,SW channel 0 enable status" "Not triggered,Triggered"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SWCHENAR,SWCHANNEL Enable Reset And Status Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " SWCHDIS[31] ,SW channel 31 disable" "No effect,Reset"
|
|
bitfld.long 0x00 30. " [30] ,SW channel 30 disable" "No effect,Reset"
|
|
bitfld.long 0x00 29. " [29] ,SW channel 29 disable" "No effect,Reset"
|
|
bitfld.long 0x00 28. " [28] ,SW channel 28 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,SW channel 27 disable" "No effect,Reset"
|
|
bitfld.long 0x00 26. " [26] ,SW channel 26 disable" "No effect,Reset"
|
|
bitfld.long 0x00 25. " [25] ,SW channel 25 disable" "No effect,Reset"
|
|
bitfld.long 0x00 24. " [24] ,SW channel 24 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,SW channel 23 disable" "No effect,Reset"
|
|
bitfld.long 0x00 22. " [22] ,SW channel 22 disable" "No effect,Reset"
|
|
bitfld.long 0x00 21. " [21] ,SW channel 21 disable" "No effect,Reset"
|
|
bitfld.long 0x00 20. " [20] ,SW channel 20 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,SW channel 19 disable" "No effect,Reset"
|
|
bitfld.long 0x00 18. " [18] ,SW channel 18 disable" "No effect,Reset"
|
|
bitfld.long 0x00 17. " [17] ,SW channel 17 disable" "No effect,Reset"
|
|
bitfld.long 0x00 16. " [16] ,SW channel 16 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SW channel 15 disable" "No effect,Reset"
|
|
bitfld.long 0x00 14. " [14] ,SW channel 14 disable" "No effect,Reset"
|
|
bitfld.long 0x00 13. " [13] ,SW channel 13 disable" "No effect,Reset"
|
|
bitfld.long 0x00 12. " [12] ,SW channel 12 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SW channel 11 disable" "No effect,Reset"
|
|
bitfld.long 0x00 10. " [10] ,SW channel 10 disable" "No effect,Reset"
|
|
bitfld.long 0x00 9. " [9] ,SW channel 9 disable" "No effect,Reset"
|
|
bitfld.long 0x00 8. " [8] ,SW channel 8 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SW channel 7 disable" "No effect,Reset"
|
|
bitfld.long 0x00 6. " [6] ,SW channel 6 disable" "No effect,Reset"
|
|
bitfld.long 0x00 5. " [5] ,SW channel 5 disable" "No effect,Reset"
|
|
bitfld.long 0x00 4. " [4] ,SW channel 4 disable" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SW channel 3 disable" "No effect,Reset"
|
|
bitfld.long 0x00 2. " [2] ,SW channel 2 disable" "No effect,Reset"
|
|
bitfld.long 0x00 1. " [1] ,SW channel 1 disable" "No effect,Reset"
|
|
bitfld.long 0x00 0. " [0] ,SW channel 0 disable" "No effect,Reset"
|
|
else
|
|
eventfld.long 0x00 15. " SWCHDIS[15] ,SW channel 15 disable" "No effect,Reset"
|
|
eventfld.long 0x00 14. " [14] ,SW channel 14 disable" "No effect,Reset"
|
|
eventfld.long 0x00 13. " [13] ,SW channel 13 disable" "No effect,Reset"
|
|
eventfld.long 0x00 12. " [12] ,SW channel 12 disable" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,SW channel 11 disable" "No effect,Reset"
|
|
eventfld.long 0x00 10. " [10] ,SW channel 10 disable" "No effect,Reset"
|
|
eventfld.long 0x00 9. " [9] ,SW channel 9 disable" "No effect,Reset"
|
|
eventfld.long 0x00 8. " [8] ,SW channel 8 disable" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,SW channel 7 disable" "No effect,Reset"
|
|
eventfld.long 0x00 6. " [6] ,SW channel 6 disable" "No effect,Reset"
|
|
eventfld.long 0x00 5. " [5] ,SW channel 5 disable" "No effect,Reset"
|
|
eventfld.long 0x00 4. " [4] ,SW channel 4 disable" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,SW channel 3 disable" "No effect,Reset"
|
|
eventfld.long 0x00 2. " [2] ,SW channel 2 disable" "No effect,Reset"
|
|
eventfld.long 0x00 1. " [1] ,SW channel 1 disable" "No effect,Reset"
|
|
eventfld.long 0x00 0. " [0] ,SW channel 0 disable" "No effect,Reset"
|
|
endif
|
|
tree.end
|
|
newline
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CHPRIOS,Channel Priority Set Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " CPS[31] ,Channel priority 31 set" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,Channel priority 30 set" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,Channel priority 29 set" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,Channel priority 28 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Channel priority 27 set" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,Channel priority 26 set" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,Channel priority 25 set" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Channel priority 24 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Channel priority 23 set" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,Channel priority 22 set" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Channel priority 21 set" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Channel priority 20 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel priority 19 set" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Channel priority 18 set" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,Channel priority 17 set" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Channel priority 16 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel priority 15 set" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Channel priority 14 set" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Channel priority 13 set" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Channel priority 12 set" "Low,High"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " CPS[15] ,Channel priority 15 set" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Channel priority 14 set" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Channel priority 13 set" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Channel priority 12 set" "Low,High"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Channel priority 11 set" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Channel priority 10 set" "Low,High"
|
|
bitfld.long 0x00 9. " [9] ,Channel priority 9 set" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Channel priority 8 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel priority 7 set" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Channel priority 6 set" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Channel priority 5 set" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Channel priority 4 set" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel priority 3 set" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Channel priority 2 set" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Channel priority 1 set" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Channel priority 0 set" "Low,High"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CHPRIOR,Channel Priority Reset Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " CPL[31] ,Channel priority 31" "No effect,Reset"
|
|
bitfld.long 0x00 30. " [30] ,Channel priority 30" "No effect,Reset"
|
|
bitfld.long 0x00 29. " [29] ,Channel priority 29" "No effect,Reset"
|
|
bitfld.long 0x00 28. " [28] ,Channel priority 28" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Channel priority 27" "No effect,Reset"
|
|
bitfld.long 0x00 26. " [26] ,Channel priority 26" "No effect,Reset"
|
|
bitfld.long 0x00 25. " [25] ,Channel priority 25" "No effect,Reset"
|
|
bitfld.long 0x00 24. " [24] ,Channel priority 24" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Channel priority 23" "No effect,Reset"
|
|
bitfld.long 0x00 22. " [22] ,Channel priority 22" "No effect,Reset"
|
|
bitfld.long 0x00 21. " [21] ,Channel priority 21" "No effect,Reset"
|
|
bitfld.long 0x00 20. " [20] ,Channel priority 20" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Channel priority 19" "No effect,Reset"
|
|
bitfld.long 0x00 18. " [18] ,Channel priority 18" "No effect,Reset"
|
|
bitfld.long 0x00 17. " [17] ,Channel priority 17" "No effect,Reset"
|
|
bitfld.long 0x00 16. " [16] ,Channel priority 16" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Channel priority 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " [14] ,Channel priority 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " [13] ,Channel priority 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " [12] ,Channel priority 12" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Channel priority 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " [10] ,Channel priority 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " [9] ,Channel priority 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " [8] ,Channel priority 8" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel priority 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " [6] ,Channel priority 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " [5] ,Channel priority 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " [4] ,Channel priority 4" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel priority 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " [2] ,Channel priority 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " [1] ,Channel priority 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " [0] ,Channel priority 0" "No effect,Reset"
|
|
else
|
|
eventfld.long 0x00 15. " CPL[15] ,Channel priority 15" "No effect,Reset"
|
|
eventfld.long 0x00 14. " [14] ,Channel priority 14" "No effect,Reset"
|
|
eventfld.long 0x00 13. " [13] ,Channel priority 13" "No effect,Reset"
|
|
eventfld.long 0x00 12. " [12] ,Channel priority 12" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Channel priority 11" "No effect,Reset"
|
|
eventfld.long 0x00 10. " [10] ,Channel priority 10" "No effect,Reset"
|
|
eventfld.long 0x00 9. " [9] ,Channel priority 9" "No effect,Reset"
|
|
eventfld.long 0x00 8. " [8] ,Channel priority 8" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Channel priority 7" "No effect,Reset"
|
|
eventfld.long 0x00 6. " [6] ,Channel priority 6" "No effect,Reset"
|
|
eventfld.long 0x00 5. " [5] ,Channel priority 5" "No effect,Reset"
|
|
eventfld.long 0x00 4. " [4] ,Channel priority 4" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Channel priority 3" "No effect,Reset"
|
|
eventfld.long 0x00 2. " [2] ,Channel priority 2" "No effect,Reset"
|
|
eventfld.long 0x00 1. " [1] ,Channel priority 1" "No effect,Reset"
|
|
eventfld.long 0x00 0. " [0] ,Channel priority 0" "No effect,Reset"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "GCHIENAS,Global Channel Interrupt Enable Set Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " GCHIE[31] ,Global channel interrupt enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Global channel interrupt enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Global channel interrupt enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Global channel interrupt enable 28" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Global channel interrupt enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Global channel interrupt enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Global channel interrupt enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Global channel interrupt enable 24" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Global channel interrupt enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Global channel interrupt enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Global channel interrupt enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Global channel interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Global channel interrupt enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Global channel interrupt enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Global channel interrupt enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Global channel interrupt enable 16" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Global channel interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Global channel interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Global channel interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Global channel interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " GCHIE[15] ,Global channel interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Global channel interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Global channel interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Global channel interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Global channel interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Global channel interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Global channel interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Global channel interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Global channel interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Global channel interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Global channel interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Global channel interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Global channel interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Global channel interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Global channel interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Global channel interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GCHIENAR,Global Channel Interrupt Enable Reset Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " GCHID[31] ,Global channel interrupt disable 31" "No effect,Reset"
|
|
bitfld.long 0x00 30. " [30] ,Global channel interrupt disable 30" "No effect,Reset"
|
|
bitfld.long 0x00 29. " [29] ,Global channel interrupt disable 29" "No effect,Reset"
|
|
bitfld.long 0x00 28. " [28] ,Global channel interrupt disable 28" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Global channel interrupt disable 27" "No effect,Reset"
|
|
bitfld.long 0x00 26. " [26] ,Global channel interrupt disable 26" "No effect,Reset"
|
|
bitfld.long 0x00 25. " [25] ,Global channel interrupt disable 25" "No effect,Reset"
|
|
bitfld.long 0x00 24. " [24] ,Global channel interrupt disable 24" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Global channel interrupt disable 23" "No effect,Reset"
|
|
bitfld.long 0x00 22. " [22] ,Global channel interrupt disable 22" "No effect,Reset"
|
|
bitfld.long 0x00 21. " [21] ,Global channel interrupt disable 21" "No effect,Reset"
|
|
bitfld.long 0x00 20. " [20] ,Global channel interrupt disable 20" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Global channel interrupt disable 19" "No effect,Reset"
|
|
bitfld.long 0x00 18. " [18] ,Global channel interrupt disable 18" "No effect,Reset"
|
|
bitfld.long 0x00 17. " [17] ,Global channel interrupt disable 17" "No effect,Reset"
|
|
bitfld.long 0x00 16. " [16] ,Global channel interrupt disable 16" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Global channel interrupt disable 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " [14] ,Global channel interrupt disable 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " [13] ,Global channel interrupt disable 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " [12] ,Global channel interrupt disable 12" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Global channel interrupt disable 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " [10] ,Global channel interrupt disable 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " [9] ,Global channel interrupt disable 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " [8] ,Global channel interrupt disable 8" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Global channel interrupt disable 7" "No effect,Reset"
|
|
bitfld.long 0x00 6. " [6] ,Global channel interrupt disable 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " [5] ,Global channel interrupt disable 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " [4] ,Global channel interrupt disable 4" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Global channel interrupt disable 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " [2] ,Global channel interrupt disable 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " [1] ,Global channel interrupt disable 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " [0] ,Global channel interrupt disable 0" "No effect,Reset"
|
|
else
|
|
eventfld.long 0x00 15. " GCHID[15] ,Global channel interrupt disable 15" "No effect,Reset"
|
|
eventfld.long 0x00 14. " [14] ,Global channel interrupt disable 14" "No effect,Reset"
|
|
eventfld.long 0x00 13. " [13] ,Global channel interrupt disable 13" "No effect,Reset"
|
|
eventfld.long 0x00 12. " [12] ,Global channel interrupt disable 12" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Global channel interrupt disable 11" "No effect,Reset"
|
|
eventfld.long 0x00 10. " [10] ,Global channel interrupt disable 10" "No effect,Reset"
|
|
eventfld.long 0x00 9. " [9] ,Global channel interrupt disable 9" "No effect,Reset"
|
|
eventfld.long 0x00 8. " [8] ,Global channel interrupt disable 8" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Global channel interrupt disable 7" "No effect,Reset"
|
|
eventfld.long 0x00 6. " [6] ,Global channel interrupt disable 6" "No effect,Reset"
|
|
eventfld.long 0x00 5. " [5] ,Global channel interrupt disable 5" "No effect,Reset"
|
|
eventfld.long 0x00 4. " [4] ,Global channel interrupt disable 4" "No effect,Reset"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Global channel interrupt disable 3" "No effect,Reset"
|
|
eventfld.long 0x00 2. " [2] ,Global channel interrupt disable 2" "No effect,Reset"
|
|
eventfld.long 0x00 1. " [1] ,Global channel interrupt disable 1" "No effect,Reset"
|
|
eventfld.long 0x00 0. " [0] ,Global channel interrupt disable 0" "No effect,Reset"
|
|
endif
|
|
tree "DMA Request Assignment Registers"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DREQASI0,DMA Request Assignment Register 0"
|
|
bitfld.long 0x00 24.--29. " CH0 ASI ,Channel 0 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH1 ASI ,Channel 1 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH2 ASI ,Channel 2 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH3 ASI ,Channel 3 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DREQASI1,DMA Request Assignment Register 1"
|
|
bitfld.long 0x00 24.--29. " CH4 ASI ,Channel 4 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH5 ASI ,Channel 5 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH6 ASI ,Channel 6 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH7 ASI ,Channel 7 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "DREQASI2,DMA Request Assignment Register 2"
|
|
bitfld.long 0x00 24.--29. " CH8 ASI ,Channel 8 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH9 ASI ,Channel 9 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH10ASI ,Channel 10 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH11ASI ,Channel 11 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DREQASI3,DMA Request Assignment Register 3"
|
|
bitfld.long 0x00 24.--29. " CH12ASI ,Channel 12 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH13ASI ,Channel 13 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH14ASI ,Channel 14 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH15ASI ,Channel 15 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "DREQASI4,DMA Request Assignment Register 4"
|
|
bitfld.long 0x00 24.--29. " CH16ASI ,Channel 16 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH17ASI ,Channel 17 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH18ASI ,Channel 18 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH19ASI ,Channel 19 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "DREQASI5,DMA Request Assignment Register 5"
|
|
bitfld.long 0x00 24.--29. " CH20ASI ,Channel 20 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH21ASI ,Channel 21 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH22ASI ,Channel 22 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH23ASI ,Channel 23 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "DREQASI6,DMA Request Assignment Register 6"
|
|
bitfld.long 0x00 24.--29. " CH24ASI ,Channel 24 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH25ASI ,Channel 25 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH26ASI ,Channel 26 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH27ASI ,Channel 27 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DREQASI7,DMA Request Assignment Register 7"
|
|
bitfld.long 0x00 24.--29. " CH28ASI ,Channel 28 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH29ASI ,Channel 29 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH30ASI ,Channel 30 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH31ASI ,Channel 31 assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DREQASI0,DMA Request Assignment Register 0"
|
|
bitfld.long 0x00 24.--29. " CH0ASI ,Channel CH0ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH1ASI ,Channel CH1ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH2ASI ,Channel CH2ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH3ASI ,Channel CH3ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "DREQASI1,DMA Request Assignment Register 1"
|
|
bitfld.long 0x00 24.--29. " CH4ASI ,Channel CH4ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH5ASI ,Channel CH5ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH6ASI ,Channel CH6ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH7ASI ,Channel CH7ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "DREQASI2,DMA Request Assignment Register 2"
|
|
bitfld.long 0x00 24.--29. " CH8ASI ,Channel CH8ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH9ASI ,Channel CH9ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH10ASI ,Channel CH10ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH11ASI ,Channel CH11ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DREQASI3,DMA Request Assignment Register 3"
|
|
bitfld.long 0x00 24.--29. " CH12ASI ,Channel CH12ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 16.--21. " CH13ASI ,Channel CH13ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 8.--13. " CH14ASI ,Channel CH14ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
bitfld.long 0x00 0.--5. " CH15ASI ,Channel CH15ASI assignment" "Line 0,Line 1,Line 2,Line 3,Line 4,Line 5,Line 6,Line 7,Line 8,Line 9,Line 10,Line 11,Line 12,Line 13,Line 14,Line 15,Line 16,Line 17,Line 18,Line 19,Line 20,Line 21,Line 22,Line 23,Line 24,Line 25,Line 26,Line 27,Line 28,Line 29,Line 30,Line 31,Line 32,Line 33,Line 34,Line 35,Line 36,Line 37,Line 38,Line 39,Line 40,Line 41,Line 42,Line 43,Line 44,Line 45,Line 46,Line 47,Line 48,Line 49,Line 50,Line 51,Line 52,Line 53,Line 54,Line 55,Line 56,Line 57,Line 58,Line 59,Line 60,Line 61,Line 62,Line 63"
|
|
endif
|
|
tree.end
|
|
width 6.
|
|
tree "Port Assignment Registers"
|
|
sif cpuis("AWR*")
|
|
group.long 0x94++0x0F
|
|
line.long 0x00 "PAR0,Port Assignment Register 0"
|
|
sif cpuis("AWR1642")||cpuis("AWR1642-CORE1")
|
|
bitfld.long 0x00 28.--30. " CH0PA ,Port channel 0 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 24.--26. " CH1PA ,Port channel 1 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 20.--22. " CH2PA ,Port channel 2 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CH3PA ,Port channel 3 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 12.--14. " CH4PA ,Port channel 4 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 8.--10. " CH5PA ,Port channel 5 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CH6PA ,Port channel 6 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 0.--2. " CH7PA ,Port channel 7 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
else
|
|
bitfld.long 0x00 28.--30. " CH0PA ,Port channel 0 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x00 24.--26. " CH1PA ,Port channel 1 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x00 20.--22. " CH2PA ,Port channel 2 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CH3PA ,Port channel 3 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x00 12.--14. " CH4PA ,Port channel 4 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x00 8.--10. " CH5PA ,Port channel 5 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CH6PA ,Port channel 6 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x00 0.--2. " CH7PA ,Port channel 7 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
endif
|
|
line.long 0x04 "PAR1,Port Assignment Register 1"
|
|
sif cpuis("AWR1642")||cpuis("AWR1642-CORE1")
|
|
bitfld.long 0x04 28.--30. " CH8PA ,Port channel 8 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 24.--26. " CH9PA ,Port channel 9 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 20.--22. " CH10PA ,Port channel 10 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " CH11PA ,Port channel 11 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 12.--14. " CH12PA ,Port channel 12 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 8.--10. " CH13PA ,Port channel 13 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x04 4.--6. " CH14PA ,Port channel 14 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 0.--2. " CH15PA ,Port channel 15 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
else
|
|
bitfld.long 0x04 28.--30. " CH8PA ,Port channel 8 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x04 24.--26. " CH9PA ,Port channel 9 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x04 20.--22. " CH10PA ,Port channel 10 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " CH11PA ,Port channel 11 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x04 12.--14. " CH12PA ,Port channel 12 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x04 8.--10. " CH13PA ,Port channel 13 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x04 4.--6. " CH14PA ,Port channel 14 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x04 0.--2. " CH15PA ,Port channel 15 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
endif
|
|
line.long 0x08 "PAR2,Port Assignment Register 2"
|
|
sif cpuis("AWR1642")||cpuis("AWR1642-CORE1")
|
|
bitfld.long 0x08 28.--30. " CH16PA ,Port channel 16 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x08 24.--26. " CH17PA ,Port channel 17 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x08 20.--22. " CH18PA ,Port channel 18 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x08 16.--18. " CH19PA ,Port channel 19 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x08 12.--14. " CH20PA ,Port channel 20 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x08 8.--10. " CH21PA ,Port channel 21 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x08 4.--6. " CH22PA ,Port channel 22 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x08 0.--2. " CH23PA ,Port channel 23 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
else
|
|
bitfld.long 0x08 28.--30. " CH16PA ,Port channel 16 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x08 24.--26. " CH17PA ,Port channel 17 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x08 20.--22. " CH18PA ,Port channel 18 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x08 16.--18. " CH19PA ,Port channel 19 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x08 12.--14. " CH20PA ,Port channel 20 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x08 8.--10. " CH21PA ,Port channel 21 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x08 4.--6. " CH22PA ,Port channel 22 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x08 0.--2. " CH23PA ,Port channel 23 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
endif
|
|
line.long 0x0C "PAR3,Port Assignment Register 3"
|
|
sif cpuis("AWR1642")||cpuis("AWR1642-CORE1")
|
|
bitfld.long 0x0C 28.--30. " CH24PA ,Port channel 24 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x0C 24.--26. " CH25PA ,Port channel 25 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x0C 20.--22. " CH26PA ,Port channel 26 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x0C 16.--18. " CH27PA ,Port channel 27 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x0C 12.--14. " CH28PA ,Port channel 28 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x0C 8.--10. " CH29PA ,Port channel 29 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x0C 4.--6. " CH30PA ,Port channel 30 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x0C 0.--2. " CH31PA ,Port channel 31 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
else
|
|
bitfld.long 0x0C 28.--30. " CH24PA ,Port channel 24 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x0C 24.--26. " CH25PA ,Port channel 25 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x0C 20.--22. " CH26PA ,Port channel 26 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x0C 16.--18. " CH27PA ,Port channel 27 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x0C 12.--14. " CH28PA ,Port channel 28 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x0C 8.--10. " CH29PA ,Port channel 29 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
newline
|
|
bitfld.long 0x0C 4.--6. " CH30PA ,Port channel 30 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
bitfld.long 0x0C 0.--2. " CH31PA ,Port channel 31 assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B"
|
|
endif
|
|
elif cpuis("TMS570LS21*")||cpuis("TMS570LS31*")
|
|
group.long 0x94++0x07
|
|
line.long 0x00 "PAR0,Port Assignment Register 0"
|
|
bitfld.long 0x00 28.--30. " CH0PA ,Port channel 0 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 24.--26. " CH1PA ,Port channel 1 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 20.--22. " CH2PA ,Port channel 2 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CH3PA ,Port channel 3 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 12.--14. " CH4PA ,Port channel 4 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 8.--10. " CH5PA ,Port channel 5 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CH6PA ,Port channel 6 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 0.--2. " CH7PA ,Port channel 7 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
line.long 0x04 "PAR1,Port Assignment Register 1"
|
|
bitfld.long 0x04 28.--30. " CH8PA ,Port channel 8 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 24.--26. " CH9PA ,Port channel 9 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 20.--22. " CH10PA ,Port channel 10 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " CH11PA ,Port channel 11 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 12.--14. " CH12PA ,Port channel 12 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 8.--10. " CH13PA ,Port channel 13 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x04 4.--6. " CH14PA ,Port channel 14 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 0.--2. " CH15PA ,Port channel 15 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
else
|
|
group.long 0x94++0x07
|
|
line.long 0x00 "PAR0,Port Assignment Register 0"
|
|
bitfld.long 0x00 28.--30. " CH0PA ,Port channel 0 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 24.--26. " CH1PA ,Port channel 1 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 20.--22. " CH2PA ,Port channel 2 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CH3PA ,Port channel 3 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 12.--14. " CH4PA ,Port channel 4 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 8.--10. " CH5PA ,Port channel 5 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CH6PA ,Port channel 6 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x00 0.--2. " CH7PA ,Port channel 7 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
line.long 0x04 "PAR1,Port Assignment Register 1"
|
|
bitfld.long 0x04 28.--30. " CH8PA ,Port channel 8 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 24.--26. " CH9PA ,Port channel 9 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 20.--22. " CH10PA ,Port channel 10 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " CH11PA ,Port channel 11 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 12.--14. " CH12PA ,Port channel 12 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 8.--10. " CH13PA ,Port channel 13 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
newline
|
|
bitfld.long 0x04 4.--6. " CH14PA ,Port channel 14 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
bitfld.long 0x04 0.--2. " CH15PA ,Port channel 15 assignment" ",,,,Port B,Port B,Port B,Port B"
|
|
endif
|
|
tree.end
|
|
width 8.
|
|
tree "Interrupt Mapping Registers"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "FTCMAP,FTC Interrupt Mapping Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " FTCAB[31] ,Frame transfer complete interrupt of channel 31 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 30. " [30] ,Frame transfer complete interrupt of channel 30 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 29. " [29] ,Frame transfer complete interrupt of channel 29 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 28. " [28] ,Frame transfer complete interrupt of channel 28 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Frame transfer complete interrupt of channel 27 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 26. " [26] ,Frame transfer complete interrupt of channel 26 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 25. " [25] ,Frame transfer complete interrupt of channel 25 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 24. " [24] ,Frame transfer complete interrupt of channel 24 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Frame transfer complete interrupt of channel 23 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 22. " [22] ,Frame transfer complete interrupt of channel 22 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 21. " [21] ,Frame transfer complete interrupt of channel 21 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 20. " [20] ,Frame transfer complete interrupt of channel 20 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Frame transfer complete interrupt of channel 19 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 18. " [18] ,Frame transfer complete interrupt of channel 18 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 17. " [17] ,Frame transfer complete interrupt of channel 17 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 16. " [16] ,Frame transfer complete interrupt of channel 16 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Frame transfer complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Frame transfer complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Frame transfer complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Frame transfer complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " FTCAB[15] ,Frame transfer complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Frame transfer complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Frame transfer complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Frame transfer complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Frame transfer complete interrupt of channel 11 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 10. " [10] ,Frame transfer complete interrupt of channel 10 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 9. " [9] ,Frame transfer complete interrupt of channel 9 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 8. " [8] ,Frame transfer complete interrupt of channel 8 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Frame transfer complete interrupt of channel 7 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 6. " [6] ,Frame transfer complete interrupt of channel 6 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 5. " [5] ,Frame transfer complete interrupt of channel 5 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 4. " [4] ,Frame transfer complete interrupt of channel 4 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Frame transfer complete interrupt of channel 3 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 2. " [2] ,Frame transfer complete interrupt of channel 2 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 1. " [1] ,Frame transfer complete interrupt of channel 1 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 0. " [0] ,Frame transfer complete interrupt of channel 0 to group A/B" "Group A,Group B"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "LFSMAP,LFS Interrupt Mapping Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " LFSAB[31] ,Last frame started interrupt of channel 31 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 30. " [30] ,Last frame started interrupt of channel 30 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 29. " [29] ,Last frame started interrupt of channel 29 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 28. " [28] ,Last frame started interrupt of channel 28 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Last frame started interrupt of channel 27 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 26. " [26] ,Last frame started interrupt of channel 26 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 25. " [25] ,Last frame started interrupt of channel 25 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 24. " [24] ,Last frame started interrupt of channel 24 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Last frame started interrupt of channel 23 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 22. " [22] ,Last frame started interrupt of channel 22 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 21. " [21] ,Last frame started interrupt of channel 21 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 20. " [20] ,Last frame started interrupt of channel 20 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Last frame started interrupt of channel 19 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 18. " [18] ,Last frame started interrupt of channel 18 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 17. " [17] ,Last frame started interrupt of channel 17 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 16. " [16] ,Last frame started interrupt of channel 16 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Last frame started interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Last frame started interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Last frame started interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Last frame started interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " LFSAB[15] ,Last frame started interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Last frame started interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Last frame started interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Last frame started interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Last frame started interrupt of channel 11 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 10. " [10] ,Last frame started interrupt of channel 10 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 9. " [9] ,Last frame started interrupt of channel 9 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 8. " [8] ,Last frame started interrupt of channel 8 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Last frame started interrupt of channel 7 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 6. " [6] ,Last frame started interrupt of channel 6 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 5. " [5] ,Last frame started interrupt of channel 5 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 4. " [4] ,Last frame started interrupt of channel 4 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Last frame started interrupt of channel 3 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 2. " [2] ,Last frame started interrupt of channel 2 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 1. " [1] ,Last frame started interrupt of channel 1 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 0. " [0] ,Last frame started interrupt of channel 0 to group A/B" "Group A,Group B"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "HBCMAP,HBC Interrupt Mapping Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " HBCAB[31] ,Half block complete interrupt of channel 31 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 30. " [30] ,Half block complete interrupt of channel 30 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 29. " [29] ,Half block complete interrupt of channel 29 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 28. " [28] ,Half block complete interrupt of channel 28 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Half block complete interrupt of channel 27 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 26. " [26] ,Half block complete interrupt of channel 26 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 25. " [25] ,Half block complete interrupt of channel 25 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 24. " [24] ,Half block complete interrupt of channel 24 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Half block complete interrupt of channel 23 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 22. " [22] ,Half block complete interrupt of channel 22 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 21. " [21] ,Half block complete interrupt of channel 21 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 20. " [20] ,Half block complete interrupt of channel 20 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Half block complete interrupt of channel 19 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 18. " [18] ,Half block complete interrupt of channel 18 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 17. " [17] ,Half block complete interrupt of channel 17 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 16. " [16] ,Half block complete interrupt of channel 16 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Half block complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Half block complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Half block complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Half block complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " HBCAB[15] ,Half block complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Half block complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Half block complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Half block complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Half block complete interrupt of channel 11 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 10. " [10] ,Half block complete interrupt of channel 10 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 9. " [9] ,Half block complete interrupt of channel 9 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 8. " [8] ,Half block complete interrupt of channel 8 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Half block complete interrupt of channel 7 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 6. " [6] ,Half block complete interrupt of channel 6 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 5. " [5] ,Half block complete interrupt of channel 5 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 4. " [4] ,Half block complete interrupt of channel 4 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Half block complete interrupt of channel 3 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 2. " [2] ,Half block complete interrupt of channel 2 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 1. " [1] ,Half block complete interrupt of channel 1 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 0. " [0] ,Half block complete interrupt of channel 0 to group A/B" "Group A,Group B"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "BTCMAP,BTC Interrupt Mapping Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " BTCAB[31] ,Block transfer complete interrupt of channel 31 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 30. " [30] ,Block transfer complete interrupt of channel 30 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 29. " [29] ,Block transfer complete interrupt of channel 29 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 28. " [28] ,Block transfer complete interrupt of channel 28 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Block transfer complete interrupt of channel 27 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 26. " [26] ,Block transfer complete interrupt of channel 26 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 25. " [25] ,Block transfer complete interrupt of channel 25 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 24. " [24] ,Block transfer complete interrupt of channel 24 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Block transfer complete interrupt of channel 23 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 22. " [22] ,Block transfer complete interrupt of channel 22 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 21. " [21] ,Block transfer complete interrupt of channel 21 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 20. " [20] ,Block transfer complete interrupt of channel 20 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Block transfer complete interrupt of channel 19 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 18. " [18] ,Block transfer complete interrupt of channel 18 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 17. " [17] ,Block transfer complete interrupt of channel 17 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 16. " [16] ,Block transfer complete interrupt of channel 16 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Block transfer complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Block transfer complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Block transfer complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Block transfer complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " BTCAB[15] ,Block transfer complete interrupt of channel 15 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 14. " [14] ,Block transfer complete interrupt of channel 14 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 13. " [13] ,Block transfer complete interrupt of channel 13 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 12. " [12] ,Block transfer complete interrupt of channel 12 to group A/B" "Group A,Group B"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Block transfer complete interrupt of channel 11 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 10. " [10] ,Block transfer complete interrupt of channel 10 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 9. " [9] ,Block transfer complete interrupt of channel 9 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 8. " [8] ,Block transfer complete interrupt of channel 8 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Block transfer complete interrupt of channel 7 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 6. " [6] ,Block transfer complete interrupt of channel 6 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 5. " [5] ,Block transfer complete interrupt of channel 5 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 4. " [4] ,Block transfer complete interrupt of channel 4 to group A/B" "Group A,Group B"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Block transfer complete interrupt of channel 3 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 2. " [2] ,Block transfer complete interrupt of channel 2 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 1. " [1] ,Block transfer complete interrupt of channel 1 to group A/B" "Group A,Group B"
|
|
bitfld.long 0x00 0. " [0] ,Block transfer complete interrupt of channel 0 to group A/B" "Group A,Group B"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "BERMAP,BER Interrupt Mapping Register"
|
|
bitfld.long 0x00 31. " BERAB[31] ,Bus error interrupt of channel 31 to group A/B" "A,B"
|
|
bitfld.long 0x00 30. " [30] ,Bus error interrupt of channel 30 to group A/B" "A,B"
|
|
bitfld.long 0x00 29. " [29] ,Bus error interrupt of channel 29 to group A/B" "A,B"
|
|
bitfld.long 0x00 28. " [28] ,Bus error interrupt of channel 28 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Bus error interrupt of channel 27 to group A/B" "A,B"
|
|
bitfld.long 0x00 26. " [26] ,Bus error interrupt of channel 26 to group A/B" "A,B"
|
|
bitfld.long 0x00 25. " [25] ,Bus error interrupt of channel 25 to group A/B" "A,B"
|
|
bitfld.long 0x00 24. " [24] ,Bus error interrupt of channel 24 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Bus error interrupt of channel 23 to group A/B" "A,B"
|
|
bitfld.long 0x00 22. " [22] ,Bus error interrupt of channel 22 to group A/B" "A,B"
|
|
bitfld.long 0x00 21. " [21] ,Bus error interrupt of channel 21 to group A/B" "A,B"
|
|
bitfld.long 0x00 20. " [20] ,Bus error interrupt of channel 20 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Bus error interrupt of channel 19 to group A/B" "A,B"
|
|
bitfld.long 0x00 18. " [18] ,Bus error interrupt of channel 18 to group A/B" "A,B"
|
|
bitfld.long 0x00 17. " [17] ,Bus error interrupt of channel 17 to group A/B" "A,B"
|
|
bitfld.long 0x00 16. " [16] ,Bus error interrupt of channel 16 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Bus error interrupt of channel 15 to group A/B" "A,B"
|
|
bitfld.long 0x00 14. " [14] ,Bus error interrupt of channel 14 to group A/B" "A,B"
|
|
bitfld.long 0x00 13. " [13] ,Bus error interrupt of channel 13 to group A/B" "A,B"
|
|
bitfld.long 0x00 12. " [12] ,Bus error interrupt of channel 12 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Bus error interrupt of channel 11 to group A/B" "A,B"
|
|
bitfld.long 0x00 10. " [10] ,Bus error interrupt of channel 10 to group A/B" "A,B"
|
|
bitfld.long 0x00 9. " [9] ,Bus error interrupt of channel 9 to group A/B" "A,B"
|
|
bitfld.long 0x00 8. " [8] ,Bus error interrupt of channel 8 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Bus error interrupt of channel 7 to group A/B" "A,B"
|
|
bitfld.long 0x00 6. " [6] ,Bus error interrupt of channel 6 to group A/B" "A,B"
|
|
bitfld.long 0x00 5. " [5] ,Bus error interrupt of channel 5 to group A/B" "A,B"
|
|
bitfld.long 0x00 4. " [4] ,Bus error interrupt of channel 4 to group A/B" "A,B"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Bus error interrupt of channel 3 to group A/B" "A,B"
|
|
bitfld.long 0x00 2. " [2] ,Bus error interrupt of channel 2 to group A/B" "A,B"
|
|
bitfld.long 0x00 1. " [1] ,Bus error interrupt of channel 1 to group A/B" "A,B"
|
|
bitfld.long 0x00 0. " [0] ,Bus error interrupt of channel 0 to group A/B" "A,B"
|
|
endif
|
|
tree.end
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "FTCINTENAS,FTC Interrupt Enable Set Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " FTCINTENA[31] ,FTC (frame transfer complete) interrupt enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,FTC (frame transfer complete) interrupt enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,FTC (frame transfer complete) interrupt enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,FTC (frame transfer complete) interrupt enable 28" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,FTC (frame transfer complete) interrupt enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,FTC (frame transfer complete) interrupt enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,FTC (frame transfer complete) interrupt enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,FTC (frame transfer complete) interrupt enable 24" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,FTC (frame transfer complete) interrupt enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,FTC (frame transfer complete) interrupt enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,FTC (frame transfer complete) interrupt enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,FTC (frame transfer complete) interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,FTC (frame transfer complete) interrupt enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,FTC (frame transfer complete) interrupt enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,FTC (frame transfer complete) interrupt enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,FTC (frame transfer complete) interrupt enable 16" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,FTC (frame transfer complete) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,FTC (frame transfer complete) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,FTC (frame transfer complete) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,FTC (frame transfer complete) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " FTCINTENA[15] ,FTC (frame transfer complete) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,FTC (frame transfer complete) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,FTC (frame transfer complete) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,FTC (frame transfer complete) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,FTC (frame transfer complete) interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,FTC (frame transfer complete) interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,FTC (frame transfer complete) interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,FTC (frame transfer complete) interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,FTC (frame transfer complete) interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,FTC (frame transfer complete) interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,FTC (frame transfer complete) interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,FTC (frame transfer complete) interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,FTC (frame transfer complete) interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,FTC (frame transfer complete) interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,FTC (frame transfer complete) interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,FTC (frame transfer complete) interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "FTCINTENAR,FTC Interrupt Enable Reset Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " FTCINTDIS[31] ,FTC (frame transfer complete) interrupt disable 31" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,FTC (frame transfer complete) interrupt disable 30" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,FTC (frame transfer complete) interrupt disable 29" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,FTC (frame transfer complete) interrupt disable 28" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,FTC (frame transfer complete) interrupt disable 27" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,FTC (frame transfer complete) interrupt disable 26" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,FTC (frame transfer complete) interrupt disable 25" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,FTC (frame transfer complete) interrupt disable 24" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,FTC (frame transfer complete) interrupt disable 23" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,FTC (frame transfer complete) interrupt disable 22" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,FTC (frame transfer complete) interrupt disable 21" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,FTC (frame transfer complete) interrupt disable 20" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,FTC (frame transfer complete) interrupt disable 19" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,FTC (frame transfer complete) interrupt disable 18" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,FTC (frame transfer complete) interrupt disable 17" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,FTC (frame transfer complete) interrupt disable 16" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,FTC (frame transfer complete) interrupt disable 15" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,FTC (frame transfer complete) interrupt disable 14" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,FTC (frame transfer complete) interrupt disable 13" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,FTC (frame transfer complete) interrupt disable 12" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,FTC (frame transfer complete) interrupt disable 11" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,FTC (frame transfer complete) interrupt disable 10" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,FTC (frame transfer complete) interrupt disable 9" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,FTC (frame transfer complete) interrupt disable 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,FTC (frame transfer complete) interrupt disable 7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,FTC (frame transfer complete) interrupt disable 6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,FTC (frame transfer complete) interrupt disable 5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,FTC (frame transfer complete) interrupt disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,FTC (frame transfer complete) interrupt disable 3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,FTC (frame transfer complete) interrupt disable 2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,FTC (frame transfer complete) interrupt disable 1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,FTC (frame transfer complete) interrupt disable 0" "No,Yes"
|
|
else
|
|
eventfld.long 0x00 15. " FTCINTDIS[15] ,FTC (frame transfer complete) interrupt disable 15" "No,Yes"
|
|
eventfld.long 0x00 14. " [14] ,FTC (frame transfer complete) interrupt disable 14" "No,Yes"
|
|
eventfld.long 0x00 13. " [13] ,FTC (frame transfer complete) interrupt disable 13" "No,Yes"
|
|
eventfld.long 0x00 12. " [12] ,FTC (frame transfer complete) interrupt disable 12" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,FTC (frame transfer complete) interrupt disable 11" "No,Yes"
|
|
eventfld.long 0x00 10. " [10] ,FTC (frame transfer complete) interrupt disable 10" "No,Yes"
|
|
eventfld.long 0x00 9. " [9] ,FTC (frame transfer complete) interrupt disable 9" "No,Yes"
|
|
eventfld.long 0x00 8. " [8] ,FTC (frame transfer complete) interrupt disable 8" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,FTC (frame transfer complete) interrupt disable 7" "No,Yes"
|
|
eventfld.long 0x00 6. " [6] ,FTC (frame transfer complete) interrupt disable 6" "No,Yes"
|
|
eventfld.long 0x00 5. " [5] ,FTC (frame transfer complete) interrupt disable 5" "No,Yes"
|
|
eventfld.long 0x00 4. " [4] ,FTC (frame transfer complete) interrupt disable 4" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,FTC (frame transfer complete) interrupt disable 3" "No,Yes"
|
|
eventfld.long 0x00 2. " [2] ,FTC (frame transfer complete) interrupt disable 2" "No,Yes"
|
|
eventfld.long 0x00 1. " [1] ,FTC (frame transfer complete) interrupt disable 1" "No,Yes"
|
|
eventfld.long 0x00 0. " [0] ,FTC (frame transfer complete) interrupt disable 0" "No,Yes"
|
|
endif
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "LFSINTENAS,LFS Interrupt Enable Set Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " LFSINTENA[31] ,LFS (last frame started) interrupt enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,LFS (last frame started) interrupt enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,LFS (last frame started) interrupt enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,LFS (last frame started) interrupt enable 28" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,LFS (last frame started) interrupt enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,LFS (last frame started) interrupt enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,LFS (last frame started) interrupt enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,LFS (last frame started) interrupt enable 24" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,LFS (last frame started) interrupt enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,LFS (last frame started) interrupt enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,LFS (last frame started) interrupt enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,LFS (last frame started) interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,LFS (last frame started) interrupt enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,LFS (last frame started) interrupt enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,LFS (last frame started) interrupt enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,LFS (last frame started) interrupt enable 16" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,LFS (last frame started) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,LFS (last frame started) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,LFS (last frame started) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,LFS (last frame started) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " LFSINTENA[15] ,LFS (last frame started) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,LFS (last frame started) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,LFS (last frame started) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,LFS (last frame started) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,LFS (last frame started) interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,LFS (last frame started) interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,LFS (last frame started) interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,LFS (last frame started) interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,LFS (last frame started) interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,LFS (last frame started) interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,LFS (last frame started) interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,LFS (last frame started) interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,LFS (last frame started) interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,LFS (last frame started) interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,LFS (last frame started) interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,LFS (last frame started) interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "LFSINTENAR,LFS Interrupt Enable Reset Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " LFSINTDIS[31] ,LFS (last frame started) interrupt disable 31" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,LFS (last frame started) interrupt disable 30" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,LFS (last frame started) interrupt disable 29" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,LFS (last frame started) interrupt disable 28" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,LFS (last frame started) interrupt disable 27" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,LFS (last frame started) interrupt disable 26" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,LFS (last frame started) interrupt disable 25" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,LFS (last frame started) interrupt disable 24" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,LFS (last frame started) interrupt disable 23" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,LFS (last frame started) interrupt disable 22" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,LFS (last frame started) interrupt disable 21" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,LFS (last frame started) interrupt disable 20" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,LFS (last frame started) interrupt disable 19" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,LFS (last frame started) interrupt disable 18" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,LFS (last frame started) interrupt disable 17" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,LFS (last frame started) interrupt disable 16" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,LFS (last frame started) interrupt disable 15" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,LFS (last frame started) interrupt disable 14" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,LFS (last frame started) interrupt disable 13" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,LFS (last frame started) interrupt disable 12" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,LFS (last frame started) interrupt disable 11" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,LFS (last frame started) interrupt disable 10" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,LFS (last frame started) interrupt disable 9" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,LFS (last frame started) interrupt disable 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,LFS (last frame started) interrupt disable 7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,LFS (last frame started) interrupt disable 6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,LFS (last frame started) interrupt disable 5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,LFS (last frame started) interrupt disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,LFS (last frame started) interrupt disable 3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,LFS (last frame started) interrupt disable 2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,LFS (last frame started) interrupt disable 1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,LFS (last frame started) interrupt disable 0" "No,Yes"
|
|
else
|
|
eventfld.long 0x00 15. " LFSINTDIS[15] ,LFS (last frame started) interrupt disable 15" "No,Yes"
|
|
eventfld.long 0x00 14. " [14] ,LFS (last frame started) interrupt disable 14" "No,Yes"
|
|
eventfld.long 0x00 13. " [13] ,LFS (last frame started) interrupt disable 13" "No,Yes"
|
|
eventfld.long 0x00 12. " [12] ,LFS (last frame started) interrupt disable 12" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,LFS (last frame started) interrupt disable 11" "No,Yes"
|
|
eventfld.long 0x00 10. " [10] ,LFS (last frame started) interrupt disable 10" "No,Yes"
|
|
eventfld.long 0x00 9. " [9] ,LFS (last frame started) interrupt disable 9" "No,Yes"
|
|
eventfld.long 0x00 8. " [8] ,LFS (last frame started) interrupt disable 8" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,LFS (last frame started) interrupt disable 7" "No,Yes"
|
|
eventfld.long 0x00 6. " [6] ,LFS (last frame started) interrupt disable 6" "No,Yes"
|
|
eventfld.long 0x00 5. " [5] ,LFS (last frame started) interrupt disable 5" "No,Yes"
|
|
eventfld.long 0x00 4. " [4] ,LFS (last frame started) interrupt disable 4" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,LFS (last frame started) interrupt disable 3" "No,Yes"
|
|
eventfld.long 0x00 2. " [2] ,LFS (last frame started) interrupt disable 2" "No,Yes"
|
|
eventfld.long 0x00 1. " [1] ,LFS (last frame started) interrupt disable 1" "No,Yes"
|
|
eventfld.long 0x00 0. " [0] ,LFS (last frame started) interrupt disable 0" "No,Yes"
|
|
endif
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "HBCINTENAS,HBC Interrupt Enable Set Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " HBCINTENA[31] ,HBC (half block complete) interrupt enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,HBC (half block complete) interrupt enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,HBC (half block complete) interrupt enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,HBC (half block complete) interrupt enable 28" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,HBC (half block complete) interrupt enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,HBC (half block complete) interrupt enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,HBC (half block complete) interrupt enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,HBC (half block complete) interrupt enable 24" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,HBC (half block complete) interrupt enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,HBC (half block complete) interrupt enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,HBC (half block complete) interrupt enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,HBC (half block complete) interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,HBC (half block complete) interrupt enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,HBC (half block complete) interrupt enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,HBC (half block complete) interrupt enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,HBC (half block complete) interrupt enable 16" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,HBC (half block complete) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,HBC (half block complete) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,HBC (half block complete) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,HBC (half block complete) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " HBCINTENA[15] ,HBC (half block complete) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,HBC (half block complete) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,HBC (half block complete) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,HBC (half block complete) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,HBC (half block complete) interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,HBC (half block complete) interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,HBC (half block complete) interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,HBC (half block complete) interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,HBC (half block complete) interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,HBC (half block complete) interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,HBC (half block complete) interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,HBC (half block complete) interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,HBC (half block complete) interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,HBC (half block complete) interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,HBC (half block complete) interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,HBC (half block complete) interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "HBCINTENAR,HBC Interrupt Enable Reset Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " HBCINTENA[31] ,HBC (half block complete) interrupt disable 31" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,HBC (half block complete) interrupt disable 30" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,HBC (half block complete) interrupt disable 29" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,HBC (half block complete) interrupt disable 28" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,HBC (half block complete) interrupt disable 27" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,HBC (half block complete) interrupt disable 26" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,HBC (half block complete) interrupt disable 25" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,HBC (half block complete) interrupt disable 24" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,HBC (half block complete) interrupt disable 23" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,HBC (half block complete) interrupt disable 22" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,HBC (half block complete) interrupt disable 21" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,HBC (half block complete) interrupt disable 20" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,HBC (half block complete) interrupt disable 19" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,HBC (half block complete) interrupt disable 18" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,HBC (half block complete) interrupt disable 17" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,HBC (half block complete) interrupt disable 16" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,HBC (half block complete) interrupt disable 15" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,HBC (half block complete) interrupt disable 14" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,HBC (half block complete) interrupt disable 13" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,HBC (half block complete) interrupt disable 12" "No,Yes"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " HBCINTENA[15] ,HBC (half block complete) interrupt disable 15" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,HBC (half block complete) interrupt disable 14" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,HBC (half block complete) interrupt disable 13" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,HBC (half block complete) interrupt disable 12" "No,Yes"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,HBC (half block complete) interrupt disable 11" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,HBC (half block complete) interrupt disable 10" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,HBC (half block complete) interrupt disable 9" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,HBC (half block complete) interrupt disable 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,HBC (half block complete) interrupt disable 7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,HBC (half block complete) interrupt disable 6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,HBC (half block complete) interrupt disable 5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,HBC (half block complete) interrupt disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,HBC (half block complete) interrupt disable 3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,HBC (half block complete) interrupt disable 2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,HBC (half block complete) interrupt disable 1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,HBC (half block complete) interrupt disable 0" "No,Yes"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "BTCINTENAS,BTC Interrupt Enable Set Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " BTCINTENA[31] ,BTC (block transfer complete) interrupt enable 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,BTC (block transfer complete) interrupt enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,BTC (block transfer complete) interrupt enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,BTC (block transfer complete) interrupt enable 28" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,BTC (block transfer complete) interrupt enable 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,BTC (block transfer complete) interrupt enable 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,BTC (block transfer complete) interrupt enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,BTC (block transfer complete) interrupt enable 24" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,BTC (block transfer complete) interrupt enable 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,BTC (block transfer complete) interrupt enable 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,BTC (block transfer complete) interrupt enable 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,BTC (block transfer complete) interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,BTC (block transfer complete) interrupt enable 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,BTC (block transfer complete) interrupt enable 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,BTC (block transfer complete) interrupt enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,BTC (block transfer complete) interrupt enable 16" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,BTC (block transfer complete) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,BTC (block transfer complete) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,BTC (block transfer complete) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,BTC (block transfer complete) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " BTCINTENA[15] ,BTC (block transfer complete) interrupt enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,BTC (block transfer complete) interrupt enable 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,BTC (block transfer complete) interrupt enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,BTC (block transfer complete) interrupt enable 12" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,BTC (block transfer complete) interrupt enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,BTC (block transfer complete) interrupt enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,BTC (block transfer complete) interrupt enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,BTC (block transfer complete) interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,BTC (block transfer complete) interrupt enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,BTC (block transfer complete) interrupt enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,BTC (block transfer complete) interrupt enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,BTC (block transfer complete) interrupt enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,BTC (block transfer complete) interrupt enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,BTC (block transfer complete) interrupt enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,BTC (block transfer complete) interrupt enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,BTC (block transfer complete) interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "BTCINTENAR,BTC Interrupt Enable Reset Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " BTCINTENA[31] ,BTC (block transfer complete) interrupt disable 31" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,BTC (block transfer complete) interrupt disable 30" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,BTC (block transfer complete) interrupt disable 29" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,BTC (block transfer complete) interrupt disable 28" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,BTC (block transfer complete) interrupt disable 27" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,BTC (block transfer complete) interrupt disable 26" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,BTC (block transfer complete) interrupt disable 25" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,BTC (block transfer complete) interrupt disable 24" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,BTC (block transfer complete) interrupt disable 23" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,BTC (block transfer complete) interrupt disable 22" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,BTC (block transfer complete) interrupt disable 21" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,BTC (block transfer complete) interrupt disable 20" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,BTC (block transfer complete) interrupt disable 19" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,BTC (block transfer complete) interrupt disable 18" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,BTC (block transfer complete) interrupt disable 17" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,BTC (block transfer complete) interrupt disable 16" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,BTC (block transfer complete) interrupt disable 15" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,BTC (block transfer complete) interrupt disable 14" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,BTC (block transfer complete) interrupt disable 13" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,BTC (block transfer complete) interrupt disable 12" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,BTC (block transfer complete) interrupt disable 11" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,BTC (block transfer complete) interrupt disable 10" "No,Yes"
|
|
bitfld.long 0x00 9. " [9] ,BTC (block transfer complete) interrupt disable 9" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,BTC (block transfer complete) interrupt disable 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,BTC (block transfer complete) interrupt disable 7" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,BTC (block transfer complete) interrupt disable 6" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,BTC (block transfer complete) interrupt disable 5" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,BTC (block transfer complete) interrupt disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,BTC (block transfer complete) interrupt disable 3" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,BTC (block transfer complete) interrupt disable 2" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,BTC (block transfer complete) interrupt disable 1" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,BTC (block transfer complete) interrupt disable 0" "No,Yes"
|
|
else
|
|
eventfld.long 0x00 15. " BTCINTENA[15] ,BTC (block transfer complete) interrupt disable 15" "No,Yes"
|
|
eventfld.long 0x00 14. " [14] ,BTC (block transfer complete) interrupt disable 14" "No,Yes"
|
|
eventfld.long 0x00 13. " [13] ,BTC (block transfer complete) interrupt disable 13" "No,Yes"
|
|
eventfld.long 0x00 12. " [12] ,BTC (block transfer complete) interrupt disable 12" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,BTC (block transfer complete) interrupt disable 11" "No,Yes"
|
|
eventfld.long 0x00 10. " [10] ,BTC (block transfer complete) interrupt disable 10" "No,Yes"
|
|
eventfld.long 0x00 9. " [9] ,BTC (block transfer complete) interrupt disable 9" "No,Yes"
|
|
eventfld.long 0x00 8. " [8] ,BTC (block transfer complete) interrupt disable 8" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,BTC (block transfer complete) interrupt disable 7" "No,Yes"
|
|
eventfld.long 0x00 6. " [6] ,BTC (block transfer complete) interrupt disable 6" "No,Yes"
|
|
eventfld.long 0x00 5. " [5] ,BTC (block transfer complete) interrupt disable 5" "No,Yes"
|
|
eventfld.long 0x00 4. " [4] ,BTC (block transfer complete) interrupt disable 4" "No,Yes"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,BTC (block transfer complete) interrupt disable 3" "No,Yes"
|
|
eventfld.long 0x00 2. " [2] ,BTC (block transfer complete) interrupt disable 2" "No,Yes"
|
|
eventfld.long 0x00 1. " [1] ,BTC (block transfer complete) interrupt disable 1" "No,Yes"
|
|
eventfld.long 0x00 0. " [0] ,BTC (block transfer complete) interrupt disable 0" "No,Yes"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Flag Registers"
|
|
width 10.
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "GINTFLAG,Global Interrupt Flag Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 31. " GINT[31] ,Global interrupt flag for channel 31" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " [30] ,Global interrupt flag for channel 30" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " [29] ,Global interrupt flag for channel 29" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " [28] ,Global interrupt flag for channel 28" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Global interrupt flag for channel 27" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " [26] ,Global interrupt flag for channel 26" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " [25] ,Global interrupt flag for channel 25" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " [24] ,Global interrupt flag for channel 24" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Global interrupt flag for channel 23" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " [22] ,Global interrupt flag for channel 22" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " [21] ,Global interrupt flag for channel 21" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " [20] ,Global interrupt flag for channel 20" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Global interrupt flag for channel 19" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " [18] ,Global interrupt flag for channel 18" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " [17] ,Global interrupt flag for channel 17" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " [16] ,Global interrupt flag for channel 16" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Global interrupt flag for channel 15" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Global interrupt flag for channel 14" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Global interrupt flag for channel 13" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Global interrupt flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 15. " GINT[15] ,Global interrupt flag for channel 15" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Global interrupt flag for channel 14" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Global interrupt flag for channel 13" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Global interrupt flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " [11] ,Global interrupt flag for channel 11" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Global interrupt flag for channel 10" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Global interrupt flag for channel 9" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " [8] ,Global interrupt flag for channel 8" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Global interrupt flag for channel 7" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " [6] ,Global interrupt flag for channel 6" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " [5] ,Global interrupt flag for channel 5" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Global interrupt flag for channel 4" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Global interrupt flag for channel 3" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " [2] ,Global interrupt flag for channel 2" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " [1] ,Global interrupt flag for channel 1" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Global interrupt flag for channel 0" "Not pending,Pending"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "FTCFLAG,FTC Interrupt Flag Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
eventfld.long 0x00 31. " FTCI[31] ,Frame transfer complete flag for channel 31" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " [30] ,Frame transfer complete flag for channel 30" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " [29] ,Frame transfer complete flag for channel 29" "Not pending,Pending"
|
|
eventfld.long 0x00 28. " [28] ,Frame transfer complete flag for channel 28" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Frame transfer complete flag for channel 27" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " [26] ,Frame transfer complete flag for channel 26" "Not pending,Pending"
|
|
eventfld.long 0x00 25. " [25] ,Frame transfer complete flag for channel 25" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " [24] ,Frame transfer complete flag for channel 24" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Frame transfer complete flag for channel 23" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " [22] ,Frame transfer complete flag for channel 22" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " [21] ,Frame transfer complete flag for channel 21" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " [20] ,Frame transfer complete flag for channel 20" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Frame transfer complete flag for channel 19" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " [18] ,Frame transfer complete flag for channel 18" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " [17] ,Frame transfer complete flag for channel 17" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " [16] ,Frame transfer complete flag for channel 16" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Frame transfer complete flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Frame transfer complete flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Frame transfer complete flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Frame transfer complete flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
else
|
|
eventfld.long 0x00 15. " FTCI[15] ,Frame transfer complete flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Frame transfer complete flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Frame transfer complete flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Frame transfer complete flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 11. " [11] ,Frame transfer complete flag for channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " [10] ,Frame transfer complete flag for channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " [9] ,Frame transfer complete flag for channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " [8] ,Frame transfer complete flag for channel 8" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Frame transfer complete flag for channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Frame transfer complete flag for channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Frame transfer complete flag for channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " [4] ,Frame transfer complete flag for channel 4" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Frame transfer complete flag for channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Frame transfer complete flag for channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " [1] ,Frame transfer complete flag for channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Frame transfer complete flag for channel 0" "Not pending,Pending"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "LFSFLAG,LFS Interrupt Flag Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
eventfld.long 0x00 31. " LFSI[31] ,Last frame transfer started flag for channel 31" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " [30] ,Last frame transfer started flag for channel 30" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " [29] ,Last frame transfer started flag for channel 29" "Not pending,Pending"
|
|
eventfld.long 0x00 28. " [28] ,Last frame transfer started flag for channel 28" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Last frame transfer started flag for channel 27" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " [26] ,Last frame transfer started flag for channel 26" "Not pending,Pending"
|
|
eventfld.long 0x00 25. " [25] ,Last frame transfer started flag for channel 25" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " [24] ,Last frame transfer started flag for channel 24" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Last frame transfer started flag for channel 23" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " [22] ,Last frame transfer started flag for channel 22" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " [21] ,Last frame transfer started flag for channel 21" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " [20] ,Last frame transfer started flag for channel 20" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Last frame transfer started flag for channel 19" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " [18] ,Last frame transfer started flag for channel 18" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " [17] ,Last frame transfer started flag for channel 17" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " [16] ,Last frame transfer started flag for channel 16" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Last frame transfer started flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Last frame transfer started flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Last frame transfer started flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Last frame transfer started flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
else
|
|
eventfld.long 0x00 15. " LFSI[15] ,Last frame transfer started flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Last frame transfer started flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Last frame transfer started flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Last frame transfer started flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 11. " [11] ,Last frame transfer started flag for channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " [10] ,Last frame transfer started flag for channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " [9] ,Last frame transfer started flag for channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " [8] ,Last frame transfer started flag for channel 8" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Last frame transfer started flag for channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Last frame transfer started flag for channel for channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Last frame transfer started flag for channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " [4] ,Last frame transfer started flag for channel 4" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Last frame transfer started flag for channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Last frame transfer started flag for channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " [1] ,Last frame transfer started flag for channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Last frame transfer started flag for channel 0" "Not pending,Pending"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "HBCFLAG,HBC Interrupt Flag Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
eventfld.long 0x00 31. " HBCI[31] ,Half of block transfer complete flag for channel 31" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " [30] ,Half of block transfer complete flag for channel 30" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " [29] ,Half of block transfer complete flag for channel 29" "Not pending,Pending"
|
|
eventfld.long 0x00 28. " [28] ,Half of block transfer complete flag for channel 28" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Half of block transfer complete flag for channel 27" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " [26] ,Half of block transfer complete flag for channel 26" "Not pending,Pending"
|
|
eventfld.long 0x00 25. " [25] ,Half of block transfer complete flag for channel 25" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " [24] ,Half of block transfer complete flag for channel 24" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Half of block transfer complete flag for channel 23" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " [22] ,Half of block transfer complete flag for channel 22" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " [21] ,Half of block transfer complete flag for channel 21" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " [20] ,Half of block transfer complete flag for channel 20" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Half of block transfer complete flag for channel 19" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " [18] ,Half of block transfer complete flag for channel 18" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " [17] ,Half of block transfer complete flag for channel 17" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " [16] ,Half of block transfer complete flag for channel 16" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Half of block transfer complete flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Half of block transfer complete flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Half of block transfer complete flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Half of block transfer complete flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
else
|
|
eventfld.long 0x00 15. " HBCI[15] ,Half of block transfer complete flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Half of block transfer complete flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Half of block transfer complete flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Half of block transfer complete flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 11. " [11] ,Half of block transfer complete flag for channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " [10] ,Half of block transfer complete flag for channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " [9] ,Half of block transfer complete flag for channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " [8] ,Half of block transfer complete flag for channel 8" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Half of block transfer complete flag for channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Half of block transfer complete flag for channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Half of block transfer complete flag for channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " [4] ,Half of block transfer complete flag for channel 4" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Half of block transfer complete flag for channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Half of block transfer complete flag for channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " [1] ,Half of block transfer complete flag for channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Half of block transfer complete flag for channel 0" "Not pending,Pending"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "BTCFLAG,BER Interrupt Flag Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
eventfld.long 0x00 31. " BTCI[31] ,Block transfer complete flag for channel 31" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " [30] ,Block transfer complete flag for channel 30" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " [29] ,Block transfer complete flag for channel 29" "Not pending,Pending"
|
|
eventfld.long 0x00 28. " [28] ,Block transfer complete flag for channel 28" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Block transfer complete flag for channel 27" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " [26] ,Block transfer complete flag for channel 26" "Not pending,Pending"
|
|
eventfld.long 0x00 25. " [25] ,Block transfer complete flag for channel 25" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " [24] ,Block transfer complete flag for channel 24" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Block transfer complete flag for channel 23" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " [22] ,Block transfer complete flag for channel 22" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " [21] ,Block transfer complete flag for channel 21" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " [20] ,Block transfer complete flag for channel 20" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Block transfer complete flag for channel 19" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " [18] ,Block transfer complete flag for channel 18" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " [17] ,Block transfer complete flag for channel 17" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " [16] ,Block transfer complete flag for channel 16" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Block transfer complete flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Block transfer complete flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Block transfer complete flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Block transfer complete flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
else
|
|
eventfld.long 0x00 15. " BTCI[15] ,Block transfer complete flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Block transfer complete flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Block transfer complete flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Block transfer complete flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 11. " [11] ,Block transfer complete flag for channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " [10] ,Block transfer complete flag for channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " [9] ,Block transfer complete flag for channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " [8] ,Block transfer complete flag for channel 8" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Block transfer complete flag for channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Block transfer complete flag for channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Block transfer complete flag for channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " [4] ,Block transfer complete flag for channel 4" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Block transfer complete flag for channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Block transfer complete flag for channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " [1] ,Block transfer complete flag for channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Block transfer complete flag for channel 0" "Not pending,Pending"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "BERFLAG,BER Interrupt Flag Register"
|
|
eventfld.long 0x00 31. " BERI[31] ,Bus error flag for channel 31" "Not pending,Pending"
|
|
eventfld.long 0x00 30. " [30] ,Bus error flag for channel 30" "Not pending,Pending"
|
|
eventfld.long 0x00 29. " [29] ,Bus error flag for channel 29" "Not pending,Pending"
|
|
eventfld.long 0x00 28. " [28] ,Bus error flag for channel 28" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Bus error flag for channel 27" "Not pending,Pending"
|
|
eventfld.long 0x00 26. " [26] ,Bus error flag for channel 26" "Not pending,Pending"
|
|
eventfld.long 0x00 25. " [25] ,Bus error flag for channel 25" "Not pending,Pending"
|
|
eventfld.long 0x00 24. " [24] ,Bus error flag for channel 24" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Bus error flag for channel 23" "Not pending,Pending"
|
|
eventfld.long 0x00 22. " [22] ,Bus error flag for channel 22" "Not pending,Pending"
|
|
eventfld.long 0x00 21. " [21] ,Bus error flag for channel 21" "Not pending,Pending"
|
|
eventfld.long 0x00 20. " [20] ,Bus error flag for channel 20" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Bus error flag for channel 19" "Not pending,Pending"
|
|
eventfld.long 0x00 18. " [18] ,Bus error flag for channel 18" "Not pending,Pending"
|
|
eventfld.long 0x00 17. " [17] ,Bus error flag for channel 17" "Not pending,Pending"
|
|
eventfld.long 0x00 16. " [16] ,Bus error flag for channel 16" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Bus error flag for channel 15" "Not pending,Pending"
|
|
eventfld.long 0x00 14. " [14] ,Bus error flag for channel 14" "Not pending,Pending"
|
|
eventfld.long 0x00 13. " [13] ,Bus error flag for channel 13" "Not pending,Pending"
|
|
eventfld.long 0x00 12. " [12] ,Bus error flag for channel 12" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Bus error flag for channel 11" "Not pending,Pending"
|
|
eventfld.long 0x00 10. " [10] ,Bus error flag for channel 10" "Not pending,Pending"
|
|
eventfld.long 0x00 9. " [9] ,Bus error flag for channel 9" "Not pending,Pending"
|
|
eventfld.long 0x00 8. " [8] ,Bus error flag for channel 8" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Bus error flag for channel 7" "Not pending,Pending"
|
|
eventfld.long 0x00 6. " [6] ,Bus error flag for channel 6" "Not pending,Pending"
|
|
eventfld.long 0x00 5. " [5] ,Bus error flag for channel 5" "Not pending,Pending"
|
|
eventfld.long 0x00 4. " [4] ,Bus error flag for channel 4" "Not pending,Pending"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,Bus error flag for channel 3" "Not pending,Pending"
|
|
eventfld.long 0x00 2. " [2] ,Bus error flag for channel 2" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " [1] ,Bus error flag for channel 1" "Not pending,Pending"
|
|
eventfld.long 0x00 0. " [0] ,Bus error flag for channel 0" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "BERFLAG,BER Interrupt Flag Register"
|
|
endif
|
|
tree.end
|
|
newline
|
|
width 12.
|
|
tree "Interrupt Channel Offset Registers"
|
|
hgroup.long 0x14C++0x03
|
|
hide.long 0x00 "FTCAOFFSET,FTCA Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x150++0x03
|
|
hide.long 0x00 "LFSAOFFSET,LFSA Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x154++0x03
|
|
hide.long 0x00 "HBCAOFFSET,HBCA Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x158++0x03
|
|
hide.long 0x00 "BTCAOFFSET,BTCA Interrupt Channel Offset Register"
|
|
in
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
hgroup.long 0x15C++0x03
|
|
hide.long 0x00 "BERAOFFSET,BERA Interrupt Channel Offset Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "FTCBOFFSET,FTCB Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x164++0x03
|
|
hide.long 0x00 "LFSBOFFSET,LFSB Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x168++0x03
|
|
hide.long 0x00 "HBCBOFFSET,HBCB Interrupt Channel Offset Register"
|
|
in
|
|
hgroup.long 0x16C++0x03
|
|
hide.long 0x00 "BTCBOFFSET,BTCB Interrupt Channel Offset Register"
|
|
in
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
hgroup.long 0x170++0x03
|
|
hide.long 0x00 "BERBOFFSET,BERB Interrupt Channel Offset Register"
|
|
in
|
|
endif
|
|
tree.end
|
|
newline
|
|
width 8.
|
|
group.long 0x178++0x13
|
|
line.long 0x00 "PTCRL,Port Control Register"
|
|
rbitfld.long 0x00 24. " PENDB ,Port B transactions pending" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " BYB ,Bypass FIFO B" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 17. " PSFRHQPB ,Port B high priority queue priority scheme" "Fixed,Rotated"
|
|
bitfld.long 0x00 16. " PSFRLQPB ,Port B low priority queue priority scheme" "Fixed,Rotated"
|
|
sif cpuis("AWR1443")||cpuis("AWR1443-CORE0")||cpuis("AWR1443-CORE1")||cpuis("AWR1843")||cpuis("AWR6843*")
|
|
newline
|
|
bitfld.long 0x00 8. " PENDA ,Port A transactions pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " BYA ,Bypass FIFO A" "Not limited,Limited"
|
|
bitfld.long 0x00 1. " PSFRHQPA ,Port A high priority queue priority scheme" "Fixed,Rotated"
|
|
bitfld.long 0x00 0. " PSFRLQPA ,Port A low priority queue priority scheme" "Fixed,Rotated"
|
|
endif
|
|
line.long 0x04 "RTCTRL,RAM Test Control Register"
|
|
bitfld.long 0x04 0. " RTC ,RAM test control" "Disabled,Enabled"
|
|
line.long 0x08 "DCTRL,Debug Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x08 24.--28. " CHNUM ,Channel number" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
else
|
|
rbitfld.long 0x08 24.--28. " CHNUM ,Channel number" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,Channel 18,Channel 19,Channel 20,Channel 21,Channel 22,Channel 23,Channel 24,Channel 25,Channel 26,Channel 27,Channel 28,Channel 29,Channel 30,Channel 31"
|
|
endif
|
|
eventfld.long 0x08 16. " DMADBGS ,DMA debug status" "Not detected,Detected"
|
|
bitfld.long 0x08 0. " DBGEN ,Debug enable" "Disabled,Enabled"
|
|
line.long 0x0C "WPR,Watch Point Register"
|
|
newline
|
|
line.long 0x10 "WMR,Watch Point Mask Register"
|
|
bitfld.long 0x10 31. " WM[31:0] ,Watch point bit 31 mask" "0,1"
|
|
bitfld.long 0x10 30. ",Watch point bit 30 mask" "0,1"
|
|
bitfld.long 0x10 29. ",Watch point bit 29 mask" "0,1"
|
|
bitfld.long 0x10 28. ",Watch point bit 28 mask" "0,1"
|
|
bitfld.long 0x10 27. ",Watch point bit 27 mask" "0,1"
|
|
bitfld.long 0x10 26. ",Watch point bit 26 mask" "0,1"
|
|
bitfld.long 0x10 25. ",Watch point bit 25 mask" "0,1"
|
|
bitfld.long 0x10 24. ",Watch point bit 24 mask" "0,1"
|
|
bitfld.long 0x10 23. ",Watch point bit 23 mask" "0,1"
|
|
bitfld.long 0x10 22. ",Watch point bit 22 mask" "0,1"
|
|
bitfld.long 0x10 21. ",Watch point bit 21 mask" "0,1"
|
|
bitfld.long 0x10 20. ",Watch point bit 20 mask" "0,1"
|
|
bitfld.long 0x10 19. ",Watch point bit 19 mask" "0,1"
|
|
bitfld.long 0x10 18. ",Watch point bit 18 mask" "0,1"
|
|
bitfld.long 0x10 17. ",Watch point bit 17 mask" "0,1"
|
|
bitfld.long 0x10 16. ",Watch point bit 16 mask" "0,1"
|
|
bitfld.long 0x10 15. ",Watch point bit 15 mask" "0,1"
|
|
bitfld.long 0x10 14. ",Watch point bit 14 mask" "0,1"
|
|
bitfld.long 0x10 13. ",Watch point bit 13 mask" "0,1"
|
|
bitfld.long 0x10 12. ",Watch point bit 12 mask" "0,1"
|
|
bitfld.long 0x10 11. ",Watch point bit 11 mask" "0,1"
|
|
bitfld.long 0x10 10. ",Watch point bit 10 mask" "0,1"
|
|
bitfld.long 0x10 9. ",Watch point bit 9 mask" "0,1"
|
|
bitfld.long 0x10 8. ",Watch point bit 8 mask" "0,1"
|
|
bitfld.long 0x10 7. ",Watch point bit 7 mask" "0,1"
|
|
bitfld.long 0x10 6. ",Watch point bit 6 mask" "0,1"
|
|
bitfld.long 0x10 5. ",Watch point bit 5 mask" "0,1"
|
|
bitfld.long 0x10 4. ",Watch point bit 4 mask" "0,1"
|
|
bitfld.long 0x10 3. ",Watch point bit 3 mask" "0,1"
|
|
bitfld.long 0x10 2. ",Watch point bit 2 mask" "0,1"
|
|
bitfld.long 0x10 1. ",Watch point bit 1 mask" "0,1"
|
|
bitfld.long 0x10 0. ",Watch point bit 0 mask" "0,1"
|
|
width 11.
|
|
tree "Active Channel Registers"
|
|
sif cpuis("AWR1443")||cpuis("AWR1443-CORE0")||cpuis("AWR1443-CORE1")||cpuis("AWR1843")||cpuis("AWR6843*")
|
|
group.long 0x18C++0x0B
|
|
line.long 0x00 "PAACSADDR,Port A Active Channel Source Address Register"
|
|
line.long 0x04 "PAACDADDR,Port A Active Channel Destination Address Register"
|
|
line.long 0x08 "PAACTC,Port A Active Channel Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " PAFTCOUNT ,Port A active channel frame count"
|
|
hexmask.long.word 0x08 0.--12. 1. " PAETCOUNT ,Port A active channel element count"
|
|
endif
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long 0x198++0x0B
|
|
line.long 0x00 "PBACSADDR,Port B Active Channel Source Address Register"
|
|
line.long 0x04 "PBACDADDR,Port B Active Channel Destination Address Register"
|
|
line.long 0x08 "PBACTC,PortB Active Channel Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " PBFTCOUNT ,Port B active channel frame count"
|
|
hexmask.long.word 0x08 0.--12. 1. " PBETCOUNT ,Port B active channel element count"
|
|
else
|
|
rgroup.long 0x198++0x0B
|
|
line.long 0x00 "PBACSADDR,Port B Active Channel Source Address Register"
|
|
line.long 0x04 "PBACDADDR,Port B Active Channel Destination Address Register"
|
|
line.long 0x08 "PBACTC,PortB Active Channel Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " PBFTCOUNT ,Port B active channel frame count"
|
|
hexmask.long.word 0x08 0.--12. 1. " PBETCOUNT ,Port B active channel element count"
|
|
endif
|
|
tree.end
|
|
newline
|
|
width 8.
|
|
group.long 0x1A8++0x07
|
|
line.long 0x00 "DMAPCR,Parity Control Register"
|
|
bitfld.long 0x00 16. " ERRA ,Error action" "Unchanged,Disabled"
|
|
bitfld.long 0x00 8. " TEST ,Parity bits memory mapping" "Not mapped,Mapped"
|
|
bitfld.long 0x00 0.--3. " PARITY_ENA ,Parity error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x04 "DMAPAR,Parity Error Address Register"
|
|
eventfld.long 0x04 24. " EDFLG ,Parity error detection flag" "No error,Error"
|
|
hexmask.long.word 0x04 0.--11. 0x01 " ERROR_ADDRESS ,Error address"
|
|
tree "DMA Memory Protection Registers"
|
|
width 11.
|
|
group.long 0x1B0++0x27
|
|
line.long 0x00 "DMAMPCTRL,DMA Memory Protection Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 28. " INT3AB ,Interrupt assignment of region 3 to group A/B" "VIM,DSP"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 28. " INT3AB ,Interrupt assignment of region 3 to group A/B" "VIM,2nd CPU"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 27. " INT3ENA ,Interrupt enable of region 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " REG3AP ,Region 3 access permission" "R/W,Read,Write,Not allowed"
|
|
bitfld.long 0x00 24. " REG3ENA ,Region 3 enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 20. " INT2AB ,Interrupt assignment of region 2 to group A/B" "VIM,DSP"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 20. " INT2AB ,Interrupt assignment of region 2 to group A/B" "VIM,2nd CPU"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 19. " INT2ENA ,Interrupt enable of region 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17.--18. " REG2AP ,Region 2 access permission" "R/W,Read,Write,Not allowed"
|
|
bitfld.long 0x00 16. " REG2ENA ,Region 2 enable" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 12. " INT1AB ,Interrupt assignment of region 1 to group A/B" "VIM,DSP"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 12. " INT1AB ,Interrupt assignment of region 1 to group A/B" "VIM,2nd CPU"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 11. " INT1ENA ,Interrupt enable of region 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " REG1AP ,Region 1 access permission" "R/W,Read,Write,Not allowed"
|
|
bitfld.long 0x00 8. " REG1ENA ,Region 1 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " INT0AB ,Interrupt assignment of region 0 to group A/B" "VIM,DSP"
|
|
bitfld.long 0x00 3. " INT0ENA ,Interrupt enable of region 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1.--2. " REG0AP ,Region 0 access permission" "R/W,Read,Write,Not allowed"
|
|
bitfld.long 0x00 0. " REG0ENA ,Region 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMAMPST,Memory Protection Status Register"
|
|
eventfld.long 0x04 24. " REG3FT ,Region 3 fault" "Not detected,Detected"
|
|
eventfld.long 0x04 16. " REG2FT ,Region 2 fault" "Not detected,Detected"
|
|
eventfld.long 0x04 8. " REG1FT ,Region 1 fault" "Not detected,Detected"
|
|
newline
|
|
eventfld.long 0x04 0. " REG0FT ,Region 0 fault" "Not detected,Detected"
|
|
line.long 0x08 "DMAMPR0S,DMA Protection Region Starting Address 0 Register"
|
|
line.long 0x0C "DMAMPR0E,DMA Protection Region End Address 0 Register"
|
|
line.long 0x10 "DMAMPR1S,DMA Protection Region Starting Address 1 Register"
|
|
line.long 0x14 "DMAMPR1E,DMA Protection Region End Address 1 Register"
|
|
line.long 0x18 "DMAMPR2S,DMA Protection Region Starting Address 2 Register"
|
|
line.long 0x1C "DMAMPR2E,DMA Protection Region End Address 2 Register"
|
|
line.long 0x20 "DMAMPR3S,DMA Protection Region Starting Address 3 Register"
|
|
line.long 0x24 "DMAMPR3E,DMA Protection Region End Address 3 Register"
|
|
tree.end
|
|
base ad:0xFCF81000
|
|
tree "Control Packet Registers"
|
|
width 9.
|
|
tree.open "Primary Control Packet Registers"
|
|
tree "Primary Control Packet 0"
|
|
group.long (0x0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 1"
|
|
group.long (0x20)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x20+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 2"
|
|
group.long (0x40)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x40+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 3"
|
|
group.long (0x60)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x60+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 4"
|
|
group.long (0x80)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x80+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 5"
|
|
group.long (0xA0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0xA0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 6"
|
|
group.long (0xC0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0xC0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 7"
|
|
group.long (0xE0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0xE0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 8"
|
|
group.long (0x100)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x100+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 9"
|
|
group.long (0x120)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x120+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 10"
|
|
group.long (0x140)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x140+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 11"
|
|
group.long (0x160)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x160+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 12"
|
|
group.long (0x180)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x180+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 13"
|
|
group.long (0x1A0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x1A0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 14"
|
|
group.long (0x1C0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x1C0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 15"
|
|
group.long (0x1E0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x1E0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 16"
|
|
group.long (0x200)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x200+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 17"
|
|
group.long (0x220)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x220+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 18"
|
|
group.long (0x240)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x240+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 19"
|
|
group.long (0x260)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x260+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 20"
|
|
group.long (0x280)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x280+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 21"
|
|
group.long (0x2A0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x2A0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 22"
|
|
group.long (0x2C0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x2C0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 23"
|
|
group.long (0x2E0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x2E0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 24"
|
|
group.long (0x300)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x300+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 25"
|
|
group.long (0x320)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x320+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 26"
|
|
group.long (0x340)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x340+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 27"
|
|
group.long (0x360)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x360+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 28"
|
|
group.long (0x380)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x380+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 29"
|
|
group.long (0x3A0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x3A0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 30"
|
|
group.long (0x3C0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x3C0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree "Primary Control Packet 31"
|
|
group.long (0x3E0)++0x0B
|
|
line.long 0x00 "ISADDR,Initial Source Address Register"
|
|
line.long 0x04 "IDADDR,Initial Destination Address Register"
|
|
line.long 0x08 "ITCOUNT,Initial Transfer Count Register"
|
|
hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial frame transfer count"
|
|
hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial element transfer count"
|
|
group.long (0x3E0+0x10)++0x0B
|
|
line.long 0x00 "CHCTRL,Channel Control Register"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,Ch16,Ch17,Ch18,Ch19,Ch20,Ch21,Ch22,Ch23,Ch24,Ch25,Ch26,Ch27,Ch28,Ch29,Ch30,Ch31,?..."
|
|
else
|
|
bitfld.long 0x00 16.--21. " CHAIN ,Next channel to be triggered" "No channel,Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " RES ,Read element size" "8 bits,16 bits,32 bits,64 bits"
|
|
bitfld.long 0x00 12.--13. " WES ,Write element size" "8 bits,16 bits,32 bits,64 bits"
|
|
newline
|
|
bitfld.long 0x00 8. " TTYPE ,Transfer type" "Frame,Block"
|
|
bitfld.long 0x00 3.--4. " ADDMR ,Addressing mode read" "Constant,Post-increment,,Indexed"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " ADDMW ,Addressing mode write" "Constant,Post-increment,,Indexed"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Single block,Autoinitiation"
|
|
else
|
|
bitfld.long 0x00 0. " AIM ,Autoinitiation mode" "Disabled,Enabled"
|
|
endif
|
|
line.long 0x04 "EIOFF,Element Index Offset Register"
|
|
hexmask.long.word 0x04 16.--28. 0x01 " EIDXD ,Destination address element index"
|
|
hexmask.long.word 0x04 0.--12. 0x01 " EIDXS ,Source address element index"
|
|
line.long 0x08 "FIOFF,Frame Index Offset Register"
|
|
hexmask.long.word 0x08 16.--28. 0x01 " FIDXD ,Destination address frame index"
|
|
hexmask.long.word 0x08 0.--12. 0x01 " FIDXS ,Source address frame index"
|
|
tree.end
|
|
tree.end
|
|
tree.open "Working Control Packet Registers"
|
|
tree "Working Control Packet 0"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 1"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x10+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x10+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x10+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 2"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x20+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x20+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x20+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 3"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x30+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x30+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x30+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 4"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x40+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x40+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x40+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 5"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x50+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x50+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x50+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 6"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x60+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x60+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x60+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 7"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x70+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x70+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x70+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 8"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x80+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x80+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x80+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 9"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x90+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x90+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x90+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 10"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0xA0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0xA0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0xA0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 11"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0xB0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0xB0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0xB0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 12"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0xC0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0xC0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0xC0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 13"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0xD0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0xD0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0xD0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 14"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0xE0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0xE0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0xE0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 15"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0xF0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0xF0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0xF0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 16"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x100+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x100+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x100+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 17"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x110+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x110+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x110+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 18"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x120+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x120+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x120+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 19"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x130+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x130+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x130+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 20"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x140+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x140+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x140+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 21"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x150+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x150+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x150+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 22"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x160+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x160+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x160+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 23"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x170+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x170+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x170+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 24"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x180+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x180+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x180+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 25"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x190+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x190+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x190+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 26"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x1A0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x1A0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x1A0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 27"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x1B0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x1B0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x1B0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 28"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x1C0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x1C0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x1C0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 29"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x1D0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x1D0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x1D0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 30"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x1E0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x1E0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x1E0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree "Working Control Packet 31"
|
|
sif !cpuis("TMS570LS3137-EP")
|
|
group.long (0x1F0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
else
|
|
rgroup.long (0x1F0+0x800)++0x07
|
|
line.long 0x00 "CSADDR,Current Source Address Register"
|
|
line.long 0x04 "CDADDR,Current Destination Address Register"
|
|
endif
|
|
rgroup.long (0x1F0+0x808)++0x03
|
|
line.long 0x00 "CTCOUNT,Current Transfer Count Register"
|
|
hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current frame transfer count"
|
|
hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current element transfer count"
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif cpuis("AWR1843*")
|
|
tree "VIM (Vectored Interrupt Manager)"
|
|
base ad:0xFFFFFD00
|
|
width 13.
|
|
group.long 0xEC++0x07
|
|
line.long 0x00 "ECCSTAT,Interrupt Vector Table ECC Status Register"
|
|
eventfld.long 0x00 8. " SBERR ,Single bit error" "No error,Error"
|
|
eventfld.long 0x00 0. " UERR ,Double bit error" "No error,Error"
|
|
line.long 0x04 "ECCCTL,Interrupt Vector Table ECC Control Register"
|
|
bitfld.long 0x04 24.--27. " SBE_EVT_EN ,Control the generation of error signal out based on SBE" ",,,,,Disabled,,,,,Enabled,?..."
|
|
bitfld.long 0x04 16.--19. " EDAC_MODE ,Enable SBE correction" ",,,,,Disabled,,,,,Enabled,?..."
|
|
newline
|
|
bitfld.long 0x04 8.--11. " TEST_DIAG_EN ,Memory mapping of ECC bits for read/write operation" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x04 0.--3. " ECCENA ,VIM ECC enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "UERRADDR,Uncorrectable Error Address Register"
|
|
hexmask.long.tbyte 0x00 10.--31. 0x04 " INTVECTOFF ,Interrupt vector table offset"
|
|
hexmask.long.word 0x00 2.--9. 0x04 " ADDERR ,Uncorrectable error address register"
|
|
bitfld.long 0x00 0.--1. " WO ,Word offset" "0,?..."
|
|
group.long 0xF8++0x07
|
|
line.long 0x00 "FBVECADDR,Fallback Vector Address Register"
|
|
line.long 0x04 "SBERRADDR,Single Bit Error Address Register"
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "IRQINDEX,IRQ Index Offset Vector Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRQINDEX ,IRQ index vector"
|
|
line.long 0x04 "FIQINDEX,FIQ Index Offset Vector Register"
|
|
hexmask.long.byte 0x04 0.--7. 0x01 " FIQINDEX ,FIQ index offset vector"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "FIRQPR0,FIQ/IRQ Program Control Register 0"
|
|
bitfld.long 0x00 31. " FIRQPR0_[31] ,MSS_DTHE (crypto/SHA) SHA -S interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 30. " [30] ,MSS_MIBSPIB level 1 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 29. " [29] ,MSS_DCAN level 1 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 28. " [28] ,MSS_QSPI interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 27. " [27] ,MSS_QSPI interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,MSS_MIBSPIA level 0 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 25. " [25] ,MSS_RTIB (WDT/RTIB) TB base interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 24. " [24] ,MSS_RTIB (WDT/RTIB) overflow interrupt 1 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 23. " [23] ,MSS_GIO low-level interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 22. " [22] ,MSS Cortex R4F interrupt PMU type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Software-triggered interrupt 4 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 20. " [20] ,MSS_ESM low-level interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 19. " [19] ,MSS_MCRC (CRC) interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 18. " [18] ,MSS_GIO GPIO_0_host_interrup type" "IRQ,FIQ"
|
|
bitfld.long 0x00 17. " [17] ,MSS_MIBSPIB level 0 interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,MSS_DCAN level 0 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 15. " [15] ,MSS_RTIB (WDT/RTIB) overflow interrupt 0 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 14. " [14] ,MSS_RTIB (WDT/RTIB) interrupt 3 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 13. " [13] ,MSS_RTIB (WDT/RTIB) interrupt 2 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 12. " [12] ,MSS_MIBSPIA level 0 interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,MSS_RTIB (WDT/RTIB) interrupt 1 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 10. " [10] ,MSS_RTIB (WDT/RTIB) interrupt 0 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 9. " [9] ,MSS_GIO high-level interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 8. " [8] ,MSS_RTIA time-base type" "IRQ,FIQ"
|
|
bitfld.long 0x00 7. " [7] ,MSS_RTIA overflow interrupt 1 type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,MSS_RTIA overflow interrupt 0 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 5. " [5] ,MSS_RTIA compare interrupt 3 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 4. " [4] ,MSS_RTIA compare interrupt 2 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 3. " [3] ,MSS_RTIA compare interrupt 1 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 2. " [2] ,MSS_RTIA compare interrupt 0 type" "IRQ,FIQ"
|
|
line.long 0x04 "FIRQPR1,FIQ/IRQ Program Control Register 1"
|
|
bitfld.long 0x04 31. " FIRQPR1_[63] ,GEM MSS_STC done interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 30. " [62] ,MSS_DEBUGSS (debug subsystem) interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 29. " [61] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ2 type" "IRQ,FIQ"
|
|
bitfld.long 0x04 28. " [60] ,DSS to MSS mailbox empty interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 27. " [59] ,DSS to MSS mailbox full interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 26. " [58] ,MSS_DMM2 level -1 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 25. " [57] ,MSS_DMM2 level -0 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 24. " [56] ,MSS_DTHE (crypto/AES) AES-P module interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 22. " [54] ,MSS_DTHE (crypto/AES) AES-S module interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 21. " [53] ,MSS_DTHE (crypto/PKA) PKA module interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 20. " [52] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ1 type" "IRQ,FIQ"
|
|
bitfld.long 0x04 19. " [51] ,MSS_DMA2 bus error interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 18. " [50] ,MSS_DMA2 block transfer complete interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 17. " [49] ,MSS_DMA2 half-block transfer complete interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 16. " [48] ,MSS_GIO GPIO_2_host_interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 15. " [47] ,Floating point unit interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 13. " [45] ,MSS_DMA2 last frame complete interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 11. " [43] ,MSS_DMM level -1 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 9. " [41] ,MSS_DMA2 frame block transfer complete interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 8. " [40] ,MSS_DMA block transfer complete interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 7. " [39] ,MSS_DMA half-block transfer complete interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 6. " [38] ,MSS_DTHE (crypto/TRNG) TRNG interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 5. " [37] ,MSS_DTHE (crypto/SHA) SHA -P interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 4. " [36] ,MSS_DMM level -0 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 2. " [34] ,MSS_DMA last frame transfer start interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,MSS_DMA frame transfer complete interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 0. " [32] ,MSS_GIO GPIO_1_host_interrupt type" "IRQ,FIQ"
|
|
line.long 0x08 "FIRQPR2,FIQ/IRQ Program Control Register 2"
|
|
bitfld.long 0x08 31. " FIRQPR2_[95] ,RADARSS to MSS mailbox interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x08 22. " [86] ,GEM IRQ-7/MSS_DMM interrupt 32 type" "IRQ,FIQ"
|
|
bitfld.long 0x08 21. " [85] ,MSS_PBIST interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x08 20. " [84] ,Software-triggered interrupt 5 type" "IRQ,FIQ"
|
|
bitfld.long 0x08 19. " [83] ,MSS_DCCB (dual clock compare) module2-done interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 18. " [82] ,MSS_DCCA (dual clock compare) module1-done interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x08 15. " [79] ,Software-triggered interrupt 3 type" "IRQ,FIQ"
|
|
bitfld.long 0x08 14. " [78] ,Software-triggered interrupt 2 type" "IRQ,FIQ"
|
|
bitfld.long 0x08 13. " [77] ,Software-triggered interrupt 1 type" "IRQ,FIQ"
|
|
bitfld.long 0x08 12. " [76] ,Software-triggered interrupt 0 type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 11. " [75] ,MSS_SCIB (UART2) level 1 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x08 10. " [74] ,MSS_SCIA (UART1) level 1 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x08 9. " [73] ,MSS_DMM interrupt 33 type" "IRQ,FIQ"
|
|
bitfld.long 0x08 7. " [71] ,MSS_DMM interrupt 30 or radar subsystem logical frame start type" "IRQ,FIQ"
|
|
bitfld.long 0x08 6. " [70] ,MSS_DMA bus error interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 5. " [69] ,MSS_DMM interrupt 36 type" "IRQ,FIQ"
|
|
bitfld.long 0x08 4. " [68] ,MSS_DMM interrupt 35 type" "IRQ,FIQ"
|
|
bitfld.long 0x08 3. " [67] ,MSS_DMM interrupt 34 type" "IRQ,FIQ"
|
|
bitfld.long 0x08 2. " [66] ,MSS_I2C interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x08 1. " [65] ,MSS_SCIB (UART2) level 0 interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 0. " [64] ,MSS_SCIA (UART1) level 0 interrupt type" "IRQ,FIQ"
|
|
line.long 0x0C "FIRQPR3,FIQ/IRQ Program Control Register 3"
|
|
bitfld.long 0x0C 31. " FIRQPR3_[127] ,DSS_HW_ACC FFT accelerator access error interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 30. " [126] ,DSS_HW_ACC FFT accelerator - done interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 29. " [125] ,DSS_HW_ACC FFT accelerator -param done interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 28. " [124] ,MSS_PBIST: gem MSS_STC done type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 27. " [123] ,Chirp available interrupt/MSS_DMM interrupt 31 type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 25. " [121] ,MSS_DMM interrupt 37 type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 24. " [120] ,DSS_CBUFF (common buffer) error interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 22. " [118] ,DSS_CBUFF (common buffer) interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 21. " [117] ,DSS_TPCC (EDMA TPCC0) error interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 20. " [116] ,DSS_TPCC (EDMA TPCC0) interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 19. " [115] ,DSS_TPTC1 (EDMA TPTC1) error interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 18. " [114] ,DSS_TPTC1 (EDMA TPTC1) interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 17. " [113] ,DSS_TPTC0 (EDMA TPTC0) error interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 16. " [112] ,DSS_TPTC0 (EDMA TPTC0) interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 15. " [111] ,ePWM3 interrupt-2 type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 14. " [110] ,ePWM3 interrupt-1 type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 13. " [109] ,ePWM2 interrupt-2 type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 12. " [108] ,ePWM2 interrupt-1 type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 11. " [107] ,ePWM1 interrupt-2 type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 10. " [106] ,All RadarSS interrupts combined type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 9. " [105] ,MSS_STC done interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 8. " [104] ,ePWM1 interrupt-1 type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 5. " [101] ,Frame end interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 4. " [100] ,Chirp end interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 3. " [99] ,Chirp start interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 2. " [98] ,MSS_DMM interrupt 29/frame start interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 1. " [97] ,ADC valid fall interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 0. " [96] ,RADARSS mailbox read complete interrupt sent from RADARSS to MSS type" "IRQ,FIQ"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "INTREQ0,Pending Interrupt Read Location Register 0"
|
|
eventfld.long 0x00 31. " INTREQ0_[31] ,MSS_DTHE (crypto/SHA) SHA -S interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " [30] ,MSS_MIBSPIB level 1 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " [29] ,MSS_DCAN level 1 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " [28] ,MSS_QSPI interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 27. " [27] ,MSS_QSPI interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 26. " [26] ,MSS_MIBSPIA level 0 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " [25] ,MSS_RTIB (WDT/RTIB) TB base interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " [24] ,MSS_RTIB (WDT/RTIB) overflow interrupt 1 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " [23] ,MSS_GIO low-level interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " [22] ,MSS Cortex R4F interrupt PMU pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 21. " [21] ,Software-triggered interrupt 4 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " [20] ,MSS_ESM low-level interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " [19] ,MSS_MCRC (CRC) interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " [18] ,MSS_GIO GPIO_0_host_interrup pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " [17] ,MSS_MIBSPIB level 0 interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 16. " [16] ,MSS_DCAN level 0 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " [15] ,MSS_RTIB (WDT/RTIB) overflow interrupt 0 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " [14] ,MSS_RTIB (WDT/RTIB) interrupt 3 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " [13] ,MSS_RTIB (WDT/RTIB) interrupt 2 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [12] ,MSS_MIBSPIA level 0 interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,MSS_RTIB (WDT/RTIB) interrupt 1 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,MSS_RTIB (WDT/RTIB) interrupt 0 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " [9] ,MSS_GIO high-level interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " [8] ,MSS_RTIA time-base pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " [7] ,MSS_RTIA overflow interrupt 1 pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 6. " [6] ,MSS_RTIA overflow interrupt 0 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " [5] ,MSS_RTIA compare interrupt 3 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,MSS_RTIA compare interrupt 2 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " [3] ,MSS_RTIA compare interrupt 1 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,MSS_RTIA compare interrupt 0 pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 0. " [0] ,MSS_ESM high-level interrupt(NMI) pending" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTREQ1,Pending Interrupt Read Location Register 1"
|
|
eventfld.long 0x04 31. " INTREQ1_[63] ,GEM MSS_STC done interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 30. " [62] ,MSS_DEBUGSS (debug subsystem) interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 29. " [61] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ2 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 28. " [60] ,DSS to MSS mailbox empty interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 27. " [59] ,DSS to MSS mailbox full interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 26. " [58] ,MSS_DMM2 level -1 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 25. " [57] ,MSS_DMM2 level -0 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 24. " [56] ,MSS_DTHE (crypto/AES) AES-P module interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 22. " [54] ,MSS_DTHE (crypto/AES) AES-S module interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 21. " [53] ,MSS_DTHE (crypto/PKA) PKA module interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 20. " [52] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ1 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 19. " [51] ,MSS_DMA2 bus error interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 18. " [50] ,MSS_DMA2 block transfer complete interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 17. " [49] ,MSS_DMA2 half-block transfer complete interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 16. " [48] ,MSS_GIO GPIO_2_host_interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 15. " [47] ,Floating point unit interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 13. " [45] ,MSS_DMA2 last frame complete interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 11. " [43] ,MSS_DMM level -1 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 9. " [41] ,MSS_DMA2 frame block transfer complete interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 8. " [40] ,MSS_DMA block transfer complete interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 7. " [39] ,MSS_DMA half-block transfer complete interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " [38] ,MSS_DTHE (crypto/TRNG) TRNG interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " [37] ,MSS_DTHE (crypto/SHA) SHA -P interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 4. " [36] ,MSS_DMM level -0 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " [34] ,MSS_DMA last frame transfer start interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 1. " [33] ,MSS_DMA frame transfer complete interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 0. " [32] ,MSS_GIO GPIO_1_host_interrupt pending" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTREQ2,Pending Interrupt Read Location Register 2"
|
|
eventfld.long 0x08 31. " INTREQ2_[95] ,RADARSS to MSS mailbox interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 22. " [86] ,GEM IRQ-7/MSS_DMM interrupt 32 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 21. " [85] ,MSS_PBIST interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 20. " [84] ,Software-triggered interrupt 5 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 19. " [83] ,MSS_DCCB (dual clock compare) module2-done interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 18. " [82] ,MSS_DCCA (dual clock compare) module1-done interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 15. " [79] ,Software-triggered interrupt 3 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 14. " [78] ,Software-triggered interrupt 2 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 13. " [77] ,Software-triggered interrupt 1 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 12. " [76] ,Software-triggered interrupt 0 pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 11. " [75] ,MSS_SCIB (UART2) level 1 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 10. " [74] ,MSS_SCIA (UART1) level 1 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 9. " [73] ,MSS_DMM interrupt 33 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " [71] ,MSS_DMM interrupt 30 or radar subsystem logical frame start pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " [70] ,MSS_DMA bus error interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 5. " [69] ,MSS_DMM interrupt 36 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " [68] ,MSS_DMM interrupt 35 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " [67] ,MSS_DMM interrupt 34 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " [66] ,MSS_I2C interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 1. " [65] ,MSS_SCIB (UART2) level 0 interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 0. " [64] ,MSS_SCIA (UART1) level 0 interrupt pending" "No interrupt,Interrupt"
|
|
line.long 0x0C "INTREQ3,Pending Interrupt Read Location Register 3"
|
|
eventfld.long 0x0C 31. " INTREQ3_[127] ,DSS_HW_ACC FFT accelerator access error interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 30. " [126] ,DSS_HW_ACC FFT accelerator - done interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 29. " [125] ,DSS_HW_ACC FFT accelerator -param done interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 28. " [124] ,MSS_PBIST: gem MSS_STC done pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 27. " [123] ,Chirp available interrupt/MSS_DMM interrupt 31 pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 25. " [121] ,MSS_DMM interrupt 37 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 24. " [120] ,DSS_CBUFF (common buffer) error interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 22. " [118] ,DSS_CBUFF (common buffer) interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 21. " [117] ,DSS_TPCC (EDMA TPCC0) error interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 20. " [116] ,DSS_TPCC (EDMA TPCC0) interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 19. " [115] ,DSS_TPTC1 (EDMA TPTC1) error interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 18. " [114] ,DSS_TPTC1 (EDMA TPTC1) interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 17. " [113] ,DSS_TPTC0 (EDMA TPTC0) error interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 16. " [112] ,DSS_TPTC0 (EDMA TPTC0) interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 15. " [111] ,ePWM3 interrupt-2 pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 14. " [110] ,ePWM3 interrupt-1 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 13. " [109] ,ePWM2 interrupt-2 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " [108] ,ePWM2 interrupt-1 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 11. " [107] ,ePWM1 interrupt-2 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " [106] ,All RadarSS interrupts combined pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 9. " [105] ,MSS_STC done interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " [104] ,ePWM1 interrupt-1 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 5. " [101] ,Frame end interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " [100] ,Chirp end interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 3. " [99] ,Chirp start interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 2. " [98] ,MSS_DMM interrupt 29/frame start interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 1. " [97] ,ADC valid fall interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " [96] ,RADARSS mailbox read complete interrupt sent from RADARSS to MSS pending" "No interrupt,Interrupt"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "REQENASET0,Interrupt Enable Set Register 0"
|
|
bitfld.long 0x00 31. " REQENASET0_[31] ,MSS_DTHE (crypto/SHA) SHA -S interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,MSS_MIBSPIB level 1 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,MSS_DCAN level 1 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,MSS_QSPI interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,MSS_QSPI interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,MSS_MIBSPIA level 0 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,MSS_RTIB (WDT/RTIB) TB base interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,MSS_RTIB (WDT/RTIB) overflow interrupt 1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,MSS_GIO low-level interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,MSS Cortex R4F interrupt PMU set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Software-triggered interrupt 4 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,MSS_ESM low-level interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,MSS_MCRC (CRC) interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,MSS_GIO GPIO_0_host_interrup set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,MSS_MIBSPIB level 0 interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,MSS_DCAN level 0 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,MSS_RTIB (WDT/RTIB) overflow interrupt 0 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,MSS_RTIB (WDT/RTIB) interrupt 3 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,MSS_RTIB (WDT/RTIB) interrupt 2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,MSS_MIBSPIA level 0 interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,MSS_RTIB (WDT/RTIB) interrupt 1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,MSS_RTIB (WDT/RTIB) interrupt 0 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,MSS_GIO high-level interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,MSS_RTIA time-base set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,MSS_RTIA overflow interrupt 1 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,MSS_RTIA overflow interrupt 0 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,MSS_RTIA compare interrupt 3 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,MSS_RTIA compare interrupt 2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,MSS_RTIA compare interrupt 1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,MSS_RTIA compare interrupt 0 set enable" "Disabled,Enabled"
|
|
line.long 0x04 "REQENASET1,Interrupt Set Enable Register 1"
|
|
bitfld.long 0x04 31. " REQENASET1_[63] ,GEM MSS_STC done interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,MSS_DEBUGSS (debug subsystem) interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,DSS to MSS mailbox empty interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " [59] ,DSS to MSS mailbox full interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 26. " [58] ,MSS_DMM2 level -1 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,MSS_DMM2 level -0 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,MSS_DTHE (crypto/AES) AES-P module interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,MSS_DTHE (crypto/AES) AES-S module interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,MSS_DTHE (crypto/PKA) PKA module interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 20. " [52] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " [51] ,MSS_DMA2 bus error interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,MSS_DMA2 block transfer complete interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,MSS_DMA2 half-block transfer complete interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,MSS_GIO GPIO_2_host_interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " [47] ,Floating point unit interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,MSS_DMA2 last frame complete interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " [43] ,MSS_DMM level -1 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,MSS_DMA2 frame block transfer complete interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,MSS_DMA block transfer complete interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " [39] ,MSS_DMA half-block transfer complete interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,MSS_DTHE (crypto/TRNG) TRNG interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,MSS_DTHE (crypto/SHA) SHA -P interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,MSS_DMM level -0 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,MSS_DMA last frame transfer start interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,MSS_DMA frame transfer complete interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,MSS_GIO GPIO_1_host_interrupt set enable" "Disabled,Enabled"
|
|
line.long 0x08 "REQENASET2,Interrupt Set Enable Register 2"
|
|
bitfld.long 0x08 31. " REQENASET2_[95] ,RADARSS to MSS mailbox interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,GEM IRQ-7/MSS_DMM interrupt 32 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,MSS_PBIST interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Software-triggered interrupt 5 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " [83] ,MSS_DCCB (dual clock compare) module2-done interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 18. " [82] ,MSS_DCCA (dual clock compare) module1-done interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " [79] ,Software-triggered interrupt 3 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Software-triggered interrupt 2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Software-triggered interrupt 1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Software-triggered interrupt 0 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " [75] ,MSS_SCIB (UART2) level 1 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,MSS_SCIA (UART1) level 1 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,MSS_DMM interrupt 33 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " [71] ,MSS_DMM interrupt 30 or radar subsystem logical frame start set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,MSS_DMA bus error interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " [69] ,MSS_DMM interrupt 36 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,MSS_DMM interrupt 35 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " [67] ,MSS_DMM interrupt 34 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,MSS_I2C interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,MSS_SCIB (UART2) level 0 interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 0. " [64] ,MSS_SCIA (UART1) level 0 interrupt set enable" "Disabled,Enabled"
|
|
line.long 0x0C "REQENASET3,Interrupt Set Enable Register 3"
|
|
bitfld.long 0x0C 31. " REQENASET3_[127] ,DSS_HW_ACC FFT accelerator -access error interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,DSS_HW_ACC FFT accelerator - done interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,DSS_HW_ACC FFT accelerator -param done interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,MSS_PBIST: gem MSS_STC done set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " [123] ,Chirp available interrupt/MSS_DMM interrupt 31 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 25. " [121] ,MSS_DMM interrupt 37 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,DSS_CBUFF (common buffer) error interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,DSS_CBUFF (common buffer) interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,DSS_TPCC (EDMA TPCC0) error interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,DSS_TPCC (EDMA TPCC0) interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 19. " [115] ,DSS_TPTC1 (EDMA TPTC1) error interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,DSS_TPTC1 (EDMA TPTC1) interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,DSS_TPTC0 (EDMA TPTC0) error interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,DSS_TPTC0 (EDMA TPTC0) interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " [111] ,ePWM3 interrupt-2 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 14. " [110] ,ePWM3 interrupt-1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,ePWM2 interrupt-2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,ePWM2 interrupt-1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " [107] ,ePWM1 interrupt-2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,All RadarSS interrupts combined set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 9. " [105] ,MSS_STC done interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,ePWM1 interrupt-1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Frame end interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Chirp end interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " [99] ,Chirp start interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " [98] ,MSS_DMM interrupt 29/frame start interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,ADC valid fall interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,RADARSS mailbox read complete interrupt sent from RADARSS to MSS set enable" "Disabled,Enabled"
|
|
group.long 0x40++0x0F
|
|
line.long 0x00 "REQENACLR0,Interrupt Enable Clear Register 0"
|
|
bitfld.long 0x00 31. " REQENACLR0_[31] ,MSS_DTHE (crypto/SHA) SHA -S interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,MSS_MIBSPIB level 1 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,MSS_DCAN level 1 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,MSS_QSPI interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,MSS_QSPI interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,MSS_MIBSPIA level 0 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,MSS_RTIB (WDT/RTIB) TB base interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,MSS_RTIB (WDT/RTIB) overflow interrupt 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,MSS_GIO low-level interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,MSS Cortex R4F interrupt PMU clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Software-triggered interrupt 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,MSS_ESM low-level interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,MSS_MCRC (CRC) interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,MSS_GIO GPIO_0_host_interrup clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,MSS_MIBSPIB level 0 interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,MSS_DCAN level 0 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,MSS_RTIB (WDT/RTIB) overflow interrupt 0 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,MSS_RTIB (WDT/RTIB) interrupt 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,MSS_RTIB (WDT/RTIB) interrupt 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,MSS_MIBSPIA level 0 interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,MSS_RTIB (WDT/RTIB) interrupt 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,MSS_RTIB (WDT/RTIB) interrupt 0 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,MSS_GIO high-level interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,MSS_RTIA time-base clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,MSS_RTIA overflow interrupt 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,MSS_RTIA overflow interrupt 0 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,MSS_RTIA compare interrupt 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,MSS_RTIA compare interrupt 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,MSS_RTIA compare interrupt 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,MSS_RTIA compare interrupt 0 clear enable" "Disabled,Enabled"
|
|
line.long 0x04 "REQENACLR1,Interrupt Clear Enable Register 1"
|
|
bitfld.long 0x04 31. " REQENACLR1_[63] ,GEM MSS_STC done interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,MSS_DEBUGSS (debug subsystem) interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,DSS to MSS mailbox empty interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " [59] ,DSS to MSS mailbox full interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 26. " [58] ,MSS_DMM2 level -1 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,MSS_DMM2 level -0 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,MSS_DTHE (crypto/AES) AES-P module interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,MSS_DTHE (crypto/AES) AES-S module interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,MSS_DTHE (crypto/PKA) PKA module interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 20. " [52] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " [51] ,MSS_DMA2 bus error interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,MSS_DMA2 block transfer complete interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,MSS_DMA2 half-block transfer complete interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,MSS_GIO GPIO_2_host_interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " [47] ,Floating point unit interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,MSS_DMA2 last frame complete interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " [43] ,MSS_DMM level -1 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,MSS_DMA2 frame block transfer complete interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,MSS_DMA block transfer complete interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " [39] ,MSS_DMA half-block transfer complete interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,MSS_DTHE (crypto/TRNG) TRNG interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,MSS_DTHE (crypto/SHA) SHA -P interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,MSS_DMM level -0 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,MSS_DMA last frame transfer start interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,MSS_DMA frame transfer complete interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,MSS_GIO GPIO_1_host_interrupt clear enable" "Disabled,Enabled"
|
|
line.long 0x08 "REQENACLR2,Interrupt Clear Enable Register 2"
|
|
bitfld.long 0x08 31. " REQENACLR2_[95] ,RADARSS to MSS mailbox interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,GEM IRQ-7/MSS_DMM interrupt 32 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,MSS_PBIST interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Software-triggered interrupt 5 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " [83] ,MSS_DCCB (dual clock compare) module2-done interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 18. " [82] ,MSS_DCCA (dual clock compare) module1-done interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " [79] ,Software-triggered interrupt 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Software-triggered interrupt 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Software-triggered interrupt 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Software-triggered interrupt 0 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " [75] ,MSS_SCIB (UART2) level 1 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,MSS_SCIA (UART1) level 1 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,MSS_DMM interrupt 33 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " [71] ,MSS_DMM interrupt 30 or radar subsystem logical frame start clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,MSS_DMA bus error interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " [69] ,MSS_DMM interrupt 36 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,MSS_DMM interrupt 35 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " [67] ,MSS_DMM interrupt 34 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,MSS_I2C interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,MSS_SCIB (UART2) level 0 interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 0. " [64] ,MSS_SCIA (UART1) level 0 interrupt clear enable" "Disabled,Enabled"
|
|
line.long 0x0C "REQENACLR3,Interrupt Clear Enable Register 3"
|
|
bitfld.long 0x0C 31. " REQENACLR3_[127] ,DSS_HW_ACC FFT accelerator -access error interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,DSS_HW_ACC FFT accelerator - done interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,DSS_HW_ACC FFT accelerator -param done interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,MSS_PBIST: gem MSS_STC done clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " [123] ,Chirp available interrupt/MSS_DMM interrupt 31 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 25. " [121] ,MSS_DMM interrupt 37 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,DSS_CBUFF (common buffer) error interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,DSS_CBUFF (common buffer) interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,DSS_TPCC (EDMA TPCC0) error interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,DSS_TPCC (EDMA TPCC0) interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 19. " [115] ,DSS_TPTC1 (EDMA TPTC1) error interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,DSS_TPTC1 (EDMA TPTC1) interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,DSS_TPTC0 (EDMA TPTC0) error interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,DSS_TPTC0 (EDMA TPTC0) interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " [111] ,ePWM3 interrupt-2 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 14. " [110] ,ePWM3 interrupt-1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,ePWM2 interrupt-2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,ePWM2 interrupt-1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " [107] ,ePWM1 interrupt-2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,All RadarSS interrupts combined clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 9. " [105] ,MSS_STC done interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,ePWM1 interrupt-1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Frame end interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Chirp end interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " [99] ,Chirp start interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " [98] ,MSS_DMM interrupt 29/frame start interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,ADC valid fall interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,RADARSS mailbox read complete interrupt sent from RADARSS to MSS clear enable" "Disabled,Enabled"
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "WAKEENASET0,Wake-Up Enable Set Register 0"
|
|
bitfld.long 0x00 31. " WAKEENASET0_[31] ,MSS_DTHE (crypto/SHA) SHA -S wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,MSS_MIBSPIB level 1 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,MSS_DCAN level 1 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,MSS_QSPI wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,MSS_QSPI wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,MSS_MIBSPIA level 0 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,MSS_RTIB (WDT/RTIB) TB base wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,MSS_RTIB (WDT/RTIB) overflow wake-up interrupt 1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,MSS_GIO low-level wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,MSS Cortex R4F wake-up interrupt PMU set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Software-triggered wake-up interrupt 4 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,MSS_ESM low-level wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,MSS_MCRC (CRC) wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,MSS_GIO wake-up GPIO_0_host_interrup set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,MSS_MIBSPIB level 0 wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,MSS_DCAN level 0 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,MSS_RTIB (WDT/RTIB) overflow wake-up interrupt 0 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,MSS_RTIB (WDT/RTIB) wake-up interrupt 3 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,MSS_RTIB (WDT/RTIB) interrupt 2 wake-up set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,MSS_MIBSPIA level 0 wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,MSS_RTIB (WDT/RTIB) wake-up interrupt 1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,MSS_RTIB (WDT/RTIB) wake-up interrupt 0 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,MSS_GIO high-level wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,MSS_RTIA time-base interrupt wake-up set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,MSS_RTIA overflow wake-up interrupt 1 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,MSS_RTIA overflow wake-up interrupt 0 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,MSS_RTIA compare wake-up interrupt 3 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,MSS_RTIA compare wake-up interrupt 2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,MSS_RTIA compare wake-up interrupt 1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,MSS_RTIA compare wake-up interrupt 0 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [0] ,MSS_ESM high-level wake-up interrupt(NMI) set enable" "Disabled,Enabled"
|
|
line.long 0x04 "WAKEENASET1,Wake-Up Enable Set Register 1"
|
|
bitfld.long 0x04 31. " WAKEENASET1_[63] ,GEM MSS_STC done wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,MSS_DEBUGSS (debug subsystem) wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ2 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,DSS to MSS mailbox empty wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " [59] ,DSS to MSS mailbox full wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 26. " [58] ,MSS_DMM2 level -1 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,MSS_DMM2 level -0 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,MSS_DTHE (crypto/AES) AES-P module wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,MSS_DTHE (crypto/AES) AES-S module wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,MSS_DTHE (crypto/PKA) PKA module wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 20. " [52] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ1 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " [51] ,MSS_DMA2 bus error wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,MSS_DMA2 block transfer complete wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,MSS_DMA2 half-block transfer complete wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,MSS_GIO wake-up GPIO_2_host_interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " [47] ,Floating point unit wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,MSS_DMA2 last frame complete wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " [43] ,MSS_DMM level -1 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,MSS_DMA2 frame block transfer complete wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,MSS_DMA block transfer complete wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " [39] ,MSS_DMA half-block transfer complete wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,MSS_DTHE (crypto/TRNG) TRNG wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,MSS_DTHE (crypto/SHA) SHA -P wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,MSS_DMM level -0 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,MSS_DMA last frame transfer start wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,MSS_DMA frame transfer complete wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,MSS_GIO wake-up GPIO_1_host_interrupt set enable" "Disabled,Enabled"
|
|
line.long 0x08 "WAKEENASET2,Wake-Up Enable Set Register 2"
|
|
bitfld.long 0x08 31. " WAKEENASET2_[95] ,RADARSS to MSS mailbox wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,GEM IRQ-7/MSS_DMM wake-up interrupt 32 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,MSS_PBIST wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Software-triggered wake-up interrupt 5 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " [83] ,MSS_DCCB (dual clock compare) module2-done wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 18. " [82] ,MSS_DCCA (dual clock compare) module1-done wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " [79] ,Software-triggered wake-up interrupt 3 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Software-triggered wake-up interrupt 2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Software-triggered wake-up interrupt 1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Software-triggered wake-up interrupt 0 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " [75] ,MSS_SCIB (UART2) level 1 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,MSS_SCIA (UART1) level 1 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,MSS_DMM wake-up interrupt 33 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " [71] ,MSS_DMM interrupt 30 or radar subsystem logical frame start wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,MSS_DMA bus error wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " [69] ,MSS_DMM wake-up interrupt 36 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,MSS_DMM wake-up interrupt 35 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " [67] ,MSS_DMM wake-up interrupt 34 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,MSS_I2C wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,MSS_SCIB (UART2) level 0 wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 0. " [64] ,MSS_SCIA (UART1) level 0 wake-up interrupt set enable" "Disabled,Enabled"
|
|
line.long 0x0C "WAKEENASET3,Wake-Up Enable Set Register 3"
|
|
bitfld.long 0x0C 31. " WAKEENASET3_[127] ,DSS_HW_ACC FFT accelerator -access error wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,DSS_HW_ACC FFT accelerator - done wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,DSS_HW_ACC FFT accelerator -param done wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,MSS_PBIST: gem MSS_STC done wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " [123] ,Chirp available interrupt/MSS_DMM wake-up interrupt 31 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 25. " [121] ,MSS_DMM interrupt 37 wake-up set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,DSS_CBUFF (common buffer) error wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,DSS_CBUFF (common buffer) interrupt wake-up set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,DSS_TPCC (EDMA TPCC0) error wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,DSS_TPCC (EDMA TPCC0) wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 19. " [115] ,DSS_TPTC1 (EDMA TPTC1) error wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,DSS_TPTC1 (EDMA TPTC1) wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,DSS_TPTC0 (EDMA TPTC0) error wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,DSS_TPTC0 (EDMA TPTC0) wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " [111] ,ePWM3 wake-up interrupt-2 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 14. " [110] ,ePWM3 wake-up interrupt-1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,ePWM2 wake-up interrupt-2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,ePWM2 wake-up interrupt-1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " [107] ,ePWM1 wake-up interrupt-2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,All RadarSS wake-up interrupts combined set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 9. " [105] ,MSS_STC done wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,ePWM1 wake-up interrupt-1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Frame end wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Chirp end wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " [99] ,Chirp start wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " [98] ,MSS_DMM interrupt 29/frame start wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,ADC valid fall wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,RADARSS mailbox read complete wake-up interrupt sent from RADARSS to MSS set enable" "Disabled,Enabled"
|
|
group.long 0x60++0x0F
|
|
line.long 0x00 "WAKEENACLR0,Wake-Up Enable Clear Register 0"
|
|
bitfld.long 0x00 31. " WAKEENACLR0_[31] ,MSS_DTHE (crypto/SHA) SHA -S wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,MSS_MIBSPIB level 1 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,MSS_DCAN level 1 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,MSS_QSPI wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,MSS_QSPI wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,MSS_MIBSPIA level 0 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,MSS_RTIB (WDT/RTIB) TB base wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,MSS_RTIB (WDT/RTIB) overflow wake-up interrupt 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,MSS_GIO low-level wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,MSS Cortex R4F wake-up interrupt PMU clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Software-triggered wake-up interrupt 4 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,MSS_ESM low-level wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,MSS_MCRC (CRC) wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,MSS_GIO wake-up GPIO_0_host_interrup clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,MSS_MIBSPIB level 0 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,MSS_DCAN level 0 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,MSS_RTIB (WDT/RTIB) overflow wake-up interrupt 0 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,MSS_RTIB (WDT/RTIB) wake-up interrupt 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,MSS_RTIB (WDT/RTIB) interrupt 2 wake-up clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,MSS_MIBSPIA level 0 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,MSS_RTIB (WDT/RTIB) wake-up interrupt 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,MSS_RTIB (WDT/RTIB) wake-up interrupt 0 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,MSS_GIO high-level wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,MSS_RTIA time-base interrupt wake-up clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,MSS_RTIA overflow wake-up interrupt 1 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,MSS_RTIA overflow wake-up interrupt 0 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,MSS_RTIA compare wake-up interrupt 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,MSS_RTIA compare wake-up interrupt 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,MSS_RTIA compare wake-up interrupt 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,MSS_RTIA compare wake-up interrupt 0 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [0] ,MSS_ESM high-level wake-up interrupt(NMI) clear enable" "Disabled,Enabled"
|
|
line.long 0x04 "WAKEENACLR1,Wake-Up Enable Clear Register 1"
|
|
bitfld.long 0x04 31. " WAKEENACLR1_[63] ,GEM MSS_STC done wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,MSS_DEBUGSS (debug subsystem) wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ2 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,DSS to MSS mailbox empty wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " [59] ,DSS to MSS mailbox full wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 26. " [58] ,MSS_DMM2 level -1 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,MSS_DMM2 level -0 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,MSS_DTHE (crypto/AES) AES-P module wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,MSS_DTHE (crypto/AES) AES-S module wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [53] ,MSS_DTHE (crypto/PKA) PKA module wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 20. " [52] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ1 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " [51] ,MSS_DMA2 bus error wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,MSS_DMA2 block transfer complete wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,MSS_DMA2 half-block transfer complete wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [48] ,MSS_GIO wake-up GPIO_2_host_interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " [47] ,Floating point unit wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,MSS_DMA2 last frame complete wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " [43] ,MSS_DMM level -1 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,MSS_DMA2 frame block transfer complete wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,MSS_DMA block transfer complete wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " [39] ,MSS_DMA half-block transfer complete wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [38] ,MSS_DTHE (crypto/TRNG) TRNG wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,MSS_DTHE (crypto/SHA) SHA -P wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,MSS_DMM level -0 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,MSS_DMA last frame transfer start wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,MSS_DMA frame transfer complete wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,MSS_GIO wake-up GPIO_1_host_interrupt clear enable" "Disabled,Enabled"
|
|
line.long 0x08 "WAKEENACLR2,Wake-Up Enable Clear Register 2"
|
|
bitfld.long 0x08 31. " WAKEENACLR2_[95] ,RADARSS to MSS mailbox wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,GEM IRQ-7/MSS_DMM wake-up interrupt 32 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,MSS_PBIST wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Software-triggered wake-up interrupt 5 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " [83] ,MSS_DCCB (dual clock compare) module2-done wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 18. " [82] ,MSS_DCCA (dual clock compare) module1-done wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " [79] ,Software-triggered wake-up interrupt 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Software-triggered wake-up interrupt 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Software-triggered wake-up interrupt 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Software-triggered wake-up interrupt 0 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " [75] ,MSS_SCIB (UART2) level 1 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,MSS_SCIA (UART1) level 1 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,MSS_DMM wake-up interrupt 33 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " [71] ,MSS_DMM interrupt 30 or radar subsystem logical frame start wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,MSS_DMA bus error wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " [69] ,MSS_DMM wake-up interrupt 36 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,MSS_DMM wake-up interrupt 35 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " [67] ,MSS_DMM wake-up interrupt 34 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,MSS_I2C wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,MSS_SCIB (UART2) level 0 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 0. " [64] ,MSS_SCIA (UART1) level 0 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
line.long 0x0C "WAKEENACLR3,Wake-Up Enable Clear Register 3"
|
|
bitfld.long 0x0C 31. " WAKEENACLR3_[127] ,DSS_HW_ACC FFT accelerator -access error wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,DSS_HW_ACC FFT accelerator - done wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,DSS_HW_ACC FFT accelerator -param done wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,MSS_PBIST: gem MSS_STC done wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " [123] ,Chirp available interrupt/MSS_DMM wake-up interrupt 31 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 25. " [121] ,MSS_DMM interrupt 37 wake-up clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,DSS_CBUFF (common buffer) error wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,DSS_CBUFF (common buffer) interrupt wake-up clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,DSS_TPCC (EDMA TPCC0) error wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,DSS_TPCC (EDMA TPCC0) wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 19. " [115] ,DSS_TPTC1 (EDMA TPTC1) error wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,DSS_TPTC1 (EDMA TPTC1) wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,DSS_TPTC0 (EDMA TPTC0) error wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,DSS_TPTC0 (EDMA TPTC0) wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " [111] ,ePWM3 wake-up interrupt-2 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 14. " [110] ,ePWM3 wake-up interrupt-1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,ePWM2 wake-up interrupt-2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,ePWM2 wake-up interrupt-1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " [107] ,ePWM1 wake-up interrupt-2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,All RadarSS wake-up interrupts combined clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 9. " [105] ,MSS_STC done wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,ePWM1 wake-up interrupt-1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Frame end wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Chirp end wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " [99] ,Chirp start wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " [98] ,MSS_DMM interrupt 29/frame start wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,ADC valid fall wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,RADARSS mailbox read complete wake-up interrupt sent from RADARSS to MSS clear enable" "Disabled,Enabled"
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "IRQVECREG,IRQ Interrupt Vector Register"
|
|
line.long 0x04 "FIQVECREG,IRQ Interrupt Vector Register"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CAPEVT,Capture Event Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAPEVTSRC1 ,Capture event source 1 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAPEVTSRC0 ,Capture event source 0 mapping control"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CHANCTRL0,Interrupt Control Register 0"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP0 ,Interrupt CHAN0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP1 ,Interrupt CHAN1 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP2 ,Interrupt CHAN2 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP3 ,Interrupt CHAN3 mapping control"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CHANCTRL1,Interrupt Control Register 1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP4 ,Interrupt CHAN4 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP5 ,Interrupt CHAN5 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP6 ,Interrupt CHAN6 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP7 ,Interrupt CHAN7 mapping control"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CHANCTRL2,Interrupt Control Register 2"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP8 ,Interrupt CHAN8 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP9 ,Interrupt CHAN9 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP10 ,Interrupt CHAN10 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP11 ,Interrupt CHAN11 mapping control"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANCTRL3,Interrupt Control Register 3"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP12 ,Interrupt CHAN12 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP13 ,Interrupt CHAN13 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP14 ,Interrupt CHAN14 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP15 ,Interrupt CHAN15 mapping control"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CHANCTRL4,Interrupt Control Register 4"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP16 ,Interrupt CHAN16 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP17 ,Interrupt CHAN17 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP18 ,Interrupt CHAN18 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP19 ,Interrupt CHAN19 mapping control"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CHANCTRL5,Interrupt Control Register 5"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP20 ,Interrupt CHAN20 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP21 ,Interrupt CHAN21 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP22 ,Interrupt CHAN22 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP23 ,Interrupt CHAN23 mapping control"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CHANCTRL6,Interrupt Control Register 6"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP24 ,Interrupt CHAN24 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP25 ,Interrupt CHAN25 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP26 ,Interrupt CHAN26 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP27 ,Interrupt CHAN27 mapping control"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CHANCTRL7,Interrupt Control Register 7"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP28 ,Interrupt CHAN28 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP29 ,Interrupt CHAN29 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP30 ,Interrupt CHAN30 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP31 ,Interrupt CHAN31 mapping control"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CHANCTRL8,Interrupt Control Register 8"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP32 ,Interrupt CHAN32 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP33 ,Interrupt CHAN33 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP34 ,Interrupt CHAN34 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP35 ,Interrupt CHAN35 mapping control"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CHANCTRL9,Interrupt Control Register 9"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP36 ,Interrupt CHAN36 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP37 ,Interrupt CHAN37 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP38 ,Interrupt CHAN38 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP39 ,Interrupt CHAN39 mapping control"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CHANCTRL10,Interrupt Control Register 10"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP40 ,Interrupt CHAN40 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP41 ,Interrupt CHAN41 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP42 ,Interrupt CHAN42 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP43 ,Interrupt CHAN43 mapping control"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CHANCTRL11,Interrupt Control Register 11"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP44 ,Interrupt CHAN44 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP45 ,Interrupt CHAN45 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP46 ,Interrupt CHAN46 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP47 ,Interrupt CHAN47 mapping control"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "CHANCTRL12,Interrupt Control Register 12"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP48 ,Interrupt CHAN48 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP49 ,Interrupt CHAN49 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP50 ,Interrupt CHAN50 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP51 ,Interrupt CHAN51 mapping control"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CHANCTRL13,Interrupt Control Register 13"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP52 ,Interrupt CHAN52 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP53 ,Interrupt CHAN53 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP54 ,Interrupt CHAN54 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP55 ,Interrupt CHAN55 mapping control"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "CHANCTRL14,Interrupt Control Register 14"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP56 ,Interrupt CHAN56 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP57 ,Interrupt CHAN57 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP58 ,Interrupt CHAN58 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP59 ,Interrupt CHAN59 mapping control"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "CHANCTRL15,Interrupt Control Register 15"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP60 ,Interrupt CHAN60 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP61 ,Interrupt CHAN61 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP62 ,Interrupt CHAN62 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP63 ,Interrupt CHAN63 mapping control"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CHANCTRL16,Interrupt Control Register 16"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP64 ,Interrupt CHAN64 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP65 ,Interrupt CHAN65 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP66 ,Interrupt CHAN66 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP67 ,Interrupt CHAN67 mapping control"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CHANCTRL17,Interrupt Control Register 17"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP68 ,Interrupt CHAN68 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP69 ,Interrupt CHAN69 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP70 ,Interrupt CHAN70 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP71 ,Interrupt CHAN71 mapping control"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CHANCTRL18,Interrupt Control Register 18"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP72 ,Interrupt CHAN72 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP73 ,Interrupt CHAN73 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP74 ,Interrupt CHAN74 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP75 ,Interrupt CHAN75 mapping control"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CHANCTRL19,Interrupt Control Register 19"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP76 ,Interrupt CHAN76 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP77 ,Interrupt CHAN77 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP78 ,Interrupt CHAN78 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP79 ,Interrupt CHAN79 mapping control"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CHANCTRL20,Interrupt Control Register 20"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP80 ,Interrupt CHAN80 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP81 ,Interrupt CHAN81 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP82 ,Interrupt CHAN82 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP83 ,Interrupt CHAN83 mapping control"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "CHANCTRL21,Interrupt Control Register 21"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP84 ,Interrupt CHAN84 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP85 ,Interrupt CHAN85 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP86 ,Interrupt CHAN86 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP87 ,Interrupt CHAN87 mapping control"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CHANCTRL22,Interrupt Control Register 22"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP88 ,Interrupt CHAN88 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP89 ,Interrupt CHAN89 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP90 ,Interrupt CHAN90 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP91 ,Interrupt CHAN91 mapping control"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "CHANCTRL23,Interrupt Control Register 23"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP92 ,Interrupt CHAN92 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP93 ,Interrupt CHAN93 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP94 ,Interrupt CHAN94 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP95 ,Interrupt CHAN95 mapping control"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "CHANCTRL24,Interrupt Control Register 24"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP96 ,Interrupt CHAN96 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP97 ,Interrupt CHAN97 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP98 ,Interrupt CHAN98 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP99 ,Interrupt CHAN99 mapping control"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CHANCTRL25,Interrupt Control Register 25"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP100 ,Interrupt CHAN100 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP101 ,Interrupt CHAN101 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP102 ,Interrupt CHAN102 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP103 ,Interrupt CHAN103 mapping control"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "CHANCTRL26,Interrupt Control Register 26"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP104 ,Interrupt CHAN104 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP105 ,Interrupt CHAN105 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP106 ,Interrupt CHAN106 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP107 ,Interrupt CHAN107 mapping control"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "CHANCTRL27,Interrupt Control Register 27"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP108 ,Interrupt CHAN108 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP109 ,Interrupt CHAN109 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP110 ,Interrupt CHAN110 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP111 ,Interrupt CHAN111 mapping control"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CHANCTRL28,Interrupt Control Register 28"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP112 ,Interrupt CHAN112 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP113 ,Interrupt CHAN113 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP114 ,Interrupt CHAN114 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP115 ,Interrupt CHAN115 mapping control"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "CHANCTRL29,Interrupt Control Register 29"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP116 ,Interrupt CHAN116 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP117 ,Interrupt CHAN117 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP118 ,Interrupt CHAN118 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP119 ,Interrupt CHAN119 mapping control"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "CHANCTRL30,Interrupt Control Register 30"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP120 ,Interrupt CHAN120 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP121 ,Interrupt CHAN121 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP122 ,Interrupt CHAN122 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP123 ,Interrupt CHAN123 mapping control"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CHANCTRL31,Interrupt Control Register 31"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP124 ,Interrupt CHAN124 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP125 ,Interrupt CHAN125 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP126 ,Interrupt CHAN126 mapping control"
|
|
width 0x0B
|
|
tree.end
|
|
elif cpuis("AWR6843*")
|
|
tree "VIM (Vectored Interrupt Manager)"
|
|
base ad:0xFFFFFD00
|
|
width 13.
|
|
group.long 0xEC++0x07
|
|
line.long 0x00 "ECCSTAT,Interrupt Vector Table ECC Status Register"
|
|
eventfld.long 0x00 8. " SBERR ,Single bit error" "No error,Error"
|
|
eventfld.long 0x00 0. " UERR ,Double bit error" "No error,Error"
|
|
line.long 0x04 "ECCCTL,Interrupt Vector Table ECC Control Register"
|
|
bitfld.long 0x04 24.--27. " SBE_EVT_EN ,Control the generation of error signal out based on SBE" ",,,,,Disabled,,,,,Enabled,?..."
|
|
bitfld.long 0x04 16.--19. " EDAC_MODE ,Enable SBE correction" ",,,,,Disabled,,,,,Enabled,?..."
|
|
bitfld.long 0x04 8.--11. " TEST_DIAG_EN ,Memory mapping of ECC bits for read/write operation" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x04 0.--3. " ECCENA ,VIM ECC enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "UERRADDR,Uncorrectable Error Address Register"
|
|
hexmask.long.tbyte 0x00 10.--31. 0x04 " INTVECTOFF ,Interrupt vector table offset"
|
|
hexmask.long.word 0x00 2.--9. 0x04 " ADDERR ,Uncorrectable error address register"
|
|
bitfld.long 0x00 0.--1. " WO ,Word offset" "0,?..."
|
|
group.long 0xF8++0x07
|
|
line.long 0x00 "FBVECADDR,Fallback Vector Address Register"
|
|
line.long 0x04 "SBERRADDR,Single Bit Error Address Register"
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "IRQINDEX,IRQ Index Offset Vector Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRQINDEX ,IRQ index vector"
|
|
line.long 0x04 "FIQINDEX,FIQ Index Offset Vector Register"
|
|
hexmask.long.byte 0x04 0.--7. 0x01 " FIQINDEX ,FIQ index offset vector"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "FIRQPR0,FIQ/IRQ Program Control Register 0"
|
|
bitfld.long 0x00 31. " FIRQPR0_[31] ,MSS_DTHE (crypto/SHA) SHA -S interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 30. " [30] ,MSS_MIBSPIB level 1 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 28. " [28] ,MSS_DMM S/W interrupt 38" "IRQ,FIQ"
|
|
bitfld.long 0x00 27. " [27] ,MSS_QSPI interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 26. " [26] ,MSS_MIBSPIA level 0 interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,MSS_RTIB (WDT/RTIB) TB base interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 24. " [24] ,MSS_RTIB (WDT/RTIB) overflow interrupt 1 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 23. " [23] ,MSS_GIO low-level interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 22. " [22] ,MSS Cortex R4F interrupt PMU type" "IRQ,FIQ"
|
|
bitfld.long 0x00 21. " [21] ,Software-triggered interrupt 4 type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 20. " [20] ,MSS_ESM low-level interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 19. " [19] ,MSS_MCRC (CRC) interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 18. " [18] ,MSS_GIO GPIO_0_host_interrup type" "IRQ,FIQ"
|
|
bitfld.long 0x00 17. " [17] ,MSS_MIBSPIB level 0 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 15. " [15] ,MSS_RTIB (WDT/RTIB) overflow interrupt 0 type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 14. " [14] ,MSS_RTIB (WDT/RTIB) interrupt 3 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 13. " [13] ,MSS_RTIB (WDT/RTIB) interrupt 2 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 12. " [12] ,MSS_MIBSPIA level 0 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 11. " [11] ,MSS_RTIB (WDT/RTIB) interrupt 1 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 10. " [10] ,MSS_RTIB (WDT/RTIB) interrupt 0 type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,MSS_GIO high-level interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x00 8. " [8] ,MSS_RTIA time-base type" "IRQ,FIQ"
|
|
bitfld.long 0x00 7. " [7] ,MSS_RTIA overflow interrupt 1 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 6. " [6] ,MSS_RTIA overflow interrupt 0 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 5. " [5] ,MSS_RTIA compare interrupt 3 type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,MSS_RTIA compare interrupt 2 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 3. " [3] ,MSS_RTIA compare interrupt 1 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 2. " [2] ,MSS_RTIA compare interrupt 0 type" "IRQ,FIQ"
|
|
bitfld.long 0x00 0. " [0] ,MSS_ESM high-level interrupt(NMI)" "IRQ,FIQ"
|
|
line.long 0x04 "FIRQPR1,FIQ/IRQ Program Control Register 1"
|
|
bitfld.long 0x04 31. " FIRQPR1_[63] ,GEM MSS_STC done interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 30. " [62] ,MSS_DEBUGSS (debug subsystem) interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 29. " [61] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ2 type" "IRQ,FIQ"
|
|
bitfld.long 0x04 28. " [60] ,DSS to MSS mailbox empty interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 27. " [59] ,DSS to MSS mailbox full interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 26. " [58] ,MSS_DMM2 level -1 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 25. " [57] ,MSS_DMM2 level -0 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 24. " [56] ,MSS_DTHE (crypto/AES) AES-P module interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 23. " [55] ,MSS_MCAN (crypto/AES) AES-P module interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 22. " [54] ,MSS_DTHE (crypto/AES) AES-S module interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 21. " [53] ,MSS_DTHE (crypto/PKA) PKA module interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 20. " [52] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ1 type" "IRQ,FIQ"
|
|
bitfld.long 0x04 19. " [51] ,MSS_DMA2 bus error interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 18. " [50] ,MSS_DMA2 block transfer complete interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 17. " [49] ,MSS_DMA2 half-block transfer complete interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 16. " [48] ,MSS_GIO GPIO_2_host_interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 15. " [47] ,Floating point unit interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 14. " [46] ,MSS_MCAN last frame complete interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 13. " [45] ,MSS_DMA2 last frame complete interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 12. " [44] ,MSS_MCAN last frame complete interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 11. " [43] ,MSS_DMM level -1 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 10. " [42] ,MSS_MCAN level -1 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 9. " [41] ,MSS_DMA2 frame block transfer complete interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 8. " [40] ,MSS_DMA block transfer complete interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 7. " [39] ,MSS_DMA half-block transfer complete interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 6. " [38] ,MSS_DTHE (crypto/TRNG) TRNG interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 5. " [37] ,MSS_DTHE (crypto/SHA) SHA -P interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 4. " [36] ,MSS_DMM level -0 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 3. " [35] ,MSS_MCAN level -0 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 2. " [34] ,MSS_DMA last frame transfer start interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,MSS_DMA frame transfer complete interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x04 0. " [32] ,MSS_GIO GPIO_1_host_interrupt type" "IRQ,FIQ"
|
|
line.long 0x08 "FIRQPR2,FIQ/IRQ Program Control Register 2"
|
|
bitfld.long 0x08 31. " FIRQPR2_[95] ,RADARSS to MSS mailbox interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x08 22. " [86] ,GEM IRQ-7/MSS_DMM interrupt 32 type" "IRQ,FIQ"
|
|
bitfld.long 0x08 21. " [85] ,MSS_PBIST interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x08 20. " [84] ,Software-triggered interrupt 5 type" "IRQ,FIQ"
|
|
bitfld.long 0x08 19. " [83] ,MSS_DCCB (dual clock compare) module2-done interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 18. " [82] ,MSS_DCCA (dual clock compare) module1-done interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x08 15. " [79] ,Software-triggered interrupt 3 type" "IRQ,FIQ"
|
|
bitfld.long 0x08 14. " [78] ,Software-triggered interrupt 2 type" "IRQ,FIQ"
|
|
bitfld.long 0x08 13. " [77] ,Software-triggered interrupt 1 type" "IRQ,FIQ"
|
|
bitfld.long 0x08 12. " [76] ,Software-triggered interrupt 0 type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 11. " [75] ,MSS_SCIB (UART2) level 1 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x08 10. " [74] ,MSS_SCIA (UART1) level 1 interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x08 9. " [73] ,MSS_DMM interrupt 33 type" "IRQ,FIQ"
|
|
bitfld.long 0x08 7. " [71] ,MSS_DMM interrupt 30 or radar subsystem logical frame start type" "IRQ,FIQ"
|
|
bitfld.long 0x08 6. " [70] ,MSS_DMA bus error interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 5. " [69] ,MSS_DMM interrupt 36 type" "IRQ,FIQ"
|
|
bitfld.long 0x08 4. " [68] ,MSS_DMM interrupt 35 type" "IRQ,FIQ"
|
|
bitfld.long 0x08 3. " [67] ,MSS_DMM interrupt 34 type" "IRQ,FIQ"
|
|
bitfld.long 0x08 2. " [66] ,MSS_I2C interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x08 1. " [65] ,MSS_SCIB (UART2) level 0 interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 0. " [64] ,MSS_SCIA (UART1) level 0 interrupt type" "IRQ,FIQ"
|
|
line.long 0x0C "FIRQPR3,FIQ/IRQ Program Control Register 3"
|
|
bitfld.long 0x0C 31. " FIRQPR3_[127] ,DSS_HW_ACC FFT accelerator access error interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 30. " [126] ,DSS_HW_ACC FFT accelerator - done interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 29. " [125] ,DSS_HW_ACC FFT accelerator -param done interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 28. " [124] ,MSS_PBIST: gem MSS_STC done type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 27. " [123] ,Chirp available interrupt/MSS_DMM interrupt 31 type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 25. " [121] ,MSS_DMM interrupt 37 type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 24. " [120] ,DSS_CBUFF (common buffer) error interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 22. " [118] ,DSS_CBUFF (common buffer) interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 21. " [117] ,DSS_TPCC (EDMA TPCC0) error interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 20. " [116] ,DSS_TPCC (EDMA TPCC0) interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 19. " [115] ,DSS_TPTC1 (EDMA TPTC1) error interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 18. " [114] ,DSS_TPTC1 (EDMA TPTC1) interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 17. " [113] ,DSS_TPTC0 (EDMA TPTC0) error interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 16. " [112] ,DSS_TPTC0 (EDMA TPTC0) interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 15. " [111] ,ePWM3 interrupt-2 type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 14. " [110] ,ePWM3 interrupt-1 type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 13. " [109] ,ePWM2 interrupt-2 type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 12. " [108] ,ePWM2 interrupt-1 type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 11. " [107] ,ePWM1 interrupt-2 type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 10. " [106] ,All RadarSS interrupts combined type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 9. " [105] ,MSS_STC done interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 8. " [104] ,ePWM1 interrupt-1 type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 5. " [101] ,Frame end interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 4. " [100] ,Chirp end interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 3. " [99] ,Chirp start interrupt type" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 2. " [98] ,MSS_DMM interrupt 29/frame start interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 1. " [97] ,ADC valid fall interrupt type" "IRQ,FIQ"
|
|
bitfld.long 0x0C 0. " [96] ,RADARSS mailbox read complete interrupt sent from RADARSS to MSS type" "IRQ,FIQ"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "INTREQ0,Pending Interrupt Read Location Register 0"
|
|
eventfld.long 0x00 31. " INTREQ0_[31] ,MSS_DTHE (crypto/SHA) SHA -S interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " [30] ,MSS_MIBSPIB level 1 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " [28] ,MSS_DMM S/W interrupt 38" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 27. " [27] ,MSS_QSPI interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " [26] ,MSS_MIBSPIA level 0 interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 25. " [25] ,MSS_RTIB (WDT/RTIB) TB base interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " [24] ,MSS_RTIB (WDT/RTIB) overflow interrupt 1 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " [23] ,MSS_GIO low-level interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " [22] ,MSS Cortex R4F interrupt PMU pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " [21] ,Software-triggered interrupt 4 pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 20. " [20] ,MSS_ESM low-level interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " [19] ,MSS_MCRC (CRC) interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " [18] ,MSS_GIO GPIO_0_host_interrup pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " [17] ,MSS_MIBSPIB level 0 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " [15] ,MSS_RTIB (WDT/RTIB) overflow interrupt 0 pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 14. " [14] ,MSS_RTIB (WDT/RTIB) interrupt 3 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " [13] ,MSS_RTIB (WDT/RTIB) interrupt 2 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [12] ,MSS_MIBSPIA level 0 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " [11] ,MSS_RTIB (WDT/RTIB) interrupt 1 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,MSS_RTIB (WDT/RTIB) interrupt 0 pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 9. " [9] ,MSS_GIO high-level interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " [8] ,MSS_RTIA time-base pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " [7] ,MSS_RTIA overflow interrupt 1 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " [6] ,MSS_RTIA overflow interrupt 0 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " [5] ,MSS_RTIA compare interrupt 3 pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 4. " [4] ,MSS_RTIA compare interrupt 2 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " [3] ,MSS_RTIA compare interrupt 1 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,MSS_RTIA compare interrupt 0 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " [0] ,MSS_ESM high-level interrupt(NMI) pending" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTREQ1,Pending Interrupt Read Location Register 1"
|
|
eventfld.long 0x04 31. " INTREQ1_[63] ,GEM MSS_STC done interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 30. " [62] ,MSS_DEBUGSS (debug subsystem) interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 29. " [61] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ2 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 28. " [60] ,DSS to MSS mailbox empty interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 27. " [59] ,DSS to MSS mailbox full interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 26. " [58] ,MSS_DMM2 level -1 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 25. " [57] ,MSS_DMM2 level -0 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 24. " [56] ,MSS_DTHE (crypto/AES) AES-P module interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 23. " [55] ,MSS_MCAN (crypto/AES) AES-P module interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 22. " [54] ,MSS_DTHE (crypto/AES) AES-S module interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 21. " [53] ,MSS_DTHE (crypto/PKA) PKA module interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 20. " [52] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ1 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 19. " [51] ,MSS_DMA2 bus error interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 18. " [50] ,MSS_DMA2 block transfer complete interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 17. " [49] ,MSS_DMA2 half-block transfer complete interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 16. " [48] ,MSS_GIO GPIO_2_host_interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 15. " [47] ,Floating point unit interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 14. " [46] ,MSS_MCAN last frame complete interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 13. " [45] ,MSS_DMA2 last frame complete interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 12. " [44] ,MSS_MCAN last frame complete interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 11. " [43] ,MSS_DMM level -1 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 10. " [42] ,MSS_MCAN level -1 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 9. " [41] ,MSS_DMA2 frame block transfer complete interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 8. " [40] ,MSS_DMA block transfer complete interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 7. " [39] ,MSS_DMA half-block transfer complete interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 6. " [38] ,MSS_DTHE (crypto/TRNG) TRNG interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " [37] ,MSS_DTHE (crypto/SHA) SHA -P interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 4. " [36] ,MSS_DMM level -0 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " [35] ,MSS_MCAN level -0 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " [34] ,MSS_DMA last frame transfer start interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 1. " [33] ,MSS_DMA frame transfer complete interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 0. " [32] ,MSS_GIO GPIO_1_host_interrupt pending" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTREQ2,Pending Interrupt Read Location Register 2"
|
|
eventfld.long 0x08 31. " INTREQ2_[95] ,RADARSS to MSS mailbox interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 22. " [86] ,GEM IRQ-7/MSS_DMM interrupt 32 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 21. " [85] ,MSS_PBIST interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 20. " [84] ,Software-triggered interrupt 5 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 19. " [83] ,MSS_DCCB (dual clock compare) module2-done interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 18. " [82] ,MSS_DCCA (dual clock compare) module1-done interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 15. " [79] ,Software-triggered interrupt 3 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 14. " [78] ,Software-triggered interrupt 2 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 13. " [77] ,Software-triggered interrupt 1 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 12. " [76] ,Software-triggered interrupt 0 pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 11. " [75] ,MSS_SCIB (UART2) level 1 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 10. " [74] ,MSS_SCIA (UART1) level 1 interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 9. " [73] ,MSS_DMM interrupt 33 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " [71] ,MSS_DMM interrupt 30 or radar subsystem logical frame start pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " [70] ,MSS_DMA bus error interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 5. " [69] ,MSS_DMM interrupt 36 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " [68] ,MSS_DMM interrupt 35 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " [67] ,MSS_DMM interrupt 34 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " [66] ,MSS_I2C interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 1. " [65] ,MSS_SCIB (UART2) level 0 interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 0. " [64] ,MSS_SCIA (UART1) level 0 interrupt pending" "No interrupt,Interrupt"
|
|
line.long 0x0C "INTREQ3,Pending Interrupt Read Location Register 3"
|
|
eventfld.long 0x0C 31. " INTREQ3_[127] ,DSS_HW_ACC FFT accelerator access error interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 30. " [126] ,DSS_HW_ACC FFT accelerator - done interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 29. " [125] ,DSS_HW_ACC FFT accelerator -param done interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 28. " [124] ,MSS_PBIST: gem MSS_STC done pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 27. " [123] ,Chirp available interrupt/MSS_DMM interrupt 31 pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 25. " [121] ,MSS_DMM interrupt 37 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 24. " [120] ,DSS_CBUFF (common buffer) error interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 22. " [118] ,DSS_CBUFF (common buffer) interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 21. " [117] ,DSS_TPCC (EDMA TPCC0) error interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 20. " [116] ,DSS_TPCC (EDMA TPCC0) interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 19. " [115] ,DSS_TPTC1 (EDMA TPTC1) error interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 18. " [114] ,DSS_TPTC1 (EDMA TPTC1) interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 17. " [113] ,DSS_TPTC0 (EDMA TPTC0) error interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 16. " [112] ,DSS_TPTC0 (EDMA TPTC0) interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 15. " [111] ,ePWM3 interrupt-2 pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 14. " [110] ,ePWM3 interrupt-1 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 13. " [109] ,ePWM2 interrupt-2 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " [108] ,ePWM2 interrupt-1 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 11. " [107] ,ePWM1 interrupt-2 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " [106] ,All RadarSS interrupts combined pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 9. " [105] ,MSS_STC done interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " [104] ,ePWM1 interrupt-1 pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 5. " [101] ,Frame end interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " [100] ,Chirp end interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 3. " [99] ,Chirp start interrupt pending" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 2. " [98] ,MSS_DMM interrupt 29/frame start interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 1. " [97] ,ADC valid fall interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " [96] ,RADARSS mailbox read complete interrupt sent from RADARSS to MSS pending" "No interrupt,Interrupt"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "REQENASET0,Interrupt Enable Set Register 0"
|
|
bitfld.long 0x00 31. " REQENASET0_[31] ,MSS_DTHE (crypto/SHA) SHA -S interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,MSS_MIBSPIB level 1 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,MSS_DMM S/W interrupt 38" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,MSS_QSPI interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,MSS_MIBSPIA level 0 interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,MSS_RTIB (WDT/RTIB) TB base interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,MSS_RTIB (WDT/RTIB) overflow interrupt 1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,MSS_GIO low-level interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,MSS Cortex R4F interrupt PMU set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Software-triggered interrupt 4 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " [20] ,MSS_ESM low-level interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,MSS_MCRC (CRC) interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,MSS_GIO GPIO_0_host_interrup set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,MSS_MIBSPIB level 0 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,MSS_RTIB (WDT/RTIB) overflow interrupt 0 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " [14] ,MSS_RTIB (WDT/RTIB) interrupt 3 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,MSS_RTIB (WDT/RTIB) interrupt 2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,MSS_MIBSPIA level 0 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,MSS_RTIB (WDT/RTIB) interrupt 1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,MSS_RTIB (WDT/RTIB) interrupt 0 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,MSS_GIO high-level interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,MSS_RTIA time-base set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,MSS_RTIA overflow interrupt 1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,MSS_RTIA overflow interrupt 0 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,MSS_RTIA compare interrupt 3 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,MSS_RTIA compare interrupt 2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,MSS_RTIA compare interrupt 1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,MSS_RTIA compare interrupt 0 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,MSS_ESM high-level interrupt(NMI) set enable" "Disabled,Enabled"
|
|
line.long 0x04 "REQENASET1,Interrupt Set Enable Register 1"
|
|
bitfld.long 0x04 31. " REQENASET1_[63] ,GEM MSS_STC done interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,MSS_DEBUGSS (debug subsystem) interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,DSS to MSS mailbox empty interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " [59] ,DSS to MSS mailbox full interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 26. " [58] ,MSS_DMM2 level -1 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,MSS_DMM2 level -0 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,MSS_DTHE (crypto/AES) AES-P module interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " [55] ,MSS_MCAN (crypto/AES) AES-P module interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,MSS_DTHE (crypto/AES) AES-S module interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 21. " [53] ,MSS_DTHE (crypto/PKA) PKA module interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " [51] ,MSS_DMA2 bus error interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,MSS_DMA2 block transfer complete interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,MSS_DMA2 half-block transfer complete interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " [48] ,MSS_GIO GPIO_2_host_interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " [47] ,Floating point unit interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,MSS_MCAN last frame complete interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,MSS_DMA2 last frame complete interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,MSS_MCAN last frame complete interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [43] ,MSS_DMM level -1 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,MSS_MCAN level -1 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,MSS_DMA2 frame block transfer complete interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,MSS_DMA block transfer complete interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " [39] ,MSS_DMA half-block transfer complete interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 6. " [38] ,MSS_DTHE (crypto/TRNG) TRNG interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,MSS_DTHE (crypto/SHA) SHA -P interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,MSS_DMM level -0 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " [35] ,MSS_MCAN level -0 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,MSS_DMA last frame transfer start interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,MSS_DMA frame transfer complete interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,MSS_GIO GPIO_1_host_interrupt set enable" "Disabled,Enabled"
|
|
line.long 0x08 "REQENASET2,Interrupt Set Enable Register 2"
|
|
bitfld.long 0x08 31. " REQENASET2_[95] ,RADARSS to MSS mailbox interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,GEM IRQ-7/MSS_DMM interrupt 32 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,MSS_PBIST interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Software-triggered interrupt 5 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " [83] ,MSS_DCCB (dual clock compare) module2-done interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 18. " [82] ,MSS_DCCA (dual clock compare) module1-done interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " [79] ,Software-triggered interrupt 3 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Software-triggered interrupt 2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Software-triggered interrupt 1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Software-triggered interrupt 0 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " [75] ,MSS_SCIB (UART2) level 1 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,MSS_SCIA (UART1) level 1 interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,MSS_DMM interrupt 33 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " [71] ,MSS_DMM interrupt 30 or radar subsystem logical frame start set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,MSS_DMA bus error interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " [69] ,MSS_DMM interrupt 36 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,MSS_DMM interrupt 35 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " [67] ,MSS_DMM interrupt 34 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,MSS_I2C interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,MSS_SCIB (UART2) level 0 interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 0. " [64] ,MSS_SCIA (UART1) level 0 interrupt set enable" "Disabled,Enabled"
|
|
line.long 0x0C "REQENASET3,Interrupt Set Enable Register 3"
|
|
bitfld.long 0x0C 31. " REQENASET3_[127] ,DSS_HW_ACC FFT accelerator -access error interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,DSS_HW_ACC FFT accelerator - done interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,DSS_HW_ACC FFT accelerator -param done interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,MSS_PBIST: gem MSS_STC done set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " [123] ,Chirp available interrupt/MSS_DMM interrupt 31 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 25. " [121] ,MSS_DMM interrupt 37 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,DSS_CBUFF (common buffer) error interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,DSS_CBUFF (common buffer) interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,DSS_TPCC (EDMA TPCC0) error interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,DSS_TPCC (EDMA TPCC0) interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 19. " [115] ,DSS_TPTC1 (EDMA TPTC1) error interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,DSS_TPTC1 (EDMA TPTC1) interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,DSS_TPTC0 (EDMA TPTC0) error interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,DSS_TPTC0 (EDMA TPTC0) interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " [111] ,ePWM3 interrupt-2 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 14. " [110] ,ePWM3 interrupt-1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,ePWM2 interrupt-2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,ePWM2 interrupt-1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " [107] ,ePWM1 interrupt-2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,All RadarSS interrupts combined set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 9. " [105] ,MSS_STC done interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,ePWM1 interrupt-1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Frame end interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Chirp end interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " [99] ,Chirp start interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " [98] ,MSS_DMM interrupt 29/frame start interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,ADC valid fall interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,RADARSS mailbox read complete interrupt sent from RADARSS to MSS set enable" "Disabled,Enabled"
|
|
group.long 0x40++0x0F
|
|
line.long 0x00 "REQENACLR0,Interrupt Enable Clear Register 0"
|
|
bitfld.long 0x00 31. " REQENACLR0_[31] ,MSS_DTHE (crypto/SHA) SHA -S interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,MSS_MIBSPIB level 1 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,MSS_DMM S/W interrupt 38" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,MSS_QSPI interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,MSS_MIBSPIA level 0 interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,MSS_RTIB (WDT/RTIB) TB base interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,MSS_RTIB (WDT/RTIB) overflow interrupt 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,MSS_GIO low-level interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,MSS Cortex R4F interrupt PMU clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Software-triggered interrupt 4 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " [20] ,MSS_ESM low-level interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,MSS_MCRC (CRC) interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,MSS_GIO GPIO_0_host_interrup clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,MSS_MIBSPIB level 0 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,MSS_RTIB (WDT/RTIB) overflow interrupt 0 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " [14] ,MSS_RTIB (WDT/RTIB) interrupt 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,MSS_RTIB (WDT/RTIB) interrupt 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,MSS_MIBSPIA level 0 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,MSS_RTIB (WDT/RTIB) interrupt 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,MSS_RTIB (WDT/RTIB) interrupt 0 clear enable" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x00 9. " [9] ,MSS_GIO high-level interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,MSS_RTIA time-base clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,MSS_RTIA overflow interrupt 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,MSS_RTIA overflow interrupt 0 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,MSS_RTIA compare interrupt 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,MSS_RTIA compare interrupt 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,MSS_RTIA compare interrupt 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,MSS_RTIA compare interrupt 0 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,MSS_ESM high-level interrupt(NMI) clear enable" "Disabled,Enabled"
|
|
line.long 0x04 "REQENACLR1,Interrupt Clear Enable Register 1"
|
|
bitfld.long 0x04 31. " REQENACLR1_[63] ,GEM MSS_STC done interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,MSS_DEBUGSS (debug subsystem) interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,DSS to MSS mailbox empty interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " [59] ,DSS to MSS mailbox full interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 26. " [58] ,MSS_DMM2 level -1 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,MSS_DMM2 level -0 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,MSS_DTHE (crypto/AES) AES-P module interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " [55] ,MSS_MCAN (crypto/AES) AES-P module interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,MSS_DTHE (crypto/AES) AES-S module interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 21. " [53] ,MSS_DTHE (crypto/PKA) PKA module interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " [51] ,MSS_DMA2 bus error interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,MSS_DMA2 block transfer complete interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,MSS_DMA2 half-block transfer complete interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " [48] ,MSS_GIO GPIO_2_host_interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " [47] ,Floating point unit interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,MSS_MCAN last frame complete interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,MSS_DMA2 last frame complete interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,MSS_MCAN last frame complete interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [43] ,MSS_DMM level -1 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,MSS_MCAN level -1 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,MSS_DMA2 frame block transfer complete interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,MSS_DMA block transfer complete interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " [39] ,MSS_DMA half-block transfer complete interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 6. " [38] ,MSS_DTHE (crypto/TRNG) TRNG interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,MSS_DTHE (crypto/SHA) SHA -P interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,MSS_DMM level -0 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " [35] ,MSS_MCAN level -0 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,MSS_DMA last frame transfer start interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,MSS_DMA frame transfer complete interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,MSS_GIO GPIO_1_host_interrupt clear enable" "Disabled,Enabled"
|
|
line.long 0x08 "REQENACLR2,Interrupt Clear Enable Register 2"
|
|
bitfld.long 0x08 31. " REQENACLR2_[95] ,RADARSS to MSS mailbox interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,GEM IRQ-7/MSS_DMM interrupt 32 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,MSS_PBIST interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Software-triggered interrupt 5 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " [83] ,MSS_DCCB (dual clock compare) module2-done interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 18. " [82] ,MSS_DCCA (dual clock compare) module1-done interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " [79] ,Software-triggered interrupt 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Software-triggered interrupt 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Software-triggered interrupt 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Software-triggered interrupt 0 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " [75] ,MSS_SCIB (UART2) level 1 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,MSS_SCIA (UART1) level 1 interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,MSS_DMM interrupt 33 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " [71] ,MSS_DMM interrupt 30 or radar subsystem logical frame start clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,MSS_DMA bus error interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " [69] ,MSS_DMM interrupt 36 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,MSS_DMM interrupt 35 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " [67] ,MSS_DMM interrupt 34 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,MSS_I2C interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,MSS_SCIB (UART2) level 0 interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 0. " [64] ,MSS_SCIA (UART1) level 0 interrupt clear enable" "Disabled,Enabled"
|
|
line.long 0x0C "REQENACLR3,Interrupt Clear Enable Register 3"
|
|
bitfld.long 0x0C 31. " REQENACLR3_[127] ,DSS_HW_ACC FFT accelerator -access error interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,DSS_HW_ACC FFT accelerator - done interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,DSS_HW_ACC FFT accelerator -param done interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,MSS_PBIST: gem MSS_STC done clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " [123] ,Chirp available interrupt/MSS_DMM interrupt 31 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 25. " [121] ,MSS_DMM interrupt 37 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,DSS_CBUFF (common buffer) error interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,DSS_CBUFF (common buffer) interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,DSS_TPCC (EDMA TPCC0) error interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,DSS_TPCC (EDMA TPCC0) interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 19. " [115] ,DSS_TPTC1 (EDMA TPTC1) error interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,DSS_TPTC1 (EDMA TPTC1) interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,DSS_TPTC0 (EDMA TPTC0) error interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,DSS_TPTC0 (EDMA TPTC0) interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " [111] ,ePWM3 interrupt-2 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 14. " [110] ,ePWM3 interrupt-1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,ePWM2 interrupt-2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,ePWM2 interrupt-1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " [107] ,ePWM1 interrupt-2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,All RadarSS interrupts combined clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 9. " [105] ,MSS_STC done interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,ePWM1 interrupt-1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Frame end interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Chirp end interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " [99] ,Chirp start interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " [98] ,MSS_DMM interrupt 29/frame start interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,ADC valid fall interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,RADARSS mailbox read complete interrupt sent from RADARSS to MSS clear enable" "Disabled,Enabled"
|
|
group.long 0x50++0x0F
|
|
line.long 0x00 "WAKEENASET0,Wake-Up Enable Set Register 0"
|
|
bitfld.long 0x00 31. " WAKEENASET0_[31] ,MSS_DTHE (crypto/SHA) SHA -S wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,MSS_MIBSPIB level 1 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,MSS_DMM S/W interrupt 38" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,MSS_QSPI wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,MSS_MIBSPIA level 0 wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,MSS_RTIB (WDT/RTIB) TB base wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,MSS_RTIB (WDT/RTIB) overflow wake-up interrupt 1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,MSS_GIO low-level wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,MSS Cortex R4F wake-up interrupt PMU set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Software-triggered wake-up interrupt 4 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " [20] ,MSS_ESM low-level wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,MSS_MCRC (CRC) wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,MSS_GIO wake-up GPIO_0_host_interrup set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,MSS_MIBSPIB level 0 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,MSS_RTIB (WDT/RTIB) overflow wake-up interrupt 0 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " [14] ,MSS_RTIB (WDT/RTIB) wake-up interrupt 3 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,MSS_RTIB (WDT/RTIB) interrupt 2 wake-up set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,MSS_MIBSPIA level 0 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,MSS_RTIB (WDT/RTIB) wake-up interrupt 1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,MSS_RTIB (WDT/RTIB) wake-up interrupt 0 set enable" "Disabled,Enabled"
|
|
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|
|
bitfld.long 0x00 9. " [9] ,MSS_GIO high-level wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,MSS_RTIA time-base interrupt wake-up set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,MSS_RTIA overflow wake-up interrupt 1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,MSS_RTIA overflow wake-up interrupt 0 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,MSS_RTIA compare wake-up interrupt 3 set enable" "Disabled,Enabled"
|
|
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|
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bitfld.long 0x00 4. " [4] ,MSS_RTIA compare wake-up interrupt 2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,MSS_RTIA compare wake-up interrupt 1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,MSS_RTIA compare wake-up interrupt 0 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [0] ,MSS_ESM high-level wake-up interrupt(NMI) set enable" "Disabled,Enabled"
|
|
line.long 0x04 "WAKEENASET1,Wake-Up Enable Set Register 1"
|
|
bitfld.long 0x04 31. " WAKEENASET1_[63] ,GEM MSS_STC done wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,MSS_DEBUGSS (debug subsystem) wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ2 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,DSS to MSS mailbox empty wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " [59] ,DSS to MSS mailbox full wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 26. " [58] ,MSS_DMM2 level -1 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,MSS_DMM2 level -0 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,MSS_DTHE (crypto/AES) AES-P module wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " [55] ,MSS_MCAN (crypto/AES) AES-P module wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,MSS_DTHE (crypto/AES) AES-S module wake-up interrupt set enable" "Disabled,Enabled"
|
|
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|
|
bitfld.long 0x04 21. " [53] ,MSS_DTHE (crypto/PKA) PKA module wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ1 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " [51] ,MSS_DMA2 bus error wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,MSS_DMA2 block transfer complete wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,MSS_DMA2 half-block transfer complete wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " [48] ,MSS_GIO wake-up GPIO_2_host_interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " [47] ,Floating point unit wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,MSS_MCAN last frame complete wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,MSS_DMA2 last frame complete wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,MSS_MCAN last frame complete wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [43] ,MSS_DMM level -1 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,MSS_MCAN level -1 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,MSS_DMA2 frame block transfer complete wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,MSS_DMA block transfer complete wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " [39] ,MSS_DMA half-block transfer complete wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 6. " [38] ,MSS_DTHE (crypto/TRNG) TRNG wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,MSS_DTHE (crypto/SHA) SHA -P wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,MSS_DMM level -0 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " [35] ,MSS_MCAN level -0 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,MSS_DMA last frame transfer start wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,MSS_DMA frame transfer complete wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,MSS_GIO wake-up GPIO_1_host_interrupt set enable" "Disabled,Enabled"
|
|
line.long 0x08 "WAKEENASET2,Wake-Up Enable Set Register 2"
|
|
bitfld.long 0x08 31. " WAKEENASET2_[95] ,RADARSS to MSS mailbox wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,GEM IRQ-7/MSS_DMM wake-up interrupt 32 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,MSS_PBIST wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Software-triggered wake-up interrupt 5 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " [83] ,MSS_DCCB (dual clock compare) module2-done wake-up interrupt set enable" "Disabled,Enabled"
|
|
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|
|
bitfld.long 0x08 18. " [82] ,MSS_DCCA (dual clock compare) module1-done wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " [79] ,Software-triggered wake-up interrupt 3 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Software-triggered wake-up interrupt 2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Software-triggered wake-up interrupt 1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Software-triggered wake-up interrupt 0 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " [75] ,MSS_SCIB (UART2) level 1 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,MSS_SCIA (UART1) level 1 wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,MSS_DMM wake-up interrupt 33 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " [71] ,MSS_DMM interrupt 30 or radar subsystem logical frame start wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,MSS_DMA bus error wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x08 5. " [69] ,MSS_DMM wake-up interrupt 36 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,MSS_DMM wake-up interrupt 35 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " [67] ,MSS_DMM wake-up interrupt 34 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,MSS_I2C wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,MSS_SCIB (UART2) level 0 wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x08 0. " [64] ,MSS_SCIA (UART1) level 0 wake-up interrupt set enable" "Disabled,Enabled"
|
|
line.long 0x0C "WAKEENASET3,Wake-Up Enable Set Register 3"
|
|
bitfld.long 0x0C 31. " WAKEENASET3_[127] ,DSS_HW_ACC FFT accelerator -access error wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,DSS_HW_ACC FFT accelerator - done wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,DSS_HW_ACC FFT accelerator -param done wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,MSS_PBIST: gem MSS_STC done wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " [123] ,Chirp available interrupt/MSS_DMM wake-up interrupt 31 set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 25. " [121] ,MSS_DMM interrupt 37 wake-up set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,DSS_CBUFF (common buffer) error wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,DSS_CBUFF (common buffer) interrupt wake-up set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,DSS_TPCC (EDMA TPCC0) error wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,DSS_TPCC (EDMA TPCC0) wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x0C 19. " [115] ,DSS_TPTC1 (EDMA TPTC1) error wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,DSS_TPTC1 (EDMA TPTC1) wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,DSS_TPTC0 (EDMA TPTC0) error wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,DSS_TPTC0 (EDMA TPTC0) wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " [111] ,ePWM3 wake-up interrupt-2 set enable" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x0C 14. " [110] ,ePWM3 wake-up interrupt-1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,ePWM2 wake-up interrupt-2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,ePWM2 wake-up interrupt-1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " [107] ,ePWM1 wake-up interrupt-2 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,All RadarSS wake-up interrupts combined set enable" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x0C 9. " [105] ,MSS_STC done wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,ePWM1 wake-up interrupt-1 set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Frame end wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Chirp end wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " [99] ,Chirp start wake-up interrupt set enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " [98] ,MSS_DMM interrupt 29/frame start wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,ADC valid fall wake-up interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,RADARSS mailbox read complete wake-up interrupt sent from RADARSS to MSS set enable" "Disabled,Enabled"
|
|
group.long 0x60++0x0F
|
|
line.long 0x00 "WAKEENACLR0,Wake-Up Enable Clear Register 0"
|
|
bitfld.long 0x00 31. " WAKEENACLR0_[31] ,MSS_DTHE (crypto/SHA) SHA -S wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,MSS_MIBSPIB level 1 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,MSS_DMM S/W interrupt 38" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,MSS_QSPI wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,MSS_MIBSPIA level 0 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,MSS_RTIB (WDT/RTIB) TB base wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,MSS_RTIB (WDT/RTIB) overflow wake-up interrupt 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,MSS_GIO low-level wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,MSS Cortex R4F wake-up interrupt PMU clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Software-triggered wake-up interrupt 4 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. " [20] ,MSS_ESM low-level wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,MSS_MCRC (CRC) wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,MSS_GIO wake-up GPIO_0_host_interrup clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,MSS_MIBSPIB level 0 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,MSS_RTIB (WDT/RTIB) overflow wake-up interrupt 0 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " [14] ,MSS_RTIB (WDT/RTIB) wake-up interrupt 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,MSS_RTIB (WDT/RTIB) interrupt 2 wake-up clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,MSS_MIBSPIA level 0 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,MSS_RTIB (WDT/RTIB) wake-up interrupt 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,MSS_RTIB (WDT/RTIB) wake-up interrupt 0 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,MSS_GIO high-level wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,MSS_RTIA time-base interrupt wake-up clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,MSS_RTIA overflow wake-up interrupt 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,MSS_RTIA overflow wake-up interrupt 0 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,MSS_RTIA compare wake-up interrupt 3 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,MSS_RTIA compare wake-up interrupt 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,MSS_RTIA compare wake-up interrupt 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,MSS_RTIA compare wake-up interrupt 0 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [0] ,MSS_ESM high-level wake-up interrupt(NMI) clear enable" "Disabled,Enabled"
|
|
line.long 0x04 "WAKEENACLR1,Wake-Up Enable Clear Register 1"
|
|
bitfld.long 0x04 31. " WAKEENACLR1_[63] ,GEM MSS_STC done wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,MSS_DEBUGSS (debug subsystem) wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ2 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,DSS to MSS mailbox empty wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " [59] ,DSS to MSS mailbox full wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 26. " [58] ,MSS_DMM2 level -1 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,MSS_DMM2 level -0 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,MSS_DTHE (crypto/AES) AES-P module wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " [55] ,MSS_MCAN (crypto/AES) AES-P module wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,MSS_DTHE (crypto/AES) AES-S module wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 21. " [53] ,MSS_DTHE (crypto/PKA) PKA module wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,DSS to MSS software-triggered by register DSS_REG2:MSSSWIRQ:MSSSWIRQ1 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " [51] ,MSS_DMA2 bus error wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,MSS_DMA2 block transfer complete wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,MSS_DMA2 half-block transfer complete wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " [48] ,MSS_GIO wake-up GPIO_2_host_interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " [47] ,Floating point unit wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,MSS_MCAN last frame complete interrupt set enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,MSS_DMA2 last frame complete wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,MSS_MCAN last frame complete wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [43] ,MSS_DMM level -1 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,MSS_MCAN level -1 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,MSS_DMA2 frame block transfer complete wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,MSS_DMA block transfer complete wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " [39] ,MSS_DMA half-block transfer complete wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 6. " [38] ,MSS_DTHE (crypto/TRNG) TRNG wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,MSS_DTHE (crypto/SHA) SHA -P wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,MSS_DMM level -0 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " [35] ,MSS_MCAN level -0 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,MSS_DMA last frame transfer start wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,MSS_DMA frame transfer complete wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,MSS_GIO wake-up GPIO_1_host_interrupt clear enable" "Disabled,Enabled"
|
|
line.long 0x08 "WAKEENACLR2,Wake-Up Enable Clear Register 2"
|
|
bitfld.long 0x08 31. " WAKEENACLR2_[95] ,RADARSS to MSS mailbox wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,GEM IRQ-7/MSS_DMM wake-up interrupt 32 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [85] ,MSS_PBIST wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Software-triggered wake-up interrupt 5 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " [83] ,MSS_DCCB (dual clock compare) module2-done wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 18. " [82] ,MSS_DCCA (dual clock compare) module1-done wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " [79] ,Software-triggered wake-up interrupt 3 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Software-triggered wake-up interrupt 2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Software-triggered wake-up interrupt 1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Software-triggered wake-up interrupt 0 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " [75] ,MSS_SCIB (UART2) level 1 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,MSS_SCIA (UART1) level 1 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,MSS_DMM wake-up interrupt 33 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " [71] ,MSS_DMM interrupt 30 or radar subsystem logical frame start wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [70] ,MSS_DMA bus error wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " [69] ,MSS_DMM wake-up interrupt 36 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,MSS_DMM wake-up interrupt 35 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " [67] ,MSS_DMM wake-up interrupt 34 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,MSS_I2C wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [65] ,MSS_SCIB (UART2) level 0 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 0. " [64] ,MSS_SCIA (UART1) level 0 wake-up interrupt clear enable" "Disabled,Enabled"
|
|
line.long 0x0C "WAKEENACLR3,Wake-Up Enable Clear Register 3"
|
|
bitfld.long 0x0C 31. " WAKEENACLR3_[127] ,DSS_HW_ACC FFT accelerator -access error wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,DSS_HW_ACC FFT accelerator - done wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,DSS_HW_ACC FFT accelerator -param done wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,MSS_PBIST: gem MSS_STC done wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " [123] ,Chirp available interrupt/MSS_DMM wake-up interrupt 31 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 25. " [121] ,MSS_DMM interrupt 37 wake-up clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,DSS_CBUFF (common buffer) error wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,DSS_CBUFF (common buffer) interrupt wake-up clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [117] ,DSS_TPCC (EDMA TPCC0) error wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,DSS_TPCC (EDMA TPCC0) wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 19. " [115] ,DSS_TPTC1 (EDMA TPTC1) error wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,DSS_TPTC1 (EDMA TPTC1) wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,DSS_TPTC0 (EDMA TPTC0) error wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [112] ,DSS_TPTC0 (EDMA TPTC0) wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " [111] ,ePWM3 wake-up interrupt-2 clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 14. " [110] ,ePWM3 wake-up interrupt-1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,ePWM2 wake-up interrupt-2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,ePWM2 wake-up interrupt-1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " [107] ,ePWM1 wake-up interrupt-2 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,All RadarSS wake-up interrupts combined clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 9. " [105] ,MSS_STC done wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,ePWM1 wake-up interrupt-1 clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Frame end wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Chirp end wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " [99] ,Chirp start wake-up interrupt clear enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " [98] ,MSS_DMM interrupt 29/frame start wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [97] ,ADC valid fall wake-up interrupt clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,RADARSS mailbox read complete wake-up interrupt sent from RADARSS to MSS clear enable" "Disabled,Enabled"
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "IRQVECREG,IRQ Interrupt Vector Register"
|
|
line.long 0x04 "FIQVECREG,IRQ Interrupt Vector Register"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CAPEVT,Capture Event Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAPEVTSRC1 ,Capture event source 1 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAPEVTSRC0 ,Capture event source 0 mapping control"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CHANCTRL0,Interrupt Control Register 0"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP0 ,Interrupt CHAN0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP1 ,Interrupt CHAN1 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP2 ,Interrupt CHAN2 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP3 ,Interrupt CHAN3 mapping control"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CHANCTRL1,Interrupt Control Register 1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP4 ,Interrupt CHAN4 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP5 ,Interrupt CHAN5 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP6 ,Interrupt CHAN6 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP7 ,Interrupt CHAN7 mapping control"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CHANCTRL2,Interrupt Control Register 2"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP8 ,Interrupt CHAN8 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP9 ,Interrupt CHAN9 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP10 ,Interrupt CHAN10 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP11 ,Interrupt CHAN11 mapping control"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHANCTRL3,Interrupt Control Register 3"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP12 ,Interrupt CHAN12 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP13 ,Interrupt CHAN13 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP14 ,Interrupt CHAN14 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP15 ,Interrupt CHAN15 mapping control"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CHANCTRL4,Interrupt Control Register 4"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP16 ,Interrupt CHAN16 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP17 ,Interrupt CHAN17 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP18 ,Interrupt CHAN18 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP19 ,Interrupt CHAN19 mapping control"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CHANCTRL5,Interrupt Control Register 5"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP20 ,Interrupt CHAN20 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP21 ,Interrupt CHAN21 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP22 ,Interrupt CHAN22 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP23 ,Interrupt CHAN23 mapping control"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CHANCTRL6,Interrupt Control Register 6"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP24 ,Interrupt CHAN24 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP25 ,Interrupt CHAN25 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP26 ,Interrupt CHAN26 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP27 ,Interrupt CHAN27 mapping control"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CHANCTRL7,Interrupt Control Register 7"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP28 ,Interrupt CHAN28 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP29 ,Interrupt CHAN29 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP30 ,Interrupt CHAN30 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP31 ,Interrupt CHAN31 mapping control"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CHANCTRL8,Interrupt Control Register 8"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP32 ,Interrupt CHAN32 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP33 ,Interrupt CHAN33 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP34 ,Interrupt CHAN34 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP35 ,Interrupt CHAN35 mapping control"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CHANCTRL9,Interrupt Control Register 9"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP36 ,Interrupt CHAN36 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP37 ,Interrupt CHAN37 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP38 ,Interrupt CHAN38 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP39 ,Interrupt CHAN39 mapping control"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CHANCTRL10,Interrupt Control Register 10"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP40 ,Interrupt CHAN40 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP41 ,Interrupt CHAN41 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP42 ,Interrupt CHAN42 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP43 ,Interrupt CHAN43 mapping control"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CHANCTRL11,Interrupt Control Register 11"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP44 ,Interrupt CHAN44 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP45 ,Interrupt CHAN45 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP46 ,Interrupt CHAN46 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP47 ,Interrupt CHAN47 mapping control"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "CHANCTRL12,Interrupt Control Register 12"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP48 ,Interrupt CHAN48 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP49 ,Interrupt CHAN49 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP50 ,Interrupt CHAN50 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP51 ,Interrupt CHAN51 mapping control"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CHANCTRL13,Interrupt Control Register 13"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP52 ,Interrupt CHAN52 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP53 ,Interrupt CHAN53 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP54 ,Interrupt CHAN54 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP55 ,Interrupt CHAN55 mapping control"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "CHANCTRL14,Interrupt Control Register 14"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP56 ,Interrupt CHAN56 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP57 ,Interrupt CHAN57 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP58 ,Interrupt CHAN58 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP59 ,Interrupt CHAN59 mapping control"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "CHANCTRL15,Interrupt Control Register 15"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP60 ,Interrupt CHAN60 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP61 ,Interrupt CHAN61 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP62 ,Interrupt CHAN62 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP63 ,Interrupt CHAN63 mapping control"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CHANCTRL16,Interrupt Control Register 16"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP64 ,Interrupt CHAN64 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP65 ,Interrupt CHAN65 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP66 ,Interrupt CHAN66 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP67 ,Interrupt CHAN67 mapping control"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CHANCTRL17,Interrupt Control Register 17"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP68 ,Interrupt CHAN68 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP69 ,Interrupt CHAN69 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP70 ,Interrupt CHAN70 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP71 ,Interrupt CHAN71 mapping control"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CHANCTRL18,Interrupt Control Register 18"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP72 ,Interrupt CHAN72 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP73 ,Interrupt CHAN73 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP74 ,Interrupt CHAN74 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP75 ,Interrupt CHAN75 mapping control"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CHANCTRL19,Interrupt Control Register 19"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP76 ,Interrupt CHAN76 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP77 ,Interrupt CHAN77 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP78 ,Interrupt CHAN78 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP79 ,Interrupt CHAN79 mapping control"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CHANCTRL20,Interrupt Control Register 20"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP80 ,Interrupt CHAN80 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP81 ,Interrupt CHAN81 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP82 ,Interrupt CHAN82 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP83 ,Interrupt CHAN83 mapping control"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "CHANCTRL21,Interrupt Control Register 21"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP84 ,Interrupt CHAN84 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP85 ,Interrupt CHAN85 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP86 ,Interrupt CHAN86 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP87 ,Interrupt CHAN87 mapping control"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CHANCTRL22,Interrupt Control Register 22"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP88 ,Interrupt CHAN88 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP89 ,Interrupt CHAN89 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP90 ,Interrupt CHAN90 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP91 ,Interrupt CHAN91 mapping control"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "CHANCTRL23,Interrupt Control Register 23"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP92 ,Interrupt CHAN92 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP93 ,Interrupt CHAN93 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP94 ,Interrupt CHAN94 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP95 ,Interrupt CHAN95 mapping control"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "CHANCTRL24,Interrupt Control Register 24"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP96 ,Interrupt CHAN96 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP97 ,Interrupt CHAN97 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP98 ,Interrupt CHAN98 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP99 ,Interrupt CHAN99 mapping control"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CHANCTRL25,Interrupt Control Register 25"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP100 ,Interrupt CHAN100 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP101 ,Interrupt CHAN101 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP102 ,Interrupt CHAN102 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP103 ,Interrupt CHAN103 mapping control"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "CHANCTRL26,Interrupt Control Register 26"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP104 ,Interrupt CHAN104 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP105 ,Interrupt CHAN105 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP106 ,Interrupt CHAN106 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP107 ,Interrupt CHAN107 mapping control"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "CHANCTRL27,Interrupt Control Register 27"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP108 ,Interrupt CHAN108 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP109 ,Interrupt CHAN109 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP110 ,Interrupt CHAN110 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP111 ,Interrupt CHAN111 mapping control"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CHANCTRL28,Interrupt Control Register 28"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP112 ,Interrupt CHAN112 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP113 ,Interrupt CHAN113 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP114 ,Interrupt CHAN114 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP115 ,Interrupt CHAN115 mapping control"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "CHANCTRL29,Interrupt Control Register 29"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP116 ,Interrupt CHAN116 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP117 ,Interrupt CHAN117 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP118 ,Interrupt CHAN118 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP119 ,Interrupt CHAN119 mapping control"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "CHANCTRL30,Interrupt Control Register 30"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP120 ,Interrupt CHAN120 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP121 ,Interrupt CHAN121 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP122 ,Interrupt CHAN122 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAP123 ,Interrupt CHAN123 mapping control"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CHANCTRL31,Interrupt Control Register 31"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAP124 ,Interrupt CHAN124 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAP125 ,Interrupt CHAN125 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHANMAP126 ,Interrupt CHAN126 mapping control"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "VIM (Vectored Interrupt Manager)"
|
|
base ad:0xFFFFFD00
|
|
width 13.
|
|
group.long 0xEC++0x07
|
|
line.long 0x00 "ECCSTAT,Interrupt Vector Table ECC Status Register"
|
|
eventfld.long 0x00 8. " SBERR ,Single bit error" "No error,Error"
|
|
eventfld.long 0x00 0. " UERR ,Double bit error" "No error,Error"
|
|
line.long 0x04 "ECCCTL,Interrupt Vector Table ECC Control Register"
|
|
bitfld.long 0x04 24.--27. " SBE_EVT_EN ,Control the generation of error signal out based on SBE" ",,,,,Disabled,,,,,Enabled,?..."
|
|
bitfld.long 0x04 16.--19. " EDAC_MODE ,Enable SBE correction" ",,,,,Disabled,,,,,Enabled,?..."
|
|
bitfld.long 0x04 8.--11. " TEST_DIAG_EN ,Memory mapping of ECC bits for read/write operation" ",,,,,Enabled memory mapping of ECC,,,,,Disabled,?..."
|
|
newline
|
|
bitfld.long 0x04 0.--3. " ECCENA ,VIM ECC enable" ",,,,,,Disabled,,,,,Enabled,?..."
|
|
newline
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "UERRADDR,Uncorrectable Error Address Register"
|
|
group.long 0xF8++0x07
|
|
line.long 0x00 "FBVECADDR,Fallback Vector Address Register"
|
|
line.long 0x04 "SBERRADDR,Single Bit Error Address Register"
|
|
rgroup.long 0x100++0x07
|
|
line.long 0x00 "IRQINDEX,IRQ Index Offset Vector Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRQINDEX ,IRQ index vector"
|
|
line.long 0x04 "FIQINDEX,FIQ Index Offset Vector Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " FIQINDEX ,FIQ index offset vector"
|
|
group.long 0x110++0x0F
|
|
line.long 0x00 "FIRQPR0,FIQ/IRQ Program Control Register 0"
|
|
bitfld.long 0x00 31. " FIRQPR0_[31] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 30. " [30] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 29. " [29] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 28. " [28] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 27. " [27] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 25. " [25] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 24. " [24] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 23. " [23] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 22. " [22] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 20. " [20] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 19. " [19] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 18. " [18] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 17. " [17] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 15. " [15] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 14. " [14] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 13. " [13] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 12. " [12] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 10. " [10] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 9. " [9] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 8. " [8] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 7. " [7] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 5. " [5] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 4. " [4] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 3. " [3] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x00 2. " [2] ,Type of interrupt" "IRQ,FIQ"
|
|
line.long 0x04 "FIRQPR1,FIQ/IRQ Program Control Register 1"
|
|
bitfld.long 0x04 31. " FIRQPR1_[63] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 30. " [62] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 29. " [61] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 28. " [60] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 27. " [59] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 26. " [58] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 25. " [57] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 24. " [56] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 23. " [55] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 22. " [54] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 21. " [53] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 20. " [52] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 19. " [51] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 18. " [50] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 17. " [49] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 16. " [48] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 15. " [47] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 14. " [46] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 13. " [45] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 12. " [44] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 11. " [43] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 10. " [42] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 9. " [41] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 8. " [40] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 7. " [39] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 6. " [38] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 5. " [37] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 4. " [36] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 3. " [35] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 2. " [34] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x04 0. " [32] ,Type of interrupt" "IRQ,FIQ"
|
|
line.long 0x08 "FIRQPR2,FIQ/IRQ Program Control Register 2"
|
|
bitfld.long 0x08 31. " FIRQPR2_[95] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 30. " [94] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 29. " [93] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 28. " [92] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 27. " [91] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 26. " [90] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 25. " [89] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 24. " [88] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 23. " [87] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 22. " [86] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 21. " [85] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 20. " [84] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 19. " [83] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 18. " [82] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 17. " [81] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 16. " [80] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 15. " [79] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 14. " [78] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 13. " [77] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 12. " [76] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 11. " [75] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 10. " [74] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 9. " [73] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 8. " [72] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 7. " [71] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 6. " [70] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 5. " [69] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 4. " [68] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 3. " [67] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 2. " [66] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x08 1. " [65] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x08 0. " [64] ,Type of interrupt" "IRQ,FIQ"
|
|
line.long 0x0C "FIRQPR3,FIQ/IRQ Program Control Register 3"
|
|
bitfld.long 0x0C 31. " FIRQPR3_[127] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 30. " [126] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 29. " [125] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 28. " [124] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 27. " [123] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 26. " [122] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 25. " [121] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 24. " [120] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 23. " [119] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 22. " [118] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 21. " [117] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 20. " [116] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 19. " [115] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 18. " [114] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 17. " [113] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 16. " [112] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 15. " [111] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 14. " [110] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 13. " [109] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 12. " [108] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 11. " [107] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 10. " [106] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 9. " [105] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 8. " [104] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 7. " [103] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 6. " [102] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 5. " [101] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 4. " [100] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 3. " [99] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 2. " [98] ,Type of interrupt" "IRQ,FIQ"
|
|
newline
|
|
bitfld.long 0x0C 1. " [97] ,Type of interrupt" "IRQ,FIQ"
|
|
bitfld.long 0x0C 0. " [96] ,Type of interrupt" "IRQ,FIQ"
|
|
group.long 0x120++0x0F
|
|
line.long 0x00 "INTREQ0,Pending Interrupt Read Location Register 0"
|
|
eventfld.long 0x00 31. " INTREQ0_[31] ,Interrupt request channel 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " [30] ,Interrupt request channel 30" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " [29] ,Interrupt request channel 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " [28] ,Interrupt request channel 28" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 27. " [27] ,Interrupt request channel 27" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 26. " [26] ,Interrupt request channel 26" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " [25] ,Interrupt request channel 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " [24] ,Interrupt request channel 24" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 23. " [23] ,Interrupt request channel 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " [22] ,Interrupt request channel 22" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 21. " [21] ,Interrupt request channel 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " [20] ,Interrupt request channel 20" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " [19] ,Interrupt request channel 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " [18] ,Interrupt request channel 18" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " [17] ,Interrupt request channel 17" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 16. " [16] ,Interrupt request channel 16" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 15. " [15] ,Interrupt request channel 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " [14] ,Interrupt request channel 14" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " [13] ,Interrupt request channel 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [12] ,Interrupt request channel 12" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Interrupt request channel 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Interrupt request channel 10" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " [9] ,Interrupt request channel 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " [8] ,Interrupt request channel 8" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " [7] ,Interrupt request channel 7" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 6. " [6] ,Interrupt request channel 6" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " [5] ,Interrupt request channel 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,Interrupt request channel 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " [3] ,Interrupt request channel 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt request channel 2" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " [1] ,Interrupt request channel 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt request channel 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTREQ1,Pending Interrupt Read Location Register 1"
|
|
eventfld.long 0x04 31. " INTREQ1_[63] ,Interrupt request channel 63" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 30. " [62] ,Interrupt request channel 62" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 29. " [61] ,Interrupt request channel 61" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 28. " [60] ,Interrupt request channel 60" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 27. " [59] ,Interrupt request channel 59" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 26. " [58] ,Interrupt request channel 58" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 25. " [57] ,Interrupt request channel 57" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 24. " [56] ,Interrupt request channel 56" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 23. " [55] ,Interrupt request channel 55" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 22. " [54] ,Interrupt request channel 54" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 21. " [53] ,Interrupt request channel 53" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 20. " [52] ,Interrupt request channel 52" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 19. " [51] ,Interrupt request channel 51" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 18. " [50] ,Interrupt request channel 50" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 17. " [49] ,Interrupt request channel 49" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 16. " [48] ,Interrupt request channel 48" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 15. " [47] ,Interrupt request channel 47" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 14. " [46] ,Interrupt request channel 46" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 13. " [45] ,Interrupt request channel 45" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 12. " [44] ,Interrupt request channel 44" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 11. " [43] ,Interrupt request channel 43" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 10. " [42] ,Interrupt request channel 42" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 9. " [41] ,Interrupt request channel 41" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 8. " [40] ,Interrupt request channel 40" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 7. " [39] ,Interrupt request channel 39" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 6. " [38] ,Interrupt request channel 38" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 5. " [37] ,Interrupt request channel 37" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 4. " [36] ,Interrupt request channel 36" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " [35] ,Interrupt request channel 35" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " [34] ,Interrupt request channel 34" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 1. " [33] ,Interrupt request channel 33" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 0. " [32] ,Interrupt request channel 32" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTREQ2,Pending Interrupt Read Location Register 2"
|
|
eventfld.long 0x08 31. " INTREQ2_[95] ,Interrupt request channel 95" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 30. " [94] ,Interrupt request channel 94" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 29. " [93] ,Interrupt request channel 93" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 28. " [92] ,Interrupt request channel 92" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 27. " [91] ,Interrupt request channel 91" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 26. " [90] ,Interrupt request channel 90" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 25. " [89] ,Interrupt request channel 89" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 24. " [88] ,Interrupt request channel 88" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 23. " [87] ,Interrupt request channel 87" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 22. " [86] ,Interrupt request channel 86" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 21. " [85] ,Interrupt request channel 85" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 20. " [84] ,Interrupt request channel 84" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 19. " [83] ,Interrupt request channel 83" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 18. " [82] ,Interrupt request channel 82" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 17. " [81] ,Interrupt request channel 81" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 16. " [80] ,Interrupt request channel 80" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 15. " [79] ,Interrupt request channel 79" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 14. " [78] ,Interrupt request channel 78" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 13. " [77] ,Interrupt request channel 77" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 12. " [76] ,Interrupt request channel 76" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 11. " [75] ,Interrupt request channel 75" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 10. " [74] ,Interrupt request channel 74" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 9. " [73] ,Interrupt request channel 73" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " [72] ,Interrupt request channel 72" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " [71] ,Interrupt request channel 71" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 6. " [70] ,Interrupt request channel 70" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 5. " [69] ,Interrupt request channel 69" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " [68] ,Interrupt request channel 68" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " [67] ,Interrupt request channel 67" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " [66] ,Interrupt request channel 66" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x08 1. " [65] ,Interrupt request channel 65" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " [64] ,Interrupt request channel 64" "No interrupt,Interrupt"
|
|
line.long 0x0C "INTREQ3,Pending Interrupt Read Location Register 3"
|
|
eventfld.long 0x0C 31. " INTREQ3_[127] ,Interrupt request channel 127" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 30. " [126] ,Interrupt request channel 126" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 29. " [125] ,Interrupt request channel 125" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 28. " [124] ,Interrupt request channel 124" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 27. " [123] ,Interrupt request channel 123" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 26. " [122] ,Interrupt request channel 122" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 25. " [121] ,Interrupt request channel 121" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 24. " [120] ,Interrupt request channel 120" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 23. " [119] ,Interrupt request channel 119" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 22. " [118] ,Interrupt request channel 118" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 21. " [117] ,Interrupt request channel 117" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 20. " [116] ,Interrupt request channel 116" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 19. " [115] ,Interrupt request channel 115" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 18. " [114] ,Interrupt request channel 114" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 17. " [113] ,Interrupt request channel 113" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 16. " [112] ,Interrupt request channel 112" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 15. " [111] ,Interrupt request channel 111" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 14. " [110] ,Interrupt request channel 110" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 13. " [109] ,Interrupt request channel 109" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 12. " [108] ,Interrupt request channel 108" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 11. " [107] ,Interrupt request channel 107" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 10. " [106] ,Interrupt request channel 106" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 9. " [105] ,Interrupt request channel 105" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 8. " [104] ,Interrupt request channel 104" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 7. " [103] ,Interrupt request channel 103" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 6. " [102] ,Interrupt request channel 102" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 5. " [101] ,Interrupt request channel 101" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 4. " [100] ,Interrupt request channel 100" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 3. " [99] ,Interrupt request channel 99" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 2. " [98] ,Interrupt request channel 98" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x0C 1. " [97] ,Interrupt request channel 97" "No interrupt,Interrupt"
|
|
eventfld.long 0x0C 0. " [96] ,Interrupt request channel 96" "No interrupt,Interrupt"
|
|
group.long 0x130++0x0F
|
|
line.long 0x00 "REQENASET0,Interrupt Enable Set Register 0"
|
|
bitfld.long 0x00 31. " REQENASET0_[31] ,Enable interrupt request channel 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Enable set interrupt request channel 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Enable set interrupt request channel 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Enable set interrupt request channel 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Enable set interrupt request channel 27" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Enable set interrupt request channel 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Enable set interrupt request channel 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Enable set interrupt request channel 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Enable set interrupt request channel 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Enable set interrupt request channel 22" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Enable set interrupt request channel 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Enable set interrupt request channel 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Enable set interrupt request channel 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Enable set interrupt request channel 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Enable set interrupt request channel 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Enable set interrupt request channel 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Enable set interrupt request channel 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Enable set interrupt request channel 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Enable set interrupt request channel 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Enable set interrupt request channel 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Enable set interrupt request channel 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Enable set interrupt request channel 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Enable set interrupt request channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Enable set interrupt request channel 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Enable set interrupt request channel 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Enable set interrupt request channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Enable set interrupt request channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Enable set interrupt request channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Enable set interrupt request channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Enable set interrupt request channel 2" "Disabled,Enabled"
|
|
line.long 0x04 "REQENASET1,Interrupt Enable Set Register 1"
|
|
bitfld.long 0x04 31. " REQENASET1_[63] ,Enable set interrupt request channel 63" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,Enable set interrupt request channel 62" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,Enable set interrupt request channel 61" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,Enable set interrupt request channel 60" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " [59] ,Enable set interrupt request channel 59" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 26. " [58] ,Enable set interrupt request channel 58" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,Enable set interrupt request channel 57" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,Enable set interrupt request channel 56" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " [55] ,Enable set interrupt request channel 55" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,Enable set interrupt request channel 54" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 21. " [53] ,Enable set interrupt request channel 53" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Enable set interrupt request channel 52" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " [51] ,Enable set interrupt request channel 51" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Enable set interrupt request channel 50" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,Enable set interrupt request channel 49" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " [48] ,Enable set interrupt request channel 48" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " [47] ,Enable set interrupt request channel 47" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Enable set interrupt request channel 46" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,Enable set interrupt request channel 45" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Enable set interrupt request channel 44" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [43] ,Enable set interrupt request channel 43" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Enable set interrupt request channel 42" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,Enable set interrupt request channel 41" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Enable set interrupt request channel 40" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " [39] ,Enable set interrupt request channel 39" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 6. " [38] ,Enable set interrupt request channel 38" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,Enable set interrupt request channel 37" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Enable set interrupt request channel 36" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " [35] ,Enable set interrupt request channel 35" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Enable set interrupt request channel 34" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,Enable set interrupt request channel 33" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Enable set interrupt request channel 32" "Disabled,Enabled"
|
|
line.long 0x08 "REQENASET2,Interrupt Enable Set Register 2"
|
|
bitfld.long 0x08 31. " REQENASET2_[95] ,Enable set interrupt request channel 95" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [94] ,Enable set interrupt request channel 94" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [93] ,Enable set interrupt request channel 93" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [92] ,Enable set interrupt request channel 92" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " [91] ,Enable set interrupt request channel 91" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 26. " [90] ,Enable set interrupt request channel 90" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [89] ,Enable set interrupt request channel 89" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [88] ,Enable set interrupt request channel 88" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " [87] ,Enable set interrupt request channel 87" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,Enable set interrupt request channel 86" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 21. " [85] ,Enable set interrupt request channel 85" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Enable set interrupt request channel 84" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " [83] ,Enable set interrupt request channel 83" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [82] ,Enable set interrupt request channel 82" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [81] ,Enable set interrupt request channel 81" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16. " [80] ,Enable set interrupt request channel 80" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " [79] ,Enable set interrupt request channel 79" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Enable set interrupt request channel 78" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Enable set interrupt request channel 77" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Enable set interrupt request channel 76" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " [75] ,Enable set interrupt request channel 75" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,Enable set interrupt request channel 74" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,Enable set interrupt request channel 73" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [72] ,Enable set interrupt request channel 72" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " [71] ,Enable set interrupt request channel 71" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 6. " [70] ,Enable set interrupt request channel 70" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [69] ,Enable set interrupt request channel 69" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,Enable set interrupt request channel 68" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " [67] ,Enable set interrupt request channel 67" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,Enable set interrupt request channel 66" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 1. " [65] ,Enable set interrupt request channel 65" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [64] ,Enable set interrupt request channel 64" "Disabled,Enabled"
|
|
line.long 0x0C "REQENASET3,Interrupt Enable Set Register 3"
|
|
bitfld.long 0x0C 31. " INTREQ3_[127] ,Enable set interrupt request channel 127" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,Enable set interrupt request channel 126" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,Enable set interrupt request channel 125" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,Enable set interrupt request channel 124" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " [123] ,Enable set interrupt request channel 123" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 26. " [122] ,Enable set interrupt request channel 122" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [121] ,Enable set interrupt request channel 121" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,Enable set interrupt request channel 120" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " [119] ,Enable set interrupt request channel 119" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,Enable set interrupt request channel 118" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 21. " [117] ,Enable set interrupt request channel 117" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,Enable set interrupt request channel 116" "Disabled,Enabled"
|
|
bitfld.long 0x0C 19. " [115] ,Enable set interrupt request channel 115" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,Enable set interrupt request channel 114" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,Enable set interrupt request channel 113" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 16. " [112] ,Enable set interrupt request channel 112" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " [111] ,Enable set interrupt request channel 111" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [110] ,Enable set interrupt request channel 110" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,Enable set interrupt request channel 109" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,Enable set interrupt request channel 108" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 11. " [107] ,Enable set interrupt request channel 107" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,Enable set interrupt request channel 106" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [105] ,Enable set interrupt request channel 105" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,Enable set interrupt request channel 104" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " [103] ,Enable set interrupt request channel 103" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 6. " [102] ,Enable set interrupt request channel 102" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Enable set interrupt request channel 101" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Enable set interrupt request channel 100" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " [99] ,Enable set interrupt request channel 99" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [98] ,Enable set interrupt request channel 98" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 1. " [97] ,Enable set interrupt request channel 97" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,Enable set interrupt request channel 96" "Disabled,Enabled"
|
|
group.long 0x140++0x0F
|
|
line.long 0x00 "REQENACLR0,Interrupt Enable Clear Register 0"
|
|
bitfld.long 0x00 31. " REQENACLR0_[31] ,Enable clear interrupt request channel 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Enable clear interrupt request channel 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Enable clear interrupt request channel 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Enable clear interrupt request channel 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Enable clear interrupt request channel 27" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Enable clear interrupt request channel 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Enable clear interrupt request channel 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Enable clear interrupt request channel 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Enable clear interrupt request channel 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Enable clear interrupt request channel 22" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Enable clear interrupt request channel 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Enable clear interrupt request channel 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Enable clear interrupt request channel 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Enable clear interrupt request channel 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Enable clear interrupt request channel 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Enable clear interrupt request channel 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Enable clear interrupt request channel 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Enable clear interrupt request channel 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Enable clear interrupt request channel 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Enable clear interrupt request channel 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Enable clear interrupt request channel 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Enable clear interrupt request channel 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Enable clear interrupt request channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Enable clear interrupt request channel 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Enable clear interrupt request channel 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Enable clear interrupt request channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Enable clear interrupt request channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Enable clear interrupt request channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Enable clear interrupt request channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Enable clear interrupt request channel 2" "Disabled,Enabled"
|
|
line.long 0x04 "REQENACLR1,Interrupt Enable Clear Register 1"
|
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bitfld.long 0x04 31. " REQENACLR1_[63] ,Enable clear interrupt request channel 63" "Disabled,Enabled"
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bitfld.long 0x04 30. " [62] ,Enable clear interrupt request channel 62" "Disabled,Enabled"
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bitfld.long 0x04 29. " [61] ,Enable clear interrupt request channel 61" "Disabled,Enabled"
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bitfld.long 0x04 28. " [60] ,Enable clear interrupt request channel 60" "Disabled,Enabled"
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bitfld.long 0x04 27. " [59] ,Enable clear interrupt request channel 59" "Disabled,Enabled"
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newline
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bitfld.long 0x04 26. " [58] ,Enable clear interrupt request channel 58" "Disabled,Enabled"
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bitfld.long 0x04 25. " [57] ,Enable clear interrupt request channel 57" "Disabled,Enabled"
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bitfld.long 0x04 24. " [56] ,Enable clear interrupt request channel 56" "Disabled,Enabled"
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bitfld.long 0x04 23. " [55] ,Enable clear interrupt request channel 55" "Disabled,Enabled"
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bitfld.long 0x04 22. " [54] ,Enable clear interrupt request channel 54" "Disabled,Enabled"
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newline
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bitfld.long 0x04 21. " [53] ,Enable clear interrupt request channel 53" "Disabled,Enabled"
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bitfld.long 0x04 20. " [52] ,Enable clear interrupt request channel 52" "Disabled,Enabled"
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bitfld.long 0x04 19. " [51] ,Enable clear interrupt request channel 51" "Disabled,Enabled"
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bitfld.long 0x04 18. " [50] ,Enable clear interrupt request channel 50" "Disabled,Enabled"
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bitfld.long 0x04 17. " [49] ,Enable clear interrupt request channel 49" "Disabled,Enabled"
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newline
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bitfld.long 0x04 16. " [48] ,Enable clear interrupt request channel 48" "Disabled,Enabled"
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bitfld.long 0x04 15. " [47] ,Enable clear interrupt request channel 47" "Disabled,Enabled"
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bitfld.long 0x04 14. " [46] ,Enable clear interrupt request channel 46" "Disabled,Enabled"
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bitfld.long 0x04 13. " [45] ,Enable clear interrupt request channel 45" "Disabled,Enabled"
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bitfld.long 0x04 12. " [44] ,Enable clear interrupt request channel 44" "Disabled,Enabled"
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newline
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bitfld.long 0x04 11. " [43] ,Enable clear interrupt request channel 43" "Disabled,Enabled"
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bitfld.long 0x04 10. " [42] ,Enable clear interrupt request channel 42" "Disabled,Enabled"
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bitfld.long 0x04 9. " [41] ,Enable clear interrupt request channel 41" "Disabled,Enabled"
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bitfld.long 0x04 8. " [40] ,Enable clear interrupt request channel 40" "Disabled,Enabled"
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bitfld.long 0x04 7. " [39] ,Enable clear interrupt request channel 39" "Disabled,Enabled"
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newline
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bitfld.long 0x04 6. " [38] ,Enable clear interrupt request channel 38" "Disabled,Enabled"
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bitfld.long 0x04 5. " [37] ,Enable clear interrupt request channel 37" "Disabled,Enabled"
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bitfld.long 0x04 4. " [36] ,Enable clear interrupt request channel 36" "Disabled,Enabled"
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bitfld.long 0x04 3. " [35] ,Enable clear interrupt request channel 35" "Disabled,Enabled"
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bitfld.long 0x04 2. " [34] ,Enable clear interrupt request channel 34" "Disabled,Enabled"
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newline
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bitfld.long 0x04 1. " [33] ,Enable clear interrupt request channel 33" "Disabled,Enabled"
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bitfld.long 0x04 0. " [32] ,Enable clear interrupt request channel 32" "Disabled,Enabled"
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line.long 0x08 "REQENACLR2,Interrupt Enable Clear Register 2"
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bitfld.long 0x08 31. " REQENACLR2_[95] ,Enable clear interrupt request channel 95" "Disabled,Enabled"
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bitfld.long 0x08 30. " [94] ,Enable clear interrupt request channel 94" "Disabled,Enabled"
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bitfld.long 0x08 29. " [93] ,Enable clear interrupt request channel 93" "Disabled,Enabled"
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bitfld.long 0x08 28. " [92] ,Enable clear interrupt request channel 92" "Disabled,Enabled"
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bitfld.long 0x08 27. " [91] ,Enable clear interrupt request channel 91" "Disabled,Enabled"
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newline
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bitfld.long 0x08 26. " [90] ,Enable clear interrupt request channel 90" "Disabled,Enabled"
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bitfld.long 0x08 25. " [89] ,Enable clear interrupt request channel 89" "Disabled,Enabled"
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bitfld.long 0x08 24. " [88] ,Enable clear interrupt request channel 88" "Disabled,Enabled"
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bitfld.long 0x08 23. " [87] ,Enable clear interrupt request channel 87" "Disabled,Enabled"
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bitfld.long 0x08 22. " [86] ,Enable clear interrupt request channel 86" "Disabled,Enabled"
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newline
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bitfld.long 0x08 21. " [85] ,Enable clear interrupt request channel 85" "Disabled,Enabled"
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bitfld.long 0x08 20. " [84] ,Enable clear interrupt request channel 84" "Disabled,Enabled"
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bitfld.long 0x08 19. " [83] ,Enable clear interrupt request channel 83" "Disabled,Enabled"
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bitfld.long 0x08 18. " [82] ,Enable clear interrupt request channel 82" "Disabled,Enabled"
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bitfld.long 0x08 17. " [81] ,Enable clear interrupt request channel 81" "Disabled,Enabled"
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newline
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bitfld.long 0x08 16. " [80] ,Enable clear interrupt request channel 80" "Disabled,Enabled"
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bitfld.long 0x08 15. " [79] ,Enable clear interrupt request channel 79" "Disabled,Enabled"
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bitfld.long 0x08 14. " [78] ,Enable clear interrupt request channel 78" "Disabled,Enabled"
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bitfld.long 0x08 13. " [77] ,Enable clear interrupt request channel 77" "Disabled,Enabled"
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bitfld.long 0x08 12. " [76] ,Enable clear interrupt request channel 76" "Disabled,Enabled"
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newline
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bitfld.long 0x08 11. " [75] ,Enable clear interrupt request channel 75" "Disabled,Enabled"
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bitfld.long 0x08 10. " [74] ,Enable clear interrupt request channel 74" "Disabled,Enabled"
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bitfld.long 0x08 9. " [73] ,Enable clear interrupt request channel 73" "Disabled,Enabled"
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bitfld.long 0x08 8. " [72] ,Enable clear interrupt request channel 72" "Disabled,Enabled"
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bitfld.long 0x08 7. " [71] ,Enable clear interrupt request channel 71" "Disabled,Enabled"
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newline
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bitfld.long 0x08 6. " [70] ,Enable clear interrupt request channel 70" "Disabled,Enabled"
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bitfld.long 0x08 5. " [69] ,Enable clear interrupt request channel 69" "Disabled,Enabled"
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bitfld.long 0x08 4. " [68] ,Enable clear interrupt request channel 68" "Disabled,Enabled"
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bitfld.long 0x08 3. " [67] ,Enable clear interrupt request channel 67" "Disabled,Enabled"
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bitfld.long 0x08 2. " [66] ,Enable clear interrupt request channel 66" "Disabled,Enabled"
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newline
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bitfld.long 0x08 1. " [65] ,Enable clear interrupt request channel 65" "Disabled,Enabled"
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bitfld.long 0x08 0. " [64] ,Enable clear interrupt request channel 64" "Disabled,Enabled"
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line.long 0x0C "REQENACLR3,Interrupt Enable Clear Register 3"
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bitfld.long 0x0C 31. " REQENACLR3_[127] ,Enable clear interrupt request channel 127" "Disabled,Enabled"
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bitfld.long 0x0C 30. " [126] ,Enable clear interrupt request channel 126" "Disabled,Enabled"
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bitfld.long 0x0C 29. " [125] ,Enable clear interrupt request channel 125" "Disabled,Enabled"
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bitfld.long 0x0C 28. " [124] ,Enable clear interrupt request channel 124" "Disabled,Enabled"
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bitfld.long 0x0C 27. " [123] ,Enable clear interrupt request channel 123" "Disabled,Enabled"
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newline
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bitfld.long 0x0C 26. " [122] ,Enable clear interrupt request channel 122" "Disabled,Enabled"
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bitfld.long 0x0C 25. " [121] ,Enable clear interrupt request channel 121" "Disabled,Enabled"
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bitfld.long 0x0C 24. " [120] ,Enable clear interrupt request channel 120" "Disabled,Enabled"
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bitfld.long 0x0C 23. " [119] ,Enable clear interrupt request channel 119" "Disabled,Enabled"
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bitfld.long 0x0C 22. " [118] ,Enable clear interrupt request channel 118" "Disabled,Enabled"
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newline
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bitfld.long 0x0C 21. " [117] ,Enable clear interrupt request channel 117" "Disabled,Enabled"
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bitfld.long 0x0C 20. " [116] ,Enable clear interrupt request channel 116" "Disabled,Enabled"
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bitfld.long 0x0C 19. " [115] ,Enable clear interrupt request channel 115" "Disabled,Enabled"
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bitfld.long 0x0C 18. " [114] ,Enable clear interrupt request channel 114" "Disabled,Enabled"
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bitfld.long 0x0C 17. " [113] ,Enable clear interrupt request channel 113" "Disabled,Enabled"
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newline
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bitfld.long 0x0C 16. " [112] ,Enable clear interrupt request channel 112" "Disabled,Enabled"
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bitfld.long 0x0C 15. " [111] ,Enable clear interrupt request channel 111" "Disabled,Enabled"
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bitfld.long 0x0C 14. " [110] ,Enable clear interrupt request channel 110" "Disabled,Enabled"
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bitfld.long 0x0C 13. " [109] ,Enable clear interrupt request channel 109" "Disabled,Enabled"
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bitfld.long 0x0C 12. " [108] ,Enable clear interrupt request channel 108" "Disabled,Enabled"
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newline
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bitfld.long 0x0C 11. " [107] ,Enable clear interrupt request channel 107" "Disabled,Enabled"
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bitfld.long 0x0C 10. " [106] ,Enable clear interrupt request channel 106" "Disabled,Enabled"
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bitfld.long 0x0C 9. " [105] ,Enable clear interrupt request channel 105" "Disabled,Enabled"
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bitfld.long 0x0C 8. " [104] ,Enable clear interrupt request channel 104" "Disabled,Enabled"
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bitfld.long 0x0C 7. " [103] ,Enable clear interrupt request channel 103" "Disabled,Enabled"
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newline
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bitfld.long 0x0C 6. " [102] ,Enable clear interrupt request channel 102" "Disabled,Enabled"
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bitfld.long 0x0C 5. " [101] ,Enable clear interrupt request channel 101" "Disabled,Enabled"
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bitfld.long 0x0C 4. " [100] ,Enable clear interrupt request channel 100" "Disabled,Enabled"
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bitfld.long 0x0C 3. " [99] ,Enable clear interrupt request channel 99" "Disabled,Enabled"
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bitfld.long 0x0C 2. " [98] ,Enable clear interrupt request channel 98" "Disabled,Enabled"
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newline
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bitfld.long 0x0C 1. " [97] ,Enable clear interrupt request channel 97" "Disabled,Enabled"
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bitfld.long 0x0C 0. " [96] ,Enable clear interrupt request channel 96" "Disabled,Enabled"
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group.long 0x150++0x0F
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line.long 0x00 "WAKEENASET0,Wake-Up Enable Set Register 0"
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bitfld.long 0x00 31. " WAKEENASET0_[31] ,Wake-up enable set interrupt request channel 31" "Disabled,Enabled"
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bitfld.long 0x00 30. " [30] ,Wake-up enable set interrupt request channel 30" "Disabled,Enabled"
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bitfld.long 0x00 29. " [29] ,Wake-up enable set interrupt request channel 29" "Disabled,Enabled"
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bitfld.long 0x00 28. " [28] ,Wake-up enable set interrupt request channel 28" "Disabled,Enabled"
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bitfld.long 0x00 27. " [27] ,Wake-up enable set interrupt request channel 27" "Disabled,Enabled"
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newline
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bitfld.long 0x00 26. " [26] ,Wake-up enable set interrupt request channel 26" "Disabled,Enabled"
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bitfld.long 0x00 25. " [25] ,Wake-up enable set interrupt request channel 25" "Disabled,Enabled"
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bitfld.long 0x00 24. " [24] ,Wake-up enable set interrupt request channel 24" "Disabled,Enabled"
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bitfld.long 0x00 23. " [23] ,Wake-up enable set interrupt request channel 23" "Disabled,Enabled"
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bitfld.long 0x00 22. " [22] ,Wake-up enable set interrupt request channel 22" "Disabled,Enabled"
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newline
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bitfld.long 0x00 21. " [21] ,Wake-up enable set interrupt request channel 21" "Disabled,Enabled"
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bitfld.long 0x00 20. " [20] ,Wake-up enable set interrupt request channel 20" "Disabled,Enabled"
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bitfld.long 0x00 19. " [19] ,Wake-up enable set interrupt request channel 19" "Disabled,Enabled"
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bitfld.long 0x00 18. " [18] ,Wake-up enable set interrupt request channel 18" "Disabled,Enabled"
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bitfld.long 0x00 17. " [17] ,Wake-up enable set interrupt request channel 17" "Disabled,Enabled"
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newline
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bitfld.long 0x00 16. " [16] ,Wake-up enable set interrupt request channel 16" "Disabled,Enabled"
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bitfld.long 0x00 15. " [15] ,Wake-up enable set interrupt request channel 15" "Disabled,Enabled"
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bitfld.long 0x00 14. " [14] ,Wake-up enable set interrupt request channel 14" "Disabled,Enabled"
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bitfld.long 0x00 13. " [13] ,Wake-up enable set interrupt request channel 13" "Disabled,Enabled"
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bitfld.long 0x00 12. " [12] ,Wake-up enable set interrupt request channel 12" "Disabled,Enabled"
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newline
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bitfld.long 0x00 11. " [11] ,Wake-up enable set interrupt request channel 11" "Disabled,Enabled"
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bitfld.long 0x00 10. " [10] ,Wake-up enable set interrupt request channel 10" "Disabled,Enabled"
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bitfld.long 0x00 9. " [9] ,Wake-up enable set interrupt request channel 9" "Disabled,Enabled"
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bitfld.long 0x00 8. " [8] ,Wake-up enable set interrupt request channel 8" "Disabled,Enabled"
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bitfld.long 0x00 7. " [7] ,Wake-up enable set interrupt request channel 7" "Disabled,Enabled"
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newline
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bitfld.long 0x00 6. " [6] ,Wake-up enable set interrupt request channel 6" "Disabled,Enabled"
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bitfld.long 0x00 5. " [5] ,Wake-up enable set interrupt request channel 5" "Disabled,Enabled"
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bitfld.long 0x00 4. " [4] ,Wake-up enable set interrupt request channel 4" "Disabled,Enabled"
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bitfld.long 0x00 3. " [3] ,Wake-up enable set interrupt request channel 3" "Disabled,Enabled"
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bitfld.long 0x00 2. " [2] ,Wake-up enable set interrupt request channel 2" "Disabled,Enabled"
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line.long 0x04 "WAKEENASET1,Wake-Up Enable Set Register 1"
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bitfld.long 0x04 31. " WAKEENASET1_[63] ,Wake-up enable set interrupt request channel 63" "Disabled,Enabled"
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bitfld.long 0x04 30. " [62] ,Wake-up enable set interrupt request channel 62" "Disabled,Enabled"
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bitfld.long 0x04 29. " [61] ,Wake-up enable set interrupt request channel 61" "Disabled,Enabled"
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bitfld.long 0x04 28. " [60] ,Wake-up enable set interrupt request channel 60" "Disabled,Enabled"
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bitfld.long 0x04 27. " [59] ,Wake-up enable set interrupt request channel 59" "Disabled,Enabled"
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newline
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bitfld.long 0x04 26. " [58] ,Wake-up enable set interrupt request channel 58" "Disabled,Enabled"
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bitfld.long 0x04 25. " [57] ,Wake-up enable set interrupt request channel 57" "Disabled,Enabled"
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bitfld.long 0x04 24. " [56] ,Wake-up enable set interrupt request channel 56" "Disabled,Enabled"
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bitfld.long 0x04 23. " [55] ,Wake-up enable set interrupt request channel 55" "Disabled,Enabled"
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bitfld.long 0x04 22. " [54] ,Wake-up enable set interrupt request channel 54" "Disabled,Enabled"
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newline
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bitfld.long 0x04 21. " [53] ,Wake-up enable set interrupt request channel 53" "Disabled,Enabled"
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bitfld.long 0x04 20. " [52] ,Wake-up enable set interrupt request channel 52" "Disabled,Enabled"
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bitfld.long 0x04 19. " [51] ,Wake-up enable set interrupt request channel 51" "Disabled,Enabled"
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bitfld.long 0x04 18. " [50] ,Wake-up enable set interrupt request channel 50" "Disabled,Enabled"
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bitfld.long 0x04 17. " [49] ,Wake-up enable set interrupt request channel 49" "Disabled,Enabled"
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newline
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bitfld.long 0x04 16. " [48] ,Wake-up enable set interrupt request channel 48" "Disabled,Enabled"
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bitfld.long 0x04 15. " [47] ,Wake-up enable set interrupt request channel 47" "Disabled,Enabled"
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bitfld.long 0x04 14. " [46] ,Wake-up enable set interrupt request channel 46" "Disabled,Enabled"
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bitfld.long 0x04 13. " [45] ,Wake-up enable set interrupt request channel 45" "Disabled,Enabled"
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bitfld.long 0x04 12. " [44] ,Wake-up enable set interrupt request channel 44" "Disabled,Enabled"
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newline
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bitfld.long 0x04 11. " [43] ,Wake-up enable set interrupt request channel 43" "Disabled,Enabled"
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bitfld.long 0x04 10. " [42] ,Wake-up enable set interrupt request channel 42" "Disabled,Enabled"
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bitfld.long 0x04 9. " [41] ,Wake-up enable set interrupt request channel 41" "Disabled,Enabled"
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bitfld.long 0x04 8. " [40] ,Wake-up enable set interrupt request channel 40" "Disabled,Enabled"
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bitfld.long 0x04 7. " [39] ,Wake-up enable set interrupt request channel 39" "Disabled,Enabled"
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newline
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bitfld.long 0x04 6. " [38] ,Wake-up enable set interrupt request channel 38" "Disabled,Enabled"
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bitfld.long 0x04 5. " [37] ,Wake-up enable set interrupt request channel 37" "Disabled,Enabled"
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bitfld.long 0x04 4. " [36] ,Wake-up enable set interrupt request channel 36" "Disabled,Enabled"
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bitfld.long 0x04 3. " [35] ,Wake-up enable set interrupt request channel 35" "Disabled,Enabled"
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bitfld.long 0x04 2. " [34] ,Wake-up enable set interrupt request channel 34" "Disabled,Enabled"
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newline
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bitfld.long 0x04 1. " [33] ,Wake-up enable set interrupt request channel 33" "Disabled,Enabled"
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bitfld.long 0x04 0. " [32] ,Wake-up enable set interrupt request channel 32" "Disabled,Enabled"
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line.long 0x08 "WAKEENASET2,Wake-Up Enable Set Register 2"
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bitfld.long 0x08 31. " WAKEENASET2_[95] ,Wake-up enable set interrupt request channel 95" "Disabled,Enabled"
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bitfld.long 0x08 30. " [94] ,Wake-up enable set interrupt request channel 94" "Disabled,Enabled"
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bitfld.long 0x08 29. " [93] ,Wake-up enable set interrupt request channel 93" "Disabled,Enabled"
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bitfld.long 0x08 28. " [92] ,Wake-up enable set interrupt request channel 92" "Disabled,Enabled"
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bitfld.long 0x08 27. " [91] ,Wake-up enable set interrupt request channel 91" "Disabled,Enabled"
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newline
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bitfld.long 0x08 26. " [90] ,Wake-up enable set interrupt request channel 90" "Disabled,Enabled"
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bitfld.long 0x08 25. " [89] ,Wake-up enable set interrupt request channel 89" "Disabled,Enabled"
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bitfld.long 0x08 24. " [88] ,Wake-up enable set interrupt request channel 88" "Disabled,Enabled"
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bitfld.long 0x08 23. " [87] ,Wake-up enable set interrupt request channel 87" "Disabled,Enabled"
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bitfld.long 0x08 22. " [86] ,Wake-up enable set interrupt request channel 86" "Disabled,Enabled"
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newline
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bitfld.long 0x08 21. " [85] ,Wake-up enable set interrupt request channel 85" "Disabled,Enabled"
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bitfld.long 0x08 20. " [84] ,Wake-up enable set interrupt request channel 84" "Disabled,Enabled"
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bitfld.long 0x08 19. " [83] ,Wake-up enable set interrupt request channel 83" "Disabled,Enabled"
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bitfld.long 0x08 18. " [82] ,Wake-up enable set interrupt request channel 82" "Disabled,Enabled"
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bitfld.long 0x08 17. " [81] ,Wake-up enable set interrupt request channel 81" "Disabled,Enabled"
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newline
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bitfld.long 0x08 16. " [80] ,Wake-up enable set interrupt request channel 80" "Disabled,Enabled"
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bitfld.long 0x08 15. " [79] ,Wake-up enable set interrupt request channel 79" "Disabled,Enabled"
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bitfld.long 0x08 14. " [78] ,Wake-up enable set interrupt request channel 78" "Disabled,Enabled"
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bitfld.long 0x08 13. " [77] ,Wake-up enable set interrupt request channel 77" "Disabled,Enabled"
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bitfld.long 0x08 12. " [76] ,Wake-up enable set interrupt request channel 76" "Disabled,Enabled"
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newline
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bitfld.long 0x08 11. " [75] ,Wake-up enable set interrupt request channel 75" "Disabled,Enabled"
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bitfld.long 0x08 10. " [74] ,Wake-up enable set interrupt request channel 74" "Disabled,Enabled"
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bitfld.long 0x08 9. " [73] ,Wake-up enable set interrupt request channel 73" "Disabled,Enabled"
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bitfld.long 0x08 8. " [72] ,Wake-up enable set interrupt request channel 72" "Disabled,Enabled"
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bitfld.long 0x08 7. " [71] ,Wake-up enable set interrupt request channel 71" "Disabled,Enabled"
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newline
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bitfld.long 0x08 6. " [70] ,Wake-up enable set interrupt request channel 70" "Disabled,Enabled"
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bitfld.long 0x08 5. " [69] ,Wake-up enable set interrupt request channel 69" "Disabled,Enabled"
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bitfld.long 0x08 4. " [68] ,Wake-up enable set interrupt request channel 68" "Disabled,Enabled"
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bitfld.long 0x08 3. " [67] ,Wake-up enable set interrupt request channel 67" "Disabled,Enabled"
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bitfld.long 0x08 2. " [66] ,Wake-up enable set interrupt request channel 66" "Disabled,Enabled"
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newline
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bitfld.long 0x08 1. " [65] ,Wake-up enable set interrupt request channel 65" "Disabled,Enabled"
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bitfld.long 0x08 0. " [64] ,Wake-up enable set interrupt request channel 64" "Disabled,Enabled"
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line.long 0x0C "WAKEENASET3,Wake-Up Enable Set Register 3"
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bitfld.long 0x0C 31. " WAKEENASET3_[127] ,Wake-up enable set interrupt request channel 127" "Disabled,Enabled"
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bitfld.long 0x0C 30. " [126] ,Wake-up enable set interrupt request channel 126" "Disabled,Enabled"
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bitfld.long 0x0C 29. " [125] ,Wake-up enable set interrupt request channel 125" "Disabled,Enabled"
|
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bitfld.long 0x0C 28. " [124] ,Wake-up enable set interrupt request channel 124" "Disabled,Enabled"
|
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bitfld.long 0x0C 27. " [123] ,Wake-up enable set interrupt request channel 123" "Disabled,Enabled"
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newline
|
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bitfld.long 0x0C 26. " [122] ,Wake-up enable set interrupt request channel 122" "Disabled,Enabled"
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bitfld.long 0x0C 25. " [121] ,Wake-up enable set interrupt request channel 121" "Disabled,Enabled"
|
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bitfld.long 0x0C 24. " [120] ,Wake-up enable set interrupt request channel 120" "Disabled,Enabled"
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bitfld.long 0x0C 23. " [119] ,Wake-up enable set interrupt request channel 119" "Disabled,Enabled"
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bitfld.long 0x0C 22. " [118] ,Wake-up enable set interrupt request channel 118" "Disabled,Enabled"
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newline
|
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bitfld.long 0x0C 21. " [117] ,Wake-up enable set interrupt request channel 117" "Disabled,Enabled"
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bitfld.long 0x0C 20. " [116] ,Wake-up enable set interrupt request channel 116" "Disabled,Enabled"
|
|
bitfld.long 0x0C 19. " [115] ,Wake-up enable set interrupt request channel 115" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,Wake-up enable set interrupt request channel 114" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,Wake-up enable set interrupt request channel 113" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 16. " [112] ,Wake-up enable set interrupt request channel 112" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " [111] ,Wake-up enable set interrupt request channel 111" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [110] ,Wake-up enable set interrupt request channel 110" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,Wake-up enable set interrupt request channel 109" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,Wake-up enable set interrupt request channel 108" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 11. " [107] ,Wake-up enable set interrupt request channel 107" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,Wake-up enable set interrupt request channel 106" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [105] ,Wake-up enable set interrupt request channel 105" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,Wake-up enable set interrupt request channel 104" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " [103] ,Wake-up enable set interrupt request channel 103" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 6. " [102] ,Wake-up enable set interrupt request channel 102" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Wake-up enable set interrupt request channel 101" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Wake-up enable set interrupt request channel 100" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " [99] ,Wake-up enable set interrupt request channel 99" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [98] ,Wake-up enable set interrupt request channel 98" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 1. " [97] ,Wake-up enable set interrupt request channel 97" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,Wake-up enable set interrupt request channel 96" "Disabled,Enabled"
|
|
group.long 0x160++0x0F
|
|
line.long 0x00 "WAKEENACLR0,Wake-Up Enable Clear Register 0"
|
|
bitfld.long 0x00 31. " WAKEENACLR0_[31] ,Wake-up enable clear interrupt request channel 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Wake-up enable clear interrupt request channel 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Wake-up enable clear interrupt request channel 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Wake-up enable clear interrupt request channel 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Wake-up enable clear interrupt request channel 27" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Wake-up enable clear interrupt request channel 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Wake-up enable clear interrupt request channel 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Wake-up enable clear interrupt request channel 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Wake-up enable clear interrupt request channel 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Wake-up enable clear interrupt request channel 22" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Wake-up enable clear interrupt request channel 21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Wake-up enable clear interrupt request channel 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Wake-up enable clear interrupt request channel 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Wake-up enable clear interrupt request channel 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Wake-up enable clear interrupt request channel 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Wake-up enable clear interrupt request channel 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Wake-up enable clear interrupt request channel 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Wake-up enable clear interrupt request channel 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Wake-up enable clear interrupt request channel 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Wake-up enable clear interrupt request channel 12" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Wake-up enable clear interrupt request channel 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Wake-up enable clear interrupt request channel 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Wake-up enable clear interrupt request channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Wake-up enable clear interrupt request channel 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Wake-up enable clear interrupt request channel 7" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Wake-up enable clear interrupt request channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Wake-up enable clear interrupt request channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Wake-up enable clear interrupt request channel 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Wake-up enable clear interrupt request channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Wake-up enable clear interrupt request channel 2" "Disabled,Enabled"
|
|
line.long 0x04 "WAKEENACLR1,Wake-Up Enable Clear Register 1"
|
|
bitfld.long 0x04 31. " WAKEENACLR1_[63] ,Wake-up enable clear interrupt request channel 63" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [62] ,Wake-up enable clear interrupt request channel 62" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [61] ,Wake-up enable clear interrupt request channel 61" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [60] ,Wake-up enable clear interrupt request channel 60" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " [59] ,Wake-up enable clear interrupt request channel 59" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 26. " [58] ,Wake-up enable clear interrupt request channel 58" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [57] ,Wake-up enable clear interrupt request channel 57" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [56] ,Wake-up enable clear interrupt request channel 56" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " [55] ,Wake-up enable clear interrupt request channel 55" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [54] ,Wake-up enable clear interrupt request channel 54" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 21. " [53] ,Wake-up enable clear interrupt request channel 53" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [52] ,Wake-up enable clear interrupt request channel 52" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " [51] ,Wake-up enable clear interrupt request channel 51" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [50] ,Wake-up enable clear interrupt request channel 50" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [49] ,Wake-up enable clear interrupt request channel 49" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " [48] ,Wake-up enable clear interrupt request channel 48" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " [47] ,Wake-up enable clear interrupt request channel 47" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [46] ,Wake-up enable clear interrupt request channel 46" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [45] ,Wake-up enable clear interrupt request channel 45" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [44] ,Wake-up enable clear interrupt request channel 44" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [43] ,Wake-up enable clear interrupt request channel 43" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [42] ,Wake-up enable clear interrupt request channel 42" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [41] ,Wake-up enable clear interrupt request channel 41" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [40] ,Wake-up enable clear interrupt request channel 40" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " [39] ,Wake-up enable clear interrupt request channel 39" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 6. " [38] ,Wake-up enable clear interrupt request channel 38" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [37] ,Wake-up enable clear interrupt request channel 37" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [36] ,Wake-up enable clear interrupt request channel 36" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " [35] ,Wake-up enable clear interrupt request channel 35" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [34] ,Wake-up enable clear interrupt request channel 34" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,Wake-up enable clear interrupt request channel 33" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [32] ,Wake-up enable clear interrupt request channel 32" "Disabled,Enabled"
|
|
line.long 0x08 "WAKEENACLR2,Wake-Up Enable Clear Register 2"
|
|
bitfld.long 0x08 31. " WAKEENACLR2_[95] ,Wake-up enable clear interrupt request channel 95" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [94] ,Wake-up enable clear interrupt request channel 94" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [93] ,Wake-up enable clear interrupt request channel 93" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [92] ,Wake-up enable clear interrupt request channel 92" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " [91] ,Wake-up enable clear interrupt request channel 91" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 26. " [90] ,Wake-up enable clear interrupt request channel 90" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [89] ,Wake-up enable clear interrupt request channel 89" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [88] ,Wake-up enable clear interrupt request channel 88" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " [87] ,Wake-up enable clear interrupt request channel 87" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [86] ,Wake-up enable clear interrupt request channel 86" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 21. " [85] ,Wake-up enable clear interrupt request channel 85" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [84] ,Wake-up enable clear interrupt request channel 84" "Disabled,Enabled"
|
|
bitfld.long 0x08 19. " [83] ,Wake-up enable clear interrupt request channel 83" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [82] ,Wake-up enable clear interrupt request channel 82" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [81] ,Wake-up enable clear interrupt request channel 81" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16. " [80] ,Wake-up enable clear interrupt request channel 80" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " [79] ,Wake-up enable clear interrupt request channel 79" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [78] ,Wake-up enable clear interrupt request channel 78" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [77] ,Wake-up enable clear interrupt request channel 77" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [76] ,Wake-up enable clear interrupt request channel 76" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " [75] ,Wake-up enable clear interrupt request channel 75" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [74] ,Wake-up enable clear interrupt request channel 74" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [73] ,Wake-up enable clear interrupt request channel 73" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [72] ,Wake-up enable clear interrupt request channel 72" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " [71] ,Wake-up enable clear interrupt request channel 71" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 6. " [70] ,Wake-up enable clear interrupt request channel 70" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [69] ,Wake-up enable clear interrupt request channel 69" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [68] ,Wake-up enable clear interrupt request channel 68" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " [67] ,Wake-up enable clear interrupt request channel 67" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [66] ,Wake-up enable clear interrupt request channel 66" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 1. " [65] ,Wake-up enable clear interrupt request channel 65" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [64] ,Wake-up enable clear interrupt request channel 64" "Disabled,Enabled"
|
|
line.long 0x0C "WAKEENACLR3,Wake-Up Enable Clear Register 3"
|
|
bitfld.long 0x0C 31. " WAKEENACLR3_[127] ,Wake-up enable clear interrupt request channel 127" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [126] ,Wake-up enable clear interrupt request channel 126" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [125] ,Wake-up enable clear interrupt request channel 125" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [124] ,Wake-up enable clear interrupt request channel 124" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " [123] ,Wake-up enable clear interrupt request channel 123" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 26. " [122] ,Wake-up enable clear interrupt request channel 122" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [121] ,Wake-up enable clear interrupt request channel 121" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [120] ,Wake-up enable clear interrupt request channel 120" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " [119] ,Wake-up enable clear interrupt request channel 119" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [118] ,Wake-up enable clear interrupt request channel 118" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 21. " [117] ,Wake-up enable clear interrupt request channel 117" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [116] ,Wake-up enable clear interrupt request channel 116" "Disabled,Enabled"
|
|
bitfld.long 0x0C 19. " [115] ,Wake-up enable clear interrupt request channel 115" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [114] ,Wake-up enable clear interrupt request channel 114" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [113] ,Wake-up enable clear interrupt request channel 113" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 16. " [112] ,Wake-up enable clear interrupt request channel 112" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " [111] ,Wake-up enable clear interrupt request channel 111" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [110] ,Wake-up enable clear interrupt request channel 110" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [109] ,Wake-up enable clear interrupt request channel 109" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [108] ,Wake-up enable clear interrupt request channel 108" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 11. " [107] ,Wake-up enable clear interrupt request channel 107" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [106] ,Wake-up enable clear interrupt request channel 106" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [105] ,Wake-up enable clear interrupt request channel 105" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [104] ,Wake-up enable clear interrupt request channel 104" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " [103] ,Wake-up enable clear interrupt request channel 103" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 6. " [102] ,Wake-up enable clear interrupt request channel 102" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [101] ,Wake-up enable clear interrupt request channel 101" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [100] ,Wake-up enable clear interrupt request channel 100" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " [99] ,Wake-up enable clear interrupt request channel 99" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [98] ,Wake-up enable clear interrupt request channel 98" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 1. " [97] ,Wake-up enable clear interrupt request channel 97" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [96] ,Wake-up enable clear interrupt request channel 96" "Disabled,Enabled"
|
|
rgroup.long 0x170++0x07
|
|
line.long 0x00 "IRQVECREG,IRQ Interrupt Vector Register"
|
|
line.long 0x04 "FIQVECREG,IRQ Interrupt Vector Register"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "CAPEVT,Capture Event Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAPEVTSRC1 ,Capture event source 1 mapping control"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAPEVTSRC0 ,Capture event source 0 mapping control"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CHANCTRL0,Interrupt Control Register 0"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "CHANCTRL1,Interrupt Control Register 1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "CHANCTRL2,Interrupt Control Register 2"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "CHANCTRL3,Interrupt Control Register 3"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CHANCTRL4,Interrupt Control Register 4"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "CHANCTRL5,Interrupt Control Register 5"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "CHANCTRL6,Interrupt Control Register 6"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "CHANCTRL7,Interrupt Control Register 7"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CHANCTRL8,Interrupt Control Register 8"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "CHANCTRL9,Interrupt Control Register 9"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "CHANCTRL10,Interrupt Control Register 10"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "CHANCTRL11,Interrupt Control Register 11"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "CHANCTRL12,Interrupt Control Register 12"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "CHANCTRL13,Interrupt Control Register 13"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "CHANCTRL14,Interrupt Control Register 14"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "CHANCTRL15,Interrupt Control Register 15"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "CHANCTRL16,Interrupt Control Register 16"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "CHANCTRL17,Interrupt Control Register 17"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "CHANCTRL18,Interrupt Control Register 18"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "CHANCTRL19,Interrupt Control Register 19"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "CHANCTRL20,Interrupt Control Register 20"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "CHANCTRL21,Interrupt Control Register 21"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "CHANCTRL22,Interrupt Control Register 22"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "CHANCTRL23,Interrupt Control Register 23"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "CHANCTRL24,Interrupt Control Register 24"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "CHANCTRL25,Interrupt Control Register 25"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "CHANCTRL26,Interrupt Control Register 26"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "CHANCTRL27,Interrupt Control Register 27"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "CHANCTRL28,Interrupt Control Register 28"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "CHANCTRL29,Interrupt Control Register 29"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "CHANCTRL30,Interrupt Control Register 30"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "CHANCTRL31,Interrupt Control Register 31"
|
|
hexmask.long.byte 0x00 24.--30. 1. " CHANMAPX0 ,Interrupt CHANx0 mapping control"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CHANMAPX1 ,Interrupt CHANx1 mapping control"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CHANMAPX2 ,Interrupt CHANx2 mapping control"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " CHANMAPX3 ,Interrupt CHANx3 mapping control"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.open "EDMA (Enhanced Direct Memory Access)"
|
|
tree.open "TPCC"
|
|
tree "TPCC0"
|
|
base ad:0x50010000
|
|
width 10.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "PID,Peripheral ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major revision"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision"
|
|
line.long 0x04 "CCCFG,CC Configuration Register"
|
|
bitfld.long 0x04 25. " MPEXIST ,Memory protection existence MPEXIST" "Not protected,Protected"
|
|
bitfld.long 0x04 24. " CHMAPEXIST ,Channel mapping existence" "Not mapped,Mapped"
|
|
bitfld.long 0x04 20.--21. " NUMREGN ,Number of MP and shadow regions" ",,,8 regions"
|
|
newline
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x04 16.--18. " NUM_EVQUE ,Number of queues/number of TCs" ",2 EDMA3TCs/Event,,4 EDMA3TCs/Event,?..."
|
|
elif cpuis("AWR6843*")
|
|
bitfld.long 0x04 16.--18. " NUM_EVQUE ,Number of queues/number of TCs" "1 TC/Event queue,2 TC/Event queue,3 TC/Event queue,4 TC/Event queue,5 TC/Event queue,6 TC/Event queue,7 TC/Event queue,8 TC/Event queue"
|
|
else
|
|
bitfld.long 0x04 16.--18. " NUMTC ,Number of queues/number of TCs" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("AWR6843*")
|
|
newline
|
|
bitfld.long 0x04 12.--14. " NUMPAENTRY ,Number of PARAM entries" ",,,128,256,?..."
|
|
bitfld.long 0x04 8.--10. " NUMINTCH ,Number of interrupt channels" ",,16,,64,?..."
|
|
bitfld.long 0x04 4.--6. " NUMQDMACH ,Number of QDMA channels" ",,,,8,?..."
|
|
bitfld.long 0x04 0.--2. " NUMDMACH ,Number of DMA channels" ",,,,,64,?..."
|
|
else
|
|
newline
|
|
bitfld.long 0x04 12.--14. " NUMPAENTRY ,Number of PARAM entries" ",,,128,,512,?..."
|
|
bitfld.long 0x04 8.--10. " NUMINTCH ,Number of interrupt channels" ",,16,,64,?..."
|
|
bitfld.long 0x04 4.--6. " NUMQDMACH ,Number of QDMA channels" ",,,,8,?..."
|
|
bitfld.long 0x04 0.--2. " NUMDMACH ,Number of DMA channels" ",,,16,,64,?..."
|
|
endif
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
|
|
hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,PARAM entry number for QDMA channel N"
|
|
bitfld.long 0x00 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PARAM entry defined by PAENTRY" "OPT,SRC,BCNT/ACNT,DST,DBIDX/SBIDX,BCNTRLD/LINK,DCIDX/SCIDX,CCNT"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "DMAQNUMN,DMA Queue Number Register"
|
|
bitfld.long 0x00 28.--30. " E7 ,DMA queue number for event #7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " E6 ,DMA queue number for event #6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " E5 ,DMA queue number for event #5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " E4 ,DMA queue number for event #4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " E3 ,DMA queue number for event #3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " E2 ,DMA queue number for event #2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " E1 ,DMA queue number for event #1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " E0 ,DMA queue number for event #0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register"
|
|
bitfld.long 0x00 28.--30. " E7 ,QDMA queue number for event #7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " E6 ,QDMA queue number for event #6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " E5 ,QDMA queue number for event #5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " E4 ,QDMA queue number for event #4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " E3 ,QDMA queue number for event #3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " E2 ,QDMA queue number for event #2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " E1 ,QDMA queue number for event #1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " E0 ,QDMA queue number for event #0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x280++0x07
|
|
line.long 0x00 "QUETCMAP,Queue To TC Mapping Register"
|
|
bitfld.long 0x00 4.--6. " TCNUMQ1 ,TC number for queue N" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " TCNUMQ0 ,TC number for queue N" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "QUEPRI,Queue Priority Register"
|
|
bitfld.long 0x04 4.--6. " PRIQ1 ,Priority level for queue 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " PRIQ0 ,Priority level for queue 0" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "EMR,Event Missed Register"
|
|
bitfld.long 0x00 31. " E31 ,Event missed #31" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " E30 ,Event missed #30" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " E29 ,Event missed #29" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " E28 ,Event missed #28" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " E27 ,Event missed #27" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " E26 ,Event missed #26" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 25. " E25 ,Event missed #25" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " E24 ,Event missed #24" "Not occurred,Occurred"
|
|
bitfld.long 0x00 23. " E23 ,Event missed #23" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " E22 ,Event missed #22" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " E21 ,Event missed #21" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " E20 ,Event missed #20" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 19. " E19 ,Event missed #19" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " E18 ,Event missed #18" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " E17 ,Event missed #17" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " E16 ,Event missed #16" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " E15 ,Event missed #15" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " E14 ,Event missed #14" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 13. " E13 ,Event missed #13" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " E12 ,Event missed #12" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " E11 ,Event missed #11" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " E10 ,Event missed #10" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " E9 ,Event missed #9" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " E8 ,Event missed #8" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 7. " E7 ,Event missed #7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " E6 ,Event missed #6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " E5 ,Event missed #5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " E4 ,Event missed #4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " E3 ,Event missed #3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " E2 ,Event missed #2" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,Event missed #1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " E0 ,Event missed #0" "Not occurred,Occurred"
|
|
line.long 0x04 "EMRH,Event Missed Register (High Part)"
|
|
bitfld.long 0x04 31. " E63 ,Event missed #63" "Not occurred,Occurred"
|
|
bitfld.long 0x04 30. " E62 ,Event missed #62" "Not occurred,Occurred"
|
|
bitfld.long 0x04 29. " E61 ,Event missed #61" "Not occurred,Occurred"
|
|
bitfld.long 0x04 28. " E60 ,Event missed #60" "Not occurred,Occurred"
|
|
bitfld.long 0x04 27. " E59 ,Event missed #59" "Not occurred,Occurred"
|
|
bitfld.long 0x04 26. " E58 ,Event missed #58" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 25. " E57 ,Event missed #57" "Not occurred,Occurred"
|
|
bitfld.long 0x04 24. " E56 ,Event missed #56" "Not occurred,Occurred"
|
|
bitfld.long 0x04 23. " E55 ,Event missed #55" "Not occurred,Occurred"
|
|
bitfld.long 0x04 22. " E54 ,Event missed #54" "Not occurred,Occurred"
|
|
bitfld.long 0x04 21. " E53 ,Event missed #53" "Not occurred,Occurred"
|
|
bitfld.long 0x04 20. " E52 ,Event missed #52" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 19. " E51 ,Event missed #51" "Not occurred,Occurred"
|
|
bitfld.long 0x04 18. " E50 ,Event missed #50" "Not occurred,Occurred"
|
|
bitfld.long 0x04 17. " E49 ,Event missed #49" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16. " E48 ,Event missed #48" "Not occurred,Occurred"
|
|
bitfld.long 0x04 15. " E47 ,Event missed #47" "Not occurred,Occurred"
|
|
bitfld.long 0x04 14. " E46 ,Event missed #46" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 13. " E45 ,Event missed #45" "Not occurred,Occurred"
|
|
bitfld.long 0x04 12. " E44 ,Event missed #44" "Not occurred,Occurred"
|
|
bitfld.long 0x04 11. " E43 ,Event missed #43" "Not occurred,Occurred"
|
|
bitfld.long 0x04 10. " E42 ,Event missed #42" "Not occurred,Occurred"
|
|
bitfld.long 0x04 9. " E41 ,Event missed #41" "Not occurred,Occurred"
|
|
bitfld.long 0x04 8. " E40 ,Event missed #40" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 7. " E39 ,Event missed #39" "Not occurred,Occurred"
|
|
bitfld.long 0x04 6. " E38 ,Event missed #38" "Not occurred,Occurred"
|
|
bitfld.long 0x04 5. " E37 ,Event missed #37" "Not occurred,Occurred"
|
|
bitfld.long 0x04 4. " E36 ,Event missed #36" "Not occurred,Occurred"
|
|
bitfld.long 0x04 3. " E35 ,Event missed #35" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " E34 ,Event missed #34" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 1. " E33 ,Event missed #33" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0. " E32 ,Event missed #32" "Not occurred,Occurred"
|
|
wgroup.long 0x308++0x07
|
|
line.long 0x00 "EMCR,Event Missed Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Event missed clear #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Event missed clear #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Event missed clear #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " E28 ,Event missed clear #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Event missed clear #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Event missed clear #26" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 25. " E25 ,Event missed clear #25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " E24 ,Event missed clear #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Event missed clear #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " E22 ,Event missed clear #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Event missed clear #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Event missed clear #20" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 19. " E19 ,Event missed clear #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Event missed clear #18" "No effect,Clear"
|
|
bitfld.long 0x00 17. " E17 ,Event missed clear #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " E16 ,Event missed clear #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Event missed clear #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Event missed clear #14" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 13. " E13 ,Event missed clear #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Event missed clear #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Event missed clear #11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " E10 ,Event missed clear #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Event missed clear #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Event missed clear #8" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 7. " E7 ,Event missed clear #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event missed clear #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event missed clear #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event missed clear #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event missed clear #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event missed clear #2" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,Event missed clear #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Event missed clear #0" "No effect,Clear"
|
|
line.long 0x04 "EMCRH,Event Missed Clear Register (High Part)"
|
|
bitfld.long 0x04 31. " E63 ,Event missed clear #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Event missed clear #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Event missed clear #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " E60 ,Event missed clear #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Event missed clear #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Event missed clear #58" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 25. " E57 ,Event missed clear #57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " E56 ,Event missed clear #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Event missed clear #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " E54 ,Event missed clear #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Event missed clear #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Event missed clear #52" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 19. " E51 ,Event missed clear #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Event missed clear #50" "No effect,Clear"
|
|
bitfld.long 0x04 17. " E49 ,Event missed clear #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " E48 ,Event missed clear #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Event missed clear #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Event missed clear #46" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 13. " E45 ,Event missed clear #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Event missed clear #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Event missed clear #43" "No effect,Clear"
|
|
bitfld.long 0x04 10. " E42 ,Event missed clear #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Event missed clear #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Event missed clear #40" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 7. " E39 ,Event missed clear #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Event missed clear #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Event missed clear #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " E36 ,Event missed clear #36" "No effect,Clear"
|
|
bitfld.long 0x04 3. " E35 ,Event missed clear #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Event missed clear #34" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 1. " E33 ,Event missed clear #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Event missed clear #32" "No effect,Clear"
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "QEMR,QDMA Event Missed Register"
|
|
bitfld.long 0x00 7. " E7 ,Event missed #7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " E6 ,Event missed #6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " E5 ,Event missed #5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " E4 ,Event missed #4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " E3 ,Event missed #3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " E2 ,Event missed #2" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,Event missed #1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " E0 ,Event missed #0" "Not occurred,Occurred"
|
|
wgroup.long 0x314++0x03
|
|
line.long 0x00 "QEMR,QDMA Event Missed Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,Event missed clear #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event missed clear #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event missed clear #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event missed clear #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event missed clear #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event missed clear #2" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,Event missed clear #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Event missed clear #0" "No effect,Clear"
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "CCERR,CC Error Register"
|
|
bitfld.long 0x00 16. " TCERR ,Transfer completion code error" "No error,Error"
|
|
bitfld.long 0x00 7. " QTHRXCD7 ,Queue threshold error for Q7" "No error,Error"
|
|
bitfld.long 0x00 6. " QTHRXCD6 ,Queue threshold error for Q6" "No error,Error"
|
|
bitfld.long 0x00 5. " QTHRXCD5 ,Queue threshold error for Q5" "No error,Error"
|
|
bitfld.long 0x00 4. " QTHRXCD4 ,Queue threshold error for Q4" "No error,Error"
|
|
bitfld.long 0x00 3. " QTHRXCD3 ,Queue threshold error for Q3" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " QTHRXCD2 ,Queue threshold error for Q2" "No error,Error"
|
|
bitfld.long 0x00 1. " QTHRXCD1 ,Queue threshold error for Q1" "No error,Error"
|
|
bitfld.long 0x00 0. " QTHRXCD0 ,Queue threshold error for Q0" "No error,Error"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
wgroup.long 0x31C++0x07
|
|
line.long 0x00 "CCERRCLR,CC Error Clear Register"
|
|
bitfld.long 0x00 16. " TCERR ,Transfer completion code error" "No effect,Clear"
|
|
bitfld.long 0x00 7. " QTHRXCD7 ,Clear error for CCERR.QTHRXCD7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " QTHRXCD6 ,Clear error for CCERR.QTHRXCD6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " QTHRXCD5 ,Clear error for CCERR.QTHRXCD5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " QTHRXCD4 ,Clear error for CCERR.QTHRXCD4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " QTHRXCD3 ,Clear error for CCERR.QTHRXCD3" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " QTHRXCD2 ,Clear error for CCERR.QTHRXCD2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " QTHRXCD1 ,Clear error for CCERR.QTHRXCD1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " QTHRXCD0 ,Clear error for CCERR.QTHRXCD0" "No effect,Clear"
|
|
line.long 0x04 "EEVAL,Error Eval Register"
|
|
bitfld.long 0x04 1. " SET ,Error interrupt set" "No error,Error"
|
|
bitfld.long 0x04 0. " EVAL ,Error interrupt evaluate" "No error,Error"
|
|
else
|
|
wgroup.long 0x31C++0x07
|
|
line.long 0x00 "CCERR,CC Error Clear Register"
|
|
bitfld.long 0x00 16. " TCERR ,Transfer completion code error" "No effect,Clear"
|
|
bitfld.long 0x00 7. " QTHRXCD7 ,Clear error for CCERR.QTHRXCD7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " QTHRXCD6 ,Clear error for CCERR.QTHRXCD6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " QTHRXCD5 ,Clear error for CCERR.QTHRXCD5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " QTHRXCD4 ,Clear error for CCERR.QTHRXCD4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " QTHRXCD3 ,Clear error for CCERR.QTHRXCD3" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " QTHRXCD2 ,Clear error for CCERR.QTHRXCD2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " QTHRXCD1 ,Clear error for CCERR.QTHRXCD1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " QTHRXCD0 ,Clear error for CCERR.QTHRXCD0" "No effect,Clear"
|
|
line.long 0x04 "CCERR,Error Eval Register"
|
|
bitfld.long 0x04 1. " SET ,Error interrupt set" "No error,Error"
|
|
bitfld.long 0x04 0. " EVAL ,Error interrupt evaluate" "No error,Error"
|
|
endif
|
|
group.long 0x340++0x07
|
|
line.long 0x00 "DRAEM,DMA Region Access Enable Register"
|
|
bitfld.long 0x00 31. " E31 ,DMA region access enable for region M bit #31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " E30 ,DMA region access enable for region M bit #30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " E29 ,DMA region access enable for region M bit #29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " E28 ,DMA region access enable for region M bit #28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " E27 ,DMA region access enable for region M bit #27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " E26 ,DMA region access enable for region M bit #26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " E25 ,DMA region access enable for region M bit #25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " E24 ,DMA region access enable for region M bit #24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " E23 ,DMA region access enable for region M bit #23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " E22 ,DMA region access enable for region M bit #22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " E21 ,DMA region access enable for region M bit #21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " E20 ,DMA region access enable for region M bit #20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " E19 ,DMA region access enable for region M bit #19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " E18 ,DMA region access enable for region M bit #18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " E17 ,DMA region access enable for region M bit #17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " E16 ,DMA region access enable for region M bit #16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " E15 ,DMA region access enable for region M bit #15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " E14 ,DMA region access enable for region M bit #14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " E13 ,DMA region access enable for region M bit #13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " E12 ,DMA region access enable for region M bit #12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " E11 ,DMA region access enable for region M bit #11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " E10 ,DMA region access enable for region M bit #10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " E9 ,DMA region access enable for region M bit #9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " E8 ,DMA region access enable for region M bit #8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " E7 ,DMA region access enable for region M bit #7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " E6 ,DMA region access enable for region M bit #6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E5 ,DMA region access enable for region M bit #5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " E4 ,DMA region access enable for region M bit #4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " E3 ,DMA region access enable for region M bit #3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " E2 ,DMA region access enable for region M bit #2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,DMA region access enable for region M bit #1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " E0 ,DMA region access enable for region M bit #0" "Disabled,Enabled"
|
|
line.long 0x04 "DRAEHM,DMA Region Access Enable Register"
|
|
bitfld.long 0x04 31. " E63 ,DMA region access enable for region M bit #63" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " E62 ,DMA region access enable for region M bit #62" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " E61 ,DMA region access enable for region M bit #61" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " E60 ,DMA region access enable for region M bit #60" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " E59 ,DMA region access enable for region M bit #59" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " E58 ,DMA region access enable for region M bit #58" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " E57 ,DMA region access enable for region M bit #57" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " E56 ,DMA region access enable for region M bit #56" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " E55 ,DMA region access enable for region M bit #55" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " E54 ,DMA region access enable for region M bit #54" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " E53 ,DMA region access enable for region M bit #53" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " E52 ,DMA region access enable for region M bit #52" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " E51 ,DMA region access enable for region M bit #51" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " E50 ,DMA region access enable for region M bit #50" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " E49 ,DMA region access enable for region M bit #49" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " E48 ,DMA region access enable for region M bit #48" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " E47 ,DMA region access enable for region M bit #47" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " E46 ,DMA region access enable for region M bit #46" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " E45 ,DMA region access enable for region M bit #45" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " E44 ,DMA region access enable for region M bit #44" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " E43 ,DMA region access enable for region M bit #43" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " E42 ,DMA region access enable for region M bit #42" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " E41 ,DMA region access enable for region M bit #41" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " E40 ,DMA region access enable for region M bit #40" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " E39 ,DMA region access enable for region M bit #39" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " E38 ,DMA region access enable for region M bit #38" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E37 ,DMA region access enable for region M bit #37" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " E36 ,DMA region access enable for region M bit #36" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " E35 ,DMA region access enable for region M bit #35" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " E34 ,DMA region access enable for region M bit #34" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " E33 ,DMA region access enable for region M bit #33" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " E32 ,DMA region access enable for region M bit #32" "Disabled,Enabled"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "QRAEN,QDMA Region Access Enable Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA region access enable for region M bit #7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " E6 ,QDMA region access enable for region M bit #6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E5 ,QDMA region access enable for region M bit #5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " E4 ,QDMA region access enable for region M bit #4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " E3 ,QDMA region access enable for region M bit #3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " E2 ,QDMA region access enable for region M bit #2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,QDMA region access enable for region M bit #1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " E0 ,QDMA region access enable for region M bit #0" "Disabled,Enabled"
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "QNE0,Event Queue Entry Diagram For Queue n - Entry 0"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x404++0x03
|
|
line.long 0x00 "QNE1,Event Queue Entry Diagram For Queue n - Entry 1"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x408++0x03
|
|
line.long 0x00 "QNE2,Event Queue Entry Diagram For Queue n - Entry 2"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "QNE3,Event Queue Entry Diagram For Queue n - Entry 3"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x410++0x03
|
|
line.long 0x00 "QNE4,Event Queue Entry Diagram For Queue n - Entry 4"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x414++0x03
|
|
line.long 0x00 "QNE5,Event Queue Entry Diagram For Queue n - Entry 5"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x418++0x03
|
|
line.long 0x00 "QNE6,Event Queue Entry Diagram For Queue n - Entry 6"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x41C++0x03
|
|
line.long 0x00 "QNE7,Event Queue Entry Diagram For Queue n - Entry 7"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x420++0x03
|
|
line.long 0x00 "QNE8,Event Queue Entry Diagram For Queue n - Entry 8"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x424++0x03
|
|
line.long 0x00 "QNE9,Event Queue Entry Diagram For Queue n - Entry 9"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x428++0x03
|
|
line.long 0x00 "QNE10,Event Queue Entry Diagram For Queue n - Entry 10"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x42C++0x03
|
|
line.long 0x00 "QNE11,Event Queue Entry Diagram For Queue n - Entry 11"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x430++0x03
|
|
line.long 0x00 "QNE12,Event Queue Entry Diagram For Queue n - Entry 12"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x434++0x03
|
|
line.long 0x00 "QNE13,Event Queue Entry Diagram For Queue n - Entry 13"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x438++0x03
|
|
line.long 0x00 "QNE14,Event Queue Entry Diagram For Queue n - Entry 14"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x43C++0x03
|
|
line.long 0x00 "QNE15,Event Queue Entry Diagram For Queue n - Entry 15"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x600++0x03
|
|
line.long 0x00 "QSTATN,QSTATn Register Set"
|
|
bitfld.long 0x00 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded"
|
|
bitfld.long 0x00 16.--20. " WM ,Watermark for maximum queue usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--12. " NUMVAL ,Number of valid entries in queueN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0.--3. " STRTPTR ,Start pointer" "0th,1th,2th,3th,4th,5th,6th,7th,8th,9th,10th,11th,12th,13th,14th,15th"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "QWMTHRA,Queue Threshold A For Q[3:0] Register"
|
|
bitfld.long 0x00 8.--12. " Q1 ,Queue threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x00 0.--4. " Q0 ,Queue threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
width 18.
|
|
newline
|
|
rgroup.long 0x640++0x03
|
|
line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register"
|
|
bitfld.long 0x00 23. " QUEACTV7 ,Queue 7 active QUEACTV7" "Not active,Active"
|
|
bitfld.long 0x00 22. " QUEACTV6 ,Queue 6 active QUEACTV6" "Not active,Active"
|
|
bitfld.long 0x00 21. " QUEACTV5 ,Queue 5 active QUEACTV5" "Not active,Active"
|
|
bitfld.long 0x00 20. " QUEACTV4 ,Queue 4 active QUEACTV4" "Not active,Active"
|
|
bitfld.long 0x00 19. " QUEACTV3 ,Queue 3 active QUEACTV3" "Not active,Active"
|
|
bitfld.long 0x00 18. " QUEACTV2 ,Queue 2 active QUEACTV2" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 17. " QUEACTV1 ,Queue 1 active QUEACTV1" "Not active,Active"
|
|
bitfld.long 0x00 16. " QUEACTV0 ,Queue 0 active QUEACTV0" "Not active,Active"
|
|
bitfld.long 0x00 8.--13. " COMPACTV ,Completion request active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4. " ACTV ,Channel controller active" "Idle,Busy"
|
|
bitfld.long 0x00 2. " TRACTV ,Transfer request active" "Not active,Active"
|
|
bitfld.long 0x00 1. " QEVTACTV ,QDMA event active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 0. " EVTACTV ,DMA event active" "Not active,Active"
|
|
newline
|
|
width 9.
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "AETCTL,Advanced Event Trigger Control Register"
|
|
bitfld.long 0x00 31. " EN ,AET enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
bitfld.long 0x00 8.--13. " ENDINT ,AET end interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,56,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 7. " ENDINT ,AET end interrupt" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 6. " TYPE ,AET event type" "DMA,QDMA"
|
|
bitfld.long 0x00 0.--5. " STRTEVT ,AET start event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x704++0x03
|
|
line.long 0x00 "AETSTAT,Advanced Event Trigger Status Register"
|
|
bitfld.long 0x00 0. " STAT ,AET status" "Low,High"
|
|
wgroup.long 0x708++0x03
|
|
line.long 0x00 "AETCMD,AET Command Register"
|
|
bitfld.long 0x00 0. " CLR ,AET clear command" "No effect,Clear"
|
|
newline
|
|
width 17.
|
|
group.long 0x1000++0x07
|
|
line.long 0x00 "ER_SET/CLR,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31 ,Event #31" "Inactive,Active"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30 ,Event #30" "Inactive,Active"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29 ,Event #29" "Inactive,Active"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28 ,Event #28" "Inactive,Active"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27 ,Event #27" "Inactive,Active"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26 ,Event #26" "Inactive,Active"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25 ,Event #25" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24 ,Event #24" "Inactive,Active"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23 ,Event #23" "Inactive,Active"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22 ,Event #22" "Inactive,Active"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21 ,Event #21" "Inactive,Active"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20 ,Event #20" "Inactive,Active"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19 ,Event #19" "Inactive,Active"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18 ,Event #18" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17 ,Event #17" "Inactive,Active"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16 ,Event #16" "Inactive,Active"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15 ,Event #15" "Inactive,Active"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14 ,Event #14" "Inactive,Active"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13 ,Event #13" "Inactive,Active"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12 ,Event #12" "Inactive,Active"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11 ,Event #11" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10 ,Event #10" "Inactive,Active"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9 ,Event #9" "Inactive,Active"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8 ,Event #8" "Inactive,Active"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7 ,Event #7" "Inactive,Active"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6 ,Event #6" "Inactive,Active"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5 ,Event #5" "Inactive,Active"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4 ,Event #4" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3 ,Event #3" "Inactive,Active"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2 ,Event #2" "Inactive,Active"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1 ,Event #1" "Inactive,Active"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0 ,Event #0" "Inactive,Active"
|
|
line.long 0x04 "ERH_SET/CLR,Event Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " E63 ,Event #63" "Inactive,Active"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " E62 ,Event #62" "Inactive,Active"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " E61 ,Event #61" "Inactive,Active"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " E60 ,Event #60" "Inactive,Active"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " E59 ,Event #59" "Inactive,Active"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " E58 ,Event #58" "Inactive,Active"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " E57 ,Event #57" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " E56 ,Event #56" "Inactive,Active"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " E55 ,Event #55" "Inactive,Active"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " E54 ,Event #54" "Inactive,Active"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " E53 ,Event #53" "Inactive,Active"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " E52 ,Event #52" "Inactive,Active"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " E51 ,Event #51" "Inactive,Active"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " E50 ,Event #50" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " E49 ,Event #49" "Inactive,Active"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " E48 ,Event #48" "Inactive,Active"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " E47 ,Event #47" "Inactive,Active"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " E46 ,Event #46" "Inactive,Active"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " E45 ,Event #45" "Inactive,Active"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " E44 ,Event #44" "Inactive,Active"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " E43 ,Event #43" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " E42 ,Event #42" "Inactive,Active"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " E41 ,Event #41" "Inactive,Active"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " E40 ,Event #40" "Inactive,Active"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " E39 ,Event #39" "Inactive,Active"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " E38 ,Event #38" "Inactive,Active"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " E37 ,Event #37" "Inactive,Active"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " E36 ,Event #36" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " E35 ,Event #35" "Inactive,Active"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " E34 ,Event #34" "Inactive,Active"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " E33 ,Event #33" "Inactive,Active"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " E32 ,Event #32" "Inactive,Active"
|
|
rgroup.long 0x1018++0x07
|
|
line.long 0x00 "CER,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "Not chained,Chained"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "Not chained,Chained"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "Not chained,Chained"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "Not chained,Chained"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "Not chained,Chained"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "Not chained,Chained"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "Not chained,Chained"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "Not chained,Chained"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "Not chained,Chained"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "Not chained,Chained"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "Not chained,Chained"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "Not chained,Chained"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "Not chained,Chained"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "Not chained,Chained"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "Not chained,Chained"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "Not chained,Chained"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "Not chained,Chained"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "Not chained,Chained"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "Not chained,Chained"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "Not chained,Chained"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "Not chained,Chained"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not chained,Chained"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not chained,Chained"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not chained,Chained"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not chained,Chained"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not chained,Chained"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not chained,Chained"
|
|
line.long 0x04 "CERH,Chained Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "Not chained,Chained"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "Not chained,Chained"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "Not chained,Chained"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "Not chained,Chained"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "Not chained,Chained"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "Not chained,Chained"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "Not chained,Chained"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "Not chained,Chained"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "Not chained,Chained"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "Not chained,Chained"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "Not chained,Chained"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "Not chained,Chained"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "Not chained,Chained"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "Not chained,Chained"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "Not chained,Chained"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "Not chained,Chained"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "Not chained,Chained"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "Not chained,Chained"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "Not chained,Chained"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "Not chained,Chained"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "Not chained,Chained"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "Not chained,Chained"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "Not chained,Chained"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "Not chained,Chained"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "Not chained,Chained"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "Not chained,Chained"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "Not chained,Chained"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "Not chained,Chained"
|
|
group.long 0x1020++0x07
|
|
line.long 0x00 "EER_SET/CLR,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31 ,Event #31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30 ,Event #30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29 ,Event #29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28 ,Event #28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27 ,Event #27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26 ,Event #26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25 ,Event #25" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24 ,Event #24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23 ,Event #23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22 ,Event #22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21 ,Event #21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20 ,Event #20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19 ,Event #19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18 ,Event #18" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17 ,Event #17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16 ,Event #16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15 ,Event #15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14 ,Event #14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13 ,Event #13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12 ,Event #12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11 ,Event #11" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10 ,Event #10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9 ,Event #9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8 ,Event #8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7 ,Event #7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6 ,Event #6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5 ,Event #5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4 ,Event #4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3 ,Event #3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2 ,Event #2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1 ,Event #1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0 ,Event #0" "Disabled,Enabled"
|
|
line.long 0x04 "EERH_SET/CLR,Event Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " E63 ,Event #63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " E62 ,Event #62" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " E61 ,Event #61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " E60 ,Event #60" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " E59 ,Event #59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " E58 ,Event #58" "Disabled,Enabled"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " E57 ,Event #57" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " E56 ,Event #56" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " E55 ,Event #55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " E54 ,Event #54" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " E53 ,Event #53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " E52 ,Event #52" "Disabled,Enabled"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " E51 ,Event #51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " E50 ,Event #50" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " E49 ,Event #49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " E48 ,Event #48" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " E47 ,Event #47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " E46 ,Event #46" "Disabled,Enabled"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " E45 ,Event #45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " E44 ,Event #44" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " E43 ,Event #43" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " E42 ,Event #42" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " E41 ,Event #41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " E40 ,Event #40" "Disabled,Enabled"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " E39 ,Event #39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " E38 ,Event #38" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " E37 ,Event #37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " E36 ,Event #36" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " E35 ,Event #35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " E34 ,Event #34" "Disabled,Enabled"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " E33 ,Event #33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " E32 ,Event #32" "Disabled,Enabled"
|
|
rgroup.long 0x1038++0x07
|
|
line.long 0x00 "SER,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "Not stored,Stored"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "Not stored,Stored"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "Not stored,Stored"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "Not stored,Stored"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "Not stored,Stored"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "Not stored,Stored"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "Not stored,Stored"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "Not stored,Stored"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "Not stored,Stored"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "Not stored,Stored"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "Not stored,Stored"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not stored,Stored"
|
|
line.long 0x04 "SERH,EDMA TPCC Secondary Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "Not stored,Stored"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "Not stored,Stored"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "Not stored,Stored"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "Not stored,Stored"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "Not stored,Stored"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "Not stored,Stored"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "Not stored,Stored"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "Not stored,Stored"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "Not stored,Stored"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "Not stored,Stored"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "Not stored,Stored"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "Not stored,Stored"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "Not stored,Stored"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "Not stored,Stored"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "Not stored,Stored"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "Not stored,Stored"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "Not stored,Stored"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "Not stored,Stored"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "Not stored,Stored"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "Not stored,Stored"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "Not stored,Stored"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "Not stored,Stored"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "Not stored,Stored"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "Not stored,Stored"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "Not stored,Stored"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "Not stored,Stored"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "Not stored,Stored"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "Not stored,Stored"
|
|
wgroup.long 0x1040++0x07
|
|
line.long 0x00 "SECR,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "No effect,Clear"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "No effect,Clear"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "No effect,Clear"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
line.long 0x04 "SECRH,Secondary Event Clear Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "No effect,Clear"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "No effect,Clear"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "No effect,Clear"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "No effect,Clear"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "No effect,Clear"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "No effect,Clear"
|
|
group.long 0x1050++0x07
|
|
line.long 0x00 "IER_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31 ,Interrupt associated with TCC #31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30 ,Interrupt associated with TCC #30" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29 ,Interrupt associated with TCC #29" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28 ,Interrupt associated with TCC #28" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27 ,Interrupt associated with TCC #27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26 ,Interrupt associated with TCC #26" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25 ,Interrupt associated with TCC #25" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24 ,Interrupt associated with TCC #24" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23 ,Interrupt associated with TCC #23" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22 ,Interrupt associated with TCC #22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21 ,Interrupt associated with TCC #21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20 ,Interrupt associated with TCC #20" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19 ,Interrupt associated with TCC #19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18 ,Interrupt associated with TCC #18" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17 ,Interrupt associated with TCC #17" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16 ,Interrupt associated with TCC #16" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15 ,Interrupt associated with TCC #15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14 ,Interrupt associated with TCC #14" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13 ,Interrupt associated with TCC #13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12 ,Interrupt associated with TCC #12" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11 ,Interrupt associated with TCC #11" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10 ,Interrupt associated with TCC #10" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9 ,Interrupt associated with TCC #9" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8 ,Interrupt associated with TCC #8" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I7 ,Interrupt associated with TCC #7" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I6 ,Interrupt associated with TCC #6" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I5 ,Interrupt associated with TCC #5" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I4 ,Interrupt associated with TCC #4" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3 ,Interrupt associated with TCC #3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2 ,Interrupt associated with TCC #2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1 ,Interrupt associated with TCC #1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0 ,Interrupt associated with TCC #0" "No interrupt,Interrupt"
|
|
line.long 0x04 "IERH_SET/CLR,EDMA TPCC Interrupts Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " I63 ,Interrupt associated with TCC #63" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " I62 ,Interrupt associated with TCC #62" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " I61 ,Interrupt associated with TCC #61" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " I60 ,Interrupt associated with TCC #60" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " I59 ,Interrupt associated with TCC #59" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " I58 ,Interrupt associated with TCC #58" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " I57 ,Interrupt associated with TCC #57" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " I56 ,Interrupt associated with TCC #56" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " I55 ,Interrupt associated with TCC #55" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " I54 ,Interrupt associated with TCC #54" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " I53 ,Interrupt associated with TCC #53" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " I52 ,Interrupt associated with TCC #52" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " I51 ,Interrupt associated with TCC #51" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " I50 ,Interrupt associated with TCC #50" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " I49 ,Interrupt associated with TCC #49" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " I48 ,Interrupt associated with TCC #48" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " I47 ,Interrupt associated with TCC #47" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " I46 ,Interrupt associated with TCC #46" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " I45 ,Interrupt associated with TCC #45" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " I44 ,Interrupt associated with TCC #44" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " I43 ,Interrupt associated with TCC #43" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " I42 ,Interrupt associated with TCC #42" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " I41 ,Interrupt associated with TCC #41" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " I40 ,Interrupt associated with TCC #40" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " I39 ,Interrupt associated with TCC #39" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " I38 ,Interrupt associated with TCC #38" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " I37 ,Interrupt associated with TCC #37" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " I36 ,Interrupt associated with TCC #36" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " I35 ,Interrupt associated with TCC #35" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " I34 ,Interrupt associated with TCC #34" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " I33 ,Interrupt associated with TCC #33" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " I32 ,Interrupt associated with TCC #32" "No interrupt,Interrupt"
|
|
rgroup.long 0x1068++0x07
|
|
line.long 0x00 "IPR,Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt associated with TCC #31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt associated with TCC #30" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " I29 ,Interrupt associated with TCC #29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt associated with TCC #28" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " I27 ,Interrupt associated with TCC #27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt associated with TCC #26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " I25 ,Interrupt associated with TCC #25" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 24. " I24 ,Interrupt associated with TCC #24" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " I23 ,Interrupt associated with TCC #23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt associated with TCC #22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " I21 ,Interrupt associated with TCC #21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt associated with TCC #20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " I19 ,Interrupt associated with TCC #19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt associated with TCC #18" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 17. " I17 ,Interrupt associated with TCC #17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt associated with TCC #16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " I15 ,Interrupt associated with TCC #15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt associated with TCC #14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " I13 ,Interrupt associated with TCC #13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt associated with TCC #12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " I11 ,Interrupt associated with TCC #11" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. " I10 ,Interrupt associated with TCC #10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " I9 ,Interrupt associated with TCC #9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt associated with TCC #8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " I7 ,Interrupt associated with TCC #7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt associated with TCC #6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " I5 ,Interrupt associated with TCC #5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt associated with TCC #4" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " I3 ,Interrupt associated with TCC #3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt associated with TCC #2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " I1 ,Interrupt associated with TCC #1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt associated with TCC #0" "No interrupt,Interrupt"
|
|
line.long 0x04 "IPRH,Interrupt Pending Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt associated with TCC #63" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt associated with TCC #62" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " I61 ,Interrupt associated with TCC #61" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt associated with TCC #60" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 27. " I59 ,Interrupt associated with TCC #59" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt associated with TCC #58" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " I57 ,Interrupt associated with TCC #57" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 24. " I56 ,Interrupt associated with TCC #56" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 23. " I55 ,Interrupt associated with TCC #55" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt associated with TCC #54" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " I53 ,Interrupt associated with TCC #53" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt associated with TCC #52" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 19. " I51 ,Interrupt associated with TCC #51" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt associated with TCC #50" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 17. " I49 ,Interrupt associated with TCC #49" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt associated with TCC #48" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 15. " I47 ,Interrupt associated with TCC #47" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt associated with TCC #46" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " I45 ,Interrupt associated with TCC #45" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt associated with TCC #44" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 11. " I43 ,Interrupt associated with TCC #43" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 10. " I42 ,Interrupt associated with TCC #42" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " I41 ,Interrupt associated with TCC #41" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt associated with TCC #40" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " I39 ,Interrupt associated with TCC #39" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt associated with TCC #38" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " I37 ,Interrupt associated with TCC #37" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt associated with TCC #36" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 3. " I35 ,Interrupt associated with TCC #35" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt associated with TCC #34" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " I33 ,Interrupt associated with TCC #33" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt associated with TCC #32" "No interrupt,Interrupt"
|
|
wgroup.long 0x1070++0x07
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt associated with TCC #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt associated with TCC #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " I29 ,Interrupt associated with TCC #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt associated with TCC #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " I27 ,Interrupt associated with TCC #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt associated with TCC #26" "No effect,Clear"
|
|
bitfld.long 0x00 25. " I25 ,Interrupt associated with TCC #25" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 24. " I24 ,Interrupt associated with TCC #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " I23 ,Interrupt associated with TCC #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt associated with TCC #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " I21 ,Interrupt associated with TCC #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt associated with TCC #20" "No effect,Clear"
|
|
bitfld.long 0x00 19. " I19 ,Interrupt associated with TCC #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt associated with TCC #18" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 17. " I17 ,Interrupt associated with TCC #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt associated with TCC #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " I15 ,Interrupt associated with TCC #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt associated with TCC #14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " I13 ,Interrupt associated with TCC #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt associated with TCC #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " I11 ,Interrupt associated with TCC #11" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 10. " I10 ,Interrupt associated with TCC #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " I9 ,Interrupt associated with TCC #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt associated with TCC #8" "No effect,Clear"
|
|
bitfld.long 0x00 7. " I7 ,Interrupt associated with TCC #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt associated with TCC #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " I5 ,Interrupt associated with TCC #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt associated with TCC #4" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " I3 ,Interrupt associated with TCC #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt associated with TCC #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " I1 ,Interrupt associated with TCC #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt associated with TCC #0" "No effect,Clear"
|
|
line.long 0x04 "ICRH,Interrupt Clear Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt associated with TCC #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt associated with TCC #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " I61 ,Interrupt associated with TCC #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt associated with TCC #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " I59 ,Interrupt associated with TCC #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt associated with TCC #58" "No effect,Clear"
|
|
bitfld.long 0x04 25. " I57 ,Interrupt associated with TCC #57" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 24. " I56 ,Interrupt associated with TCC #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " I55 ,Interrupt associated with TCC #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt associated with TCC #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " I53 ,Interrupt associated with TCC #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt associated with TCC #52" "No effect,Clear"
|
|
bitfld.long 0x04 19. " I51 ,Interrupt associated with TCC #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt associated with TCC #50" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 17. " I49 ,Interrupt associated with TCC #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt associated with TCC #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " I47 ,Interrupt associated with TCC #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt associated with TCC #46" "No effect,Clear"
|
|
bitfld.long 0x04 13. " I45 ,Interrupt associated with TCC #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt associated with TCC #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " I43 ,Interrupt associated with TCC #43" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10. " I42 ,Interrupt associated with TCC #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " I41 ,Interrupt associated with TCC #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt associated with TCC #40" "No effect,Clear"
|
|
bitfld.long 0x04 7. " I39 ,Interrupt associated with TCC #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt associated with TCC #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " I37 ,Interrupt associated with TCC #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt associated with TCC #36" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 3. " I35 ,Interrupt associated with TCC #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt associated with TCC #34" "No effect,Clear"
|
|
bitfld.long 0x04 1. " I33 ,Interrupt associated with TCC #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt associated with TCC #32" "No effect,Clear"
|
|
wgroup.long 0x1078++0x03
|
|
line.long 0x00 "IEVAL,Interrupt EVAL Register"
|
|
bitfld.long 0x00 1. " SET ,Interrupt set" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Interrupt evaluate" "Not set,Set"
|
|
rgroup.long 0x1080++0x03
|
|
line.long 0x00 "QER,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not occurred,Occurred"
|
|
group.long 0x1084++0x03
|
|
line.long 0x00 "QEER_SET/CLR,QDMA Event Enable Register"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7 ,Event #7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6 ,Event #6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5 ,Event #5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4 ,Event #4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3 ,Event #3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2 ,Event #2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1 ,Event #1" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0 ,Event #0" "Disabled,Enabled"
|
|
rgroup.long 0x1090++0x03
|
|
line.long 0x00 "QSER,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not stored,Stored"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not stored,Stored"
|
|
wgroup.long 0x1094++0x03
|
|
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
group.long 0x2000++0x07
|
|
line.long 0x00 "ER_RN_SET/CLR,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31 ,Event #31" "Inactive,Active"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30 ,Event #30" "Inactive,Active"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29 ,Event #29" "Inactive,Active"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28 ,Event #28" "Inactive,Active"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27 ,Event #27" "Inactive,Active"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26 ,Event #26" "Inactive,Active"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25 ,Event #25" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24 ,Event #24" "Inactive,Active"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23 ,Event #23" "Inactive,Active"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22 ,Event #22" "Inactive,Active"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21 ,Event #21" "Inactive,Active"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20 ,Event #20" "Inactive,Active"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19 ,Event #19" "Inactive,Active"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18 ,Event #18" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17 ,Event #17" "Inactive,Active"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16 ,Event #16" "Inactive,Active"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15 ,Event #15" "Inactive,Active"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14 ,Event #14" "Inactive,Active"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13 ,Event #13" "Inactive,Active"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12 ,Event #12" "Inactive,Active"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11 ,Event #11" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10 ,Event #10" "Inactive,Active"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9 ,Event #9" "Inactive,Active"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8 ,Event #8" "Inactive,Active"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7 ,Event #7" "Inactive,Active"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6 ,Event #6" "Inactive,Active"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5 ,Event #5" "Inactive,Active"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4 ,Event #4" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3 ,Event #3" "Inactive,Active"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2 ,Event #2" "Inactive,Active"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1 ,Event #1" "Inactive,Active"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0 ,Event #0" "Inactive,Active"
|
|
line.long 0x04 "ERH_RN_SET/CLR,Event Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " E63 ,Event #63" "Inactive,Active"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " E62 ,Event #62" "Inactive,Active"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " E61 ,Event #61" "Inactive,Active"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " E60 ,Event #60" "Inactive,Active"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " E59 ,Event #59" "Inactive,Active"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " E58 ,Event #58" "Inactive,Active"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " E57 ,Event #57" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " E56 ,Event #56" "Inactive,Active"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " E55 ,Event #55" "Inactive,Active"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " E54 ,Event #54" "Inactive,Active"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " E53 ,Event #53" "Inactive,Active"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " E52 ,Event #52" "Inactive,Active"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " E51 ,Event #51" "Inactive,Active"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " E50 ,Event #50" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " E49 ,Event #49" "Inactive,Active"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " E48 ,Event #48" "Inactive,Active"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " E47 ,Event #47" "Inactive,Active"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " E46 ,Event #46" "Inactive,Active"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " E45 ,Event #45" "Inactive,Active"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " E44 ,Event #44" "Inactive,Active"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " E43 ,Event #43" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x44 10. 0x0C 10. " E42 ,Event #42" "Inactive,Active"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " E41 ,Event #41" "Inactive,Active"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " E40 ,Event #40" "Inactive,Active"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " E39 ,Event #39" "Inactive,Active"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " E38 ,Event #38" "Inactive,Active"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " E37 ,Event #37" "Inactive,Active"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " E36 ,Event #36" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " E35 ,Event #35" "Inactive,Active"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " E34 ,Event #34" "Inactive,Active"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " E33 ,Event #33" "Inactive,Active"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " E32 ,Event #32" "Inactive,Active"
|
|
rgroup.long 0x2018++0x07
|
|
line.long 0x00 "CER_RN,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "Not chained,Chained"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "Not chained,Chained"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "Not chained,Chained"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "Not chained,Chained"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "Not chained,Chained"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "Not chained,Chained"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "Not chained,Chained"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "Not chained,Chained"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "Not chained,Chained"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "Not chained,Chained"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "Not chained,Chained"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "Not chained,Chained"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "Not chained,Chained"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "Not chained,Chained"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "Not chained,Chained"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "Not chained,Chained"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "Not chained,Chained"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "Not chained,Chained"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "Not chained,Chained"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "Not chained,Chained"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "Not chained,Chained"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not chained,Chained"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not chained,Chained"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not chained,Chained"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not chained,Chained"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not chained,Chained"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not chained,Chained"
|
|
line.long 0x04 "CERH_RN,Chained Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "Not chained,Chained"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "Not chained,Chained"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "Not chained,Chained"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "Not chained,Chained"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "Not chained,Chained"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "Not chained,Chained"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "Not chained,Chained"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "Not chained,Chained"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "Not chained,Chained"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "Not chained,Chained"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "Not chained,Chained"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "Not chained,Chained"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "Not chained,Chained"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "Not chained,Chained"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "Not chained,Chained"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "Not chained,Chained"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "Not chained,Chained"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "Not chained,Chained"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "Not chained,Chained"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "Not chained,Chained"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "Not chained,Chained"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "Not chained,Chained"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "Not chained,Chained"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "Not chained,Chained"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "Not chained,Chained"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "Not chained,Chained"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "Not chained,Chained"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "Not chained,Chained"
|
|
group.long 0x2020++0x07
|
|
line.long 0x00 "EER_RN_SET/CLR,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31 ,Event #31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30 ,Event #30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29 ,Event #29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28 ,Event #28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27 ,Event #27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26 ,Event #26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25 ,Event #25" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24 ,Event #24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23 ,Event #23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22 ,Event #22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21 ,Event #21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20 ,Event #20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19 ,Event #19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18 ,Event #18" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17 ,Event #17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16 ,Event #16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15 ,Event #15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14 ,Event #14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13 ,Event #13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12 ,Event #12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11 ,Event #11" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10 ,Event #10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9 ,Event #9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8 ,Event #8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7 ,Event #7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6 ,Event #6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5 ,Event #5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4 ,Event #4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3 ,Event #3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2 ,Event #2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1 ,Event #1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0 ,Event #0" "Disabled,Enabled"
|
|
line.long 0x04 "EERH_RN_SET/CLR,Event Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " E63 ,Event #63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " E62 ,Event #62" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " E61 ,Event #61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " E60 ,Event #60" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " E59 ,Event #59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " E58 ,Event #58" "Disabled,Enabled"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " E57 ,Event #57" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " E56 ,Event #56" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " E55 ,Event #55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " E54 ,Event #54" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " E53 ,Event #53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " E52 ,Event #52" "Disabled,Enabled"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " E51 ,Event #51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " E50 ,Event #50" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " E49 ,Event #49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " E48 ,Event #48" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " E47 ,Event #47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " E46 ,Event #46" "Disabled,Enabled"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " E45 ,Event #45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " E44 ,Event #44" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " E43 ,Event #43" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " E42 ,Event #42" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " E41 ,Event #41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " E40 ,Event #40" "Disabled,Enabled"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " E39 ,Event #39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " E38 ,Event #38" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " E37 ,Event #37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " E36 ,Event #36" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " E35 ,Event #35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " E34 ,Event #34" "Disabled,Enabled"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " E33 ,Event #33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " E32 ,Event #32" "Disabled,Enabled"
|
|
rgroup.long 0x2038++0x07
|
|
line.long 0x00 "SER_RN,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "Not stored,Stored"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "Not stored,Stored"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "Not stored,Stored"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "Not stored,Stored"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "Not stored,Stored"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "Not stored,Stored"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "Not stored,Stored"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "Not stored,Stored"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "Not stored,Stored"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "Not stored,Stored"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "Not stored,Stored"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not stored,Stored"
|
|
line.long 0x04 "SERH_RN,Secondary Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "Not stored,Stored"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "Not stored,Stored"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "Not stored,Stored"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "Not stored,Stored"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "Not stored,Stored"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "Not stored,Stored"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "Not stored,Stored"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "Not stored,Stored"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "Not stored,Stored"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "Not stored,Stored"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "Not stored,Stored"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "Not stored,Stored"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "Not stored,Stored"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "Not stored,Stored"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "Not stored,Stored"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "Not stored,Stored"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "Not stored,Stored"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "Not stored,Stored"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "Not stored,Stored"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "Not stored,Stored"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "Not stored,Stored"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "Not stored,Stored"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "Not stored,Stored"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "Not stored,Stored"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "Not stored,Stored"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "Not stored,Stored"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "Not stored,Stored"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "Not stored,Stored"
|
|
wgroup.long 0x2040++0x07
|
|
line.long 0x00 "SECR_RN,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "No effect,Clear"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "No effect,Clear"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "No effect,Clear"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
line.long 0x04 "SECRH_RN,Secondary Event Clear Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "No effect,Clear"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "No effect,Clear"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "No effect,Clear"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "No effect,Clear"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "No effect,Clear"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "No effect,Clear"
|
|
group.long 0x2050++0x07
|
|
line.long 0x00 "IER_RN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31 ,Interrupt associated with TCC #31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30 ,Interrupt associated with TCC #30" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29 ,Interrupt associated with TCC #29" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28 ,Interrupt associated with TCC #28" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27 ,Interrupt associated with TCC #27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26 ,Interrupt associated with TCC #26" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25 ,Interrupt associated with TCC #25" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24 ,Interrupt associated with TCC #24" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23 ,Interrupt associated with TCC #23" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22 ,Interrupt associated with TCC #22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21 ,Interrupt associated with TCC #21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20 ,Interrupt associated with TCC #20" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19 ,Interrupt associated with TCC #19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18 ,Interrupt associated with TCC #18" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17 ,Interrupt associated with TCC #17" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16 ,Interrupt associated with TCC #16" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15 ,Interrupt associated with TCC #15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14 ,Interrupt associated with TCC #14" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13 ,Interrupt associated with TCC #13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12 ,Interrupt associated with TCC #12" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11 ,Interrupt associated with TCC #11" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10 ,Interrupt associated with TCC #10" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9 ,Interrupt associated with TCC #9" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8 ,Interrupt associated with TCC #8" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I7 ,Interrupt associated with TCC #7" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I6 ,Interrupt associated with TCC #6" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I5 ,Interrupt associated with TCC #5" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I4 ,Interrupt associated with TCC #4" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3 ,Interrupt associated with TCC #3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2 ,Interrupt associated with TCC #2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1 ,Interrupt associated with TCC #1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0 ,Interrupt associated with TCC #0" "No interrupt,Interrupt"
|
|
line.long 0x04 "IERH_RN_SET/CLR,Interrupt Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " I63 ,Interrupt associated with TCC #63" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " I62 ,Interrupt associated with TCC #62" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " I61 ,Interrupt associated with TCC #61" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " I60 ,Interrupt associated with TCC #60" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " I59 ,Interrupt associated with TCC #59" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " I58 ,Interrupt associated with TCC #58" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " I57 ,Interrupt associated with TCC #57" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " I56 ,Interrupt associated with TCC #56" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " I55 ,Interrupt associated with TCC #55" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " I54 ,Interrupt associated with TCC #54" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " I53 ,Interrupt associated with TCC #53" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " I52 ,Interrupt associated with TCC #52" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " I51 ,Interrupt associated with TCC #51" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " I50 ,Interrupt associated with TCC #50" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " I49 ,Interrupt associated with TCC #49" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " I48 ,Interrupt associated with TCC #48" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " I47 ,Interrupt associated with TCC #47" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " I46 ,Interrupt associated with TCC #46" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " I45 ,Interrupt associated with TCC #45" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " I44 ,Interrupt associated with TCC #44" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " I43 ,Interrupt associated with TCC #43" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " I42 ,Interrupt associated with TCC #42" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " I41 ,Interrupt associated with TCC #41" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " I40 ,Interrupt associated with TCC #40" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " I39 ,Interrupt associated with TCC #39" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " I38 ,Interrupt associated with TCC #38" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " I37 ,Interrupt associated with TCC #37" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " I36 ,Interrupt associated with TCC #36" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " I35 ,Interrupt associated with TCC #35" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " I34 ,Interrupt associated with TCC #34" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " I33 ,Interrupt associated with TCC #33" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " I32 ,Interrupt associated with TCC #32" "No interrupt,Interrupt"
|
|
rgroup.long 0x2068++0x07
|
|
line.long 0x00 "IPR_RN,Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt associated with TCC #31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt associated with TCC #30" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " I29 ,Interrupt associated with TCC #29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt associated with TCC #28" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " I27 ,Interrupt associated with TCC #27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt associated with TCC #26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " I25 ,Interrupt associated with TCC #25" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 24. " I24 ,Interrupt associated with TCC #24" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " I23 ,Interrupt associated with TCC #23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt associated with TCC #22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " I21 ,Interrupt associated with TCC #21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt associated with TCC #20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " I19 ,Interrupt associated with TCC #19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt associated with TCC #18" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 17. " I17 ,Interrupt associated with TCC #17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt associated with TCC #16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " I15 ,Interrupt associated with TCC #15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt associated with TCC #14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " I13 ,Interrupt associated with TCC #13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt associated with TCC #12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " I11 ,Interrupt associated with TCC #11" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. " I10 ,Interrupt associated with TCC #10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " I9 ,Interrupt associated with TCC #9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt associated with TCC #8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " I7 ,Interrupt associated with TCC #7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt associated with TCC #6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " I5 ,Interrupt associated with TCC #5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt associated with TCC #4" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " I3 ,Interrupt associated with TCC #3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt associated with TCC #2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " I1 ,Interrupt associated with TCC #1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt associated with TCC #0" "No interrupt,Interrupt"
|
|
line.long 0x04 "IPRH_RN,Interrupt Pending Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt associated with TCC #63" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt associated with TCC #62" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " I61 ,Interrupt associated with TCC #61" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt associated with TCC #60" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 27. " I59 ,Interrupt associated with TCC #59" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt associated with TCC #58" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " I57 ,Interrupt associated with TCC #57" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 24. " I56 ,Interrupt associated with TCC #56" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 23. " I55 ,Interrupt associated with TCC #55" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt associated with TCC #54" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " I53 ,Interrupt associated with TCC #53" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt associated with TCC #52" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 19. " I51 ,Interrupt associated with TCC #51" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt associated with TCC #50" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 17. " I49 ,Interrupt associated with TCC #49" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt associated with TCC #48" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 15. " I47 ,Interrupt associated with TCC #47" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt associated with TCC #46" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " I45 ,Interrupt associated with TCC #45" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt associated with TCC #44" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 11. " I43 ,Interrupt associated with TCC #43" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 10. " I42 ,Interrupt associated with TCC #42" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " I41 ,Interrupt associated with TCC #41" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt associated with TCC #40" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " I39 ,Interrupt associated with TCC #39" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt associated with TCC #38" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " I37 ,Interrupt associated with TCC #37" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt associated with TCC #36" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 3. " I35 ,Interrupt associated with TCC #35" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt associated with TCC #34" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " I33 ,Interrupt associated with TCC #33" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt associated with TCC #32" "No interrupt,Interrupt"
|
|
wgroup.long 0x2070++0x0B
|
|
line.long 0x00 "ICR_RN,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt associated with TCC #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt associated with TCC #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " I29 ,Interrupt associated with TCC #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt associated with TCC #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " I27 ,Interrupt associated with TCC #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt associated with TCC #26" "No effect,Clear"
|
|
bitfld.long 0x00 25. " I25 ,Interrupt associated with TCC #25" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 24. " I24 ,Interrupt associated with TCC #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " I23 ,Interrupt associated with TCC #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt associated with TCC #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " I21 ,Interrupt associated with TCC #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt associated with TCC #20" "No effect,Clear"
|
|
bitfld.long 0x00 19. " I19 ,Interrupt associated with TCC #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt associated with TCC #18" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 17. " I17 ,Interrupt associated with TCC #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt associated with TCC #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " I15 ,Interrupt associated with TCC #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt associated with TCC #14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " I13 ,Interrupt associated with TCC #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt associated with TCC #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " I11 ,Interrupt associated with TCC #11" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 10. " I10 ,Interrupt associated with TCC #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " I9 ,Interrupt associated with TCC #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt associated with TCC #8" "No effect,Clear"
|
|
bitfld.long 0x00 7. " I7 ,Interrupt associated with TCC #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt associated with TCC #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " I5 ,Interrupt associated with TCC #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt associated with TCC #4" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " I3 ,Interrupt associated with TCC #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt associated with TCC #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " I1 ,Interrupt associated with TCC #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt associated with TCC #0" "No effect,Clear"
|
|
line.long 0x04 "ICRH_RN,Interrupt Clear Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt associated with TCC #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt associated with TCC #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " I61 ,Interrupt associated with TCC #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt associated with TCC #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " I59 ,Interrupt associated with TCC #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt associated with TCC #58" "No effect,Clear"
|
|
bitfld.long 0x04 25. " I57 ,Interrupt associated with TCC #57" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 24. " I56 ,Interrupt associated with TCC #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " I55 ,Interrupt associated with TCC #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt associated with TCC #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " I53 ,Interrupt associated with TCC #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt associated with TCC #52" "No effect,Clear"
|
|
bitfld.long 0x04 19. " I51 ,Interrupt associated with TCC #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt associated with TCC #50" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 17. " I49 ,Interrupt associated with TCC #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt associated with TCC #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " I47 ,Interrupt associated with TCC #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt associated with TCC #46" "No effect,Clear"
|
|
bitfld.long 0x04 13. " I45 ,Interrupt associated with TCC #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt associated with TCC #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " I43 ,Interrupt associated with TCC #43" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10. " I42 ,Interrupt associated with TCC #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " I41 ,Interrupt associated with TCC #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt associated with TCC #40" "No effect,Clear"
|
|
bitfld.long 0x04 7. " I39 ,Interrupt associated with TCC #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt associated with TCC #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " I37 ,Interrupt associated with TCC #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt associated with TCC #36" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 3. " I35 ,Interrupt associated with TCC #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt associated with TCC #34" "No effect,Clear"
|
|
bitfld.long 0x04 1. " I33 ,Interrupt associated with TCC #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt associated with TCC #32" "No effect,Clear"
|
|
line.long 0x08 "IEVAL_RN,Interrupt EVAL Register"
|
|
bitfld.long 0x08 1. " SET ,Interrupt set" "Not set,Set"
|
|
bitfld.long 0x08 0. " EVAL ,Interrupt evaluate" "Not set,Set"
|
|
rgroup.long 0x2080++0x07
|
|
line.long 0x00 "QER_RN,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not occurred,Occurred"
|
|
line.long 0x04 "QEER_RN,QDMA Event Enable Register"
|
|
bitfld.long 0x04 7. " E7 ,Event #7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " E6 ,Event #6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E5 ,Event #5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " E4 ,Event #4" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " E3 ,Event #3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " E2 ,Event #2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " E1 ,Event #1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " E0 ,Event #0" "Disabled,Enabled"
|
|
wgroup.long 0x2088++0x07
|
|
line.long 0x00 "QEECR_RN,QDMA Event Enable Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
line.long 0x04 "QEESR_RN,QDMA Event Enable Set Register"
|
|
bitfld.long 0x04 7. " E7 ,Event #7" "Not set,Set"
|
|
bitfld.long 0x04 6. " E6 ,Event #6" "Not set,Set"
|
|
bitfld.long 0x04 5. " E5 ,Event #5" "Not set,Set"
|
|
bitfld.long 0x04 4. " E4 ,Event #4" "Not set,Set"
|
|
bitfld.long 0x04 3. " E3 ,Event #3" "Not set,Set"
|
|
bitfld.long 0x04 2. " E2 ,Event #2" "Not set,Set"
|
|
bitfld.long 0x04 1. " E1 ,Event #1" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x04 0. " E0 ,Event #0" "Not set,Set"
|
|
rgroup.long 0x2090++0x03
|
|
line.long 0x00 "QSER_RN,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not stored,Stored"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not stored,Stored"
|
|
wgroup.long 0x2094++0x03
|
|
line.long 0x00 "QSECR_RN,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
width 7.
|
|
newline
|
|
group.long 0x4000++0x1F
|
|
line.long 0x00 "OPT,Options Parameter Register"
|
|
rbitfld.long 0x00 31. " PRIV ,Privilege level" "User,Supervisor"
|
|
rbitfld.long 0x00 24.--27. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " WIMODE ,Backward compatibility mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " STATIC ,Static entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-sync,Ab-sync"
|
|
newline
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
line.long 0x04 "SRC,Source Address Register"
|
|
line.long 0x08 "ABCNT,A And B Byte Count Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,BCNT"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,ACNT"
|
|
line.long 0x0C "DST,Destination Address Register"
|
|
line.long 0x10 "BIDX,BIDX"
|
|
hexmask.long.word 0x10 16.--31. 1. " DBIDX ,Destination 2nd dimension index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SBIDX ,Source 2nd dimension index"
|
|
line.long 0x14 "LNK,Link And Reload Parameters Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,BCNT reload"
|
|
hexmask.long.word 0x14 0.--15. 0x01 " LINK ,Link address"
|
|
line.long 0x18 "CIDX,CIDX"
|
|
hexmask.long.word 0x18 16.--31. 1. " DCIDX ,Destination frame index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SCIDX ,Source frame index"
|
|
line.long 0x1C "CCNT,C Byte Count"
|
|
hexmask.long.word 0x1C 0.--15. 1. " CCNT ,Count for 3rd dimension"
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("AWR1642"))||(cpuis("AWR1642-CORE1"))||cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
tree "TPCC1"
|
|
base ad:0x500A0000
|
|
width 10.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "PID,Peripheral ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major revision"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision"
|
|
line.long 0x04 "CCCFG,CC Configuration Register"
|
|
bitfld.long 0x04 25. " MPEXIST ,Memory protection existence MPEXIST" "Not protected,Protected"
|
|
bitfld.long 0x04 24. " CHMAPEXIST ,Channel mapping existence" "Not mapped,Mapped"
|
|
bitfld.long 0x04 20.--21. " NUMREGN ,Number of MP and shadow regions" ",,,8 regions"
|
|
newline
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x04 16.--18. " NUM_EVQUE ,Number of queues/number of TCs" ",2 EDMA3TCs/Event,,4 EDMA3TCs/Event,?..."
|
|
elif cpuis("AWR6843*")
|
|
bitfld.long 0x04 16.--18. " NUM_EVQUE ,Number of queues/number of TCs" "1 TC/Event queue,2 TC/Event queue,3 TC/Event queue,4 TC/Event queue,5 TC/Event queue,6 TC/Event queue,7 TC/Event queue,8 TC/Event queue"
|
|
else
|
|
bitfld.long 0x04 16.--18. " NUMTC ,Number of queues/number of TCs" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("AWR6843*")
|
|
newline
|
|
bitfld.long 0x04 12.--14. " NUMPAENTRY ,Number of PARAM entries" ",,,128,256,?..."
|
|
bitfld.long 0x04 8.--10. " NUMINTCH ,Number of interrupt channels" ",,16,,64,?..."
|
|
bitfld.long 0x04 4.--6. " NUMQDMACH ,Number of QDMA channels" ",,,,8,?..."
|
|
bitfld.long 0x04 0.--2. " NUMDMACH ,Number of DMA channels" ",,,,,64,?..."
|
|
else
|
|
newline
|
|
bitfld.long 0x04 12.--14. " NUMPAENTRY ,Number of PARAM entries" ",,,128,,512,?..."
|
|
bitfld.long 0x04 8.--10. " NUMINTCH ,Number of interrupt channels" ",,16,,64,?..."
|
|
bitfld.long 0x04 4.--6. " NUMQDMACH ,Number of QDMA channels" ",,,,8,?..."
|
|
bitfld.long 0x04 0.--2. " NUMDMACH ,Number of DMA channels" ",,,16,,64,?..."
|
|
endif
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
|
|
hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,PARAM entry number for QDMA channel N"
|
|
bitfld.long 0x00 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PARAM entry defined by PAENTRY" "OPT,SRC,BCNT/ACNT,DST,DBIDX/SBIDX,BCNTRLD/LINK,DCIDX/SCIDX,CCNT"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "DMAQNUMN,DMA Queue Number Register"
|
|
bitfld.long 0x00 28.--30. " E7 ,DMA queue number for event #7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " E6 ,DMA queue number for event #6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " E5 ,DMA queue number for event #5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " E4 ,DMA queue number for event #4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " E3 ,DMA queue number for event #3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " E2 ,DMA queue number for event #2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " E1 ,DMA queue number for event #1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " E0 ,DMA queue number for event #0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register"
|
|
bitfld.long 0x00 28.--30. " E7 ,QDMA queue number for event #7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " E6 ,QDMA queue number for event #6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " E5 ,QDMA queue number for event #5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " E4 ,QDMA queue number for event #4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " E3 ,QDMA queue number for event #3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " E2 ,QDMA queue number for event #2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " E1 ,QDMA queue number for event #1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " E0 ,QDMA queue number for event #0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x280++0x07
|
|
line.long 0x00 "QUETCMAP,Queue To TC Mapping Register"
|
|
bitfld.long 0x00 4.--6. " TCNUMQ1 ,TC number for queue N" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " TCNUMQ0 ,TC number for queue N" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "QUEPRI,Queue Priority Register"
|
|
bitfld.long 0x04 4.--6. " PRIQ1 ,Priority level for queue 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " PRIQ0 ,Priority level for queue 0" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "EMR,Event Missed Register"
|
|
bitfld.long 0x00 31. " E31 ,Event missed #31" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " E30 ,Event missed #30" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " E29 ,Event missed #29" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " E28 ,Event missed #28" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " E27 ,Event missed #27" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " E26 ,Event missed #26" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 25. " E25 ,Event missed #25" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " E24 ,Event missed #24" "Not occurred,Occurred"
|
|
bitfld.long 0x00 23. " E23 ,Event missed #23" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " E22 ,Event missed #22" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " E21 ,Event missed #21" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " E20 ,Event missed #20" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 19. " E19 ,Event missed #19" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " E18 ,Event missed #18" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " E17 ,Event missed #17" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " E16 ,Event missed #16" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " E15 ,Event missed #15" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " E14 ,Event missed #14" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 13. " E13 ,Event missed #13" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " E12 ,Event missed #12" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " E11 ,Event missed #11" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " E10 ,Event missed #10" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " E9 ,Event missed #9" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " E8 ,Event missed #8" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 7. " E7 ,Event missed #7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " E6 ,Event missed #6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " E5 ,Event missed #5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " E4 ,Event missed #4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " E3 ,Event missed #3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " E2 ,Event missed #2" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,Event missed #1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " E0 ,Event missed #0" "Not occurred,Occurred"
|
|
line.long 0x04 "EMRH,Event Missed Register (High Part)"
|
|
bitfld.long 0x04 31. " E63 ,Event missed #63" "Not occurred,Occurred"
|
|
bitfld.long 0x04 30. " E62 ,Event missed #62" "Not occurred,Occurred"
|
|
bitfld.long 0x04 29. " E61 ,Event missed #61" "Not occurred,Occurred"
|
|
bitfld.long 0x04 28. " E60 ,Event missed #60" "Not occurred,Occurred"
|
|
bitfld.long 0x04 27. " E59 ,Event missed #59" "Not occurred,Occurred"
|
|
bitfld.long 0x04 26. " E58 ,Event missed #58" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 25. " E57 ,Event missed #57" "Not occurred,Occurred"
|
|
bitfld.long 0x04 24. " E56 ,Event missed #56" "Not occurred,Occurred"
|
|
bitfld.long 0x04 23. " E55 ,Event missed #55" "Not occurred,Occurred"
|
|
bitfld.long 0x04 22. " E54 ,Event missed #54" "Not occurred,Occurred"
|
|
bitfld.long 0x04 21. " E53 ,Event missed #53" "Not occurred,Occurred"
|
|
bitfld.long 0x04 20. " E52 ,Event missed #52" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 19. " E51 ,Event missed #51" "Not occurred,Occurred"
|
|
bitfld.long 0x04 18. " E50 ,Event missed #50" "Not occurred,Occurred"
|
|
bitfld.long 0x04 17. " E49 ,Event missed #49" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16. " E48 ,Event missed #48" "Not occurred,Occurred"
|
|
bitfld.long 0x04 15. " E47 ,Event missed #47" "Not occurred,Occurred"
|
|
bitfld.long 0x04 14. " E46 ,Event missed #46" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 13. " E45 ,Event missed #45" "Not occurred,Occurred"
|
|
bitfld.long 0x04 12. " E44 ,Event missed #44" "Not occurred,Occurred"
|
|
bitfld.long 0x04 11. " E43 ,Event missed #43" "Not occurred,Occurred"
|
|
bitfld.long 0x04 10. " E42 ,Event missed #42" "Not occurred,Occurred"
|
|
bitfld.long 0x04 9. " E41 ,Event missed #41" "Not occurred,Occurred"
|
|
bitfld.long 0x04 8. " E40 ,Event missed #40" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 7. " E39 ,Event missed #39" "Not occurred,Occurred"
|
|
bitfld.long 0x04 6. " E38 ,Event missed #38" "Not occurred,Occurred"
|
|
bitfld.long 0x04 5. " E37 ,Event missed #37" "Not occurred,Occurred"
|
|
bitfld.long 0x04 4. " E36 ,Event missed #36" "Not occurred,Occurred"
|
|
bitfld.long 0x04 3. " E35 ,Event missed #35" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " E34 ,Event missed #34" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 1. " E33 ,Event missed #33" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0. " E32 ,Event missed #32" "Not occurred,Occurred"
|
|
wgroup.long 0x308++0x07
|
|
line.long 0x00 "EMCR,Event Missed Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Event missed clear #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Event missed clear #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Event missed clear #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " E28 ,Event missed clear #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Event missed clear #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Event missed clear #26" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 25. " E25 ,Event missed clear #25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " E24 ,Event missed clear #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Event missed clear #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " E22 ,Event missed clear #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Event missed clear #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Event missed clear #20" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 19. " E19 ,Event missed clear #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Event missed clear #18" "No effect,Clear"
|
|
bitfld.long 0x00 17. " E17 ,Event missed clear #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " E16 ,Event missed clear #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Event missed clear #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Event missed clear #14" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 13. " E13 ,Event missed clear #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Event missed clear #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Event missed clear #11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " E10 ,Event missed clear #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Event missed clear #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Event missed clear #8" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 7. " E7 ,Event missed clear #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event missed clear #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event missed clear #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event missed clear #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event missed clear #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event missed clear #2" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,Event missed clear #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Event missed clear #0" "No effect,Clear"
|
|
line.long 0x04 "EMCRH,Event Missed Clear Register (High Part)"
|
|
bitfld.long 0x04 31. " E63 ,Event missed clear #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Event missed clear #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Event missed clear #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " E60 ,Event missed clear #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Event missed clear #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Event missed clear #58" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 25. " E57 ,Event missed clear #57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " E56 ,Event missed clear #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Event missed clear #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " E54 ,Event missed clear #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Event missed clear #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Event missed clear #52" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 19. " E51 ,Event missed clear #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Event missed clear #50" "No effect,Clear"
|
|
bitfld.long 0x04 17. " E49 ,Event missed clear #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " E48 ,Event missed clear #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Event missed clear #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Event missed clear #46" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 13. " E45 ,Event missed clear #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Event missed clear #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Event missed clear #43" "No effect,Clear"
|
|
bitfld.long 0x04 10. " E42 ,Event missed clear #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Event missed clear #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Event missed clear #40" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 7. " E39 ,Event missed clear #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Event missed clear #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Event missed clear #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " E36 ,Event missed clear #36" "No effect,Clear"
|
|
bitfld.long 0x04 3. " E35 ,Event missed clear #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Event missed clear #34" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 1. " E33 ,Event missed clear #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Event missed clear #32" "No effect,Clear"
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "QEMR,QDMA Event Missed Register"
|
|
bitfld.long 0x00 7. " E7 ,Event missed #7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " E6 ,Event missed #6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " E5 ,Event missed #5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " E4 ,Event missed #4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " E3 ,Event missed #3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " E2 ,Event missed #2" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,Event missed #1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " E0 ,Event missed #0" "Not occurred,Occurred"
|
|
wgroup.long 0x314++0x03
|
|
line.long 0x00 "QEMR,QDMA Event Missed Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,Event missed clear #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event missed clear #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event missed clear #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event missed clear #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event missed clear #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event missed clear #2" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,Event missed clear #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Event missed clear #0" "No effect,Clear"
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "CCERR,CC Error Register"
|
|
bitfld.long 0x00 16. " TCERR ,Transfer completion code error" "No error,Error"
|
|
bitfld.long 0x00 7. " QTHRXCD7 ,Queue threshold error for Q7" "No error,Error"
|
|
bitfld.long 0x00 6. " QTHRXCD6 ,Queue threshold error for Q6" "No error,Error"
|
|
bitfld.long 0x00 5. " QTHRXCD5 ,Queue threshold error for Q5" "No error,Error"
|
|
bitfld.long 0x00 4. " QTHRXCD4 ,Queue threshold error for Q4" "No error,Error"
|
|
bitfld.long 0x00 3. " QTHRXCD3 ,Queue threshold error for Q3" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " QTHRXCD2 ,Queue threshold error for Q2" "No error,Error"
|
|
bitfld.long 0x00 1. " QTHRXCD1 ,Queue threshold error for Q1" "No error,Error"
|
|
bitfld.long 0x00 0. " QTHRXCD0 ,Queue threshold error for Q0" "No error,Error"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
wgroup.long 0x31C++0x07
|
|
line.long 0x00 "CCERRCLR,CC Error Clear Register"
|
|
bitfld.long 0x00 16. " TCERR ,Transfer completion code error" "No effect,Clear"
|
|
bitfld.long 0x00 7. " QTHRXCD7 ,Clear error for CCERR.QTHRXCD7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " QTHRXCD6 ,Clear error for CCERR.QTHRXCD6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " QTHRXCD5 ,Clear error for CCERR.QTHRXCD5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " QTHRXCD4 ,Clear error for CCERR.QTHRXCD4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " QTHRXCD3 ,Clear error for CCERR.QTHRXCD3" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " QTHRXCD2 ,Clear error for CCERR.QTHRXCD2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " QTHRXCD1 ,Clear error for CCERR.QTHRXCD1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " QTHRXCD0 ,Clear error for CCERR.QTHRXCD0" "No effect,Clear"
|
|
line.long 0x04 "EEVAL,Error Eval Register"
|
|
bitfld.long 0x04 1. " SET ,Error interrupt set" "No error,Error"
|
|
bitfld.long 0x04 0. " EVAL ,Error interrupt evaluate" "No error,Error"
|
|
else
|
|
wgroup.long 0x31C++0x07
|
|
line.long 0x00 "CCERR,CC Error Clear Register"
|
|
bitfld.long 0x00 16. " TCERR ,Transfer completion code error" "No effect,Clear"
|
|
bitfld.long 0x00 7. " QTHRXCD7 ,Clear error for CCERR.QTHRXCD7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " QTHRXCD6 ,Clear error for CCERR.QTHRXCD6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " QTHRXCD5 ,Clear error for CCERR.QTHRXCD5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " QTHRXCD4 ,Clear error for CCERR.QTHRXCD4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " QTHRXCD3 ,Clear error for CCERR.QTHRXCD3" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " QTHRXCD2 ,Clear error for CCERR.QTHRXCD2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " QTHRXCD1 ,Clear error for CCERR.QTHRXCD1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " QTHRXCD0 ,Clear error for CCERR.QTHRXCD0" "No effect,Clear"
|
|
line.long 0x04 "CCERR,Error Eval Register"
|
|
bitfld.long 0x04 1. " SET ,Error interrupt set" "No error,Error"
|
|
bitfld.long 0x04 0. " EVAL ,Error interrupt evaluate" "No error,Error"
|
|
endif
|
|
group.long 0x340++0x07
|
|
line.long 0x00 "DRAEM,DMA Region Access Enable Register"
|
|
bitfld.long 0x00 31. " E31 ,DMA region access enable for region M bit #31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " E30 ,DMA region access enable for region M bit #30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " E29 ,DMA region access enable for region M bit #29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " E28 ,DMA region access enable for region M bit #28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " E27 ,DMA region access enable for region M bit #27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " E26 ,DMA region access enable for region M bit #26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " E25 ,DMA region access enable for region M bit #25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " E24 ,DMA region access enable for region M bit #24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " E23 ,DMA region access enable for region M bit #23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " E22 ,DMA region access enable for region M bit #22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " E21 ,DMA region access enable for region M bit #21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " E20 ,DMA region access enable for region M bit #20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " E19 ,DMA region access enable for region M bit #19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " E18 ,DMA region access enable for region M bit #18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " E17 ,DMA region access enable for region M bit #17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " E16 ,DMA region access enable for region M bit #16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " E15 ,DMA region access enable for region M bit #15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " E14 ,DMA region access enable for region M bit #14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " E13 ,DMA region access enable for region M bit #13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " E12 ,DMA region access enable for region M bit #12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " E11 ,DMA region access enable for region M bit #11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " E10 ,DMA region access enable for region M bit #10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " E9 ,DMA region access enable for region M bit #9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " E8 ,DMA region access enable for region M bit #8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " E7 ,DMA region access enable for region M bit #7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " E6 ,DMA region access enable for region M bit #6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E5 ,DMA region access enable for region M bit #5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " E4 ,DMA region access enable for region M bit #4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " E3 ,DMA region access enable for region M bit #3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " E2 ,DMA region access enable for region M bit #2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,DMA region access enable for region M bit #1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " E0 ,DMA region access enable for region M bit #0" "Disabled,Enabled"
|
|
line.long 0x04 "DRAEHM,DMA Region Access Enable Register"
|
|
bitfld.long 0x04 31. " E63 ,DMA region access enable for region M bit #63" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " E62 ,DMA region access enable for region M bit #62" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " E61 ,DMA region access enable for region M bit #61" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " E60 ,DMA region access enable for region M bit #60" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " E59 ,DMA region access enable for region M bit #59" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " E58 ,DMA region access enable for region M bit #58" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " E57 ,DMA region access enable for region M bit #57" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " E56 ,DMA region access enable for region M bit #56" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " E55 ,DMA region access enable for region M bit #55" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " E54 ,DMA region access enable for region M bit #54" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " E53 ,DMA region access enable for region M bit #53" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " E52 ,DMA region access enable for region M bit #52" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " E51 ,DMA region access enable for region M bit #51" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " E50 ,DMA region access enable for region M bit #50" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " E49 ,DMA region access enable for region M bit #49" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " E48 ,DMA region access enable for region M bit #48" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " E47 ,DMA region access enable for region M bit #47" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " E46 ,DMA region access enable for region M bit #46" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " E45 ,DMA region access enable for region M bit #45" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " E44 ,DMA region access enable for region M bit #44" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " E43 ,DMA region access enable for region M bit #43" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " E42 ,DMA region access enable for region M bit #42" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " E41 ,DMA region access enable for region M bit #41" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " E40 ,DMA region access enable for region M bit #40" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " E39 ,DMA region access enable for region M bit #39" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " E38 ,DMA region access enable for region M bit #38" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E37 ,DMA region access enable for region M bit #37" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " E36 ,DMA region access enable for region M bit #36" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " E35 ,DMA region access enable for region M bit #35" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " E34 ,DMA region access enable for region M bit #34" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " E33 ,DMA region access enable for region M bit #33" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " E32 ,DMA region access enable for region M bit #32" "Disabled,Enabled"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "QRAEN,QDMA Region Access Enable Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA region access enable for region M bit #7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " E6 ,QDMA region access enable for region M bit #6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E5 ,QDMA region access enable for region M bit #5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " E4 ,QDMA region access enable for region M bit #4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " E3 ,QDMA region access enable for region M bit #3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " E2 ,QDMA region access enable for region M bit #2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,QDMA region access enable for region M bit #1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " E0 ,QDMA region access enable for region M bit #0" "Disabled,Enabled"
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "QNE0,Event Queue Entry Diagram For Queue n - Entry 0"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x404++0x03
|
|
line.long 0x00 "QNE1,Event Queue Entry Diagram For Queue n - Entry 1"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x408++0x03
|
|
line.long 0x00 "QNE2,Event Queue Entry Diagram For Queue n - Entry 2"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "QNE3,Event Queue Entry Diagram For Queue n - Entry 3"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x410++0x03
|
|
line.long 0x00 "QNE4,Event Queue Entry Diagram For Queue n - Entry 4"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x414++0x03
|
|
line.long 0x00 "QNE5,Event Queue Entry Diagram For Queue n - Entry 5"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x418++0x03
|
|
line.long 0x00 "QNE6,Event Queue Entry Diagram For Queue n - Entry 6"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x41C++0x03
|
|
line.long 0x00 "QNE7,Event Queue Entry Diagram For Queue n - Entry 7"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x420++0x03
|
|
line.long 0x00 "QNE8,Event Queue Entry Diagram For Queue n - Entry 8"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x424++0x03
|
|
line.long 0x00 "QNE9,Event Queue Entry Diagram For Queue n - Entry 9"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x428++0x03
|
|
line.long 0x00 "QNE10,Event Queue Entry Diagram For Queue n - Entry 10"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x42C++0x03
|
|
line.long 0x00 "QNE11,Event Queue Entry Diagram For Queue n - Entry 11"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x430++0x03
|
|
line.long 0x00 "QNE12,Event Queue Entry Diagram For Queue n - Entry 12"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x434++0x03
|
|
line.long 0x00 "QNE13,Event Queue Entry Diagram For Queue n - Entry 13"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x438++0x03
|
|
line.long 0x00 "QNE14,Event Queue Entry Diagram For Queue n - Entry 14"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x43C++0x03
|
|
line.long 0x00 "QNE15,Event Queue Entry Diagram For Queue n - Entry 15"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x600++0x03
|
|
line.long 0x00 "QSTATN,QSTATn Register Set"
|
|
bitfld.long 0x00 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded"
|
|
bitfld.long 0x00 16.--20. " WM ,Watermark for maximum queue usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--12. " NUMVAL ,Number of valid entries in queueN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0.--3. " STRTPTR ,Start pointer" "0th,1th,2th,3th,4th,5th,6th,7th,8th,9th,10th,11th,12th,13th,14th,15th"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "QWMTHRA,Queue Threshold A For Q[3:0] Register"
|
|
bitfld.long 0x00 8.--12. " Q1 ,Queue threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x00 0.--4. " Q0 ,Queue threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
width 18.
|
|
newline
|
|
rgroup.long 0x640++0x03
|
|
line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register"
|
|
bitfld.long 0x00 23. " QUEACTV7 ,Queue 7 active QUEACTV7" "Not active,Active"
|
|
bitfld.long 0x00 22. " QUEACTV6 ,Queue 6 active QUEACTV6" "Not active,Active"
|
|
bitfld.long 0x00 21. " QUEACTV5 ,Queue 5 active QUEACTV5" "Not active,Active"
|
|
bitfld.long 0x00 20. " QUEACTV4 ,Queue 4 active QUEACTV4" "Not active,Active"
|
|
bitfld.long 0x00 19. " QUEACTV3 ,Queue 3 active QUEACTV3" "Not active,Active"
|
|
bitfld.long 0x00 18. " QUEACTV2 ,Queue 2 active QUEACTV2" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 17. " QUEACTV1 ,Queue 1 active QUEACTV1" "Not active,Active"
|
|
bitfld.long 0x00 16. " QUEACTV0 ,Queue 0 active QUEACTV0" "Not active,Active"
|
|
bitfld.long 0x00 8.--13. " COMPACTV ,Completion request active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4. " ACTV ,Channel controller active" "Idle,Busy"
|
|
bitfld.long 0x00 2. " TRACTV ,Transfer request active" "Not active,Active"
|
|
bitfld.long 0x00 1. " QEVTACTV ,QDMA event active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 0. " EVTACTV ,DMA event active" "Not active,Active"
|
|
newline
|
|
width 9.
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "AETCTL,Advanced Event Trigger Control Register"
|
|
bitfld.long 0x00 31. " EN ,AET enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
bitfld.long 0x00 8.--13. " ENDINT ,AET end interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,56,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 7. " ENDINT ,AET end interrupt" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 6. " TYPE ,AET event type" "DMA,QDMA"
|
|
bitfld.long 0x00 0.--5. " STRTEVT ,AET start event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x704++0x03
|
|
line.long 0x00 "AETSTAT,Advanced Event Trigger Status Register"
|
|
bitfld.long 0x00 0. " STAT ,AET status" "Low,High"
|
|
wgroup.long 0x708++0x03
|
|
line.long 0x00 "AETCMD,AET Command Register"
|
|
bitfld.long 0x00 0. " CLR ,AET clear command" "No effect,Clear"
|
|
newline
|
|
width 17.
|
|
group.long 0x1000++0x07
|
|
line.long 0x00 "ER_SET/CLR,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31 ,Event #31" "Inactive,Active"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30 ,Event #30" "Inactive,Active"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29 ,Event #29" "Inactive,Active"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28 ,Event #28" "Inactive,Active"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27 ,Event #27" "Inactive,Active"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26 ,Event #26" "Inactive,Active"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25 ,Event #25" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24 ,Event #24" "Inactive,Active"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23 ,Event #23" "Inactive,Active"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22 ,Event #22" "Inactive,Active"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21 ,Event #21" "Inactive,Active"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20 ,Event #20" "Inactive,Active"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19 ,Event #19" "Inactive,Active"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18 ,Event #18" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17 ,Event #17" "Inactive,Active"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16 ,Event #16" "Inactive,Active"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15 ,Event #15" "Inactive,Active"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14 ,Event #14" "Inactive,Active"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13 ,Event #13" "Inactive,Active"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12 ,Event #12" "Inactive,Active"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11 ,Event #11" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10 ,Event #10" "Inactive,Active"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9 ,Event #9" "Inactive,Active"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8 ,Event #8" "Inactive,Active"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7 ,Event #7" "Inactive,Active"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6 ,Event #6" "Inactive,Active"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5 ,Event #5" "Inactive,Active"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4 ,Event #4" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3 ,Event #3" "Inactive,Active"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2 ,Event #2" "Inactive,Active"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1 ,Event #1" "Inactive,Active"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0 ,Event #0" "Inactive,Active"
|
|
line.long 0x04 "ERH_SET/CLR,Event Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " E63 ,Event #63" "Inactive,Active"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " E62 ,Event #62" "Inactive,Active"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " E61 ,Event #61" "Inactive,Active"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " E60 ,Event #60" "Inactive,Active"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " E59 ,Event #59" "Inactive,Active"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " E58 ,Event #58" "Inactive,Active"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " E57 ,Event #57" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " E56 ,Event #56" "Inactive,Active"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " E55 ,Event #55" "Inactive,Active"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " E54 ,Event #54" "Inactive,Active"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " E53 ,Event #53" "Inactive,Active"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " E52 ,Event #52" "Inactive,Active"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " E51 ,Event #51" "Inactive,Active"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " E50 ,Event #50" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " E49 ,Event #49" "Inactive,Active"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " E48 ,Event #48" "Inactive,Active"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " E47 ,Event #47" "Inactive,Active"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " E46 ,Event #46" "Inactive,Active"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " E45 ,Event #45" "Inactive,Active"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " E44 ,Event #44" "Inactive,Active"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " E43 ,Event #43" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " E42 ,Event #42" "Inactive,Active"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " E41 ,Event #41" "Inactive,Active"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " E40 ,Event #40" "Inactive,Active"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " E39 ,Event #39" "Inactive,Active"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " E38 ,Event #38" "Inactive,Active"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " E37 ,Event #37" "Inactive,Active"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " E36 ,Event #36" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " E35 ,Event #35" "Inactive,Active"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " E34 ,Event #34" "Inactive,Active"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " E33 ,Event #33" "Inactive,Active"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " E32 ,Event #32" "Inactive,Active"
|
|
rgroup.long 0x1018++0x07
|
|
line.long 0x00 "CER,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "Not chained,Chained"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "Not chained,Chained"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "Not chained,Chained"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "Not chained,Chained"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "Not chained,Chained"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "Not chained,Chained"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "Not chained,Chained"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "Not chained,Chained"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "Not chained,Chained"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "Not chained,Chained"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "Not chained,Chained"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "Not chained,Chained"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "Not chained,Chained"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "Not chained,Chained"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "Not chained,Chained"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "Not chained,Chained"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "Not chained,Chained"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "Not chained,Chained"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "Not chained,Chained"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "Not chained,Chained"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "Not chained,Chained"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not chained,Chained"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not chained,Chained"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not chained,Chained"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not chained,Chained"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not chained,Chained"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not chained,Chained"
|
|
line.long 0x04 "CERH,Chained Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "Not chained,Chained"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "Not chained,Chained"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "Not chained,Chained"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "Not chained,Chained"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "Not chained,Chained"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "Not chained,Chained"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "Not chained,Chained"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "Not chained,Chained"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "Not chained,Chained"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "Not chained,Chained"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "Not chained,Chained"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "Not chained,Chained"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "Not chained,Chained"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "Not chained,Chained"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "Not chained,Chained"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "Not chained,Chained"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "Not chained,Chained"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "Not chained,Chained"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "Not chained,Chained"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "Not chained,Chained"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "Not chained,Chained"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "Not chained,Chained"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "Not chained,Chained"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "Not chained,Chained"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "Not chained,Chained"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "Not chained,Chained"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "Not chained,Chained"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "Not chained,Chained"
|
|
group.long 0x1020++0x07
|
|
line.long 0x00 "EER_SET/CLR,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31 ,Event #31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30 ,Event #30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29 ,Event #29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28 ,Event #28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27 ,Event #27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26 ,Event #26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25 ,Event #25" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24 ,Event #24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23 ,Event #23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22 ,Event #22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21 ,Event #21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20 ,Event #20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19 ,Event #19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18 ,Event #18" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17 ,Event #17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16 ,Event #16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15 ,Event #15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14 ,Event #14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13 ,Event #13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12 ,Event #12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11 ,Event #11" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10 ,Event #10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9 ,Event #9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8 ,Event #8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7 ,Event #7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6 ,Event #6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5 ,Event #5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4 ,Event #4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3 ,Event #3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2 ,Event #2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1 ,Event #1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0 ,Event #0" "Disabled,Enabled"
|
|
line.long 0x04 "EERH_SET/CLR,Event Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " E63 ,Event #63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " E62 ,Event #62" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " E61 ,Event #61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " E60 ,Event #60" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " E59 ,Event #59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " E58 ,Event #58" "Disabled,Enabled"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " E57 ,Event #57" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " E56 ,Event #56" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " E55 ,Event #55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " E54 ,Event #54" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " E53 ,Event #53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " E52 ,Event #52" "Disabled,Enabled"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " E51 ,Event #51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " E50 ,Event #50" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " E49 ,Event #49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " E48 ,Event #48" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " E47 ,Event #47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " E46 ,Event #46" "Disabled,Enabled"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " E45 ,Event #45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " E44 ,Event #44" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " E43 ,Event #43" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " E42 ,Event #42" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " E41 ,Event #41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " E40 ,Event #40" "Disabled,Enabled"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " E39 ,Event #39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " E38 ,Event #38" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " E37 ,Event #37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " E36 ,Event #36" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " E35 ,Event #35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " E34 ,Event #34" "Disabled,Enabled"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " E33 ,Event #33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " E32 ,Event #32" "Disabled,Enabled"
|
|
rgroup.long 0x1038++0x07
|
|
line.long 0x00 "SER,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "Not stored,Stored"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "Not stored,Stored"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "Not stored,Stored"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "Not stored,Stored"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "Not stored,Stored"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "Not stored,Stored"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "Not stored,Stored"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "Not stored,Stored"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "Not stored,Stored"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "Not stored,Stored"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "Not stored,Stored"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not stored,Stored"
|
|
line.long 0x04 "SERH,EDMA TPCC Secondary Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "Not stored,Stored"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "Not stored,Stored"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "Not stored,Stored"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "Not stored,Stored"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "Not stored,Stored"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "Not stored,Stored"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "Not stored,Stored"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "Not stored,Stored"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "Not stored,Stored"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "Not stored,Stored"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "Not stored,Stored"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "Not stored,Stored"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "Not stored,Stored"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "Not stored,Stored"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "Not stored,Stored"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "Not stored,Stored"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "Not stored,Stored"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "Not stored,Stored"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "Not stored,Stored"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "Not stored,Stored"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "Not stored,Stored"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "Not stored,Stored"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "Not stored,Stored"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "Not stored,Stored"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "Not stored,Stored"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "Not stored,Stored"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "Not stored,Stored"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "Not stored,Stored"
|
|
wgroup.long 0x1040++0x07
|
|
line.long 0x00 "SECR,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "No effect,Clear"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "No effect,Clear"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "No effect,Clear"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
line.long 0x04 "SECRH,Secondary Event Clear Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "No effect,Clear"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "No effect,Clear"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "No effect,Clear"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "No effect,Clear"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "No effect,Clear"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "No effect,Clear"
|
|
group.long 0x1050++0x07
|
|
line.long 0x00 "IER_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31 ,Interrupt associated with TCC #31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30 ,Interrupt associated with TCC #30" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29 ,Interrupt associated with TCC #29" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28 ,Interrupt associated with TCC #28" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27 ,Interrupt associated with TCC #27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26 ,Interrupt associated with TCC #26" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25 ,Interrupt associated with TCC #25" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24 ,Interrupt associated with TCC #24" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23 ,Interrupt associated with TCC #23" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22 ,Interrupt associated with TCC #22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21 ,Interrupt associated with TCC #21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20 ,Interrupt associated with TCC #20" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19 ,Interrupt associated with TCC #19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18 ,Interrupt associated with TCC #18" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17 ,Interrupt associated with TCC #17" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16 ,Interrupt associated with TCC #16" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15 ,Interrupt associated with TCC #15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14 ,Interrupt associated with TCC #14" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13 ,Interrupt associated with TCC #13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12 ,Interrupt associated with TCC #12" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11 ,Interrupt associated with TCC #11" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10 ,Interrupt associated with TCC #10" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9 ,Interrupt associated with TCC #9" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8 ,Interrupt associated with TCC #8" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I7 ,Interrupt associated with TCC #7" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I6 ,Interrupt associated with TCC #6" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I5 ,Interrupt associated with TCC #5" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I4 ,Interrupt associated with TCC #4" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3 ,Interrupt associated with TCC #3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2 ,Interrupt associated with TCC #2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1 ,Interrupt associated with TCC #1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0 ,Interrupt associated with TCC #0" "No interrupt,Interrupt"
|
|
line.long 0x04 "IERH_SET/CLR,EDMA TPCC Interrupts Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " I63 ,Interrupt associated with TCC #63" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " I62 ,Interrupt associated with TCC #62" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " I61 ,Interrupt associated with TCC #61" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " I60 ,Interrupt associated with TCC #60" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " I59 ,Interrupt associated with TCC #59" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " I58 ,Interrupt associated with TCC #58" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " I57 ,Interrupt associated with TCC #57" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " I56 ,Interrupt associated with TCC #56" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " I55 ,Interrupt associated with TCC #55" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " I54 ,Interrupt associated with TCC #54" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " I53 ,Interrupt associated with TCC #53" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " I52 ,Interrupt associated with TCC #52" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " I51 ,Interrupt associated with TCC #51" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " I50 ,Interrupt associated with TCC #50" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " I49 ,Interrupt associated with TCC #49" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " I48 ,Interrupt associated with TCC #48" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " I47 ,Interrupt associated with TCC #47" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " I46 ,Interrupt associated with TCC #46" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " I45 ,Interrupt associated with TCC #45" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " I44 ,Interrupt associated with TCC #44" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " I43 ,Interrupt associated with TCC #43" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " I42 ,Interrupt associated with TCC #42" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " I41 ,Interrupt associated with TCC #41" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " I40 ,Interrupt associated with TCC #40" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " I39 ,Interrupt associated with TCC #39" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " I38 ,Interrupt associated with TCC #38" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " I37 ,Interrupt associated with TCC #37" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " I36 ,Interrupt associated with TCC #36" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " I35 ,Interrupt associated with TCC #35" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " I34 ,Interrupt associated with TCC #34" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " I33 ,Interrupt associated with TCC #33" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " I32 ,Interrupt associated with TCC #32" "No interrupt,Interrupt"
|
|
rgroup.long 0x1068++0x07
|
|
line.long 0x00 "IPR,Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt associated with TCC #31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt associated with TCC #30" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " I29 ,Interrupt associated with TCC #29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt associated with TCC #28" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " I27 ,Interrupt associated with TCC #27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt associated with TCC #26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " I25 ,Interrupt associated with TCC #25" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 24. " I24 ,Interrupt associated with TCC #24" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " I23 ,Interrupt associated with TCC #23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt associated with TCC #22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " I21 ,Interrupt associated with TCC #21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt associated with TCC #20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " I19 ,Interrupt associated with TCC #19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt associated with TCC #18" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 17. " I17 ,Interrupt associated with TCC #17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt associated with TCC #16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " I15 ,Interrupt associated with TCC #15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt associated with TCC #14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " I13 ,Interrupt associated with TCC #13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt associated with TCC #12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " I11 ,Interrupt associated with TCC #11" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. " I10 ,Interrupt associated with TCC #10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " I9 ,Interrupt associated with TCC #9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt associated with TCC #8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " I7 ,Interrupt associated with TCC #7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt associated with TCC #6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " I5 ,Interrupt associated with TCC #5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt associated with TCC #4" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " I3 ,Interrupt associated with TCC #3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt associated with TCC #2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " I1 ,Interrupt associated with TCC #1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt associated with TCC #0" "No interrupt,Interrupt"
|
|
line.long 0x04 "IPRH,Interrupt Pending Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt associated with TCC #63" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt associated with TCC #62" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " I61 ,Interrupt associated with TCC #61" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt associated with TCC #60" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 27. " I59 ,Interrupt associated with TCC #59" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt associated with TCC #58" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " I57 ,Interrupt associated with TCC #57" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 24. " I56 ,Interrupt associated with TCC #56" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 23. " I55 ,Interrupt associated with TCC #55" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt associated with TCC #54" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " I53 ,Interrupt associated with TCC #53" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt associated with TCC #52" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 19. " I51 ,Interrupt associated with TCC #51" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt associated with TCC #50" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 17. " I49 ,Interrupt associated with TCC #49" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt associated with TCC #48" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 15. " I47 ,Interrupt associated with TCC #47" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt associated with TCC #46" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " I45 ,Interrupt associated with TCC #45" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt associated with TCC #44" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 11. " I43 ,Interrupt associated with TCC #43" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 10. " I42 ,Interrupt associated with TCC #42" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " I41 ,Interrupt associated with TCC #41" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt associated with TCC #40" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " I39 ,Interrupt associated with TCC #39" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt associated with TCC #38" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " I37 ,Interrupt associated with TCC #37" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt associated with TCC #36" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 3. " I35 ,Interrupt associated with TCC #35" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt associated with TCC #34" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " I33 ,Interrupt associated with TCC #33" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt associated with TCC #32" "No interrupt,Interrupt"
|
|
wgroup.long 0x1070++0x07
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt associated with TCC #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt associated with TCC #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " I29 ,Interrupt associated with TCC #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt associated with TCC #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " I27 ,Interrupt associated with TCC #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt associated with TCC #26" "No effect,Clear"
|
|
bitfld.long 0x00 25. " I25 ,Interrupt associated with TCC #25" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 24. " I24 ,Interrupt associated with TCC #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " I23 ,Interrupt associated with TCC #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt associated with TCC #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " I21 ,Interrupt associated with TCC #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt associated with TCC #20" "No effect,Clear"
|
|
bitfld.long 0x00 19. " I19 ,Interrupt associated with TCC #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt associated with TCC #18" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 17. " I17 ,Interrupt associated with TCC #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt associated with TCC #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " I15 ,Interrupt associated with TCC #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt associated with TCC #14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " I13 ,Interrupt associated with TCC #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt associated with TCC #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " I11 ,Interrupt associated with TCC #11" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 10. " I10 ,Interrupt associated with TCC #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " I9 ,Interrupt associated with TCC #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt associated with TCC #8" "No effect,Clear"
|
|
bitfld.long 0x00 7. " I7 ,Interrupt associated with TCC #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt associated with TCC #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " I5 ,Interrupt associated with TCC #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt associated with TCC #4" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " I3 ,Interrupt associated with TCC #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt associated with TCC #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " I1 ,Interrupt associated with TCC #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt associated with TCC #0" "No effect,Clear"
|
|
line.long 0x04 "ICRH,Interrupt Clear Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt associated with TCC #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt associated with TCC #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " I61 ,Interrupt associated with TCC #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt associated with TCC #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " I59 ,Interrupt associated with TCC #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt associated with TCC #58" "No effect,Clear"
|
|
bitfld.long 0x04 25. " I57 ,Interrupt associated with TCC #57" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 24. " I56 ,Interrupt associated with TCC #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " I55 ,Interrupt associated with TCC #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt associated with TCC #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " I53 ,Interrupt associated with TCC #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt associated with TCC #52" "No effect,Clear"
|
|
bitfld.long 0x04 19. " I51 ,Interrupt associated with TCC #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt associated with TCC #50" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 17. " I49 ,Interrupt associated with TCC #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt associated with TCC #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " I47 ,Interrupt associated with TCC #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt associated with TCC #46" "No effect,Clear"
|
|
bitfld.long 0x04 13. " I45 ,Interrupt associated with TCC #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt associated with TCC #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " I43 ,Interrupt associated with TCC #43" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10. " I42 ,Interrupt associated with TCC #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " I41 ,Interrupt associated with TCC #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt associated with TCC #40" "No effect,Clear"
|
|
bitfld.long 0x04 7. " I39 ,Interrupt associated with TCC #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt associated with TCC #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " I37 ,Interrupt associated with TCC #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt associated with TCC #36" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 3. " I35 ,Interrupt associated with TCC #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt associated with TCC #34" "No effect,Clear"
|
|
bitfld.long 0x04 1. " I33 ,Interrupt associated with TCC #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt associated with TCC #32" "No effect,Clear"
|
|
wgroup.long 0x1078++0x03
|
|
line.long 0x00 "IEVAL,Interrupt EVAL Register"
|
|
bitfld.long 0x00 1. " SET ,Interrupt set" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Interrupt evaluate" "Not set,Set"
|
|
rgroup.long 0x1080++0x03
|
|
line.long 0x00 "QER,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not occurred,Occurred"
|
|
group.long 0x1084++0x03
|
|
line.long 0x00 "QEER_SET/CLR,QDMA Event Enable Register"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7 ,Event #7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6 ,Event #6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5 ,Event #5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4 ,Event #4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3 ,Event #3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2 ,Event #2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1 ,Event #1" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0 ,Event #0" "Disabled,Enabled"
|
|
rgroup.long 0x1090++0x03
|
|
line.long 0x00 "QSER,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not stored,Stored"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not stored,Stored"
|
|
wgroup.long 0x1094++0x03
|
|
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
group.long 0x2000++0x07
|
|
line.long 0x00 "ER_RN_SET/CLR,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31 ,Event #31" "Inactive,Active"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30 ,Event #30" "Inactive,Active"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29 ,Event #29" "Inactive,Active"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28 ,Event #28" "Inactive,Active"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27 ,Event #27" "Inactive,Active"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26 ,Event #26" "Inactive,Active"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25 ,Event #25" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24 ,Event #24" "Inactive,Active"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23 ,Event #23" "Inactive,Active"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22 ,Event #22" "Inactive,Active"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21 ,Event #21" "Inactive,Active"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20 ,Event #20" "Inactive,Active"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19 ,Event #19" "Inactive,Active"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18 ,Event #18" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17 ,Event #17" "Inactive,Active"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16 ,Event #16" "Inactive,Active"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15 ,Event #15" "Inactive,Active"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14 ,Event #14" "Inactive,Active"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13 ,Event #13" "Inactive,Active"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12 ,Event #12" "Inactive,Active"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11 ,Event #11" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10 ,Event #10" "Inactive,Active"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9 ,Event #9" "Inactive,Active"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8 ,Event #8" "Inactive,Active"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7 ,Event #7" "Inactive,Active"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6 ,Event #6" "Inactive,Active"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5 ,Event #5" "Inactive,Active"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4 ,Event #4" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3 ,Event #3" "Inactive,Active"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2 ,Event #2" "Inactive,Active"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1 ,Event #1" "Inactive,Active"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0 ,Event #0" "Inactive,Active"
|
|
line.long 0x04 "ERH_RN_SET/CLR,Event Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " E63 ,Event #63" "Inactive,Active"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " E62 ,Event #62" "Inactive,Active"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " E61 ,Event #61" "Inactive,Active"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " E60 ,Event #60" "Inactive,Active"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " E59 ,Event #59" "Inactive,Active"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " E58 ,Event #58" "Inactive,Active"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " E57 ,Event #57" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " E56 ,Event #56" "Inactive,Active"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " E55 ,Event #55" "Inactive,Active"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " E54 ,Event #54" "Inactive,Active"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " E53 ,Event #53" "Inactive,Active"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " E52 ,Event #52" "Inactive,Active"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " E51 ,Event #51" "Inactive,Active"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " E50 ,Event #50" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " E49 ,Event #49" "Inactive,Active"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " E48 ,Event #48" "Inactive,Active"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " E47 ,Event #47" "Inactive,Active"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " E46 ,Event #46" "Inactive,Active"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " E45 ,Event #45" "Inactive,Active"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " E44 ,Event #44" "Inactive,Active"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " E43 ,Event #43" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x44 10. 0x0C 10. " E42 ,Event #42" "Inactive,Active"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " E41 ,Event #41" "Inactive,Active"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " E40 ,Event #40" "Inactive,Active"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " E39 ,Event #39" "Inactive,Active"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " E38 ,Event #38" "Inactive,Active"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " E37 ,Event #37" "Inactive,Active"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " E36 ,Event #36" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " E35 ,Event #35" "Inactive,Active"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " E34 ,Event #34" "Inactive,Active"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " E33 ,Event #33" "Inactive,Active"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " E32 ,Event #32" "Inactive,Active"
|
|
rgroup.long 0x2018++0x07
|
|
line.long 0x00 "CER_RN,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "Not chained,Chained"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "Not chained,Chained"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "Not chained,Chained"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "Not chained,Chained"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "Not chained,Chained"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "Not chained,Chained"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "Not chained,Chained"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "Not chained,Chained"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "Not chained,Chained"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "Not chained,Chained"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "Not chained,Chained"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "Not chained,Chained"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "Not chained,Chained"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "Not chained,Chained"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "Not chained,Chained"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "Not chained,Chained"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "Not chained,Chained"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "Not chained,Chained"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "Not chained,Chained"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "Not chained,Chained"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "Not chained,Chained"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not chained,Chained"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not chained,Chained"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not chained,Chained"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not chained,Chained"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not chained,Chained"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not chained,Chained"
|
|
line.long 0x04 "CERH_RN,Chained Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "Not chained,Chained"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "Not chained,Chained"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "Not chained,Chained"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "Not chained,Chained"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "Not chained,Chained"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "Not chained,Chained"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "Not chained,Chained"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "Not chained,Chained"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "Not chained,Chained"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "Not chained,Chained"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "Not chained,Chained"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "Not chained,Chained"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "Not chained,Chained"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "Not chained,Chained"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "Not chained,Chained"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "Not chained,Chained"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "Not chained,Chained"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "Not chained,Chained"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "Not chained,Chained"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "Not chained,Chained"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "Not chained,Chained"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "Not chained,Chained"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "Not chained,Chained"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "Not chained,Chained"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "Not chained,Chained"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "Not chained,Chained"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "Not chained,Chained"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "Not chained,Chained"
|
|
group.long 0x2020++0x07
|
|
line.long 0x00 "EER_RN_SET/CLR,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31 ,Event #31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30 ,Event #30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29 ,Event #29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28 ,Event #28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27 ,Event #27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26 ,Event #26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25 ,Event #25" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24 ,Event #24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23 ,Event #23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22 ,Event #22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21 ,Event #21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20 ,Event #20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19 ,Event #19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18 ,Event #18" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17 ,Event #17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16 ,Event #16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15 ,Event #15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14 ,Event #14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13 ,Event #13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12 ,Event #12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11 ,Event #11" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10 ,Event #10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9 ,Event #9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8 ,Event #8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7 ,Event #7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6 ,Event #6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5 ,Event #5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4 ,Event #4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3 ,Event #3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2 ,Event #2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1 ,Event #1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0 ,Event #0" "Disabled,Enabled"
|
|
line.long 0x04 "EERH_RN_SET/CLR,Event Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " E63 ,Event #63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " E62 ,Event #62" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " E61 ,Event #61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " E60 ,Event #60" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " E59 ,Event #59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " E58 ,Event #58" "Disabled,Enabled"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " E57 ,Event #57" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " E56 ,Event #56" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " E55 ,Event #55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " E54 ,Event #54" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " E53 ,Event #53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " E52 ,Event #52" "Disabled,Enabled"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " E51 ,Event #51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " E50 ,Event #50" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " E49 ,Event #49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " E48 ,Event #48" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " E47 ,Event #47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " E46 ,Event #46" "Disabled,Enabled"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " E45 ,Event #45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " E44 ,Event #44" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " E43 ,Event #43" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " E42 ,Event #42" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " E41 ,Event #41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " E40 ,Event #40" "Disabled,Enabled"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " E39 ,Event #39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " E38 ,Event #38" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " E37 ,Event #37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " E36 ,Event #36" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " E35 ,Event #35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " E34 ,Event #34" "Disabled,Enabled"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " E33 ,Event #33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " E32 ,Event #32" "Disabled,Enabled"
|
|
rgroup.long 0x2038++0x07
|
|
line.long 0x00 "SER_RN,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "Not stored,Stored"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "Not stored,Stored"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "Not stored,Stored"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "Not stored,Stored"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "Not stored,Stored"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "Not stored,Stored"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "Not stored,Stored"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "Not stored,Stored"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "Not stored,Stored"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "Not stored,Stored"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "Not stored,Stored"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not stored,Stored"
|
|
line.long 0x04 "SERH_RN,Secondary Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "Not stored,Stored"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "Not stored,Stored"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "Not stored,Stored"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "Not stored,Stored"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "Not stored,Stored"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "Not stored,Stored"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "Not stored,Stored"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "Not stored,Stored"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "Not stored,Stored"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "Not stored,Stored"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "Not stored,Stored"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "Not stored,Stored"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "Not stored,Stored"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "Not stored,Stored"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "Not stored,Stored"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "Not stored,Stored"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "Not stored,Stored"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "Not stored,Stored"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "Not stored,Stored"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "Not stored,Stored"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "Not stored,Stored"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "Not stored,Stored"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "Not stored,Stored"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "Not stored,Stored"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "Not stored,Stored"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "Not stored,Stored"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "Not stored,Stored"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "Not stored,Stored"
|
|
wgroup.long 0x2040++0x07
|
|
line.long 0x00 "SECR_RN,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "No effect,Clear"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "No effect,Clear"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "No effect,Clear"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
line.long 0x04 "SECRH_RN,Secondary Event Clear Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "No effect,Clear"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "No effect,Clear"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "No effect,Clear"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "No effect,Clear"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "No effect,Clear"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "No effect,Clear"
|
|
group.long 0x2050++0x07
|
|
line.long 0x00 "IER_RN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31 ,Interrupt associated with TCC #31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30 ,Interrupt associated with TCC #30" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29 ,Interrupt associated with TCC #29" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28 ,Interrupt associated with TCC #28" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27 ,Interrupt associated with TCC #27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26 ,Interrupt associated with TCC #26" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25 ,Interrupt associated with TCC #25" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24 ,Interrupt associated with TCC #24" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23 ,Interrupt associated with TCC #23" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22 ,Interrupt associated with TCC #22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21 ,Interrupt associated with TCC #21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20 ,Interrupt associated with TCC #20" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19 ,Interrupt associated with TCC #19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18 ,Interrupt associated with TCC #18" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17 ,Interrupt associated with TCC #17" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16 ,Interrupt associated with TCC #16" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15 ,Interrupt associated with TCC #15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14 ,Interrupt associated with TCC #14" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13 ,Interrupt associated with TCC #13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12 ,Interrupt associated with TCC #12" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11 ,Interrupt associated with TCC #11" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10 ,Interrupt associated with TCC #10" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9 ,Interrupt associated with TCC #9" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8 ,Interrupt associated with TCC #8" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I7 ,Interrupt associated with TCC #7" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I6 ,Interrupt associated with TCC #6" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I5 ,Interrupt associated with TCC #5" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I4 ,Interrupt associated with TCC #4" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3 ,Interrupt associated with TCC #3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2 ,Interrupt associated with TCC #2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1 ,Interrupt associated with TCC #1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0 ,Interrupt associated with TCC #0" "No interrupt,Interrupt"
|
|
line.long 0x04 "IERH_RN_SET/CLR,Interrupt Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " I63 ,Interrupt associated with TCC #63" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " I62 ,Interrupt associated with TCC #62" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " I61 ,Interrupt associated with TCC #61" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " I60 ,Interrupt associated with TCC #60" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " I59 ,Interrupt associated with TCC #59" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " I58 ,Interrupt associated with TCC #58" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " I57 ,Interrupt associated with TCC #57" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " I56 ,Interrupt associated with TCC #56" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " I55 ,Interrupt associated with TCC #55" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " I54 ,Interrupt associated with TCC #54" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " I53 ,Interrupt associated with TCC #53" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " I52 ,Interrupt associated with TCC #52" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " I51 ,Interrupt associated with TCC #51" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " I50 ,Interrupt associated with TCC #50" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " I49 ,Interrupt associated with TCC #49" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " I48 ,Interrupt associated with TCC #48" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " I47 ,Interrupt associated with TCC #47" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " I46 ,Interrupt associated with TCC #46" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " I45 ,Interrupt associated with TCC #45" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " I44 ,Interrupt associated with TCC #44" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " I43 ,Interrupt associated with TCC #43" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " I42 ,Interrupt associated with TCC #42" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " I41 ,Interrupt associated with TCC #41" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " I40 ,Interrupt associated with TCC #40" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " I39 ,Interrupt associated with TCC #39" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " I38 ,Interrupt associated with TCC #38" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " I37 ,Interrupt associated with TCC #37" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " I36 ,Interrupt associated with TCC #36" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " I35 ,Interrupt associated with TCC #35" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " I34 ,Interrupt associated with TCC #34" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " I33 ,Interrupt associated with TCC #33" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " I32 ,Interrupt associated with TCC #32" "No interrupt,Interrupt"
|
|
rgroup.long 0x2068++0x07
|
|
line.long 0x00 "IPR_RN,Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt associated with TCC #31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt associated with TCC #30" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " I29 ,Interrupt associated with TCC #29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt associated with TCC #28" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " I27 ,Interrupt associated with TCC #27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt associated with TCC #26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " I25 ,Interrupt associated with TCC #25" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 24. " I24 ,Interrupt associated with TCC #24" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " I23 ,Interrupt associated with TCC #23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt associated with TCC #22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " I21 ,Interrupt associated with TCC #21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt associated with TCC #20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " I19 ,Interrupt associated with TCC #19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt associated with TCC #18" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 17. " I17 ,Interrupt associated with TCC #17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt associated with TCC #16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " I15 ,Interrupt associated with TCC #15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt associated with TCC #14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " I13 ,Interrupt associated with TCC #13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt associated with TCC #12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " I11 ,Interrupt associated with TCC #11" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. " I10 ,Interrupt associated with TCC #10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " I9 ,Interrupt associated with TCC #9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt associated with TCC #8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " I7 ,Interrupt associated with TCC #7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt associated with TCC #6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " I5 ,Interrupt associated with TCC #5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt associated with TCC #4" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " I3 ,Interrupt associated with TCC #3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt associated with TCC #2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " I1 ,Interrupt associated with TCC #1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt associated with TCC #0" "No interrupt,Interrupt"
|
|
line.long 0x04 "IPRH_RN,Interrupt Pending Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt associated with TCC #63" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt associated with TCC #62" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " I61 ,Interrupt associated with TCC #61" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt associated with TCC #60" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 27. " I59 ,Interrupt associated with TCC #59" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt associated with TCC #58" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " I57 ,Interrupt associated with TCC #57" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 24. " I56 ,Interrupt associated with TCC #56" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 23. " I55 ,Interrupt associated with TCC #55" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt associated with TCC #54" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " I53 ,Interrupt associated with TCC #53" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt associated with TCC #52" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 19. " I51 ,Interrupt associated with TCC #51" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt associated with TCC #50" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 17. " I49 ,Interrupt associated with TCC #49" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt associated with TCC #48" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 15. " I47 ,Interrupt associated with TCC #47" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt associated with TCC #46" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " I45 ,Interrupt associated with TCC #45" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt associated with TCC #44" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 11. " I43 ,Interrupt associated with TCC #43" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 10. " I42 ,Interrupt associated with TCC #42" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " I41 ,Interrupt associated with TCC #41" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt associated with TCC #40" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " I39 ,Interrupt associated with TCC #39" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt associated with TCC #38" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " I37 ,Interrupt associated with TCC #37" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt associated with TCC #36" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 3. " I35 ,Interrupt associated with TCC #35" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt associated with TCC #34" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " I33 ,Interrupt associated with TCC #33" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt associated with TCC #32" "No interrupt,Interrupt"
|
|
wgroup.long 0x2070++0x0B
|
|
line.long 0x00 "ICR_RN,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt associated with TCC #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt associated with TCC #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " I29 ,Interrupt associated with TCC #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt associated with TCC #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " I27 ,Interrupt associated with TCC #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt associated with TCC #26" "No effect,Clear"
|
|
bitfld.long 0x00 25. " I25 ,Interrupt associated with TCC #25" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 24. " I24 ,Interrupt associated with TCC #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " I23 ,Interrupt associated with TCC #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt associated with TCC #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " I21 ,Interrupt associated with TCC #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt associated with TCC #20" "No effect,Clear"
|
|
bitfld.long 0x00 19. " I19 ,Interrupt associated with TCC #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt associated with TCC #18" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 17. " I17 ,Interrupt associated with TCC #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt associated with TCC #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " I15 ,Interrupt associated with TCC #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt associated with TCC #14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " I13 ,Interrupt associated with TCC #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt associated with TCC #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " I11 ,Interrupt associated with TCC #11" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 10. " I10 ,Interrupt associated with TCC #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " I9 ,Interrupt associated with TCC #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt associated with TCC #8" "No effect,Clear"
|
|
bitfld.long 0x00 7. " I7 ,Interrupt associated with TCC #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt associated with TCC #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " I5 ,Interrupt associated with TCC #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt associated with TCC #4" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " I3 ,Interrupt associated with TCC #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt associated with TCC #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " I1 ,Interrupt associated with TCC #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt associated with TCC #0" "No effect,Clear"
|
|
line.long 0x04 "ICRH_RN,Interrupt Clear Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt associated with TCC #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt associated with TCC #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " I61 ,Interrupt associated with TCC #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt associated with TCC #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " I59 ,Interrupt associated with TCC #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt associated with TCC #58" "No effect,Clear"
|
|
bitfld.long 0x04 25. " I57 ,Interrupt associated with TCC #57" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 24. " I56 ,Interrupt associated with TCC #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " I55 ,Interrupt associated with TCC #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt associated with TCC #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " I53 ,Interrupt associated with TCC #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt associated with TCC #52" "No effect,Clear"
|
|
bitfld.long 0x04 19. " I51 ,Interrupt associated with TCC #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt associated with TCC #50" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 17. " I49 ,Interrupt associated with TCC #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt associated with TCC #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " I47 ,Interrupt associated with TCC #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt associated with TCC #46" "No effect,Clear"
|
|
bitfld.long 0x04 13. " I45 ,Interrupt associated with TCC #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt associated with TCC #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " I43 ,Interrupt associated with TCC #43" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10. " I42 ,Interrupt associated with TCC #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " I41 ,Interrupt associated with TCC #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt associated with TCC #40" "No effect,Clear"
|
|
bitfld.long 0x04 7. " I39 ,Interrupt associated with TCC #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt associated with TCC #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " I37 ,Interrupt associated with TCC #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt associated with TCC #36" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 3. " I35 ,Interrupt associated with TCC #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt associated with TCC #34" "No effect,Clear"
|
|
bitfld.long 0x04 1. " I33 ,Interrupt associated with TCC #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt associated with TCC #32" "No effect,Clear"
|
|
line.long 0x08 "IEVAL_RN,Interrupt EVAL Register"
|
|
bitfld.long 0x08 1. " SET ,Interrupt set" "Not set,Set"
|
|
bitfld.long 0x08 0. " EVAL ,Interrupt evaluate" "Not set,Set"
|
|
rgroup.long 0x2080++0x07
|
|
line.long 0x00 "QER_RN,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not occurred,Occurred"
|
|
line.long 0x04 "QEER_RN,QDMA Event Enable Register"
|
|
bitfld.long 0x04 7. " E7 ,Event #7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " E6 ,Event #6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E5 ,Event #5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " E4 ,Event #4" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " E3 ,Event #3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " E2 ,Event #2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " E1 ,Event #1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " E0 ,Event #0" "Disabled,Enabled"
|
|
wgroup.long 0x2088++0x07
|
|
line.long 0x00 "QEECR_RN,QDMA Event Enable Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
line.long 0x04 "QEESR_RN,QDMA Event Enable Set Register"
|
|
bitfld.long 0x04 7. " E7 ,Event #7" "Not set,Set"
|
|
bitfld.long 0x04 6. " E6 ,Event #6" "Not set,Set"
|
|
bitfld.long 0x04 5. " E5 ,Event #5" "Not set,Set"
|
|
bitfld.long 0x04 4. " E4 ,Event #4" "Not set,Set"
|
|
bitfld.long 0x04 3. " E3 ,Event #3" "Not set,Set"
|
|
bitfld.long 0x04 2. " E2 ,Event #2" "Not set,Set"
|
|
bitfld.long 0x04 1. " E1 ,Event #1" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x04 0. " E0 ,Event #0" "Not set,Set"
|
|
rgroup.long 0x2090++0x03
|
|
line.long 0x00 "QSER_RN,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not stored,Stored"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not stored,Stored"
|
|
wgroup.long 0x2094++0x03
|
|
line.long 0x00 "QSECR_RN,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
width 7.
|
|
newline
|
|
group.long 0x4000++0x1F
|
|
line.long 0x00 "OPT,Options Parameter Register"
|
|
rbitfld.long 0x00 31. " PRIV ,Privilege level" "User,Supervisor"
|
|
rbitfld.long 0x00 24.--27. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " WIMODE ,Backward compatibility mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " STATIC ,Static entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-sync,Ab-sync"
|
|
newline
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
line.long 0x04 "SRC,Source Address Register"
|
|
line.long 0x08 "ABCNT,A And B Byte Count Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,BCNT"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,ACNT"
|
|
line.long 0x0C "DST,Destination Address Register"
|
|
line.long 0x10 "BIDX,BIDX"
|
|
hexmask.long.word 0x10 16.--31. 1. " DBIDX ,Destination 2nd dimension index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SBIDX ,Source 2nd dimension index"
|
|
line.long 0x14 "LNK,Link And Reload Parameters Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,BCNT reload"
|
|
hexmask.long.word 0x14 0.--15. 0x01 " LINK ,Link address"
|
|
line.long 0x18 "CIDX,CIDX"
|
|
hexmask.long.word 0x18 16.--31. 1. " DCIDX ,Destination frame index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SCIDX ,Source frame index"
|
|
line.long 0x1C "CCNT,C Byte Count"
|
|
hexmask.long.word 0x1C 0.--15. 1. " CCNT ,Count for 3rd dimension"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "TPTC"
|
|
tree "TPTC0"
|
|
base ad:0x50000000
|
|
width 17.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "PID,Peripheral ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major revision"
|
|
hexmask.long.byte 0x00 6.--7. 1. " CUSTOM ,Custom revision field"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision"
|
|
line.long 0x04 "TCCFG,TC Configuration Register"
|
|
bitfld.long 0x04 8.--9. " DREGDEPTH ,DST register FIFO depth parametrization" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parametrization" "0,1,2,3"
|
|
bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size parametrization" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "TCSTAT,TC Status Register"
|
|
bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3"
|
|
bitfld.long 0x00 8. " ACTV ,Channel active" "Idle,Busy"
|
|
bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,pending"
|
|
bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy"
|
|
bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "INT_SET/CLR,Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " TRDONE ,TR done event status" "Not detected,Detected"
|
|
setclrfld.long 0x00 0. 0x04 1. 0x08 1. " PROGEMPTY ,Program set empty event status" "Not detected,Detected"
|
|
wgroup.long 0x110++0x03
|
|
line.long 0x00 "INTCMD,Interrupt Command Register"
|
|
bitfld.long 0x00 1. " SET ,Set TPTC interrupt" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Evaluate state of TPTC interrupt" "Not set,Set"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "ERRSTAT_SET/CLR,Error Status Register"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " MMRAERR ,MMR address error" "No error,Error"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TRERR ,TR error" "No error,Error"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " BUSERR ,Bus error event" "No error,Error"
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "ERRDET,Error Details Register"
|
|
bitfld.long 0x00 17. " TCCHEN ,Error of OPT.TCCHEN value" "No error,Error"
|
|
bitfld.long 0x00 16. " TCINTEN ,Error of OPT.TCINTEN" "No error,Error"
|
|
bitfld.long 0x00 8.--13. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " STAT ,Transaction status" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
wgroup.long 0x130++0x03
|
|
line.long 0x00 "ERRCMD,Error Command Register"
|
|
bitfld.long 0x00 1. " SET ,Set TPTC interrupt" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Evaluate state of TPTC interrupt" "Not set,Set"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "RDRATE,Read Rate Register"
|
|
bitfld.long 0x00 0.--2. " RDRATE ,Read rate control" "0,1,2,3,4,5,6,7"
|
|
if (((per.l(ad:0x50000000+0x200)&0x03)==(0x01||0x02)))
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "POPT,Program Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "POPT,Program Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
group.long 0x204++0x0F
|
|
line.long 0x00 "PSRC,Program Set Source Address Register"
|
|
line.long 0x04 "PCNT,Program Set Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A-dimension count"
|
|
line.long 0x08 "PDST,Program Set Destination Address Register"
|
|
line.long 0x0C "PBIDX,Program Set B-Dim Idx Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "PMPPRXY,Program Set Memory Protect Proxy Register"
|
|
bitfld.long 0x00 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x00 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x00 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x50000000+0x240)&0x03)==(0x01||0x02)))
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "SAOPT,Source Active Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "SAOPT,Source Active Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
rgroup.long 0x244++0x07
|
|
line.long 0x00 "SASRC,Source Active Set Source Address Register"
|
|
line.long 0x04 "SACNT,Source Active Set Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A-dimension count"
|
|
rgroup.long 0x250++0x0F
|
|
line.long 0x00 "SABIDX,Source Active Set B-Dim Idx Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x00 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
line.long 0x04 "SAMPPRXY,Source Active Set Memory Protect Proxy Register"
|
|
bitfld.long 0x04 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x04 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x04 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "SACNTRLD,Source Active Set Count Reload Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNTRLD ,A-CNT reload value for source active register set"
|
|
line.long 0x0C "SASRCBREF,Source Active Set Source Address A-Reference Register"
|
|
rgroup.long 0x280++0x03
|
|
line.long 0x00 "DFCNTRLD,Destination FIFO Set Count Reload Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-CNT reload value for source active register set"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
rgroup.long 0x284++0x03
|
|
line.long 0x00 "DFSRCBREF,DFSRCBREF"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x300)&0x03)==(0x01||0x02)))
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "DFOPT,Destination FIFO Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "DFOPT,Destination FIFO Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "DFSRC,DFSRC"
|
|
endif
|
|
rgroup.long 0x308++0x0F
|
|
line.long 0x00 "DFCNT,Destination FIFO Set Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
|
|
line.long 0x04 "DFDST,Destination FIFO Set Destination Address"
|
|
line.long 0x08 "DFBIDX,Destination FIFO Set B-Dim Idx Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
line.long 0x0C "DFMPPRXY,Destination FIFO Memory Protect Proxy Register"
|
|
bitfld.long 0x0C 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TPTC1"
|
|
base ad:0x50000800
|
|
width 17.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "PID,Peripheral ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major revision"
|
|
hexmask.long.byte 0x00 6.--7. 1. " CUSTOM ,Custom revision field"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision"
|
|
line.long 0x04 "TCCFG,TC Configuration Register"
|
|
bitfld.long 0x04 8.--9. " DREGDEPTH ,DST register FIFO depth parametrization" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parametrization" "0,1,2,3"
|
|
bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size parametrization" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "TCSTAT,TC Status Register"
|
|
bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3"
|
|
bitfld.long 0x00 8. " ACTV ,Channel active" "Idle,Busy"
|
|
bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,pending"
|
|
bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy"
|
|
bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "INT_SET/CLR,Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " TRDONE ,TR done event status" "Not detected,Detected"
|
|
setclrfld.long 0x00 0. 0x04 1. 0x08 1. " PROGEMPTY ,Program set empty event status" "Not detected,Detected"
|
|
wgroup.long 0x110++0x03
|
|
line.long 0x00 "INTCMD,Interrupt Command Register"
|
|
bitfld.long 0x00 1. " SET ,Set TPTC interrupt" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Evaluate state of TPTC interrupt" "Not set,Set"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "ERRSTAT_SET/CLR,Error Status Register"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " MMRAERR ,MMR address error" "No error,Error"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TRERR ,TR error" "No error,Error"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " BUSERR ,Bus error event" "No error,Error"
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "ERRDET,Error Details Register"
|
|
bitfld.long 0x00 17. " TCCHEN ,Error of OPT.TCCHEN value" "No error,Error"
|
|
bitfld.long 0x00 16. " TCINTEN ,Error of OPT.TCINTEN" "No error,Error"
|
|
bitfld.long 0x00 8.--13. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " STAT ,Transaction status" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
wgroup.long 0x130++0x03
|
|
line.long 0x00 "ERRCMD,Error Command Register"
|
|
bitfld.long 0x00 1. " SET ,Set TPTC interrupt" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Evaluate state of TPTC interrupt" "Not set,Set"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "RDRATE,Read Rate Register"
|
|
bitfld.long 0x00 0.--2. " RDRATE ,Read rate control" "0,1,2,3,4,5,6,7"
|
|
if (((per.l(ad:0x50000800+0x200)&0x03)==(0x01||0x02)))
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "POPT,Program Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "POPT,Program Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
group.long 0x204++0x0F
|
|
line.long 0x00 "PSRC,Program Set Source Address Register"
|
|
line.long 0x04 "PCNT,Program Set Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A-dimension count"
|
|
line.long 0x08 "PDST,Program Set Destination Address Register"
|
|
line.long 0x0C "PBIDX,Program Set B-Dim Idx Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "PMPPRXY,Program Set Memory Protect Proxy Register"
|
|
bitfld.long 0x00 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x00 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x00 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x50000800+0x240)&0x03)==(0x01||0x02)))
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "SAOPT,Source Active Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "SAOPT,Source Active Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
rgroup.long 0x244++0x07
|
|
line.long 0x00 "SASRC,Source Active Set Source Address Register"
|
|
line.long 0x04 "SACNT,Source Active Set Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A-dimension count"
|
|
rgroup.long 0x250++0x0F
|
|
line.long 0x00 "SABIDX,Source Active Set B-Dim Idx Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x00 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
line.long 0x04 "SAMPPRXY,Source Active Set Memory Protect Proxy Register"
|
|
bitfld.long 0x04 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x04 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x04 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "SACNTRLD,Source Active Set Count Reload Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNTRLD ,A-CNT reload value for source active register set"
|
|
line.long 0x0C "SASRCBREF,Source Active Set Source Address A-Reference Register"
|
|
rgroup.long 0x280++0x03
|
|
line.long 0x00 "DFCNTRLD,Destination FIFO Set Count Reload Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-CNT reload value for source active register set"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
rgroup.long 0x284++0x03
|
|
line.long 0x00 "DFSRCBREF,DFSRCBREF"
|
|
endif
|
|
if (((per.l(ad:0x50000800+0x300)&0x03)==(0x01||0x02)))
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "DFOPT,Destination FIFO Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "DFOPT,Destination FIFO Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "DFSRC,DFSRC"
|
|
endif
|
|
rgroup.long 0x308++0x0F
|
|
line.long 0x00 "DFCNT,Destination FIFO Set Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
|
|
line.long 0x04 "DFDST,Destination FIFO Set Destination Address"
|
|
line.long 0x08 "DFBIDX,Destination FIFO Set B-Dim Idx Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
line.long 0x0C "DFMPPRXY,Destination FIFO Memory Protect Proxy Register"
|
|
bitfld.long 0x0C 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("AWR1642"))||(cpuis("AWR1642-CORE1"))||cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
tree "TPTC2"
|
|
base ad:0x50090000
|
|
width 17.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "PID,Peripheral ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major revision"
|
|
hexmask.long.byte 0x00 6.--7. 1. " CUSTOM ,Custom revision field"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision"
|
|
line.long 0x04 "TCCFG,TC Configuration Register"
|
|
bitfld.long 0x04 8.--9. " DREGDEPTH ,DST register FIFO depth parametrization" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parametrization" "0,1,2,3"
|
|
bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size parametrization" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "TCSTAT,TC Status Register"
|
|
bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3"
|
|
bitfld.long 0x00 8. " ACTV ,Channel active" "Idle,Busy"
|
|
bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,pending"
|
|
bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy"
|
|
bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "INT_SET/CLR,Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " TRDONE ,TR done event status" "Not detected,Detected"
|
|
setclrfld.long 0x00 0. 0x04 1. 0x08 1. " PROGEMPTY ,Program set empty event status" "Not detected,Detected"
|
|
wgroup.long 0x110++0x03
|
|
line.long 0x00 "INTCMD,Interrupt Command Register"
|
|
bitfld.long 0x00 1. " SET ,Set TPTC interrupt" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Evaluate state of TPTC interrupt" "Not set,Set"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "ERRSTAT_SET/CLR,Error Status Register"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " MMRAERR ,MMR address error" "No error,Error"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TRERR ,TR error" "No error,Error"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " BUSERR ,Bus error event" "No error,Error"
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "ERRDET,Error Details Register"
|
|
bitfld.long 0x00 17. " TCCHEN ,Error of OPT.TCCHEN value" "No error,Error"
|
|
bitfld.long 0x00 16. " TCINTEN ,Error of OPT.TCINTEN" "No error,Error"
|
|
bitfld.long 0x00 8.--13. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " STAT ,Transaction status" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
wgroup.long 0x130++0x03
|
|
line.long 0x00 "ERRCMD,Error Command Register"
|
|
bitfld.long 0x00 1. " SET ,Set TPTC interrupt" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Evaluate state of TPTC interrupt" "Not set,Set"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "RDRATE,Read Rate Register"
|
|
bitfld.long 0x00 0.--2. " RDRATE ,Read rate control" "0,1,2,3,4,5,6,7"
|
|
if (((per.l(ad:0x50090000+0x200)&0x03)==(0x01||0x02)))
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "POPT,Program Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "POPT,Program Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
group.long 0x204++0x0F
|
|
line.long 0x00 "PSRC,Program Set Source Address Register"
|
|
line.long 0x04 "PCNT,Program Set Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A-dimension count"
|
|
line.long 0x08 "PDST,Program Set Destination Address Register"
|
|
line.long 0x0C "PBIDX,Program Set B-Dim Idx Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "PMPPRXY,Program Set Memory Protect Proxy Register"
|
|
bitfld.long 0x00 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x00 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x00 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x50090000+0x240)&0x03)==(0x01||0x02)))
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "SAOPT,Source Active Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "SAOPT,Source Active Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
rgroup.long 0x244++0x07
|
|
line.long 0x00 "SASRC,Source Active Set Source Address Register"
|
|
line.long 0x04 "SACNT,Source Active Set Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A-dimension count"
|
|
rgroup.long 0x250++0x0F
|
|
line.long 0x00 "SABIDX,Source Active Set B-Dim Idx Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x00 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
line.long 0x04 "SAMPPRXY,Source Active Set Memory Protect Proxy Register"
|
|
bitfld.long 0x04 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x04 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x04 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "SACNTRLD,Source Active Set Count Reload Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNTRLD ,A-CNT reload value for source active register set"
|
|
line.long 0x0C "SASRCBREF,Source Active Set Source Address A-Reference Register"
|
|
rgroup.long 0x280++0x03
|
|
line.long 0x00 "DFCNTRLD,Destination FIFO Set Count Reload Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-CNT reload value for source active register set"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
rgroup.long 0x284++0x03
|
|
line.long 0x00 "DFSRCBREF,DFSRCBREF"
|
|
endif
|
|
if (((per.l(ad:0x50090000+0x300)&0x03)==(0x01||0x02)))
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "DFOPT,Destination FIFO Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "DFOPT,Destination FIFO Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "DFSRC,DFSRC"
|
|
endif
|
|
rgroup.long 0x308++0x0F
|
|
line.long 0x00 "DFCNT,Destination FIFO Set Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
|
|
line.long 0x04 "DFDST,Destination FIFO Set Destination Address"
|
|
line.long 0x08 "DFBIDX,Destination FIFO Set B-Dim Idx Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
line.long 0x0C "DFMPPRXY,Destination FIFO Memory Protect Proxy Register"
|
|
bitfld.long 0x0C 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TPTC3"
|
|
base ad:0x50090400
|
|
width 17.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "PID,Peripheral ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major revision"
|
|
hexmask.long.byte 0x00 6.--7. 1. " CUSTOM ,Custom revision field"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision"
|
|
line.long 0x04 "TCCFG,TC Configuration Register"
|
|
bitfld.long 0x04 8.--9. " DREGDEPTH ,DST register FIFO depth parametrization" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parametrization" "0,1,2,3"
|
|
bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size parametrization" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "TCSTAT,TC Status Register"
|
|
bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3"
|
|
bitfld.long 0x00 8. " ACTV ,Channel active" "Idle,Busy"
|
|
bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,pending"
|
|
bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy"
|
|
bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "INT_SET/CLR,Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " TRDONE ,TR done event status" "Not detected,Detected"
|
|
setclrfld.long 0x00 0. 0x04 1. 0x08 1. " PROGEMPTY ,Program set empty event status" "Not detected,Detected"
|
|
wgroup.long 0x110++0x03
|
|
line.long 0x00 "INTCMD,Interrupt Command Register"
|
|
bitfld.long 0x00 1. " SET ,Set TPTC interrupt" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Evaluate state of TPTC interrupt" "Not set,Set"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "ERRSTAT_SET/CLR,Error Status Register"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " MMRAERR ,MMR address error" "No error,Error"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TRERR ,TR error" "No error,Error"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " BUSERR ,Bus error event" "No error,Error"
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "ERRDET,Error Details Register"
|
|
bitfld.long 0x00 17. " TCCHEN ,Error of OPT.TCCHEN value" "No error,Error"
|
|
bitfld.long 0x00 16. " TCINTEN ,Error of OPT.TCINTEN" "No error,Error"
|
|
bitfld.long 0x00 8.--13. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " STAT ,Transaction status" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
wgroup.long 0x130++0x03
|
|
line.long 0x00 "ERRCMD,Error Command Register"
|
|
bitfld.long 0x00 1. " SET ,Set TPTC interrupt" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Evaluate state of TPTC interrupt" "Not set,Set"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "RDRATE,Read Rate Register"
|
|
bitfld.long 0x00 0.--2. " RDRATE ,Read rate control" "0,1,2,3,4,5,6,7"
|
|
if (((per.l(ad:0x50090400+0x200)&0x03)==(0x01||0x02)))
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "POPT,Program Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "POPT,Program Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
group.long 0x204++0x0F
|
|
line.long 0x00 "PSRC,Program Set Source Address Register"
|
|
line.long 0x04 "PCNT,Program Set Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A-dimension count"
|
|
line.long 0x08 "PDST,Program Set Destination Address Register"
|
|
line.long 0x0C "PBIDX,Program Set B-Dim Idx Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "PMPPRXY,Program Set Memory Protect Proxy Register"
|
|
bitfld.long 0x00 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x00 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x00 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x50090400+0x240)&0x03)==(0x01||0x02)))
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "SAOPT,Source Active Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "SAOPT,Source Active Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
rgroup.long 0x244++0x07
|
|
line.long 0x00 "SASRC,Source Active Set Source Address Register"
|
|
line.long 0x04 "SACNT,Source Active Set Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A-dimension count"
|
|
rgroup.long 0x250++0x0F
|
|
line.long 0x00 "SABIDX,Source Active Set B-Dim Idx Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x00 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
line.long 0x04 "SAMPPRXY,Source Active Set Memory Protect Proxy Register"
|
|
bitfld.long 0x04 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x04 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x04 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "SACNTRLD,Source Active Set Count Reload Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNTRLD ,A-CNT reload value for source active register set"
|
|
line.long 0x0C "SASRCBREF,Source Active Set Source Address A-Reference Register"
|
|
rgroup.long 0x280++0x03
|
|
line.long 0x00 "DFCNTRLD,Destination FIFO Set Count Reload Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-CNT reload value for source active register set"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
rgroup.long 0x284++0x03
|
|
line.long 0x00 "DFSRCBREF,DFSRCBREF"
|
|
endif
|
|
if (((per.l(ad:0x50090400+0x300)&0x03)==(0x01||0x02)))
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "DFOPT,Destination FIFO Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "DFOPT,Destination FIFO Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "DFSRC,DFSRC"
|
|
endif
|
|
rgroup.long 0x308++0x0F
|
|
line.long 0x00 "DFCNT,Destination FIFO Set Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
|
|
line.long 0x04 "DFDST,Destination FIFO Set Destination Address"
|
|
line.long 0x08 "DFBIDX,Destination FIFO Set B-Dim Idx Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
line.long 0x0C "DFMPPRXY,Destination FIFO Memory Protect Proxy Register"
|
|
bitfld.long 0x0C 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
tree.open "HSI (High-Speed Interface)"
|
|
tree "CBUFF and LVDS Registers"
|
|
base ad:0x50070000
|
|
width 25.
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONFIG_REG_0,Basic Config Register"
|
|
bitfld.long 0x00 27. " CSWCRST ,CBUFF controller SW reset" "No reset,Reset"
|
|
bitfld.long 0x00 25. " CFG_FRAME_START_TRIG ,Generate frame start SW trigger" "No effect,Generate"
|
|
bitfld.long 0x00 24. " CFG_CHIRP_AVAIL_TRIG ,Generate a Chirp available SW trigger" "No effect,Generate"
|
|
bitfld.long 0x00 16.--17. " CVC3EN ,Generate VSYNC packet on virtual channel 3" "No effect,Start,End,Start/End"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CVC2EN ,Generate VSYNC packet on virtual channel 2" "No effect,Start,End,Start/End"
|
|
bitfld.long 0x00 12.--13. " CVC1EN ,Generate VSYNC packet on virtual channel 1" "No effect,Start,End,Start/End"
|
|
bitfld.long 0x00 10.--11. " CVC0EN ,Generate VSYNC packet on virtual channel 0" "No effect,Start,End,Start/End"
|
|
bitfld.long 0x00 3. " CFG_SW_TRIG_EN ,Chirp available trigger source" "HW,SW"
|
|
newline
|
|
bitfld.long 0x00 2. " CFTRIGEN ,Frame start trigger source" "HW,SW"
|
|
bitfld.long 0x00 1. " CFG_ECC_EN ,Enable ECC on the CBUF FIFO" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFG_1LVDS_0CSI ,Select source for sending data" ",LVDS"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONFIG_REG_0,Basic Config Register"
|
|
bitfld.long 0x00 27. " CSWCRST ,CBUFF controller SW reset" "No reset,Reset"
|
|
bitfld.long 0x00 25. " CFG_FRAME_START_TRIG ,Generate frame start SW trigger" "No effect,Generate"
|
|
bitfld.long 0x00 24. " CFG_CHIRP_AVAIL_TRIG ,Generate a Chirp available SW trigger" "No effect,Generate"
|
|
bitfld.long 0x00 16.--17. " CVC3EN ,Generate VSYNC packet on virtual channel 3" "No effect,Start,End,Start/End"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CVC2EN ,Generate VSYNC packet on virtual channel 2" "No effect,Start,End,Start/End"
|
|
bitfld.long 0x00 12.--13. " CVC1EN ,Generate VSYNC packet on virtual channel 1" "No effect,Start,End,Start/End"
|
|
bitfld.long 0x00 10.--11. " CVC0EN ,Generate VSYNC packet on virtual channel 0" "No effect,Start,End,Start/End"
|
|
bitfld.long 0x00 3. " CFG_SW_TRIG_EN ,Chirp available trigger source" "HW,SW"
|
|
newline
|
|
bitfld.long 0x00 2. " CFTRIGEN ,Frame start trigger source" "HW,SW"
|
|
bitfld.long 0x00 1. " CFG_ECC_EN ,Enable ECC on the CBUF FIFO" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFG_1LVDS_0CSI ,Select source for sending data" "CSI-2,LVDS"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONFIG_REG_0,Basic Config Register"
|
|
bitfld.long 0x00 27. " CSWCRST ,CBUFF controller SW reset" "No reset,Reset"
|
|
bitfld.long 0x00 25. " CFG_FRAME_START_TRIG ,SW trigger a frame start SW trigger" "Not generated,Generated"
|
|
bitfld.long 0x00 24. " CFG_CHIRP_AVAIL_TRIG ,SW trigger a chirp available generation" "Not generated,Generated"
|
|
bitfld.long 0x00 3. " CFG_SW_TRIG_EN ,Select chirp available trigger source" "HW1,SW"
|
|
newline
|
|
bitfld.long 0x00 2. " CFTRIGEN ,Select frame start trigger source" "HW1,SW"
|
|
bitfld.long 0x00 1. " CFG_ECC_EN ,Enable ECC on the CBUF FIFO" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFG_1LVDS_0CSI ,Select source for sending data" "CSI-2,LVDS"
|
|
endif
|
|
endif
|
|
group.long 0x04++0x17
|
|
line.long 0x00 "CFG_SPHDR_ADDRESS,Short Packet Header Address Register"
|
|
line.long 0x04 "CFG_CMD_HSVAL,HSYNC Value Register"
|
|
line.long 0x08 "CFG_CMD_HEVAL,HEND Value Register"
|
|
line.long 0x0C "CFG_CMD_VSVAL,VSYNC Value Register"
|
|
line.long 0x10 "CFG_CMD_VEVAL,VEND Value Register"
|
|
line.long 0x14 "CFG_LPHDR_ADDRESS,Long Packet Address Register"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CFG_CHIRPS_PER_FRAME,Number Of Chirps Per Frame Register"
|
|
sif cpuis("AWR6843*")
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "CFG_FIFO_FREE_THRESHOLD,CSI2 FIFO Threshold For Transferring Data From CBUFF To CSI2"
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "CFG_LPPYLD_ADDRESS,Long Payload Address Register"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "CFG_FIFO_FREE_THRESHOLD,CSI2 FIFO Threshold For Transferring Data From CBUFF To CSI2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CFF_THRESHOLD ,Threshold used to fill the FIFO0 in the CSI protocol engine"
|
|
line.long 0x04 "CFG_LPPYLD_ADDRESS,Long Payload Address Register"
|
|
else
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "CFG_FIFO_FREE_THRESHOLD,CSI2 FIFO Threshold For Transferring Data From CBUFF To CSI2"
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "CFG_LPPYLD_ADDRESS,Long Payload Address Register"
|
|
endif
|
|
endif
|
|
newline
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CFG_DATA_LL0,Linked List Entry 0"
|
|
bitfld.long 0x00 28. " LL0_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL0_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL0_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL0_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL0_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL0_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL0_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL0_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL0_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CFG_DATA_LL0,Linked List Entry 0 Register"
|
|
bitfld.long 0x00 28. " LL0_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL0_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL0_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL0_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL0_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL0_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL0_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL0_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL0_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CFG_DATA_LL0,Linked List Entry 0"
|
|
bitfld.long 0x00 28. " LL0_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL0_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL0_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL0_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL0_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL0_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL0_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL0_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL0_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x30+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL0_LPHDR_VAL,Linked List Entry 0"
|
|
line.long 0x04 "CFG_DATA_LL0_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL0DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL0_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL0_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CFG_DATA_LL1,Linked List Entry 1"
|
|
bitfld.long 0x00 28. " LL1_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL1_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL1_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL1_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL1_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL1_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL1_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL1_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL1_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CFG_DATA_LL1,Linked List Entry 1 Register"
|
|
bitfld.long 0x00 28. " LL1_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL1_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL1_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL1_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL1_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL1_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL1_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL1_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL1_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CFG_DATA_LL1,Linked List Entry 1"
|
|
bitfld.long 0x00 28. " LL1_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL1_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL1_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL1_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL1_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL1_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL1_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL1_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL1_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x3C+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL1_LPHDR_VAL,Linked List Entry 1"
|
|
line.long 0x04 "CFG_DATA_LL1_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL1DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL1_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL1_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CFG_DATA_LL2,Linked List Entry 2"
|
|
bitfld.long 0x00 28. " LL2_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL2_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL2_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL2_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL2_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL2_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL2_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL2_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL2_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CFG_DATA_LL2,Linked List Entry 2 Register"
|
|
bitfld.long 0x00 28. " LL2_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL2_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL2_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL2_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL2_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL2_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL2_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL2_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL2_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CFG_DATA_LL2,Linked List Entry 2"
|
|
bitfld.long 0x00 28. " LL2_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL2_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL2_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL2_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL2_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL2_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL2_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL2_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL2_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x48+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL2_LPHDR_VAL,Linked List Entry 2"
|
|
line.long 0x04 "CFG_DATA_LL2_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL2DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL2_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL2_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CFG_DATA_LL3,Linked List Entry 3"
|
|
bitfld.long 0x00 28. " LL3_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL3_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL3_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL3_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL3_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL3_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL3_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL3_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL3_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CFG_DATA_LL3,Linked List Entry 3 Register"
|
|
bitfld.long 0x00 28. " LL3_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL3_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL3_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL3_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL3_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL3_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL3_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL3_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL3_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CFG_DATA_LL3,Linked List Entry 3"
|
|
bitfld.long 0x00 28. " LL3_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL3_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL3_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL3_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL3_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL3_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL3_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL3_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL3_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x54+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL3_LPHDR_VAL,Linked List Entry 3"
|
|
line.long 0x04 "CFG_DATA_LL3_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL3DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL3_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL3_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CFG_DATA_LL4,Linked List Entry 4"
|
|
bitfld.long 0x00 28. " LL4_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL4_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL4_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL4_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL4_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL4_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL4_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL4_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL4_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CFG_DATA_LL4,Linked List Entry 4 Register"
|
|
bitfld.long 0x00 28. " LL4_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL4_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL4_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL4_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL4_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL4_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL4_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL4_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL4_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CFG_DATA_LL4,Linked List Entry 4"
|
|
bitfld.long 0x00 28. " LL4_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL4_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL4_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL4_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL4_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL4_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL4_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL4_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL4_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x60+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL4_LPHDR_VAL,Linked List Entry 4"
|
|
line.long 0x04 "CFG_DATA_LL4_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL4DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL4_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL4_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CFG_DATA_LL5,Linked List Entry 5"
|
|
bitfld.long 0x00 28. " LL5_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL5_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL5_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL5_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL5_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL5_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL5_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL5_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL5_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CFG_DATA_LL5,Linked List Entry 5 Register"
|
|
bitfld.long 0x00 28. " LL5_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL5_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL5_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL5_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL5_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL5_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL5_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL5_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL5_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CFG_DATA_LL5,Linked List Entry 5"
|
|
bitfld.long 0x00 28. " LL5_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL5_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL5_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL5_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL5_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL5_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL5_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL5_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL5_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x6C+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL5_LPHDR_VAL,Linked List Entry 5"
|
|
line.long 0x04 "CFG_DATA_LL5_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL5DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL5_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL5_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CFG_DATA_LL6,Linked List Entry 6"
|
|
bitfld.long 0x00 28. " LL6_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL6_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL6_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL6_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL6_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL6_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL6_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL6_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL6_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CFG_DATA_LL6,Linked List Entry 6 Register"
|
|
bitfld.long 0x00 28. " LL6_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL6_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL6_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL6_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL6_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL6_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL6_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL6_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL6_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CFG_DATA_LL6,Linked List Entry 6"
|
|
bitfld.long 0x00 28. " LL6_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL6_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL6_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL6_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL6_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL6_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL6_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL6_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL6_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x78+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL6_LPHDR_VAL,Linked List Entry 6"
|
|
line.long 0x04 "CFG_DATA_LL6_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL6DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL6_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL6_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CFG_DATA_LL7,Linked List Entry 7"
|
|
bitfld.long 0x00 28. " LL7_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL7_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL7_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL7_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL7_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL7_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL7_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL7_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL7_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CFG_DATA_LL7,Linked List Entry 7 Register"
|
|
bitfld.long 0x00 28. " LL7_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL7_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL7_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL7_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL7_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL7_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL7_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL7_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL7_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CFG_DATA_LL7,Linked List Entry 7"
|
|
bitfld.long 0x00 28. " LL7_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL7_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL7_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL7_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL7_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL7_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL7_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL7_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL7_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x84+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL7_LPHDR_VAL,Linked List Entry 7"
|
|
line.long 0x04 "CFG_DATA_LL7_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL7DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL7_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL7_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CFG_DATA_LL8,Linked List Entry 8"
|
|
bitfld.long 0x00 28. " LL8_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL8_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL8_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL8_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL8_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL8_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL8_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL8_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL8_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CFG_DATA_LL8,Linked List Entry 8 Register"
|
|
bitfld.long 0x00 28. " LL8_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL8_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL8_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL8_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL8_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL8_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL8_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL8_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL8_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CFG_DATA_LL8,Linked List Entry 8"
|
|
bitfld.long 0x00 28. " LL8_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL8_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL8_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL8_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL8_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL8_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL8_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL8_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL8_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x90+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL8_LPHDR_VAL,Linked List Entry 8"
|
|
line.long 0x04 "CFG_DATA_LL8_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL8DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL8_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL8_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CFG_DATA_LL9,Linked List Entry 9"
|
|
bitfld.long 0x00 28. " LL9_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL9_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL9_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL9_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL9_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL9_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL9_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL9_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL9_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CFG_DATA_LL9,Linked List Entry 9 Register"
|
|
bitfld.long 0x00 28. " LL9_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL9_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL9_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL9_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL9_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL9_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL9_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL9_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL9_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CFG_DATA_LL9,Linked List Entry 9"
|
|
bitfld.long 0x00 28. " LL9_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL9_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL9_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL9_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL9_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL9_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL9_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL9_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL9_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x9C+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL9_LPHDR_VAL,Linked List Entry 9"
|
|
line.long 0x04 "CFG_DATA_LL9_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL9DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL9_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL9_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
newline
|
|
sif cpuis("AWR6843*")
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CFG_DATA_LL10,Linked List Entry 10"
|
|
bitfld.long 0x00 28. " LL10_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL10_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL10_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL10_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL10_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL10_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL10_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL10_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL10_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CFG_DATA_LL10,Linked List Entry 10 Register"
|
|
bitfld.long 0x00 28. " LL10_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL10_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL10_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL10_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL10_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL10_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL10_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL10_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL10_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CFG_DATA_LL10,Linked List Entry 10"
|
|
bitfld.long 0x00 28. " LL10_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL10_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL10_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL10_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL10_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL10_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL10_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL10_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL10_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0xA8+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL10_LPHDR_VAL,Linked List Entry 10"
|
|
line.long 0x04 "CFG_DATA_LL10_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL10DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL10_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL10_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CFG_DATA_LL11,Linked List Entry 11"
|
|
bitfld.long 0x00 28. " LL11_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL11_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL11_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL11_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL11_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL11_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL11_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL11_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL11_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CFG_DATA_LL11,Linked List Entry 11 Register"
|
|
bitfld.long 0x00 28. " LL11_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL11_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL11_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL11_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL11_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL11_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL11_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL11_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL11_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CFG_DATA_LL11,Linked List Entry 11"
|
|
bitfld.long 0x00 28. " LL11_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL11_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL11_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL11_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL11_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL11_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL11_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL11_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL11_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0xB4+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL11_LPHDR_VAL,Linked List Entry 11"
|
|
line.long 0x04 "CFG_DATA_LL11_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL11DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL11_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL11_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CFG_DATA_LL12,Linked List Entry 12"
|
|
bitfld.long 0x00 28. " LL12_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL12_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL12_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL12_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL12_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL12_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL12_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL12_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL12_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CFG_DATA_LL12,Linked List Entry 12 Register"
|
|
bitfld.long 0x00 28. " LL12_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL12_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL12_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL12_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL12_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL12_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL12_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL12_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL12_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CFG_DATA_LL12,Linked List Entry 12"
|
|
bitfld.long 0x00 28. " LL12_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL12_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL12_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL12_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL12_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL12_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL12_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL12_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL12_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0xC0+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL12_LPHDR_VAL,Linked List Entry 12"
|
|
line.long 0x04 "CFG_DATA_LL12_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL12DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL12_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL12_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CFG_DATA_LL13,Linked List Entry 13"
|
|
bitfld.long 0x00 28. " LL13_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL13_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL13_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL13_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL13_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL13_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL13_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL13_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL13_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CFG_DATA_LL13,Linked List Entry 13 Register"
|
|
bitfld.long 0x00 28. " LL13_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL13_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL13_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL13_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL13_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL13_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL13_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL13_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL13_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CFG_DATA_LL13,Linked List Entry 13"
|
|
bitfld.long 0x00 28. " LL13_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL13_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL13_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL13_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL13_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL13_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL13_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL13_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL13_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0xCC+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL13_LPHDR_VAL,Linked List Entry 13"
|
|
line.long 0x04 "CFG_DATA_LL13_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL13DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL13_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL13_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CFG_DATA_LL14,Linked List Entry 14"
|
|
bitfld.long 0x00 28. " LL14_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL14_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL14_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL14_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL14_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL14_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL14_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL14_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL14_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CFG_DATA_LL14,Linked List Entry 14 Register"
|
|
bitfld.long 0x00 28. " LL14_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL14_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL14_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL14_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL14_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL14_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL14_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL14_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL14_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CFG_DATA_LL14,Linked List Entry 14"
|
|
bitfld.long 0x00 28. " LL14_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL14_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL14_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL14_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL14_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL14_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL14_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL14_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL14_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0xD8+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL14_LPHDR_VAL,Linked List Entry 14"
|
|
line.long 0x04 "CFG_DATA_LL14_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL14DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL14_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL14_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CFG_DATA_LL15,Linked List Entry 15"
|
|
bitfld.long 0x00 28. " LL15_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL15_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL15_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL15_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL15_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL15_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL15_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL15_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL15_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CFG_DATA_LL15,Linked List Entry 15 Register"
|
|
bitfld.long 0x00 28. " LL15_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL15_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL15_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL15_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL15_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL15_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL15_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL15_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL15_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CFG_DATA_LL15,Linked List Entry 15"
|
|
bitfld.long 0x00 28. " LL15_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL15_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL15_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL15_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL15_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL15_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL15_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL15_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL15_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0xE4+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL15_LPHDR_VAL,Linked List Entry 15"
|
|
line.long 0x04 "CFG_DATA_LL15_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL15DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL15_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL15_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CFG_DATA_LL16,Linked List Entry 16"
|
|
bitfld.long 0x00 28. " LL16_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL16_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL16_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL16_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL16_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL16_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL16_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL16_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL16_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CFG_DATA_LL16,Linked List Entry 16 Register"
|
|
bitfld.long 0x00 28. " LL16_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL16_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL16_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL16_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL16_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL16_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL16_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL16_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL16_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CFG_DATA_LL16,Linked List Entry 16"
|
|
bitfld.long 0x00 28. " LL16_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL16_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL16_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL16_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL16_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL16_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL16_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL16_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL16_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0xF0+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL16_LPHDR_VAL,Linked List Entry 16"
|
|
line.long 0x04 "CFG_DATA_LL16_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL16DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL16_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL16_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CFG_DATA_LL17,Linked List Entry 17"
|
|
bitfld.long 0x00 28. " LL17_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL17_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL17_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL17_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL17_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL17_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL17_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL17_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL17_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CFG_DATA_LL17,Linked List Entry 17 Register"
|
|
bitfld.long 0x00 28. " LL17_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL17_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL17_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL17_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL17_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL17_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL17_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL17_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL17_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CFG_DATA_LL17,Linked List Entry 17"
|
|
bitfld.long 0x00 28. " LL17_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL17_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL17_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL17_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL17_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL17_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL17_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL17_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL17_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0xFC+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL17_LPHDR_VAL,Linked List Entry 17"
|
|
line.long 0x04 "CFG_DATA_LL17_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL17DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL17_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL17_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CFG_DATA_LL18,Linked List Entry 18"
|
|
bitfld.long 0x00 28. " LL18_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL18_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL18_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL18_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL18_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL18_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL18_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL18_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL18_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CFG_DATA_LL18,Linked List Entry 18 Register"
|
|
bitfld.long 0x00 28. " LL18_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL18_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL18_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL18_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL18_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL18_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL18_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL18_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL18_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CFG_DATA_LL18,Linked List Entry 18"
|
|
bitfld.long 0x00 28. " LL18_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL18_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL18_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL18_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL18_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL18_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL18_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL18_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL18_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x108+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL18_LPHDR_VAL,Linked List Entry 18"
|
|
line.long 0x04 "CFG_DATA_LL18_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL18DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL18_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL18_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CFG_DATA_LL19,Linked List Entry 19"
|
|
bitfld.long 0x00 28. " LL19_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL19_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL19_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL19_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL19_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL19_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL19_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL19_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL19_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CFG_DATA_LL19,Linked List Entry 19 Register"
|
|
bitfld.long 0x00 28. " LL19_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL19_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL19_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL19_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL19_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL19_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL19_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL19_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL19_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CFG_DATA_LL19,Linked List Entry 19"
|
|
bitfld.long 0x00 28. " LL19_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL19_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL19_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL19_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL19_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL19_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL19_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL19_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL19_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x114+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL19_LPHDR_VAL,Linked List Entry 19"
|
|
line.long 0x04 "CFG_DATA_LL19_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL19DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL19_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL19_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CFG_DATA_LL20,Linked List Entry 20"
|
|
bitfld.long 0x00 28. " LL20_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL20_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL20_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL20_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL20_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL20_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL20_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL20_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL20_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CFG_DATA_LL20,Linked List Entry 20 Register"
|
|
bitfld.long 0x00 28. " LL20_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL20_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL20_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL20_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL20_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL20_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL20_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL20_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL20_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CFG_DATA_LL20,Linked List Entry 20"
|
|
bitfld.long 0x00 28. " LL20_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL20_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL20_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL20_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL20_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL20_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL20_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL20_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL20_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL20_LPHDR_VAL,Linked List Entry 20"
|
|
line.long 0x04 "CFG_DATA_LL20_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL20DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL20_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL20_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "CFG_DATA_LL21,Linked List Entry 21"
|
|
bitfld.long 0x00 28. " LL21_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL21_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL21_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL21_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL21_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL21_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL21_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL21_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL21_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "CFG_DATA_LL21,Linked List Entry 21 Register"
|
|
bitfld.long 0x00 28. " LL21_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL21_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL21_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL21_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL21_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL21_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL21_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL21_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL21_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "CFG_DATA_LL21,Linked List Entry 21"
|
|
bitfld.long 0x00 28. " LL21_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL21_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL21_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL21_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL21_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL21_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL21_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL21_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL21_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x12C+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL21_LPHDR_VAL,Linked List Entry 21"
|
|
line.long 0x04 "CFG_DATA_LL21_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL21DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL21_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL21_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "CFG_DATA_LL22,Linked List Entry 22"
|
|
bitfld.long 0x00 28. " LL22_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL22_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL22_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL22_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL22_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL22_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL22_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL22_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL22_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "CFG_DATA_LL22,Linked List Entry 22 Register"
|
|
bitfld.long 0x00 28. " LL22_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL22_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL22_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL22_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL22_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL22_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL22_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL22_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL22_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "CFG_DATA_LL22,Linked List Entry 22"
|
|
bitfld.long 0x00 28. " LL22_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL22_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL22_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL22_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL22_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL22_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL22_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL22_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL22_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x138+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL22_LPHDR_VAL,Linked List Entry 22"
|
|
line.long 0x04 "CFG_DATA_LL22_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL22DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL22_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL22_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "CFG_DATA_LL23,Linked List Entry 23"
|
|
bitfld.long 0x00 28. " LL23_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL23_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL23_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL23_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL23_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL23_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL23_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL23_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL23_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "CFG_DATA_LL23,Linked List Entry 23 Register"
|
|
bitfld.long 0x00 28. " LL23_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL23_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL23_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL23_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL23_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL23_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL23_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL23_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL23_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "CFG_DATA_LL23,Linked List Entry 23"
|
|
bitfld.long 0x00 28. " LL23_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL23_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL23_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL23_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL23_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL23_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL23_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL23_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL23_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x144+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL23_LPHDR_VAL,Linked List Entry 23"
|
|
line.long 0x04 "CFG_DATA_LL23_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL23DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL23_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL23_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CFG_DATA_LL24,Linked List Entry 24"
|
|
bitfld.long 0x00 28. " LL24_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL24_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL24_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL24_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL24_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL24_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL24_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL24_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL24_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CFG_DATA_LL24,Linked List Entry 24 Register"
|
|
bitfld.long 0x00 28. " LL24_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL24_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL24_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL24_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL24_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL24_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL24_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL24_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL24_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CFG_DATA_LL24,Linked List Entry 24"
|
|
bitfld.long 0x00 28. " LL24_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL24_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL24_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL24_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL24_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL24_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL24_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL24_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL24_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x150+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL24_LPHDR_VAL,Linked List Entry 24"
|
|
line.long 0x04 "CFG_DATA_LL24_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL24DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL24_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL24_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "CFG_DATA_LL25,Linked List Entry 25"
|
|
bitfld.long 0x00 28. " LL25_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL25_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL25_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL25_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL25_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL25_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL25_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL25_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL25_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "CFG_DATA_LL25,Linked List Entry 25 Register"
|
|
bitfld.long 0x00 28. " LL25_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL25_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL25_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL25_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL25_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL25_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL25_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL25_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL25_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "CFG_DATA_LL25,Linked List Entry 25"
|
|
bitfld.long 0x00 28. " LL25_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL25_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL25_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL25_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL25_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL25_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL25_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL25_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL25_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x15C+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL25_LPHDR_VAL,Linked List Entry 25"
|
|
line.long 0x04 "CFG_DATA_LL25_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL25DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL25_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL25_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "CFG_DATA_LL26,Linked List Entry 26"
|
|
bitfld.long 0x00 28. " LL26_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL26_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL26_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL26_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL26_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL26_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL26_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL26_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL26_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "CFG_DATA_LL26,Linked List Entry 26 Register"
|
|
bitfld.long 0x00 28. " LL26_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL26_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL26_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL26_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL26_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL26_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL26_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL26_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL26_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "CFG_DATA_LL26,Linked List Entry 26"
|
|
bitfld.long 0x00 28. " LL26_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL26_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL26_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL26_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL26_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL26_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL26_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL26_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL26_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x168+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL26_LPHDR_VAL,Linked List Entry 26"
|
|
line.long 0x04 "CFG_DATA_LL26_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL26DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL26_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL26_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "CFG_DATA_LL27,Linked List Entry 27"
|
|
bitfld.long 0x00 28. " LL27_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL27_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL27_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL27_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL27_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL27_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL27_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL27_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL27_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "CFG_DATA_LL27,Linked List Entry 27 Register"
|
|
bitfld.long 0x00 28. " LL27_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL27_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL27_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL27_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL27_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL27_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL27_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL27_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL27_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "CFG_DATA_LL27,Linked List Entry 27"
|
|
bitfld.long 0x00 28. " LL27_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL27_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL27_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL27_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL27_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL27_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL27_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL27_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL27_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x174+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL27_LPHDR_VAL,Linked List Entry 27"
|
|
line.long 0x04 "CFG_DATA_LL27_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL27DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL27_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL27_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CFG_DATA_LL28,Linked List Entry 28"
|
|
bitfld.long 0x00 28. " LL28_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL28_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL28_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL28_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL28_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL28_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL28_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL28_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL28_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CFG_DATA_LL28,Linked List Entry 28 Register"
|
|
bitfld.long 0x00 28. " LL28_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL28_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL28_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL28_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL28_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL28_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL28_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL28_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL28_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CFG_DATA_LL28,Linked List Entry 28"
|
|
bitfld.long 0x00 28. " LL28_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL28_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL28_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL28_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL28_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL28_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL28_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL28_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL28_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x180+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL28_LPHDR_VAL,Linked List Entry 28"
|
|
line.long 0x04 "CFG_DATA_LL28_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL28DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL28_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL28_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "CFG_DATA_LL29,Linked List Entry 29"
|
|
bitfld.long 0x00 28. " LL29_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL29_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL29_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL29_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL29_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL29_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL29_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL29_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL29_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "CFG_DATA_LL29,Linked List Entry 29 Register"
|
|
bitfld.long 0x00 28. " LL29_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL29_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL29_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL29_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL29_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL29_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL29_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL29_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL29_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "CFG_DATA_LL29,Linked List Entry 29"
|
|
bitfld.long 0x00 28. " LL29_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL29_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL29_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL29_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL29_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL29_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL29_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL29_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL29_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x18C+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL29_LPHDR_VAL,Linked List Entry 29"
|
|
line.long 0x04 "CFG_DATA_LL29_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL29DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL29_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL29_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "CFG_DATA_LL30,Linked List Entry 30"
|
|
bitfld.long 0x00 28. " LL30_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL30_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL30_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL30_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL30_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL30_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL30_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL30_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL30_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "CFG_DATA_LL30,Linked List Entry 30 Register"
|
|
bitfld.long 0x00 28. " LL30_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL30_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL30_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL30_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL30_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL30_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL30_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL30_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL30_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "CFG_DATA_LL30,Linked List Entry 30"
|
|
bitfld.long 0x00 28. " LL30_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL30_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL30_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL30_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL30_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL30_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL30_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL30_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL30_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x198+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL30_LPHDR_VAL,Linked List Entry 30"
|
|
line.long 0x04 "CFG_DATA_LL30_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL30DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL30_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL30_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "CFG_DATA_LL31,Linked List Entry 31"
|
|
bitfld.long 0x00 28. " LL31_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL31_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL31_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL31_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL31_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL31_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL31_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL31_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL31_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x50070000))&0x01)==0x00)
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "CFG_DATA_LL31,Linked List Entry 31 Register"
|
|
bitfld.long 0x00 28. " LL31_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL31_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL31_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL31_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL31_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL31_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL31_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL31_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL31_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "CFG_DATA_LL31,Linked List Entry 31"
|
|
bitfld.long 0x00 28. " LL31_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL31_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL31_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL31_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL31_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL31_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL31_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL31_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL31_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x1A4+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL31_LPHDR_VAL,Linked List Entry 31"
|
|
line.long 0x04 "CFG_DATA_LL31_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL31DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL31_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL31_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
if (((per.l(ad:0x50070000))&0x01)==0x01)
|
|
width 31.
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "CFG_LVDS_MAPPING_LANE0_FMT_0,Lane 0 Mapping Register"
|
|
bitfld.long 0x00 31. " CFG_LVDS_MAPPING_LANE0_FMT_0_H_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 28.--30. " CFG_LVDS_MAPPING_LANE0_FMT_0_H_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27. " CFG_LVDS_MAPPING_LANE0_FMT_0_G_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 24.--26. " CFG_LVDS_MAPPING_LANE0_FMT_0_G_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. " CFG_LVDS_MAPPING_LANE0_FMT_0_F_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--22. " CFG_LVDS_MAPPING_LANE0_FMT_0_F_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19. " CFG_LVDS_MAPPING_LANE0_FMT_0_E_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " CFG_LVDS_MAPPING_LANE0_FMT_0_E_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " CFG_LVDS_MAPPING_LANE0_FMT_0_D_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 12.--14. " CFG_LVDS_MAPPING_LANE0_FMT_0_D_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. " CFG_LVDS_MAPPING_LANE0_FMT_0_C_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " CFG_LVDS_MAPPING_LANE0_FMT_0_C_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. " CFG_LVDS_MAPPING_LANE0_FMT_0_B_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 4.--6. " CFG_LVDS_MAPPING_LANE0_FMT_0_B_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. " CFG_LVDS_MAPPING_LANE0_FMT_0_A_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--2. " CFG_LVDS_MAPPING_LANE0_FMT_0_A_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "CFG_LVDS_MAPPING_LANE1_FMT_0,Lane 1 Mapping Register"
|
|
bitfld.long 0x00 31. " CFG_LVDS_MAPPING_LANE1_FMT_0_H_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 28.--30. " CFG_LVDS_MAPPING_LANE1_FMT_0_H_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27. " CFG_LVDS_MAPPING_LANE1_FMT_0_G_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 24.--26. " CFG_LVDS_MAPPING_LANE1_FMT_0_G_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. " CFG_LVDS_MAPPING_LANE1_FMT_0_F_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--22. " CFG_LVDS_MAPPING_LANE1_FMT_0_F_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19. " CFG_LVDS_MAPPING_LANE1_FMT_0_E_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " CFG_LVDS_MAPPING_LANE1_FMT_0_E_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " CFG_LVDS_MAPPING_LANE1_FMT_0_D_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 12.--14. " CFG_LVDS_MAPPING_LANE1_FMT_0_D_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. " CFG_LVDS_MAPPING_LANE1_FMT_0_C_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " CFG_LVDS_MAPPING_LANE1_FMT_0_C_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. " CFG_LVDS_MAPPING_LANE1_FMT_0_B_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 4.--6. " CFG_LVDS_MAPPING_LANE1_FMT_0_B_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. " CFG_LVDS_MAPPING_LANE1_FMT_0_A_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--2. " CFG_LVDS_MAPPING_LANE1_FMT_0_A_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "CFG_LVDS_MAPPING_LANE2_FMT_0,Lane 2 Mapping Register"
|
|
bitfld.long 0x00 31. " CFG_LVDS_MAPPING_LANE2_FMT_0_H_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 28.--30. " CFG_LVDS_MAPPING_LANE2_FMT_0_H_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27. " CFG_LVDS_MAPPING_LANE2_FMT_0_G_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 24.--26. " CFG_LVDS_MAPPING_LANE2_FMT_0_G_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. " CFG_LVDS_MAPPING_LANE2_FMT_0_F_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--22. " CFG_LVDS_MAPPING_LANE2_FMT_0_F_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19. " CFG_LVDS_MAPPING_LANE2_FMT_0_E_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " CFG_LVDS_MAPPING_LANE2_FMT_0_E_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " CFG_LVDS_MAPPING_LANE2_FMT_0_D_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 12.--14. " CFG_LVDS_MAPPING_LANE2_FMT_0_D_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. " CFG_LVDS_MAPPING_LANE2_FMT_0_C_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " CFG_LVDS_MAPPING_LANE2_FMT_0_C_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. " CFG_LVDS_MAPPING_LANE2_FMT_0_B_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 4.--6. " CFG_LVDS_MAPPING_LANE2_FMT_0_B_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. " CFG_LVDS_MAPPING_LANE2_FMT_0_A_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--2. " CFG_LVDS_MAPPING_LANE2_FMT_0_A_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "CFG_LVDS_MAPPING_LANE3_FMT_0,Lane 3 Mapping Register"
|
|
bitfld.long 0x00 31. " CFG_LVDS_MAPPING_LANE3_FMT_0_H_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 28.--30. " CFG_LVDS_MAPPING_LANE3_FMT_0_H_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27. " CFG_LVDS_MAPPING_LANE3_FMT_0_G_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 24.--26. " CFG_LVDS_MAPPING_LANE3_FMT_0_G_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. " CFG_LVDS_MAPPING_LANE3_FMT_0_F_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--22. " CFG_LVDS_MAPPING_LANE3_FMT_0_F_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19. " CFG_LVDS_MAPPING_LANE3_FMT_0_E_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " CFG_LVDS_MAPPING_LANE3_FMT_0_E_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " CFG_LVDS_MAPPING_LANE3_FMT_0_D_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 12.--14. " CFG_LVDS_MAPPING_LANE3_FMT_0_D_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. " CFG_LVDS_MAPPING_LANE3_FMT_0_C_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " CFG_LVDS_MAPPING_LANE3_FMT_0_C_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. " CFG_LVDS_MAPPING_LANE3_FMT_0_B_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 4.--6. " CFG_LVDS_MAPPING_LANE3_FMT_0_B_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. " CFG_LVDS_MAPPING_LANE3_FMT_0_A_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--2. " CFG_LVDS_MAPPING_LANE3_FMT_0_A_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "CFG_LVDS_MAPPING_LANE0_FMT_1,Lane 0 Mapping Register"
|
|
bitfld.long 0x00 31. " CFG_LVDS_MAPPING_LANE0_FMT_1_H_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 28.--30. " CFG_LVDS_MAPPING_LANE0_FMT_1_H_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27. " CFG_LVDS_MAPPING_LANE0_FMT_1_G_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 24.--26. " CFG_LVDS_MAPPING_LANE0_FMT_1_G_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. " CFG_LVDS_MAPPING_LANE0_FMT_1_F_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--22. " CFG_LVDS_MAPPING_LANE0_FMT_1_F_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19. " CFG_LVDS_MAPPING_LANE0_FMT_1_E_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " CFG_LVDS_MAPPING_LANE0_FMT_1_E_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " CFG_LVDS_MAPPING_LANE0_FMT_1_D_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 12.--14. " CFG_LVDS_MAPPING_LANE0_FMT_1_D_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. " CFG_LVDS_MAPPING_LANE0_FMT_1_C_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " CFG_LVDS_MAPPING_LANE0_FMT_1_C_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. " CFG_LVDS_MAPPING_LANE0_FMT_1_B_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 4.--6. " CFG_LVDS_MAPPING_LANE0_FMT_1_B_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. " CFG_LVDS_MAPPING_LANE0_FMT_1_A ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--2. " CFG_LVDS_MAPPING_LANE0_FMT_1_A ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "CFG_LVDS_MAPPING_LANE1_FMT_1,Lane 1 Mapping Register"
|
|
bitfld.long 0x00 31. " CFG_LVDS_MAPPING_LANE1_FMT_1_H_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 28.--30. " CFG_LVDS_MAPPING_LANE1_FMT_1_H_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27. " CFG_LVDS_MAPPING_LANE1_FMT_1_G_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 24.--26. " CFG_LVDS_MAPPING_LANE1_FMT_1_G_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. " CFG_LVDS_MAPPING_LANE1_FMT_1_F_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--22. " CFG_LVDS_MAPPING_LANE1_FMT_1_F_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19. " CFG_LVDS_MAPPING_LANE1_FMT_1_E_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " CFG_LVDS_MAPPING_LANE1_FMT_1_E_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " CFG_LVDS_MAPPING_LANE1_FMT_1_D_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 12.--14. " CFG_LVDS_MAPPING_LANE1_FMT_1_D_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. " CFG_LVDS_MAPPING_LANE1_FMT_1_C_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " CFG_LVDS_MAPPING_LANE1_FMT_1_C_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. " CFG_LVDS_MAPPING_LANE1_FMT_1_B_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 4.--6. " CFG_LVDS_MAPPING_LANE1_FMT_1_B_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. " CFG_LVDS_MAPPING_LANE1_FMT_1_A ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--2. " CFG_LVDS_MAPPING_LANE1_FMT_1_A ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "CFG_LVDS_MAPPING_LANE2_FMT_1,Lane 2 Mapping Register"
|
|
bitfld.long 0x00 31. " CFG_LVDS_MAPPING_LANE2_FMT_1_H_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 28.--30. " CFG_LVDS_MAPPING_LANE2_FMT_1_H_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27. " CFG_LVDS_MAPPING_LANE2_FMT_1_G_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 24.--26. " CFG_LVDS_MAPPING_LANE2_FMT_1_G_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. " CFG_LVDS_MAPPING_LANE2_FMT_1_F_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--22. " CFG_LVDS_MAPPING_LANE2_FMT_1_F_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19. " CFG_LVDS_MAPPING_LANE2_FMT_1_E_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " CFG_LVDS_MAPPING_LANE2_FMT_1_E_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " CFG_LVDS_MAPPING_LANE2_FMT_1_D_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 12.--14. " CFG_LVDS_MAPPING_LANE2_FMT_1_D_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. " CFG_LVDS_MAPPING_LANE2_FMT_1_C_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " CFG_LVDS_MAPPING_LANE2_FMT_1_C_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. " CFG_LVDS_MAPPING_LANE2_FMT_1_B_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 4.--6. " CFG_LVDS_MAPPING_LANE2_FMT_1_B_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. " CFG_LVDS_MAPPING_LANE2_FMT_1_A ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--2. " CFG_LVDS_MAPPING_LANE2_FMT_1_A ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "CFG_LVDS_MAPPING_LANE3_FMT_1,Lane 3 Mapping Register"
|
|
bitfld.long 0x00 31. " CFG_LVDS_MAPPING_LANE3_FMT_1_H_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 28.--30. " CFG_LVDS_MAPPING_LANE3_FMT_1_H_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27. " CFG_LVDS_MAPPING_LANE3_FMT_1_G_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 24.--26. " CFG_LVDS_MAPPING_LANE3_FMT_1_G_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. " CFG_LVDS_MAPPING_LANE3_FMT_1_F_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--22. " CFG_LVDS_MAPPING_LANE3_FMT_1_F_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19. " CFG_LVDS_MAPPING_LANE3_FMT_1_E_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " CFG_LVDS_MAPPING_LANE3_FMT_1_E_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " CFG_LVDS_MAPPING_LANE3_FMT_1_D_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 12.--14. " CFG_LVDS_MAPPING_LANE3_FMT_1_D_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. " CFG_LVDS_MAPPING_LANE3_FMT_1_C_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " CFG_LVDS_MAPPING_LANE3_FMT_1_C_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. " CFG_LVDS_MAPPING_LANE3_FMT_1_B_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 4.--6. " CFG_LVDS_MAPPING_LANE3_FMT_1_B_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. " CFG_LVDS_MAPPING_LANE3_FMT_1_A ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--2. " CFG_LVDS_MAPPING_LANE3_FMT_1_A ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
width 19.
|
|
group.long 0x1D0++0x0B
|
|
line.long 0x00 "CFG_LVDS_GEN_0,CFG_LVDS_GEN_0 Register"
|
|
bitfld.long 0x00 30.--31. " CPZ ,LVDS enable internal clock alignment" "Disabled,Enabled,Disabled,Disabled"
|
|
bitfld.long 0x00 28. " CBCRCEN ,LVDS frame CRC" "Not sent,Sent"
|
|
bitfld.long 0x00 24.--27. " CFDLY ,LVDS FIFO initial threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " CMSBF ,First bit of sent data" "LSB,MSB"
|
|
newline
|
|
bitfld.long 0x00 22. " CPOSSEL ,Align first sample start when new chirp is starting" "NEGEDGE,POSEDGE"
|
|
bitfld.long 0x00 15. " CCLKSEL1 ,Clock mode select" "DDR,SDR"
|
|
bitfld.long 0x00 11. " CCSMEN ,Continuous streaming mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CFG_BIT_CLK_MODE ,Bit clock mode" "SDR,DDR"
|
|
newline
|
|
bitfld.long 0x00 3. " CFG_LVDS_LANE3_EN ,Enable LVDS lane 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CFG_LVDS_LANE2_EN ,Enable LVDS lane 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CFG_LVDS_LANE1_EN ,Enable LVDS lane 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFG_LVDS_LANE0_EN ,Enable LVDS lane 0" "Disabled,Enabled"
|
|
line.long 0x04 "CFG_LVDS_GEN_1,CFG_LVDS_GEN_1 Register"
|
|
bitfld.long 0x04 2. " C3C3L ,Enable 3Ch3Lane mode in LVDS" "Disabled,Enabled"
|
|
line.long 0x08 "CFG_LVDS_GEN_2,CFG_LVDS_GEN_2 Register"
|
|
else
|
|
newline
|
|
width 31.
|
|
hgroup.long 0x1B0++0x03
|
|
hide.long 0x00 "CFG_LVDS_MAPPING_LANE0_FMT_0,Lane 0 Mapping Register"
|
|
hgroup.long 0x1B4++0x03
|
|
hide.long 0x00 "CFG_LVDS_MAPPING_LANE1_FMT_0,Lane 1 Mapping Register"
|
|
hgroup.long 0x1B8++0x03
|
|
hide.long 0x00 "CFG_LVDS_MAPPING_LANE2_FMT_0,Lane 2 Mapping Register"
|
|
hgroup.long 0x1BC++0x03
|
|
hide.long 0x00 "CFG_LVDS_MAPPING_LANE3_FMT_0,Lane 3 Mapping Register"
|
|
hgroup.long 0x1C0++0x03
|
|
hide.long 0x00 "CFG_LVDS_MAPPING_LANE0_FMT_1,Lane 0 Mapping Register"
|
|
hgroup.long 0x1C4++0x03
|
|
hide.long 0x00 "CFG_LVDS_MAPPING_LANE1_FMT_1,Lane 1 Mapping Register"
|
|
hgroup.long 0x1C8++0x03
|
|
hide.long 0x00 "CFG_LVDS_MAPPING_LANE2_FMT_1,Lane 2 Mapping Register"
|
|
hgroup.long 0x1CC++0x03
|
|
hide.long 0x00 "CFG_LVDS_MAPPING_LANE3_FMT_1,Lane 3 Mapping Register"
|
|
newline
|
|
width 19.
|
|
hgroup.long 0x1D0++0x03
|
|
hide.long 0x00 "CFG_LVDS_GEN_0,CFG_LVDS_GEN_0 Register"
|
|
hgroup.long 0x1D4++0x03
|
|
hide.long 0x00 "CFG_LVDS_GEN_1,CFG_LVDS_GEN_1 Register"
|
|
hgroup.long 0x1D8++0x03
|
|
hide.long 0x00 "CFG_LVDS_GEN_2,CFG_LVDS_GEN_2 Register"
|
|
endif
|
|
group.long 0x1DC++0x0B
|
|
line.long 0x00 "CFG_MASK_REG0,Mask 0 Register"
|
|
bitfld.long 0x00 12. " S_FRAME_DONE ,CBUFF has completed sending out data for the current frame" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " S_CHIRP_DONE ,CBUFF has completed sending out data for the current chirp" "Not masked,Masked"
|
|
line.long 0x04 "CFG_MASK_REG1,Mask 1 Register"
|
|
bitfld.long 0x04 12. " S_FRAME_ERR ,CBUFF has completed sending out data for the current frame" "Not masked,Masked"
|
|
bitfld.long 0x04 11. " S_CHIRP_ERR ,CBUFF has completed sending out data for the current chirp" "Not masked,Masked"
|
|
line.long 0x08 "CFG_MASK_REG2,Mask 2 Register"
|
|
rgroup.long 0x1EC++0x07
|
|
line.long 0x00 "STAT_CBUFF_REG0,CBUFF Status Register 0"
|
|
bitfld.long 0x00 12. " S_FRAME_DONE ,CBUFF has completed sending out data for the current frame" "No,Yes"
|
|
bitfld.long 0x00 11. " S_CHIRP_DONE ,CBUFF has completed sending out data for the current chirp" "No,Yes"
|
|
line.long 0x04 "STAT_CBUFF_REG1,CBUFF Status Register 1"
|
|
bitfld.long 0x04 17. " S_FRAME_ERR ,CBUFF has completed sending out data for the current frame" "No error,Error"
|
|
bitfld.long 0x04 16. " S_CHIRP_ERR ,CBUFF has completed sending out data for the current chirp" "No error,Error"
|
|
wgroup.long 0x20C++0x03
|
|
line.long 0x00 "CLR_CBUFF_REG0,CBUFF Clear Register 0"
|
|
bitfld.long 0x00 12. " S_FRAME_DONE ,CBUFF has completed sending out data for the current frame" "No effect,Clear"
|
|
bitfld.long 0x00 11. " S_CHIRP_DONE ,CBUFF has completed sending out data for the current chirp" "No effect,Clear"
|
|
rgroup.long 0x21C++0x03
|
|
line.long 0x00 "STAT_CBUFF_ECC_REG,CBUFF Status ECC Register"
|
|
bitfld.long 0x00 9. " SECCDBE ,Double bit error" "No error,Error"
|
|
bitfld.long 0x00 8. " SECCSBE ,Single bit error" "No error,Error"
|
|
hexmask.long.byte 0x00 0.--5. 0x01 " SECCADD ,6-bit address where the ECC error occurred"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "MASK_CBUFF_ECC_REG,CBUFF Mask ECC Register"
|
|
bitfld.long 0x00 9. " MECCDBE ,Mask double bit error" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MECCSBE ,Mask single bit error" "Not masked,Masked"
|
|
wgroup.long 0x224++0x03
|
|
line.long 0x00 "CLR_CBUFF_ECC_REG,CBUFF Clear ECC Register"
|
|
bitfld.long 0x00 9. " CECCDBE ,Double bit error" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CECCSBE ,Single bit error" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CECCADD ,6-bit address where the ECC error occurred" "No effect,Clear"
|
|
rgroup.long 0x228++0x03
|
|
line.long 0x00 "STAT_SAFETY,Safety Status Register"
|
|
bitfld.long 0x00 8. " SAF_CHIRP_ERR ,Safety error" "No error,Error"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAF_CRC ,CRC error between ADCB and CBUFF"
|
|
group.long 0x22C++0x07
|
|
line.long 0x00 "MASK_SAFETY,Safety Mask Register"
|
|
line.long 0x04 "CLR_SAFETY,Safety Clear Register"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("AWR1443*")
|
|
tree "CSI2_PROTOCOL_ENGINE Registers"
|
|
base ad:0x50060000
|
|
width 21.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSI2_REVISION,Module Revision"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,IP revision [7:4] major revision [3:0] minor revision"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "CSI2_SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "None,OCP,Functional,Both"
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management - idle req/ack control" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENWAKEUP ,Wake-up mode enable bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SOFT_RESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTO_IDLE ,Internal OCP gating strategy" "Free-run,Automatic"
|
|
line.long 0x04 "CSI2_SYSSTATUS,CSI2_SYS Status Status"
|
|
bitfld.long 0x04 0. " RESET_DONE ,Internal reset monitoring" "In progress,Completed"
|
|
line.long 0x08 "CSI2_IRQSTATUS,Interrupt Status Register"
|
|
bitfld.long 0x08 22. " TE1_LINE_IRQ ,Synchronize pulse for TE1 line have been received" "No event,Pending"
|
|
bitfld.long 0x08 21. " TE0_LINE_IRQ ,Synchronize pulse for TE0 line have been received" "No event,Pending"
|
|
bitfld.long 0x08 20. " TA_TO_IRQ ,Turn-around time out" "No event,Pending"
|
|
newline
|
|
bitfld.long 0x08 19. " LDO_POWER_GOOD_IRQ ,Status signal LDOPWRGOOD changed" "No event,Pending"
|
|
bitfld.long 0x08 18. " SYNC_LOST_IRQ ,Synchronization with video port is lost" "No event,Pending"
|
|
bitfld.long 0x08 17. " ACK_TRIGGER_IRQ ,Acknowledge trigger" "No event,Pending"
|
|
newline
|
|
bitfld.long 0x08 16. " TE_TRIGGER_IRQ ,Tearing effect trigger" "No event,Pending"
|
|
bitfld.long 0x08 15. " LP_RX_TO_IRQ ,Interrupt for low power RX time out" "No event,Pending"
|
|
bitfld.long 0x08 14. " HS_TX_TO_IRQ ,Interrupt for high speed TX time out" "No event,Pending"
|
|
newline
|
|
rbitfld.long 0x08 10. " COMPLEXIO_ERR_IRQ ,Error signaling from complex IO" "No event,Pending"
|
|
bitfld.long 0x08 9. " PLL_RECAL_IRQ ,PLL recal event" "No event,Pending"
|
|
bitfld.long 0x08 8. " PLL_UNLOCK_IRQ ,PLL un-clock event" "No event,Pending"
|
|
newline
|
|
bitfld.long 0x08 7. " PLL_LOCK_IRQ ,PLL clock event" "No event,Pending"
|
|
bitfld.long 0x08 5. " RESYNCHRONIZATION_IRQ ,Video mode resynchronization" "No event,Pending"
|
|
bitfld.long 0x08 4. " WAKEUP_IRQ ,Wakeup" "No event,Pending"
|
|
newline
|
|
bitfld.long 0x08 3. " VIRTUAL_CHANNEL3_IR ,Virtual channel 3" "No event,Pending"
|
|
bitfld.long 0x08 2. " VIRTUAL_CHANNEL2_IR ,Virtual channel 2" "No event,Pending"
|
|
bitfld.long 0x08 1. " VIRTUAL_CHANNEL1_IR ,Virtual channel 1" "No event,Pending"
|
|
newline
|
|
bitfld.long 0x08 0. " VIRTUAL_CHANNEL0_IR ,Virtual channel 0" "No event,Pending"
|
|
line.long 0x0C "CSI2_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x0C 22. " TE1_LINE_IRQ_EN ,Synchronize pulse for TE1 line have been received" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " TE0_LINE_IRQ_EN ,Synchronize pulse for TE0 line have been received" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " TA_TO_IRQ_EN ,Turn-around time out" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 19. " LDO_POWER_GOOD_IRQ_EN ,Status signal LDOPWRGOOD changed" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " SYNC_LOST_IRQ_EN ,Synchronization with video port is lost" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " ACK_TRIGGER_IRQ_EN ,Acknowledge trigger" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 16. " TE_TRIGGER_IRQ_EN ,Tearing effect trigger" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " LP_RX_TO_IRQ_EN ,Interrupt for low power RX time out" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " HS_TX_TO_IRQ_EN ,Interrupt for high speed TX time out" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 9. " PLL_RECAL_IRQ_EN ,PLL recal event" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " PLL_UNLOCK_IRQ_EN ,PLL un-clock event" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " PLL_LOCK_IRQ_EN ,PLL clock event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 5. " RESYNCHRONIZATION_IRQ_EN ,Video mode resynchronization" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " WAKEUP_IRQ_EN ,Wakeup" "Disabled,Enabled"
|
|
newline
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CSI2_CTRL,Global Control Register"
|
|
bitfld.long 0x00 24. " DISPC_UPDATE_SYNC ,Determines if the DISPC_UPDATE_SYNC signal from the display controller is used" "Not used,Used"
|
|
bitfld.long 0x00 23. " HSA_BLANKING_MODE ,HSA Blanking mode" "TX FIFO/LPS,LONG BLANKING PACKETS"
|
|
newline
|
|
bitfld.long 0x00 22. " HBP_BLANKING_MODE ,HBP Blanking mode" "TX FIFO/LPS,LONG BLANKING PACKETS"
|
|
bitfld.long 0x00 21. " HFP_BLANKING_MODE ,HFP Blanking mode" "TX FIFO/LPS,LONG BLANKING PACKETS"
|
|
newline
|
|
bitfld.long 0x00 20. " BLANKING_MODE ,Blanking mode" "LPS,LONG BLANKING PACKETS"
|
|
bitfld.long 0x00 19. " EOT_ENABLE ,Enable EOT packets at the end of HS transmission" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " VP_HSYNC_END ,HSYNC end pulse" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " VP_HSYNC_START ,HSYNC start pulse" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " VP_VSYNC_END ,VSYNC end pulse" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " VP_VSYNC_START ,VSYNC start pulse" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " TRIGGER_RESET_MODE ,Selection of the trigger reset mode" "Synchronized,Immediate"
|
|
bitfld.long 0x00 12.--13. " LINE_BUFFER ,Number of line buffers to be used while receiving data on the video port" "No line,1 line,2 lines,?..."
|
|
newline
|
|
bitfld.long 0x00 11. " VP_VSYNC_POL ,VP vertical synchronization signal polarity" "Low,High"
|
|
bitfld.long 0x00 10. " VP_VSYNC_POL ,VP vertical synchronization signal polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " VP_DE_POL ,VP data enable signal polarity" "Low,High"
|
|
bitfld.long 0x00 8. " VP_CLK_POL ,VP clock polarity" "Falling edge,Rising edge"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " VP_DATA_BUS_WIDTH ,Defines the size of the video port data bus" "16 bits,18 bits,24 bits,?..."
|
|
bitfld.long 0x00 5. " TRIGGER_RESET ,Send the reset trigger to the peripheral" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 4. " VP_CLK_RATIO ,The field indicates the clock ratio between VP.CLK and VP.PCLK" "/2,/3"
|
|
bitfld.long 0x00 3. " TX_FIFO_ARBITRATION ,Defines the arbitration scheme for granting the virtual channel pending ready requests in the TX FIFO" "Round-robin,Sequential"
|
|
newline
|
|
bitfld.long 0x00 2. " ECC_RX_EN ,Enables the error correction code check for the received header" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CS_RX_EN ,Enables the checksum check for the received payload" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " IF_EN ,Enable the module" "Disabled,Enabled"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CSI2_GNQ,Generic Parameter Register"
|
|
bitfld.long 0x00 24. " NB_VIDEO_PORTS ,Number of video ports" "Only 1,1 and 2"
|
|
bitfld.long 0x00 22.--23. " VP2_NB_LINE_BUFFER ,Number of video buffer lines associated to video port 2" "No line,1 line,2 lines,?..."
|
|
newline
|
|
bitfld.long 0x00 18.--20. " VP2_LINE_BUFFER_SIZE ,Determines the video line buffer size associated to video port 2" "Memory of 384x32-bits,Memory of 512x32-bits,Memory of 640x32-bits,Memory of 768x32-bits,Memory of 896x32-bits,Memory of 1024x32-bits,?..."
|
|
bitfld.long 0x00 16.--17. " VP1_NB_LINE_BUFFER ,Determines the number of video buffer lines associated to video port 1" "No line,1 line,2 lines,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--14. " VP1_LINE_BUFFER_SIZE ,Determines the video line buffer size associated to video port 1" "Memory of 384x32-bits,Memory of 512x32-bits,Memory of 640x32-bits,Memory of 768x32-bits,Memory of 896x32-bits,Memory of 1024x32-bits,?..."
|
|
bitfld.long 0x00 9.--11. " NB_DATA_LANES ,Determines the number of data lanes supported by the CSI2 protocol engine" ",1,2,3,4,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--8. " NB_DMA_REQUEST ,Determines the number of DMA_REQ signals" "No DMA,1,2,3,4,?..."
|
|
bitfld.long 0x00 3.--5. " RX_FIFODEPTH ,Determines the data RX FIFO depth (32-bit words) on the slave port" ",,,,32x33 bits,64x33 bits,128x33 bits,256x33 bits"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TX_FIFODEPTH ,Determines the data TX FIFO depth (33-bit words) on the slave port" ",,,,32x33 bits,64x33 bits,128x33 bits,256x33 bits"
|
|
width 27.
|
|
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group.long 0x48++0x5B
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line.long 0x00 "CSI2_COMPLEXIO_CFG1,Complex IO Configuration Register"
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bitfld.long 0x00 31. " SHADOWING ,Shadowing configuration" "Disabled,Enabled"
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bitfld.long 0x00 30. " GOBIT ,Allows the synchronized update of the shadow Registers when the signal DISPCUpdateSync is active" "Not allowed,Allowed"
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rbitfld.long 0x00 29. " RESET_DONE ,Internal reset monitoring of the power domain using the PPI byte clock from the complex IO" "In progress,Done"
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bitfld.long 0x00 27.--28. " PWR_CMD ,Command for power control of the complex IO" "Off,On,Ultra low power,?..."
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rbitfld.long 0x00 25.--26. " PWR_STATUS ,Status of the power control of the complex IO" "Off,On,Ultra low power,?..."
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rbitfld.long 0x00 21. " LDO_POWER_GOOD_STATE ,LDOPWRGOOD state" "Down,Up"
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bitfld.long 0x00 20. " USE_LDO_EXTERNAL ,Select the external LDO for the CSI2PHY" "Internal,External"
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bitfld.long 0x00 19. " DATA4_POL ,Differential pin order of DATA lane 4" "Plus/minus,Minus/plus"
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bitfld.long 0x00 16.--18. " DATA4_POSITION ,Position and order of the DATA lane 4" "Not used,Position 1,Position 2,Position 3,Position 4,Position 5,?..."
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bitfld.long 0x00 15. " DATA3_POL ,Differential pin order of DATA lane 3" "Plus/minus,Minus/plus"
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bitfld.long 0x00 12.--14. " DATA3_POSITION ,Position and order of the DATA lane 3" "Not used,Position 1,Position 2,Position 3,Position 4,Position 5,?..."
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bitfld.long 0x00 11. " DATA2_POL ,Differential pin order of DATA lane 2" "Plus/minus,Minus/plus"
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bitfld.long 0x00 8.--10. " DATA2_POSITION ,Position and order of the DATA lane 2" "Not used,Position 1,Position 2,Position 3,Position 4,Position 5,?..."
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bitfld.long 0x00 7. " DATA1_POL ,Differential pin order of DATA lane 1" "Plus/minus,Minus/plus"
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bitfld.long 0x00 4.--6. " DATA1_POSITION ,Position and order of the DATA lane 1" ",Position 1,Position 2,Position 3,Position 4,Position 5,?..."
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bitfld.long 0x00 3. " CLOCK_POL ,Differential pin order of DATA lane 0" "Plus/minus,Minus/plus"
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bitfld.long 0x00 0.--2. " CLOCK_POSITION ,Position and order of the CLOCK lane 0" ",Position 1,Position 2,Position 3,Position 4,?..."
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line.long 0x04 "CSI2_COMPLEXIO_IRQSTATUS,Interrupt Status Register"
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bitfld.long 0x04 31. " ULPSACTIVENOT_ALL1_IRQ ,All the ULPSActiveNOT signals corresponding to the lanes with TXULPSExit being high are high" "False,True"
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bitfld.long 0x04 30. " ULPSACTIVENOT_ALL0_IRQ ,All signals ULPSActiveNOT are 0" "False,True"
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bitfld.long 0x04 29. " ERRCONTENTIONLP1_5_IRQ ,Contention LP1 error for lane 5" "False,True"
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bitfld.long 0x04 28. " ERRCONTENTIONLP0_5_IRQ ,Contention LP0 error for lane 5" "False,True"
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bitfld.long 0x04 27. " ERRCONTENTIONLP1_4_IRQ ,Contention LP1 error for lane 4" "False,True"
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bitfld.long 0x04 26. " ERRCONTENTIONLP0_4_IRQ ,Contention LP0 error for lane 4" "False,True"
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bitfld.long 0x04 25. " ERRCONTENTIONLP1_3_IRQ ,Contention LP1 error for lane 3" "False,True"
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bitfld.long 0x04 24. " ERRCONTENTIONLP0_3_IRQ ,Contention LP0 error for lane 3" "False,True"
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bitfld.long 0x04 23. " ERRCONTENTIONLP1_2_IRQ ,Contention LP1 error for lane 2" "False,True"
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bitfld.long 0x04 22. " ERRCONTENTIONLP0_2_IRQ ,Contention LP0 error for lane 2" "False,True"
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bitfld.long 0x04 21. " ERRCONTENTIONLP1_1_IRQ ,Contention LP1 error for lane 1" "False,True"
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bitfld.long 0x04 20. " ERRCONTENTIONLP0_1_IRQ ,Contention LP0 error for lane 1" "False,True"
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bitfld.long 0x04 19. " STATEULPS5_IRQ ,Lane 5 in ultra low power state" "False,True"
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bitfld.long 0x04 18. " STATEULPS4_IRQ ,Lane 4 in ultra low power state" "False,True"
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bitfld.long 0x04 17. " STATEULPS3_IRQ ,Lane 3 in ultra low power state" "False,True"
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bitfld.long 0x04 16. " STATEULPS2_IRQ ,Lane 2 in ultra low power state" "False,True"
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bitfld.long 0x04 15. " STATEULPS1_IRQ ,Lane 1 in ultra low power state" "False,True"
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bitfld.long 0x04 14. " ERRCONTROL5_IRQ ,Control error for lane 5" "False,True"
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bitfld.long 0x04 13. " ERRCONTROL4_IRQ ,Control error for lane 4" "False,True"
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bitfld.long 0x04 12. " ERRCONTROL3_IRQ ,Control error for lane 3" "False,True"
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bitfld.long 0x04 11. " ERRCONTROL2_IRQ ,Control error for lane 2" "False,True"
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bitfld.long 0x04 10. " ERRCONTROL1_IRQ ,Control error for lane 1" "False,True"
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bitfld.long 0x04 9. " ERRESC5_IRQ ,Escape entry error for lane 5" "False,True"
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bitfld.long 0x04 8. " ERRESC4_IRQ ,Escape entry error for lane 4" "False,True"
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bitfld.long 0x04 7. " ERRESC3_IRQ ,Escape entry error for lane 3" "False,True"
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bitfld.long 0x04 6. " ERRESC2_IRQ ,Escape entry error for lane 2" "False,True"
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bitfld.long 0x04 5. " ERRESC1_IRQ ,Escape entry error for lane 1" "False,True"
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bitfld.long 0x04 4. " ERRSYNCESC5_IRQ ,Low power data transmission synchronization error for lane 5" "False,True"
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bitfld.long 0x04 3. " ERRSYNCESC4_IRQ ,Low power data transmission synchronization error for lane 4" "False,True"
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bitfld.long 0x04 2. " ERRSYNCESC3_IRQ ,Low power data transmission synchronization error for lane 3" "False,True"
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bitfld.long 0x04 1. " ERRSYNCESC2_IRQ ,Low power data transmission synchronization error for lane 2" "False,True"
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bitfld.long 0x04 0. " ERRSYNCESC1_IRQ ,Low power data transmission synchronization error for lane 1" "False,True"
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line.long 0x08 "CSI2_COMPLEXIO_IRQENABLE,Interrupt Enable Register"
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bitfld.long 0x08 31. " ULPSACTIVENOT_ALL1_IRQ_EN ,All the ULPSActiveNOT signals corresponding to the lanes with TXULPSExit being high are high" "Masked,Interrupt"
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bitfld.long 0x08 30. " ULPSACTIVENOT_ALL0_IRQ_EN ,All signals ULPSActiveNOT are 0" "Masked,Interrupt"
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bitfld.long 0x08 29. " ERRCONTENTIONLP1_5_IRQ_EN ,Contention LP1 error for lane 5" "Masked,Interrupt"
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bitfld.long 0x08 28. " ERRCONTENTIONLP0_5_IRQ_EN ,Contention LP0 error for lane 5" "Masked,Interrupt"
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bitfld.long 0x08 27. " ERRCONTENTIONLP1_4_IRQ_EN ,Contention LP1 error for lane 4" "Masked,Interrupt"
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bitfld.long 0x08 26. " ERRCONTENTIONLP0_4_IRQ_EN ,Contention LP0 error for lane 4" "Masked,Interrupt"
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bitfld.long 0x08 25. " ERRCONTENTIONLP1_3_IRQ_EN ,Contention LP1 error for lane 3" "Masked,Interrupt"
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bitfld.long 0x08 24. " ERRCONTENTIONLP0_3_IRQ_EN ,Contention LP0 error for lane 3" "Masked,Interrupt"
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bitfld.long 0x08 23. " ERRCONTENTIONLP1_2_IRQ_EN ,Contention LP1 error for lane 2" "Masked,Interrupt"
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bitfld.long 0x08 22. " ERRCONTENTIONLP0_2_IRQ_EN ,Contention LP0 error for lane 2" "Masked,Interrupt"
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bitfld.long 0x08 21. " ERRCONTENTIONLP1_1_IRQ_EN ,Contention LP1 error for lane 1" "Masked,Interrupt"
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bitfld.long 0x08 20. " ERRCONTENTIONLP0_1_IRQ_EN ,Contention LP0 error for lane 1" "Masked,Interrupt"
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bitfld.long 0x08 19. " STATEULPS5_IRQ_EN ,Lane 5 in ultra low power state" "Masked,Interrupt"
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bitfld.long 0x08 18. " STATEULPS4_IRQ_EN ,Lane 4 in ultra low power state" "Masked,Interrupt"
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bitfld.long 0x08 17. " STATEULPS3_IRQ_EN ,Lane 3 in ultra low power state" "Masked,Interrupt"
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bitfld.long 0x08 16. " STATEULPS2_IRQ_EN ,Lane 2 in ultra low power state" "Masked,Interrupt"
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bitfld.long 0x08 15. " STATEULPS1_IRQ_EN ,Lane 1 in ultra low power state" "Masked,Interrupt"
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bitfld.long 0x08 14. " ERRCONTROL5_IRQ_EN ,Control error for lane 5" "Masked,Interrupt"
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bitfld.long 0x08 13. " ERRCONTROL4_IRQ_EN ,Control error for lane 4" "Masked,Interrupt"
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bitfld.long 0x08 12. " ERRCONTROL3_IRQ_EN ,Control error for lane 3" "Masked,Interrupt"
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bitfld.long 0x08 11. " ERRCONTROL2_IRQ_EN ,Control error for lane 2" "Masked,Interrupt"
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bitfld.long 0x08 10. " ERRCONTROL1_IRQ_EN ,Control error for lane 1" "Masked,Interrupt"
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bitfld.long 0x08 9. " ERRESC5_IRQ_EN ,Escape entry error for lane 5" "Masked,Interrupt"
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bitfld.long 0x08 8. " ERRESC4_IRQ_EN ,Escape entry error for lane 4" "Masked,Interrupt"
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bitfld.long 0x08 7. " ERRESC3_IRQ_EN ,Escape entry error for lane 3" "Masked,Interrupt"
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bitfld.long 0x08 6. " ERRESC2_IRQ_EN ,Escape entry error for lane 2" "Masked,Interrupt"
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bitfld.long 0x08 5. " ERRESC1_IRQ_EN ,Escape entry error for lane 1" "Masked,Interrupt"
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bitfld.long 0x08 4. " ERRSYNCESC5_IRQ_EN ,Low power data transmission synchronization error for lane 5" "Masked,Interrupt"
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bitfld.long 0x08 3. " ERRSYNCESC4_IRQ_EN ,Low power data transmission synchronization error for lane 4" "Masked,Interrupt"
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bitfld.long 0x08 2. " ERRSYNCESC3_IRQ_EN ,Low power data transmission synchronization error for lane 3" "Masked,Interrupt"
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bitfld.long 0x08 1. " ERRSYNCESC2_IRQ_EN ,Low power data transmission synchronization error for lane 2" "Masked,Interrupt"
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bitfld.long 0x08 0. " ERRSYNCESC1_IRQ_EN ,Low power data transmission synchronization error for lane 1" "Masked,Interrupt"
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line.long 0x0C "CSI2_CLK_CTRL,Clock Control"
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bitfld.long 0x0C 30.--31. " PLL_PWR_CMD ,Command for power control of the CSI2 PLL control module" "OFF,ON (PLL only),ON (PLL and HSDIVISER),ON (PLL and HSDIVISER - no clock)"
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bitfld.long 0x0C 28.--29. " PLL_PWR_STATUS ,Status of the power control of the CSI2 PLL control module" "OFF,ON (PLL only),ON (PLL and HSDIVISER),ON (PLL and HSDIVISER - no clock)"
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bitfld.long 0x0C 21. " LP_RX_SYNCHRO_ENABLE ,Defines if the functional is higher or lower than 30 mHz" "Equal or slower,Faster"
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bitfld.long 0x0C 20. " LP_CLK_ENABLE ,Controls the gating of the TXCLKESC clock" "Disabled,Enabled"
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bitfld.long 0x0C 19. " HS_MANUAL_STOP_CTRL ,In case HS_AUTO_STOP_Enable=0 the bit-field allows manual control of the (de)assertion of the signal CSI2StopClk by the user" "De-assertion,Assertion"
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bitfld.long 0x0C 18. " HS_AUTO_STOP_ENABLE ,Enable the automatic assertion/de-assertion of CSI2StopClk signal" "Disabled,Enabled"
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bitfld.long 0x0C 16.--17. " LP_CLK_NULL_PACKET_SIZE ,Size of LP NULL" "0 bytes,1 byte,2 bytes,3 bytes"
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bitfld.long 0x0C 15. " LP_CLK_NULL_PACKET_ENABLE ,Enables the generation of NULL packet in low speed" "Disabled,Enabled"
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bitfld.long 0x0C 14. " CIO_CLK_ICG ,Gates SCPClk clock provided to CSI2-PHY and PLL-CTRL module" "Disabled,Enabled"
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bitfld.long 0x0C 13. " DDR_CLK_ALWAYS_ON ,Defines if the DDR clock is also sent when there is no HS packets sent to the peripheral (Low power mode)" "Disabled,Enabled"
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hexmask.long.word 0x0C 0.--12. 1. " LP_CLK_DIVISOR ,Defines the ratio to be used for the generation of the low power mode clock from CSI2 functional clock"
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line.long 0x10 "CSI2_TIMING1,Timing 1 Register"
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bitfld.long 0x10 31. " TA_TO ,Enables the turn-around timer" "Disabled,Enabled"
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bitfld.long 0x10 30. " TA_TO_X16 ,Multiplication factor for the number of CSI2_CLK functional clock cycles defined in TA_TO_COUNTER bit-field" "x1,x16"
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bitfld.long 0x10 29. " TA_TO_X8 ,Multiplication factor for the number of CSI2_CLK functional clock cycles defined in TA_TO_COUNTER bit-field" "x1,x8"
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hexmask.long.word 0x10 16.--28. 1. " TA_TO_COUNTER ,Turn around counter"
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bitfld.long 0x10 15. " FORCE_TX_STOP_MODE_IO ,Control of ForceTxStopMode signal" "De-asserted,Asserted"
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bitfld.long 0x10 14. " STOP_STATE_X16_IO ,Multiplication factor for the number of CSI2_CLK functional clock cycles defined in STOP_STATE_COUNTER_IO bit-field" "x1,x16"
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bitfld.long 0x10 13. " STOP_STATE_X4_IO ,Multiplication factor for the number of CSI2_CLK functional clock cycles defined in STOP_STATE_COUNTER_IO bit-field" "x1,x4"
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hexmask.long.word 0x10 0.--12. 1. " STOP_STATE_COUNTE ,Stop state counter"
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line.long 0x14 "CSI2_TIMING2,Timing 2 Register"
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bitfld.long 0x14 31. " HS_TX_TO ,Enables the HS TX timer" "Disabled,Enabled"
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bitfld.long 0x14 30. " HS_TX_TO_X64 ,Multiplication factor for the number of BYTE_CLK functional clock cycles defined in HS_TX_COUNTER bit-field" "x1,x64"
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bitfld.long 0x14 29. " HS_TX_TO_X16 ,Multiplication factor for the number of BYTE_CLK functional clock cycles defined in HS_TX_COUNTER bit" "x1,x8"
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hexmask.long.word 0x14 16.--28. 1. " HS_TX_TO_COUNTER ,HS_TX_TIMER counter"
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bitfld.long 0x14 15. " LP_RX_TO ,Enables the LP RX timer" "Disabled,Enabled"
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bitfld.long 0x14 14. " LP_RX_TO_X16 ,Multiplication factor for the number of CSI2_CLK functional clock cycles defined in LP_RX_COUNTER bit-field" "x1,x16"
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bitfld.long 0x14 13. " LP_RX_TO_X4 ,Multiplication factor for the number of CSI2_CLK functional clock cycles defined in LP_RX_COUNTER bit" "x1,x4"
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hexmask.long.word 0x14 0.--12. 1. " LP_RX_TO_COUNTER ,LP_RX_TIMER counter"
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line.long 0x18 "CSI2_VM_TIMING1,Video Mode Timing Register 1"
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hexmask.long.byte 0x18 24.--31. 1. " HSA ,Defines the horizontal sync active period used in video mode in number of byte clock cycles"
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hexmask.long.word 0x18 12.--23. 1. " HFP ,Defines the horizontal front porch used in video mode in number of byte clock cycles"
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hexmask.long.word 0x18 0.--11. 1. " HBP ,Defines the horizontal back porch used in video mode in number of byte clock cycles"
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line.long 0x1C "CSI2_VM_TIMING2,Video Mode Timing Register 2"
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bitfld.long 0x1C 24.--27. " WINDOW_SYNC ,Number of BYTE clock cycles for the synchronization window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x1C 16.--23. 1. " VSA ,Defines the vertical sync active period used in video mode in number of lines"
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hexmask.long.byte 0x1C 8.--15. 1. " VFP ,Defines the vertical front porch used in video mode in number of lines"
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hexmask.long.byte 0x1C 0.--7. 1. " VBP ,Defines the vertical back porch used in video mode in number of lines"
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line.long 0x20 "CSI2_VM_TIMING3,Video Mode Timing Register 3"
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hexmask.long.word 0x20 16.--31. 1. " TL ,Defines the number of length of the line in video mode in number of byte clock cycles"
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hexmask.long.word 0x20 0.--15. 1. " VACT ,Defines the number of active lines used in video mode"
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line.long 0x24 "CSI2_CLK_TIMING,Clock Timing Register"
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hexmask.long.byte 0x24 8.--15. 1. " DDR_CLK_PRE ,Indicates the number of PPI byte clock cycles between the start of the DDR clock and the assertion of the data request signal"
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hexmask.long.byte 0x24 0.--7. 1. " DDR_CLK_POST ,Indicates the number of PPI byte clock cycles after the de-assertion of the data request signal and the stop of the DDR clock"
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line.long 0x28 "CSI2_TX_FIFO_VC_SIZE,CSI2 TX FIFO VC Size Register"
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bitfld.long 0x28 28.--31. " VC3_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 3" "0x33bits,32x33bits,64x33bits,96x33bits,128x33bits,160x33bits,192x33bits,224x33bits,256x33bits,?..."
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bitfld.long 0x28 24.--26. " VC3_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 3" "0,32,64,96,?..."
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bitfld.long 0x28 20.--23. " VC2_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 2" "0x33bits,32x33bits,64x33bits,96x33bits,128x33bits,160x33bits,192x33bits,224x33bits,256x33bits,?..."
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bitfld.long 0x28 16.--18. " VC2_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 2" "0,32,64,96,?..."
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bitfld.long 0x28 12.--15. " VC1_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 1" "0x33bits,32x33bits,64x33bits,96x33bits,128x33bits,160x33bits,192x33bits,224x33bits,256x33bits,?..."
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bitfld.long 0x28 8.--10. " VC1_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 1" "0,32,64,96,?..."
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bitfld.long 0x28 4.--7. " VC0_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 0" "0x33bits,32x33bits,64x33bits,96x33bits,128x33bits,160x33bits,192x33bits,224x33bits,256x33bits,?..."
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bitfld.long 0x28 0.--2. " VC0_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 0" "0,32,64,96,?..."
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line.long 0x2C "CSI2_RX_FIFO_VC_SIZE,CSI2 RX FIFO VC Size Register"
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bitfld.long 0x2C 28.--31. " VC3_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 3" "0x33bits,32x33bits,64x33bits,96x33bits,128x33bits,160x33bits,192x33bits,224x33bits,256x33bits,?..."
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bitfld.long 0x2C 24.--26. " VC3_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 3" "0,32,64,96,?..."
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bitfld.long 0x2C 20.--23. " VC2_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 2" "0x33bits,32x33bits,64x33bits,96x33bits,128x33bits,160x33bits,192x33bits,224x33bits,256x33bits,?..."
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bitfld.long 0x2C 16.--18. " VC2_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 2" "0,32,64,96,?..."
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bitfld.long 0x2C 12.--15. " VC1_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 1" "0x33bits,32x33bits,64x33bits,96x33bits,128x33bits,160x33bits,192x33bits,224x33bits,256x33bits,?..."
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bitfld.long 0x2C 8.--10. " VC1_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 1" "0,32,64,96,?..."
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bitfld.long 0x2C 4.--7. " VC0_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 0" "0x33bits,32x33bits,64x33bits,96x33bits,128x33bits,160x33bits,192x33bits,224x33bits,256x33bits,?..."
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bitfld.long 0x2C 0.--2. " VC0_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 0" "0,32,64,96,?..."
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line.long 0x30 "CSI2_COMPLEXIO_CFG2,Complexio Configuration Register"
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bitfld.long 0x30 17. " LP_BUSY ,Indicates when there are still pending operations for VCs configured for LP mode" "Idle,Active"
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bitfld.long 0x30 16. " HS_BUSY ,Indicates when there are still pending operations for VCs configured for HS mode" "Idle,Active"
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bitfld.long 0x30 9. " LANE5_ULPS_SIG2 ,Enables the ULPS for the lane 5" "Inactive,Active"
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bitfld.long 0x30 8. " LANE4_ULPS_SIG2 ,Enables the ULPS for the lane 4" "Inactive,Active"
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bitfld.long 0x30 7. " LANE3_ULPS_SIG2 ,Enables the ULPS for the lane 3" "Inactive,Active"
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bitfld.long 0x30 6. " LANE2_ULPS_SIG2 ,Enables the ULPS for the lane 2" "Inactive,Active"
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bitfld.long 0x30 5. " LANE1_ULPS_SIG2 ,Enables the ULPS for the lane 1" "Inactive,Active"
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bitfld.long 0x30 4. " LANE5_ULPS_SIG1 ,Enables the ULPS for the lane 5" "Inactive,Active"
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|
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bitfld.long 0x30 3. " LANE4_ULPS_SIG1 ,Enables the ULPS for the lane 4" "Inactive,Active"
|
|
bitfld.long 0x30 2. " LANE3_ULPS_SIG1 ,Enables the ULPS for the lane 3" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x30 1. " LANE2_ULPS_SIG1 ,Enables the ULPS for the lane 2" "Inactive,Active"
|
|
bitfld.long 0x30 0. " LANE1_ULPS_SIG1 ,Enables the ULPS for the lane 1" "Inactive,Active"
|
|
line.long 0x34 "CSI2_RX_FIFO_VC_FULLNESS,CSI2 RX FIFO VC Fullness Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " VC3_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 3"
|
|
hexmask.long.byte 0x34 16.--23. 1. " VC2_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 2"
|
|
newline
|
|
hexmask.long.byte 0x34 8.--15. 1. " VC1_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 1"
|
|
hexmask.long.byte 0x34 0.--7. 1. " VC0_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 0"
|
|
line.long 0x38 "CSI2_VM_TIMING4,Video Mode Timing Register"
|
|
hexmask.long.byte 0x38 16.--23. 1. " HSA_HS_INTERLEAVING ,Defines the number of HS byte clock cycles"
|
|
hexmask.long.byte 0x38 8.--15. 1. " HFP_HS_INTERLEAVING ,Defines the number of HS byte clock cycles"
|
|
newline
|
|
hexmask.long.byte 0x38 0.--7. 1. " HBP_HS_INTERLEAVING ,Defines the number of HS byte clock cycles"
|
|
line.long 0x3C "CSI2_TX_FIFO_VC_EMPTINESS,CSI2 TX FIFO VC Emptiness Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " VC3_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 3"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " VC2_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 2"
|
|
newline
|
|
hexmask.long.byte 0x3C 8.--15. 1. " VC1_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 1"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " VC0_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 0"
|
|
line.long 0x40 "CSI2_VM_TIMING4,Video Mode Timing Register"
|
|
hexmask.long.byte 0x40 16.--23. 1. " HSA_LP_INTERLEAVING ,Defines the number of bytes of low power command mode packets"
|
|
hexmask.long.byte 0x40 8.--15. 1. " HFP_LP_INTERLEAVING ,Defines the number of bytes of low power command mode packets"
|
|
newline
|
|
hexmask.long.byte 0x40 0.--7. 1. " HBP_LP_INTERLEAVING ,Defines the number of bytes of low power command mode packets"
|
|
line.long 0x44 "CSI2_VM_TIMING6,Video Mode Timing Register"
|
|
hexmask.long.word 0x44 16.--31. 1. " BL_HS_INTERLEAVING ,Defines the number of HS byte clock cycles"
|
|
hexmask.long.word 0x44 0.--15. 1. " BL_LP_INTERLEAVING ,Defines the maximum number of bytes of low power command mode packets"
|
|
line.long 0x48 "CSI2_VM_TIMING7,CSI2 VM Timing 7 Register"
|
|
hexmask.long.word 0x48 16.--31. 1. " ENTER_HS_MODE_LATENCY ,Defines the number of HS byte clock cycles necessary for entering to HS mode"
|
|
hexmask.long.word 0x48 0.--15. 1. " BL_LP_INTERLEAVING ,Defines the number of HS byte clock cycles necessary for exiting from HS mode"
|
|
line.long 0x4C "CSI2_STOPCLK_TIMING,CSI2 Stop Clock Timing Register"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " CSI2_STOPCLK_LATENCY ,Clock gating latency from CSI2 protocol to TxByteClkHS"
|
|
line.long 0x50 "CSI2_CTRL2,CSI2 CTRL2 Register"
|
|
bitfld.long 0x50 12.--13. " LINE_BUFFER ,Number of line buffers to be used while receiving data on the video port" "No line,1 line,2 lines,?..."
|
|
bitfld.long 0x50 11. " VP_VSYNC_POL ,VP vertical synchronization signal polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x50 10. " VP_HSYNC_POL ,VP horizontal synchronization signal polarity" "Low,High"
|
|
bitfld.long 0x50 9. " VP_DE_POL ,VP data Enable signal polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x50 8. " VP_CLK_POL ,VP clock polarity" "Falling edge,Rising edge"
|
|
bitfld.long 0x50 6.--7. " VP_DATA_BUS_WIDTH ,Defines the size of the video port data bus" "16-bits,18-bits,24-bits,?..."
|
|
newline
|
|
bitfld.long 0x50 4. " VP_CLK_RATIO ,The field indicates the clock ratio between VP.CLK and VP.PCLK" "VP.PCLK=VP.CLK/2,VP.PCLK=VP.CLK/3"
|
|
line.long 0x54 "CSI2_VM_TIMING8,Video Mode Timing Register"
|
|
bitfld.long 0x54 0.--1. " HFPX ,Extension to the HFP" "0,1,2,3"
|
|
line.long 0x58 "CSI2_TE_HSYNC_WIDTH_0,CSI2 TE HSYNC Width 0 Register"
|
|
hexmask.long.word 0x58 8.--19. 1. " MIN_HSYNC_PULSE_WIDTH ,Programmable min HSYNC pulse width"
|
|
group.long 0xA6++0x03
|
|
line.long 0x00 "CSI2_TE_HSYNC_WIDTH_1,CSI2 TE HSYNC Width 1 Register"
|
|
hexmask.long.word 0x00 8.--19. 1. " MIN_HSYNC_PULSE_WIDTH ,Programmable min HSYNC pulse width"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CSI2_TE_VSYNC_WIDTH_0,CSI2 TE VSYNC Width 0 Register"
|
|
hexmask.long.word 0x00 8.--19. 1. " MIN_VSYNC_PULSE_WIDTH ,Programmable min VSYNC pulse width"
|
|
group.long 0xAA++0x03
|
|
line.long 0x00 "CSI2_TE_VSYNC_WIDTH_1,CSI2 TE VSYNC Width 1 Register"
|
|
hexmask.long.word 0x00 8.--19. 1. " MIN_VSYNC_PULSE_WIDTH ,Programmable min VSYNC pulse width"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CSI2_TE_HSYNC_NUMBER_0,CSI2 TE HSYNC Number 0 Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " LINE_NUMBER ,Programmable line number"
|
|
group.long 0xAE++0x03
|
|
line.long 0x00 "CSI2_TE_HSYNC_NUMBER_1,CSI2 TE HSYNC Number 1 Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " LINE_NUMBER ,Programmable line number"
|
|
newline
|
|
width 16.
|
|
newline
|
|
if (((per.l(ad:0x50060000+0x100))&0x10)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CSI2_VC_CTRL_0,Control Register"
|
|
bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or OCP slave data" "Continue,Start"
|
|
bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port." "Not inserted,Inserted"
|
|
newline
|
|
bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request" "DMA_req0,DMA_req1,DMA_req2,DMA_req3,No DMA req,?..."
|
|
bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request" "DMA_req0,DMA_req1,DMA_req2,DMA_req3,No DMA,?..."
|
|
rbitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
rbitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status" "Not full,Full"
|
|
newline
|
|
rbitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (Packets/BTA) are still being processed" "Not pending,Pending"
|
|
rbitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status" "Permitted,Not permitted"
|
|
newline
|
|
bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2" "Video port 1,Video port 2"
|
|
bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565" "MIPI DBI-2 spec,Video mode"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the OCP data bus" "16-bits,24-bits,2x16-bits,32-bits"
|
|
bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " ECC_TX_EN ,Enables the error correction code generation for the transmit header" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral" "Completed,Requested"
|
|
rbitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 4. " MODE ,Select mode" "Command,VP.STOLE"
|
|
bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOURCE ,Selection of the source between OCP and the video port(s)" "Slave,Video"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_EN ,Enable virtual channel" "Disabled,Enabled"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CSI2_VC_CTRL_0,Control Register"
|
|
bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or OCP slave data" "Continue,Start"
|
|
bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port." "Not inserted,Inserted"
|
|
newline
|
|
bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request" "DMA_req0,DMA_req1,DMA_req2,DMA_req3,No DMA req,?..."
|
|
bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request" "DMA_req0,DMA_req1,DMA_req2,DMA_req3,No DMA,?..."
|
|
rbitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
rbitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO Status" "Not full,Full"
|
|
newline
|
|
rbitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (Packets/BTA) are still being processed" "Not pending,Pending"
|
|
rbitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status" "Permitted,Not permitted"
|
|
newline
|
|
bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2" "Video port 1,Video port 2"
|
|
bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565" "MIPI DBI-2 spec,Video mode"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the OCP data bus" "16-bits,24-bits,2x16-bits,32-bits"
|
|
bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " ECC_TX_EN ,Enables the error correction code generation for the transmit header" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral" "Completed,Requested"
|
|
rbitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 4. " MODE ,Select mode" "Command,Video"
|
|
bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOURCE ,Selection of the source between OCP and the video port(s)" "Slave,Video"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_EN ,Enable virtual channel" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x50060000+0x100))&0x10)==0x00)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CSI2_VC_CTRL_1,Control Register"
|
|
bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or OCP slave data" "Continue,Start"
|
|
bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port." "Not inserted,Inserted"
|
|
newline
|
|
bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request" "DMA_req0,DMA_req1,DMA_req2,DMA_req3,No DMA req,?..."
|
|
bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request" "DMA_req0,DMA_req1,DMA_req2,DMA_req3,No DMA,?..."
|
|
rbitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
rbitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status" "Not full,Full"
|
|
newline
|
|
rbitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (Packets/BTA) are still being processed" "Not pending,Pending"
|
|
rbitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status" "Permitted,Not permitted"
|
|
newline
|
|
bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2" "Video port 1,Video port 2"
|
|
bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565" "MIPI DBI-2 spec,Video mode"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the OCP data bus" "16-bits,24-bits,2x16-bits,32-bits"
|
|
bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " ECC_TX_EN ,Enables the error correction code generation for the transmit header" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral" "Completed,Requested"
|
|
rbitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 4. " MODE ,Select mode" "Command,VP.STOLE"
|
|
bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOURCE ,Selection of the source between OCP and the video port(s)" "Slave,Video"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_EN ,Enable virtual channel" "Disabled,Enabled"
|
|
else
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CSI2_VC_CTRL_1,Control Register"
|
|
bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or OCP slave data" "Continue,Start"
|
|
bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port." "Not inserted,Inserted"
|
|
newline
|
|
bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request" "DMA_req0,DMA_req1,DMA_req2,DMA_req3,No DMA req,?..."
|
|
bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request" "DMA_req0,DMA_req1,DMA_req2,DMA_req3,No DMA,?..."
|
|
rbitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
rbitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO Status" "Not full,Full"
|
|
newline
|
|
rbitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (Packets/BTA) are still being processed" "Not pending,Pending"
|
|
rbitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status" "Permitted,Not permitted"
|
|
newline
|
|
bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2" "Video port 1,Video port 2"
|
|
bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565" "MIPI DBI-2 spec,Video mode"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the OCP data bus" "16-bits,24-bits,2x16-bits,32-bits"
|
|
bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " ECC_TX_EN ,Enables the error correction code generation for the transmit header" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral" "Completed,Requested"
|
|
rbitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 4. " MODE ,Select mode" "Command,Video"
|
|
bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOURCE ,Selection of the source between OCP and the video port(s)" "Slave,Video"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_EN ,Enable virtual channel" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x50060000+0x100))&0x10)==0x00)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CSI2_VC_CTRL_2,Control Register"
|
|
bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or OCP slave data" "Continue,Start"
|
|
bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port." "Not inserted,Inserted"
|
|
newline
|
|
bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request" "DMA_req0,DMA_req1,DMA_req2,DMA_req3,No DMA req,?..."
|
|
bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request" "DMA_req0,DMA_req1,DMA_req2,DMA_req3,No DMA,?..."
|
|
rbitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
rbitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status" "Not full,Full"
|
|
newline
|
|
rbitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (Packets/BTA) are still being processed" "Not pending,Pending"
|
|
rbitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status" "Permitted,Not permitted"
|
|
newline
|
|
bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2" "Video port 1,Video port 2"
|
|
bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565" "MIPI DBI-2 spec,Video mode"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the OCP data bus" "16-bits,24-bits,2x16-bits,32-bits"
|
|
bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " ECC_TX_EN ,Enables the error correction code generation for the transmit header" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral" "Completed,Requested"
|
|
rbitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 4. " MODE ,Select mode" "Command,VP.STOLE"
|
|
bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOURCE ,Selection of the source between OCP and the video port(s)" "Slave,Video"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_EN ,Enable virtual channel" "Disabled,Enabled"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CSI2_VC_CTRL_2,Control Register"
|
|
bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or OCP slave data" "Continue,Start"
|
|
bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port." "Not inserted,Inserted"
|
|
newline
|
|
bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request" "DMA_req0,DMA_req1,DMA_req2,DMA_req3,No DMA req,?..."
|
|
bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request" "DMA_req0,DMA_req1,DMA_req2,DMA_req3,No DMA,?..."
|
|
rbitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
rbitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO Status" "Not full,Full"
|
|
newline
|
|
rbitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (Packets/BTA) are still being processed" "Not pending,Pending"
|
|
rbitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status" "Permitted,Not permitted"
|
|
newline
|
|
bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2" "Video port 1,Video port 2"
|
|
bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565" "MIPI DBI-2 spec,Video mode"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the OCP data bus" "16-bits,24-bits,2x16-bits,32-bits"
|
|
bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " ECC_TX_EN ,Enables the error correction code generation for the transmit header" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral" "Completed,Requested"
|
|
rbitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 4. " MODE ,Select mode" "Command,Video"
|
|
bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOURCE ,Selection of the source between OCP and the video port(s)" "Slave,Video"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_EN ,Enable virtual channel" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x50060000+0x100))&0x10)==0x00)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "CSI2_VC_CTRL_3,Control Register"
|
|
bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or OCP slave data" "Continue,Start"
|
|
bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port." "Not inserted,Inserted"
|
|
newline
|
|
bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request" "DMA_req0,DMA_req1,DMA_req2,DMA_req3,No DMA req,?..."
|
|
bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request" "DMA_req0,DMA_req1,DMA_req2,DMA_req3,No DMA,?..."
|
|
rbitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
rbitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status" "Not full,Full"
|
|
newline
|
|
rbitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (Packets/BTA) are still being processed" "Not pending,Pending"
|
|
rbitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status" "Permitted,Not permitted"
|
|
newline
|
|
bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2" "Video port 1,Video port 2"
|
|
bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565" "MIPI DBI-2 spec,Video mode"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the OCP data bus" "16-bits,24-bits,2x16-bits,32-bits"
|
|
bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " ECC_TX_EN ,Enables the error correction code generation for the transmit header" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral" "Completed,Requested"
|
|
rbitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 4. " MODE ,Select mode" "Command,VP.STOLE"
|
|
bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOURCE ,Selection of the source between OCP and the video port(s)" "Slave,Video"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_EN ,Enable virtual channel" "Disabled,Enabled"
|
|
else
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "CSI2_VC_CTRL_3,Control Register"
|
|
bitfld.long 0x00 31. " DCS_CMD_CODE ,DCS command code value to insert between header and video port or OCP slave data" "Continue,Start"
|
|
bitfld.long 0x00 30. " DCS_CMD_ENABLE ,Enables automatic insertion of DCS command codes when data is sourced by the video port." "Not inserted,Inserted"
|
|
newline
|
|
bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request" "DMA_req0,DMA_req1,DMA_req2,DMA_req3,No DMA req,?..."
|
|
bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request" "DMA_req0,DMA_req1,DMA_req2,DMA_req3,No DMA,?..."
|
|
rbitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
rbitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO Status" "Not full,Full"
|
|
newline
|
|
rbitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities (Packets/BTA) are still being processed" "Not pending,Pending"
|
|
rbitfld.long 0x00 14. " PP_BUSY ,Ping-pong buffer busy status" "Permitted,Not permitted"
|
|
newline
|
|
bitfld.long 0x00 13. " VP_SOURCE ,Selection between video port 1 and video port 2" "Video port 1,Video port 2"
|
|
bitfld.long 0x00 12. " RGB565_ORDER ,Byte order for RBG565" "MIPI DBI-2 spec,Video mode"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " OCP_DATA_BUS_WIDTH ,Defines the size of the OCP data bus" "16-bits,24-bits,2x16-bits,32-bits"
|
|
bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. " ECC_TX_EN ,Enables the error correction code generation for the transmit header" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral" "Completed,Requested"
|
|
rbitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x00 4. " MODE ,Select mode" "Command,Video"
|
|
bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after completion of each long packet transmission" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after completion of each short packet transmission" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOURCE ,Selection of the source between OCP and the video port(s)" "Slave,Video"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_EN ,Enable virtual channel" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "CSI2_VC_TE_0,Control Register"
|
|
bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer" "End,Start"
|
|
bitfld.long 0x00 30. " TE_EN ,Tearing effect control" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " TE_LINE ,TE_LINE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 cmos signals" "TE0,TE1"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "CSI2_VC_TE_1,Control Register"
|
|
bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer" "End,Start"
|
|
bitfld.long 0x00 30. " TE_EN ,Tearing effect control" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " TE_LINE ,TE_LINE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 cmos signals" "TE0,TE1"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CSI2_VC_TE_2,Control Register"
|
|
bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer" "End,Start"
|
|
bitfld.long 0x00 30. " TE_EN ,Tearing effect control" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " TE_LINE ,TE_LINE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 cmos signals" "TE0,TE1"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "CSI2_VC_TE_3,Control Register"
|
|
bitfld.long 0x00 31. " TE_START ,Manual control of the start of the transfer" "End,Start"
|
|
bitfld.long 0x00 30. " TE_EN ,Tearing effect control" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " TE_LINE ,TE_LINE" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. " TE_LINE_NB ,Selection between TE0 and TE1 cmos signals" "TE0,TE1"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TE_SIZE ,Defines the number of byte"
|
|
width 32.
|
|
newline
|
|
wgroup.long 0x108++0x03
|
|
line.long 0x00 "CSI2_VC_LONG_PACKET_HEADER_0,Long Packet Header Information"
|
|
wgroup.long 0x110++0x03
|
|
line.long 0x00 "CSI2_VC_LONG_PACKET_HEADER_1,Long Packet Header Information"
|
|
wgroup.long 0x118++0x03
|
|
line.long 0x00 "CSI2_VC_LONG_PACKET_HEADER_2,Long Packet Header Information"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "CSI2_VC_LONG_PACKET_HEADER_3,Long Packet Header Information"
|
|
wgroup.long 0x10C++0x03
|
|
line.long 0x00 "CSI2_VC_LONG_PACKET_PAYLOAD_0,CSI2 VC Long Packet Payload 0 Register"
|
|
wgroup.long 0x114++0x03
|
|
line.long 0x00 "CSI2_VC_LONG_PACKET_PAYLOAD_1,CSI2 VC Long Packet Payload 1 Register"
|
|
wgroup.long 0x11C++0x03
|
|
line.long 0x00 "CSI2_VC_LONG_PACKET_PAYLOAD_2,CSI2 VC Long Packet Payload 2 Register"
|
|
wgroup.long 0x124++0x03
|
|
line.long 0x00 "CSI2_VC_LONG_PACKET_PAYLOAD_3,CSI2 VC Long Packet Payload 3 Register"
|
|
wgroup.long 0x110++0x03
|
|
line.long 0x00 "CSI2_VC_SHORT_PACKET_HEADER_0,CSI2 VC Short Packet Header 0 Register"
|
|
wgroup.long 0x118++0x03
|
|
line.long 0x00 "CSI2_VC_SHORT_PACKET_HEADER_1,CSI2 VC Short Packet Header 1 Register"
|
|
wgroup.long 0x120++0x03
|
|
line.long 0x00 "CSI2_VC_SHORT_PACKET_HEADER_2,CSI2 VC Short Packet Header 2 Register"
|
|
wgroup.long 0x128++0x03
|
|
line.long 0x00 "CSI2_VC_SHORT_PACKET_HEADER_3,CSI2 VC Short Packet Header 3 Register"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "CSI2_VC_IRQSTATUS_0,Interrupt Status Register"
|
|
bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video port ping-pong buffer busy status" "False,True"
|
|
bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status" "False,True"
|
|
bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status" "False,True"
|
|
newline
|
|
bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status" "False,True"
|
|
bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status" "False,True"
|
|
bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status" "False,True"
|
|
newline
|
|
bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent" "False,True"
|
|
bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status" "False,True"
|
|
bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - Check-Sum mismatch status" "False,True"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CSI2_VC_IRQSTATUS_1,Interrupt Status Register"
|
|
bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video port ping-pong buffer busy status" "False,True"
|
|
bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status" "False,True"
|
|
bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status" "False,True"
|
|
newline
|
|
bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status" "False,True"
|
|
bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status" "False,True"
|
|
bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status" "False,True"
|
|
newline
|
|
bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent" "False,True"
|
|
bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status" "False,True"
|
|
bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - Check-Sum mismatch status" "False,True"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "CSI2_VC_IRQSTATUS_2,Interrupt Status Register"
|
|
bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video port ping-pong buffer busy status" "False,True"
|
|
bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status" "False,True"
|
|
bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status" "False,True"
|
|
newline
|
|
bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status" "False,True"
|
|
bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status" "False,True"
|
|
bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status" "False,True"
|
|
newline
|
|
bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent" "False,True"
|
|
bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status" "False,True"
|
|
bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - Check-Sum mismatch status" "False,True"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "CSI2_VC_IRQSTATUS_3,Interrupt Status Register"
|
|
bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ ,Video port ping-pong buffer busy status" "False,True"
|
|
bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status" "False,True"
|
|
bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status" "False,True"
|
|
newline
|
|
bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status" "False,True"
|
|
bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status" "False,True"
|
|
bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status" "False,True"
|
|
newline
|
|
bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent" "False,True"
|
|
bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status" "False,True"
|
|
bitfld.long 0x00 0. " CS_IRQ ,Virtual channel - Check-Sum mismatch status" "False,True"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "CSI2_VC_IRQENABLE_0,Interrupt Enable Register"
|
|
bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video port ping-pong buffer busy status" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow status" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel - BTA status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow error status" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow error status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - Check-Sum mismatch status" "Disabled,Enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CSI2_VC_IRQENABLE_1,Interrupt Enable Register"
|
|
bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video port ping-pong buffer busy status" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow status" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel - BTA status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow error status" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow error status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - Check-Sum mismatch status" "Disabled,Enabled"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "CSI2_VC_IRQENABLE_2,Interrupt Enable Register"
|
|
bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video port ping-pong buffer busy status" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow status" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel - BTA status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow error status" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow error status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - Check-Sum mismatch status" "Disabled,Enabled"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "CSI2_VC_IRQENABLE_3,Interrupt Enable Register"
|
|
bitfld.long 0x00 8. " PP_BUSY_CHANGE_IRQ_EN ,Video port ping-pong buffer busy status" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow status" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " BTA_IRQ_EN ,Virtual channel - BTA status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow error status" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow error status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ECC_CORRECTION_IRQ_EN ,Virtual channel - ECC has been used to do the correction of the only 1-bit error status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CS_IRQ_EN ,Virtual channel - Check-Sum mismatch status" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CSI2_PHY Registers"
|
|
base ad:0x50060200
|
|
width 12.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "REGISTER0,First Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " REG_THSPREPARE ,REG_THSPREPARE timing parameter in multiples of DDR clock period"
|
|
hexmask.long.byte 0x00 16.--23. 1. " REG_THSPRPR_THSZERO ,REG_THSPRPR_THSZERO timing parameter in multiples of DDR clock period"
|
|
hexmask.long.byte 0x00 8.--15. 1. " REG_THSTRAIL ,REG_THSTRAIL timing parameter in multiples of DDR clock period"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " REG_THSEXIT ,REG_THSEXIT timing parameter in multiples of DDR clock frequency"
|
|
line.long 0x04 "REGISTER1,Register 1"
|
|
bitfld.long 0x04 29.--31. " REG_TTAGO ,TTA-GO timing in terms of number of TXCLKESC clocks" "2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles"
|
|
bitfld.long 0x04 27.--28. " REG_TTASURE ,TTA-SURE timing in terms of number of TXCLKESC clocks" "2 cycles,,3 cycles,4 cycles"
|
|
bitfld.long 0x04 24.--26. " REG_TTAGET ,TTA-GET timing in terms of number of TXCLKESC clocks" "3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles"
|
|
newline
|
|
bitfld.long 0x04 16.--20. " REG_TLPXBY2 ,(TLPX)/2 timing parameter in multiples of DDR clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x04 8.--15. 1. " REG_TCLKTRAIL ,REG_TCLKTRAIL timing parameter in multiples of DDR clock frequency"
|
|
hexmask.long.byte 0x04 0.--7. 1. " REG_TCLKZERO ,REG_TCLKZERO timing parameter in multiples of DDR clock period"
|
|
line.long 0x08 "REGISTER2,Register 2"
|
|
hexmask.long.byte 0x08 24.--31. 1. " HSSYNCPATTERN ,Last received bit of sync pattern"
|
|
bitfld.long 0x08 23. " DATARATE ,Data rate" "Low,High"
|
|
bitfld.long 0x08 22. " OVRRDLPTXGZ ,Override with register" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 21. " REGLPTXGZ[4] ,Tri-stated" "Not tri-stated,Tri-stated"
|
|
bitfld.long 0x08 20. " REGLPTXGZ[3] ,Tri-stated" "Not tri-stated,Tri-stated"
|
|
bitfld.long 0x08 19. " REGLPTXGZ[2] ,Tri-stated" "Not tri-stated,Tri-stated"
|
|
newline
|
|
bitfld.long 0x08 18. " REGLPTXGZ[1] ,Tri-stated" "Not tri-stated,Tri-stated"
|
|
bitfld.long 0x08 17. " REGLPTXGZ[0] ,Tri-stated" "Not tri-stated,Tri-stated"
|
|
bitfld.long 0x08 16. " OVRRDULPMTX ,Override with register" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 15. " REGULPMTX[4] ,Transmit ULPM" "No,Yes"
|
|
bitfld.long 0x08 14. " REGULPMTX[3] ,Transmit ULPM" "No,Yes"
|
|
bitfld.long 0x08 13. " REGULPMTX[2] ,Transmit ULPM" "No,Yes"
|
|
newline
|
|
bitfld.long 0x08 12. " REGULPMTX[1] ,Transmit ULPM" "No,Yes"
|
|
bitfld.long 0x08 11. " REGULPMTX[0] ,Transmit ULPM" "No,Yes"
|
|
hexmask.long.byte 0x08 0.--7. 1. " REG_TCLKPREPARE ,D-PHY spec"
|
|
line.long 0x0C "REGISTER3,Register 3"
|
|
hexmask.long.byte 0x0C 24.--31. 1. " REG_TXTRIGGERESC3 ,Transmitted pattern when REG_TXTRIGGERESC3 is asserted"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " REG_TXTRIGGERESC2 ,Transmitted pattern when REG_TXTRIGGERESC2 is asserted"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " REG_TXTRIGGERESC1 ,Transmitted pattern when REG_TXTRIGGERESC1 is asserted"
|
|
newline
|
|
hexmask.long.byte 0x0C 0.--7. 1. " REG_TXTRIGGERESC0 ,Transmitted pattern when REG_TXTRIGGERESC0 is asserted"
|
|
line.long 0x10 "REGISTER4,Register 4"
|
|
hexmask.long.byte 0x10 24.--31. 1. " REG_RXTRIGGERESC3 ,Received pattern for which REG_RXTRIGGERESC3 is asserted"
|
|
hexmask.long.byte 0x10 16.--23. 1. " REG_RXTRIGGERESC2 ,Received pattern for which REG_RXTRIGGERESC2 is asserted"
|
|
hexmask.long.byte 0x10 8.--15. 1. " REG_RXTRIGGERESC1 ,Received pattern for which REG_RXTRIGGERESC1 is asserted"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. " REG_RXTRIGGERESC0 ,Received pattern for which REG_RXTRIGGERESC0 is asserted"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "REGISTER5,Register 5"
|
|
bitfld.long 0x00 31. " RESETDONETXBYTECLK ,RESETDONETXBYTECLK" "No reset,Reset"
|
|
bitfld.long 0x00 30. " RESETDONESCPCLK ,RESETDONESCPCLK" "No reset,Reset"
|
|
bitfld.long 0x00 29. " RESETDONEPWRCLK ,RESETDONEPWRCLK" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 28. " RESETDONETXCLKESC4 ,RESETDONETXCLKESC4" "No reset,Reset"
|
|
bitfld.long 0x00 27. " RESETDONETXCLKESC3 ,RESETDONETXCLKESC3" "No reset,Reset"
|
|
bitfld.long 0x00 26. " RESETDONETXCLKESC2 ,RESETDONETXCLKESC2" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 25. " RESETDONETXCLKESC1 ,RESETDONETXCLKESC1" "No reset,Reset"
|
|
bitfld.long 0x00 24. " RESETDONETXCLKESC0 ,RESETDONETXCLKESC0" "No reset,Reset"
|
|
group.long 0x18++0x27
|
|
line.long 0x00 "REGISTER6,Register 6"
|
|
bitfld.long 0x00 31. " OVRRDHSTXEN ,Override with register" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " REGHSTXEN[4] ,REGHSTXEN" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " REGHSTXEN[3] ,REGHSTXEN" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " REGHSTXEN[2] ,REGHSTXEN" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " REGHSTXEN[1] ,REGHSTXEN" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " REGHSTXEN[0] ,REGHSTXEN" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " OVRRDHSTXTERMEN ,Override with register" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " REGHSTXTERMEN[4] ,REGHSTXTERMEN" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " REGHSTXTERMEN[3] ,REGHSTXTERMEN" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " REGHSTXTERMEN[2] ,REGHSTXTERMEN" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " REGHSTXTERMEN[1] ,REGHSTXTERMEN" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " REGHSTXTERMEN[0] ,REGHSTXTERMEN" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " OVRRDCLKLANEADDR ,Override with register" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--18. " REGCLKLANEADDR ,Clock register lane address" ",Lane0,Lane1,Lane2,,Lane3,?..."
|
|
bitfld.long 0x00 15. " OVRRDDEEMPDISABLE ,Override with register" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " REGDEEMPDISABLE[4] ,Enable De-emphasis" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " REGDEEMPDISABLE[3] ,Enable De-emphasis" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " REGDEEMPDISABLE[2] ,Enable De-emphasis" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " REGDEEMPDISABLE[1] ,Enable De-emphasis" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " REGDEEMPDISABLE[0] ,Enable De-emphasis" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " OVRRDLPTXEN ,Override with register" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " REGLPTXEN[4] ,REGLPTXEN" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " REGLPTXEN[3] ,REGLPTXEN" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " REGLPTXEN[2] ,REGLPTXEN" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " REGLPTXEN[1] ,REGLPTXEN" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " REGLPTXEN[0] ,REGLPTXEN" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BYPASSCOMPFILT ,Bypass LP-RX and LP-CD with fast buffers" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 0. " BYPASSCOMP ,Bypass LP-RX and LP-CD comparator with fast buffers" "Not bypassed,Bypassed"
|
|
line.long 0x04 "REGISTER7,Register 7"
|
|
bitfld.long 0x04 31. " OVRRDLSTXEN ,Override with register" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " REGLSTXEN[4] ,REGLSTXEN" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " REGLSTXEN[3] ,REGLSTXEN" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 28. " REGLSTXEN[2] ,REGLSTXEN" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " REGLSTXEN[1] ,REGLSTXEN" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " REGLSTXEN[0] ,REGLSTXEN" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " OVRRDLSTXTERMEN ,Override with register" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " REGLSTXTERMEN[4] ,REGLSTXTERMEN" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " REGLSTXTERMEN[3] ,REGLSTXTERMEN" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 22. " REGLSTXTERMEN[2] ,REGLSTXTERMEN" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " REGLSTXTERMEN[1] ,REGLSTXTERMEN" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " REGLSTXTERMEN[0] ,REGLSTXTERMEN" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " OVRRDULPRXEN ,Override with register" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " REGULPRXEN[4] ,REGULPRXEN" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " REGULPRXEN[3] ,REGULPRXEN" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " REGULPRXEN[2] ,REGULPRXEN" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " REGULPRXEN[1] ,REGULPRXEN" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " REGULPRXEN[0] ,REGULPRXEN" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " OVRRDLDOVDDTRACKING ,Override with register" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " REGLDOVDDTRACKING ,Enable LDO tracking VDD" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " OVRRDHSLDOOBSERVE ,Override with register" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 10. " REGHSLDOOBSERVE ,Enable HS LDO observe" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " OVRRDBIASGENTRIMMODE ,Override with register" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " REGBIASGENTRIMMODE ,REGBIASGENTRIMMODE" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " OVRRDHSTXCOREEN ,Override with register" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " REGHSTXCOREEN[4] ,REGHSTXCOREEN" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " REGHSTXCOREEN[3] ,REGHSTXCOREEN" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " REGHSTXCOREEN[2] ,REGHSTXCOREEN" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " REGHSTXCOREEN[1] ,REGHSTXCOREEN" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " REGHSTXCOREEN[0] ,REGHSTXCOREEN" "Disabled,Enabled"
|
|
line.long 0x08 "REGISTER8,Register 8"
|
|
bitfld.long 0x08 11. " OVRRDHSTXTERMRES ,EFUS usage" "Use,Overridden"
|
|
bitfld.long 0x08 6.--10. " REGHSTXTERMRES ,Resistance value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 5. " OVRRDEFUSEBIASGEN ,EFUSE usage" "Use,Overridden"
|
|
newline
|
|
bitfld.long 0x08 0.--4. " BIASGENCODE ,Current value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "REGISTER9,Register 9"
|
|
bitfld.long 0x0C 31. " OVRRDPOLARITY ,Override with register" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " REGPOLARITY3TO0[4] ,Polarity" "DX=DP|DY=DN,DX=DN|DY=DP"
|
|
bitfld.long 0x0C 29. " REGPOLARITY3TO0[3] ,Polarity" "DX=DP|DY=DN,DX=DN|DY=DP"
|
|
newline
|
|
bitfld.long 0x0C 28. " REGPOLARITY3TO0[2] ,Polarity" "DX=DP|DY=DN,DX=DN|DY=DP"
|
|
bitfld.long 0x0C 27. " REGPOLARITY3TO0[1] ,Polarity" "DX=DP|DY=DN,DX=DN|DY=DP"
|
|
bitfld.long 0x0C 26. " REGPOLARITY3TO0[0] ,Polarity" "DX=DP|DY=DN,DX=DN|DY=DP"
|
|
newline
|
|
bitfld.long 0x0C 24. " OVRRDBIASGENEN ,Override with register" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " REGBIASGENEN ,REGBIASGENEN" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " OVRRDBANDGAPEN ,Override with register" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 21. " REGBANDGAPEN ,REGBANDGAPEN" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " ENBIASGENCURROUT ,Enable biasgen current (10uA) brought out" "Disabled,Enabled"
|
|
bitfld.long 0x0C 19. " ENLDOVOLTAGECONTROL ,Control LDO output voltage through register bits" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 15.--18. " REGLDOVOLTAGE ,Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 14. " ENBIASGENCONTROL ,Control Bias current through register bits" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12.--13. " REGBIASGENTESTMODES ,REGBIASGENTESTMODES" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 11. " ENVREGCONTROL ,Enable VREG control" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9.--10. " REGVREGLOAD ,REGVREGLOAD" "0,1,2,3"
|
|
bitfld.long 0x0C 7.--8. " REGVREGBIASCURR ,REGVREGBIASCURR" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0C 6. " ENLPTXIMPBYPASS ,LP-TX bypass controlled by register bit" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " REGLPTXIMPBYPASS ,Output impedance bypassed permanently" "Not bypassed,Bypassed"
|
|
bitfld.long 0x0C 4. " OVRRDCLKIN4DDRSIGNALS ,Override signals with register settings" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 3. " REGBYPASSEN ,BYPASSEN" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " REGCLKINEN ,CLKINEN" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " REGCLKIN4DDRGODDB ,CLKIN4DDRGOODBAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 0. " REGBYPASSACKZ ,BYPASSACKZ" "0,1"
|
|
line.long 0x10 "REGISTER10,Register 10"
|
|
bitfld.long 0x10 30.--31. " LDOWAKEUPTIME ,Set LPTX wakeup time counter in PWRCLK cycles or TXCLKESC cycles" "250,313,375,500"
|
|
bitfld.long 0x10 28.--29. " LPPOWERUPTIME ,LDO wakeup time counter in number of PWRCLK cycles" "12500,6250,31250,62500"
|
|
bitfld.long 0x10 27. " ENLPTXSCPDAT ,LPTX Data Taken from register" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 26. " DATA_DX4 ,Data for DX4" "0,1"
|
|
bitfld.long 0x10 25. " DATA_DY4 ,Data for DY4" "0,1"
|
|
bitfld.long 0x10 24. " DATA_DX3 ,Data for DX3" "0,1"
|
|
newline
|
|
bitfld.long 0x10 23. " DATA_DY3 ,Data for DY3" "0,1"
|
|
bitfld.long 0x10 22. " DATA_DX2 ,Data for DX2" "0,1"
|
|
bitfld.long 0x10 21. " DATA_DY2 ,Data for DY2" "0,1"
|
|
newline
|
|
bitfld.long 0x10 20. " DATA_DX1 ,Data for DX1" "0,1"
|
|
bitfld.long 0x10 19. " DATA_DY1 ,Data for DY1" "0,1"
|
|
bitfld.long 0x10 18. " DATA_DX0 ,Data for DX0" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. " DATA_DY0 ,Data for DY0" "0,1"
|
|
bitfld.long 0x10 16. " ENHSTXSCPDAT ,HS Data Taken from register" "Disabled,Enabled"
|
|
bitfld.long 0x10 15. " DATA_DY0 ,Data for D4" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14. " DATA_DY0 ,Data for D3" "0,1"
|
|
bitfld.long 0x10 13. " DATA_DY0 ,Data for D2" "0,1"
|
|
bitfld.long 0x10 12. " DATA_DY0 ,Data for D1" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. " DATA_DY0 ,Data for D0" "0,1"
|
|
bitfld.long 0x10 10. " OVRRDLDOEN ,Override with Register bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 9. " REGLDOEN[5] ,REGLDOEN" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 8. " REGLDOEN[4] ,REGLDOEN" "Disabled,Enabled"
|
|
bitfld.long 0x10 7. " REGLDOEN[3] ,REGLDOEN" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " REGLDOEN[2] ,REGLDOEN" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 5. " REGLDOEN[1] ,REGLDOEN" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " REGLDOEN[0] ,REGLDOEN" "Disabled,Enabled"
|
|
line.long 0x14 "REGISTER11,Register 11"
|
|
hexmask.long.byte 0x14 24.--31. 1. " LOOPBACKDATABYTE3 ,Fourth byte transmitted in loop-back mode"
|
|
hexmask.long.byte 0x14 16.--23. 1. " LOOPBACKDATABYTE2 ,Third byte transmitted in loop-back mode"
|
|
hexmask.long.byte 0x14 8.--15. 1. " LOOPBACKDATABYTE1 ,Second byte transmitted in loop-back mode"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. " LOOPBACKDATABYTE0 ,First byte transmitted in loop-back mode"
|
|
line.long 0x18 "REGISTER12,Register 12"
|
|
hexmask.long.byte 0x18 24.--31. 1. " TCLKPRE ,TCLK-PRE used in loop-back mode"
|
|
hexmask.long.byte 0x18 16.--23. 1. " TCLKPOST ,TCLK-POST used in loop-back mode"
|
|
bitfld.long 0x18 15. " OVRRDLANEENABLE ,OVRRDLANEENABLE" "0,1"
|
|
newline
|
|
bitfld.long 0x18 10.--14. " REGLANEENABLE ,REGLANEENABLE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x18 0.--7. 1. " BGTRIMBITS ,BGTRIMBITS"
|
|
line.long 0x1C "REGISTER13,Register 13"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. " ANALOGTESTMODES ,ANALOGTESTMODES"
|
|
line.long 0x20 "REGISTER14,Register 14"
|
|
bitfld.long 0x20 31. " OVRRDBGCONTROL ,Override bandgap control bits with register value" "Disabled,Enabled"
|
|
hexmask.long.word 0x20 23.--30. 1. " REGBGCONTROL ,REGBGCONTROL"
|
|
bitfld.long 0x20 22. " OVRRDHSDELAYCALIBEN ,Override with register bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 21. " REGHSDELAYCALIBEN ,REGHSDELAYCALIBEN" "Disabled,Enabled"
|
|
bitfld.long 0x20 20. " OVRRDHSDELAYCALIBCLRZ ,Override with register bit" "Disabled,Enabled"
|
|
bitfld.long 0x20 19. " REGHSDELAYCALIBCLRZ ,Disable clrz" "No,Yes"
|
|
newline
|
|
bitfld.long 0x20 18. " OVRRDHSTXDELAYMASTERCTRL ,Override with register bit" "Disabled,Enabled"
|
|
bitfld.long 0x20 14.--17. " REGHSTXDELAYMASTERCTRL ,REGHSTXDELAYMASTERCTRL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x20 13. " LPCDSAMPLEOUTEN ,Enable sampled data to be brought out on WPO pins" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 12. " LPRXSAMPLEOUTEN ,Enable sampled data to be brought out on WPO pins" "Disabled,Enabled"
|
|
bitfld.long 0x20 11. " OVRRDEFUSEBG ,Override EFUSE bits" "Disabled,Enabled"
|
|
bitfld.long 0x20 10. " OVRRDHSTXDELAYSLAVECTRL ,Override with register bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 6.--9. " REGHSTXDELAYSLAVECTRL ,REGHSTXDELAYSLAVECTRL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x24 "REGISTER15,Register 15"
|
|
bitfld.long 0x24 31. " OVRRDLDOHIZEN ,Override with register bit" "Disabled,Enabled"
|
|
bitfld.long 0x24 30. " REGLDOHIZEN[5] ,Enable LDO in Hiz Mode" "Disabled,Enabled"
|
|
bitfld.long 0x24 29. " REGLDOHIZEN[4] ,Enable LDO in Hiz Mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 28. " REGLDOHIZEN[3] ,Enable LDO in Hiz Mode" "Disabled,Enabled"
|
|
bitfld.long 0x24 27. " REGLDOHIZEN[2] ,Enable LDO in Hiz Mode" "Disabled,Enabled"
|
|
bitfld.long 0x24 26. " REGLDOHIZEN[1] ,Enable LDO in Hiz Mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 25. " REGLDOHIZEN[0] ,Enable LDO in Hiz Mode" "Disabled,Enabled"
|
|
bitfld.long 0x24 21.--24. " REG_THSTXEN ,REG_THSTXEN is timing parameter for HSTXEN deassertion staggering" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x24 8. " NOTRANSITIONDISABLE[4] ,NoTransition mode disable bit" "No,Yes"
|
|
newline
|
|
bitfld.long 0x24 7. " NOTRANSITIONDISABLE[3] ,NoTransition mode disable bit" "No,Yes"
|
|
bitfld.long 0x24 6. " NOTRANSITIONDISABLE[2] ,NoTransition mode disable bit" "No,Yes"
|
|
bitfld.long 0x24 5. " NOTRANSITIONDISABLE[1] ,NoTransition mode disable bit" "No,Yes"
|
|
newline
|
|
bitfld.long 0x24 4. " NOTRANSITIONDISABLE[0] ,NoTransition mode disable bit" "No,Yes"
|
|
bitfld.long 0x24 3. " OVRRDNOTRANSITIONCTRL ,Override with register bits" "Disabled,Enabled"
|
|
bitfld.long 0x24 0.--2. " REGNOTRANSITIONCTRL ,REGNOTRANSITIONCTRL" "0,1,2,3,4,5,6,7"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("AWR1443"))||(cpuis("AWR1443-CORE0"))||(cpuis("AWR1443-CORE1"))||cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
tree.open "HWA (Hardware Accelerator)"
|
|
tree "ACC_PARAM Registers"
|
|
base ad:0x50080000
|
|
width 11.
|
|
tree "PARAM1"
|
|
group.long 0x0++0x1F
|
|
line.long 0x00 "PARAM1_0,Parameter-Set 0 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM1_1,Parameter-Set 0 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM1_2,Parameter-Set 0 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM1_3,Parameter-Set 0 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM1_4,Parameter-Set 0 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM1_5,Parameter-Set 0 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM1_6,Parameter-Set 0 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM1_7,Parameter-Set 0 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM2"
|
|
group.long 0x20++0x1F
|
|
line.long 0x00 "PARAM2_0,Parameter-Set 1 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM2_1,Parameter-Set 1 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM2_2,Parameter-Set 1 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM2_3,Parameter-Set 1 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM2_4,Parameter-Set 1 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM2_5,Parameter-Set 1 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM2_6,Parameter-Set 1 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM2_7,Parameter-Set 1 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM3"
|
|
group.long 0x40++0x1F
|
|
line.long 0x00 "PARAM3_0,Parameter-Set 2 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM3_1,Parameter-Set 2 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM3_2,Parameter-Set 2 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM3_3,Parameter-Set 2 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM3_4,Parameter-Set 2 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM3_5,Parameter-Set 2 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM3_6,Parameter-Set 2 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM3_7,Parameter-Set 2 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM4"
|
|
group.long 0x60++0x1F
|
|
line.long 0x00 "PARAM4_0,Parameter-Set 3 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM4_1,Parameter-Set 3 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM4_2,Parameter-Set 3 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM4_3,Parameter-Set 3 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM4_4,Parameter-Set 3 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM4_5,Parameter-Set 3 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM4_6,Parameter-Set 3 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM4_7,Parameter-Set 3 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM5"
|
|
group.long 0x80++0x1F
|
|
line.long 0x00 "PARAM5_0,Parameter-Set 4 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM5_1,Parameter-Set 4 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM5_2,Parameter-Set 4 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM5_3,Parameter-Set 4 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM5_4,Parameter-Set 4 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM5_5,Parameter-Set 4 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM5_6,Parameter-Set 4 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM5_7,Parameter-Set 4 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM6"
|
|
group.long 0xA0++0x1F
|
|
line.long 0x00 "PARAM6_0,Parameter-Set 5 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM6_1,Parameter-Set 5 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM6_2,Parameter-Set 5 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM6_3,Parameter-Set 5 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM6_4,Parameter-Set 5 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM6_5,Parameter-Set 5 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM6_6,Parameter-Set 5 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM6_7,Parameter-Set 5 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM7"
|
|
group.long 0xC0++0x1F
|
|
line.long 0x00 "PARAM7_0,Parameter-Set 6 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM7_1,Parameter-Set 6 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM7_2,Parameter-Set 6 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM7_3,Parameter-Set 6 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM7_4,Parameter-Set 6 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM7_5,Parameter-Set 6 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM7_6,Parameter-Set 6 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM7_7,Parameter-Set 6 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM8"
|
|
group.long 0xE0++0x1F
|
|
line.long 0x00 "PARAM8_0,Parameter-Set 7 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM8_1,Parameter-Set 7 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM8_2,Parameter-Set 7 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM8_3,Parameter-Set 7 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM8_4,Parameter-Set 7 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM8_5,Parameter-Set 7 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM8_6,Parameter-Set 7 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM8_7,Parameter-Set 7 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM9"
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "PARAM9_0,Parameter-Set 8 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM9_1,Parameter-Set 8 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM9_2,Parameter-Set 8 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM9_3,Parameter-Set 8 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM9_4,Parameter-Set 8 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM9_5,Parameter-Set 8 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM9_6,Parameter-Set 8 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM9_7,Parameter-Set 8 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM10"
|
|
group.long 0x120++0x1F
|
|
line.long 0x00 "PARAM10_0,Parameter-Set 9 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM10_1,Parameter-Set 9 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM10_2,Parameter-Set 9 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM10_3,Parameter-Set 9 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM10_4,Parameter-Set 9 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM10_5,Parameter-Set 9 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM10_6,Parameter-Set 9 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM10_7,Parameter-Set 9 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM11"
|
|
group.long 0x140++0x1F
|
|
line.long 0x00 "PARAM11_0,Parameter-Set 10 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM11_1,Parameter-Set 10 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM11_2,Parameter-Set 10 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM11_3,Parameter-Set 10 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM11_4,Parameter-Set 10 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM11_5,Parameter-Set 10 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM11_6,Parameter-Set 10 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM11_7,Parameter-Set 10 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM12"
|
|
group.long 0x160++0x1F
|
|
line.long 0x00 "PARAM12_0,Parameter-Set 11 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM12_1,Parameter-Set 11 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM12_2,Parameter-Set 11 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM12_3,Parameter-Set 11 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM12_4,Parameter-Set 11 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM12_5,Parameter-Set 11 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM12_6,Parameter-Set 11 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM12_7,Parameter-Set 11 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM13"
|
|
group.long 0x180++0x1F
|
|
line.long 0x00 "PARAM13_0,Parameter-Set 12 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM13_1,Parameter-Set 12 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM13_2,Parameter-Set 12 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM13_3,Parameter-Set 12 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM13_4,Parameter-Set 12 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM13_5,Parameter-Set 12 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM13_6,Parameter-Set 12 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM13_7,Parameter-Set 12 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM14"
|
|
group.long 0x1A0++0x1F
|
|
line.long 0x00 "PARAM14_0,Parameter-Set 13 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM14_1,Parameter-Set 13 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM14_2,Parameter-Set 13 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM14_3,Parameter-Set 13 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM14_4,Parameter-Set 13 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM14_5,Parameter-Set 13 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM14_6,Parameter-Set 13 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM14_7,Parameter-Set 13 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM15"
|
|
group.long 0x1C0++0x1F
|
|
line.long 0x00 "PARAM15_0,Parameter-Set 14 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM15_1,Parameter-Set 14 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM15_2,Parameter-Set 14 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM15_3,Parameter-Set 14 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM15_4,Parameter-Set 14 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM15_5,Parameter-Set 14 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM15_6,Parameter-Set 14 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM15_7,Parameter-Set 14 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM16"
|
|
group.long 0x1E0++0x1F
|
|
line.long 0x00 "PARAM16_0,Parameter-Set 15 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM16_1,Parameter-Set 15 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM16_2,Parameter-Set 15 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM16_3,Parameter-Set 15 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM16_4,Parameter-Set 15 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM16_5,Parameter-Set 15 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM16_6,Parameter-Set 15 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM16_7,Parameter-Set 15 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "ACC_STATIC Registers"
|
|
base ad:0x50080800
|
|
width 16.
|
|
group.long 0x00++0x3F
|
|
line.long 0x00 "HWACCREG1,Hardware Accelerator Register 1"
|
|
bitfld.long 0x00 28. " FFT1DEN ,FFT1DEN" "0,1"
|
|
bitfld.long 0x00 24.--27. " PARAMSTOP ,PARAMSTOP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " PARAMSTART ,PARAMSTART" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 8.--19. 1. " NLOOPS ,NLOOPS"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " ACCRESET ,Reset" "0,1,2,3,4,5,6,Reset"
|
|
bitfld.long 0x00 3. " ACCCLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " ACCENABLE ,ACCENABLE" "Disabled,,,,,,,Enabled"
|
|
line.long 0x04 "HWACCREG2,Hardware Accelerator Register 2"
|
|
bitfld.long 0x04 15. " DMA2ACCTRIG[15] ,DMA channel 15 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 14. " [14] ,DMA channel 14 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 13. " [13] ,DMA channel 13 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 12. " [12] ,DMA channel 12 completion indication" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,DMA channel 11 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 10. " [10] ,DMA channel 10 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 9. " [9] ,DMA channel 9 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 8. " [8] ,DMA channel 8 completion indication" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,DMA channel 7 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 6. " [6] ,DMA channel 6 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 5. " [5] ,DMA channel 5 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 4. " [4] ,DMA channel 4 completion indication" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,DMA channel 3 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 2. " [2] ,DMA channel 2 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 1. " [1] ,DMA channel 1 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 0. " [0] ,DMA channel 0 completion indication" "Not completed,Completed"
|
|
line.long 0x08 "HWACCREG3,Hardware Accelerator Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " CR42DMATRIG ,Trigger from CR4 to DMA"
|
|
bitfld.long 0x08 0. " CR42ACCTRIG ,Trigger from CR4 to accelerator" "Not triggered,Triggered"
|
|
line.long 0x0C "HWACCREG4,Hardware Accelerator Register 4"
|
|
hexmask.long.word 0x0C 16.--31. 1. " PARAMDONECLR ,Clear from CR4"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PARAMDONESTAT ,Status to CR4"
|
|
line.long 0x10 "HWACCREG5,Hardware Accelerator Register 5"
|
|
line.long 0x14 "HWACCREG6,Hardware Accelerator Register 6"
|
|
line.long 0x18 "HWACCREG7,Hardware Accelerator Register 7"
|
|
bitfld.long 0x18 24. " STG1LUTSELWR ,Bus matrix write function select" "Window LUT,FFT 1st stage RAM"
|
|
bitfld.long 0x18 16. " DITHERTWIDEN ,DITHERTWIDEN" "0,1"
|
|
hexmask.long.word 0x18 0.--9. 1. " BPMRATE ,BPMRATE"
|
|
line.long 0x1C "HWACCREG8,Hardware Accelerator Register 8"
|
|
bitfld.long 0x1C 24.--28. " FFTSUMDIV ,FFTSUMDIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. " INTERFTHRESH ,INTERFTHRESH"
|
|
line.long 0x20 "HWACCREG9,Hardware Accelerator Register 9"
|
|
hexmask.long.tbyte 0x20 0.--20. 1. " ICMULTSCALE ,ICMULTSCALE"
|
|
line.long 0x24 "HWACCREG10,Hardware Accelerator Register 10"
|
|
hexmask.long.tbyte 0x24 0.--20. 1. " QCMULTSCALE ,QCMULTSCALE"
|
|
line.long 0x28 "HWACCREG11,Hardware Accelerator Register 11"
|
|
bitfld.long 0x28 31. " LFSRLOAD ,LFSRLOAD" "0,1"
|
|
hexmask.long 0x28 0.--28. 1. " LFSRSEED ,LFSRSEED"
|
|
line.long 0x2C "HWACCREG12,Hardware Accelerator Register 12"
|
|
bitfld.long 0x2C 24. " ACC_TRIGGER_IN_CLR ,ACC_TRIGGER_IN_CLR" "0,1"
|
|
hexmask.long.tbyte 0x2C 0.--18. 1. " ACC_TRIGGER_IN_STAT ,ACC_TRIGGER_IN_STAT"
|
|
line.long 0x30 "HWACCREG13,Hardware Accelerator Register 13"
|
|
hexmask.long.tbyte 0x30 0.--17. 1. " CFAR_THRESH ,CFAR threshold"
|
|
line.long 0x34 "HWACCREG14,Hardware Accelerator Register 14"
|
|
bitfld.long 0x34 8.--10. " OUTRAMAONIN ,Two output RAMS array control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 4.--6. " OUTRAMAGOODIN ,Two output RAMS array control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 0.--2. " OUTRAMISO ,Two output RAMS isolation control" "0,1,2,3,4,5,6,7"
|
|
line.long 0x38 "HWACCREG15,Hardware Accelerator Register 15"
|
|
line.long 0x3C "HWACCREG16,Hardware Accelerator Register 16"
|
|
rgroup.long 0x40++0x17
|
|
line.long 0x00 "MAX1VALUE,Max 1 Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " MAX1VALUE ,MAX1VALUE"
|
|
line.long 0x04 "MAX1INDEX,Max 1 Index Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " MAX1INDEX ,MAX1INDEX"
|
|
line.long 0x08 "ISUM1LSB,ISUM1LSB Register"
|
|
line.long 0x0C "ISUM1MSB,ISUM1MSB Register"
|
|
bitfld.long 0x0C 0.--3. " ISUM1MSB ,ISUM1MSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "QSUM1LSB,QSUM1LSB Register"
|
|
line.long 0x14 "QSUM1MSB,QSUM1MSB Register"
|
|
bitfld.long 0x14 0.--3. " QSUM1MSB ,QSUM1MSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x58++0x17
|
|
line.long 0x00 "MAX2VALUE,Max 2 Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " MAX2VALUE ,MAX2VALUE"
|
|
line.long 0x04 "MAX2INDEX,Max 2 Index Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " MAX2INDEX ,MAX2INDEX"
|
|
line.long 0x08 "ISUM2LSB,ISUM2LSB Register"
|
|
line.long 0x0C "ISUM2MSB,ISUM2MSB Register"
|
|
bitfld.long 0x0C 0.--3. " ISUM2MSB ,ISUM2MSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "QSUM2LSB,QSUM2LSB Register"
|
|
line.long 0x14 "QSUM2MSB,QSUM2MSB Register"
|
|
bitfld.long 0x14 0.--3. " QSUM2MSB ,QSUM2MSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x70++0x17
|
|
line.long 0x00 "MAX3VALUE,Max 3 Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " MAX3VALUE ,MAX3VALUE"
|
|
line.long 0x04 "MAX3INDEX,Max 3 Index Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " MAX3INDEX ,MAX3INDEX"
|
|
line.long 0x08 "ISUM3LSB,ISUM3LSB Register"
|
|
line.long 0x0C "ISUM3MSB,ISUM3MSB Register"
|
|
bitfld.long 0x0C 0.--3. " ISUM3MSB ,ISUM3MSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "QSUM3LSB,QSUM3LSB Register"
|
|
line.long 0x14 "QSUM3MSB,QSUM3MSB Register"
|
|
bitfld.long 0x14 0.--3. " QSUM3MSB ,QSUM3MSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x88++0x17
|
|
line.long 0x00 "MAX4VALUE,Max 4 Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " MAX4VALUE ,MAX4VALUE"
|
|
line.long 0x04 "MAX4INDEX,Max 4 Index Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " MAX4INDEX ,MAX4INDEX"
|
|
line.long 0x08 "ISUM4LSB,ISUM4LSB Register"
|
|
line.long 0x0C "ISUM4MSB,ISUM4MSB Register"
|
|
bitfld.long 0x0C 0.--3. " ISUM4MSB ,ISUM4MSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "QSUM4LSB,QSUM4LSB Register"
|
|
line.long 0x14 "QSUM4MSB,QSUM4MSB Register"
|
|
bitfld.long 0x14 0.--3. " QSUM4MSB ,QSUM4MSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xA0++0x0B
|
|
line.long 0x00 "DCOFFSETI,DCOFFSETI Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 0x01 " DCOFFSETI ,DCOFFSETI"
|
|
line.long 0x04 "DCOFFSETQ,DCOFFSETQ Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 0x01 " DCOFFSETQ ,DCOFFSETQ"
|
|
line.long 0x08 "CFARTEST,CFARTEST Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CFARTEST ,CFARTEST"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "RDSTATUS,RDSTATUS Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " LOOPCNT ,LOOPCNT"
|
|
hexmask.long.byte 0x00 0.--3. 0x01 " PARAMADDR ,PARAMADDR"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "SIGDMACH1DONE,SIGDMACH1DONE Register"
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "SIGDMACH2DONE,SIGDMACH2DONE Register"
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "SIGDMACH3DONE,SIGDMACH3DONE Register"
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "SIGDMACH4DONE,SIGDMACH4DONE Register"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "SIGDMACH5DONE,SIGDMACH5DONE Register"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "SIGDMACH6DONE,SIGDMACH6DONE Register"
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "SIGDMACH7DONE,SIGDMACH7DONE Register"
|
|
rgroup.long 0xCC++0x03
|
|
line.long 0x00 "SIGDMACH8DONE,SIGDMACH8DONE Register"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "SIGDMACH9DONE,SIGDMACH9DONE Register"
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "SIGDMACH10DONE,SIGDMACH10DONE Register"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "SIGDMACH11DONE,SIGDMACH11DONE Register"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "SIGDMACH12DONE,SIGDMACH12DONE Register"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "SIGDMACH13DONE,SIGDMACH13DONE Register"
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "SIGDMACH14DONE,SIGDMACH14DONE Register"
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "SIGDMACH15DONE,SIGDMACH15DONE Register"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "SIGDMACH16DONE,SIGDMACH16DONE Register"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "MEMACCESSERR,MEMACCESSERR Register"
|
|
rbitfld.long 0x00 16.--19. " STATERRCODE ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--11. 1. " ERRCODEMASK ,Mask for STATERRCODE"
|
|
rbitfld.long 0x00 0.--3. " ERRCODECLR ,Error code clear" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xF4++0x13
|
|
line.long 0x00 "FFTCLIP,FFTCLIP Register"
|
|
bitfld.long 0x00 16. " CLRFFTCLIPSTAT ,CLRFFTCLIPSTAT" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. " FFTCLCIPSTAT ,FFTCLCIPSTAT"
|
|
line.long 0x04 "FFTPEAKCNT,FFTPEAKCNT Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " FFTPEAKCNT ,FFTPEAKCNT"
|
|
line.long 0x08 "HWACCREG1RD,HWACCREG1RD Register"
|
|
line.long 0x0C "HWACCREG2RD,HWACCREG2RD Register"
|
|
line.long 0x10 "HWACCREG3RD,HWACCREG3RD Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.open "RTI (Real Time Interrupt)"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
tree "WDT/RTI1"
|
|
base ad:0x50020000
|
|
width 19.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "RTIGCTRL,RTI Global Control Register"
|
|
bitfld.long 0x00 16.--19. " NTUSEL ,Select NTU signal" "NTU0,,,,,NTU1,,,,,NTU2,,,,,NTU3"
|
|
bitfld.long 0x00 15. " COS ,Continue on suspend" "Stopped,Running"
|
|
bitfld.long 0x00 1. " CNT1EN ,Counter 1 enable" "Stopped,Running"
|
|
bitfld.long 0x00 0. " CNT0EN ,Counter 0 enable" "Stopped,Running"
|
|
line.long 0x04 "RTITBCTRL,RTI Timebase Control Register"
|
|
bitfld.long 0x04 1. " INC ,Increment free running counter 0" "Not incremented,Incremented"
|
|
bitfld.long 0x04 0. " TBEXT ,Timebase external" "RTIUC0,NTU"
|
|
line.long 0x08 "RTICAPCTRL,RTI Capture Control Register"
|
|
bitfld.long 0x08 1. " CAPCNTR1 ,Capture counter 1" "Source 0,Source 1"
|
|
bitfld.long 0x08 0. " CAPCNTR0 ,Capture counter 0" "Source 0,Source 1"
|
|
line.long 0x0C "RTICOMPCTRL,RTI Compare Control Register"
|
|
bitfld.long 0x0C 12. " COMPSEL3 ,Compare select 3" "RTIFRC0,RTIFRC1"
|
|
bitfld.long 0x0C 8. " COMPSEL2 ,Compare select 2" "RTIFRC0,RTIFRC1"
|
|
bitfld.long 0x0C 4. " COMPSEL1 ,Compare select 1" "RTIFRC0,RTIFRC1"
|
|
bitfld.long 0x0C 0. " COMPSEL0 ,Compare select 0" "RTIFRC0,RTIFRC1"
|
|
line.long 0x10 "RTIFRC0,RTI Free Running Counter 0 Register"
|
|
line.long 0x14 "RTIUC0,RTI Up Counter 0 Register"
|
|
line.long 0x18 "RTICPUC0,RTI Compare Up Counter 0 Register"
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RTICAFRC0,RTI Capture Free Running Counter 0 Register"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RTICAUC0,RTI Capture Up Counter 0 Register"
|
|
in
|
|
newline
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "RTIFRC1,RTI Free Running Counter 1 Register"
|
|
line.long 0x04 "RTIUC1,RTI Up Counter 1 Register"
|
|
line.long 0x08 "RTICPUC1,RTI Compare Up Counter 1 Register"
|
|
newline
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "RTICAFRC1,RTI Capture Free Running Counter 1 Register"
|
|
in
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "RTICAUC1,RTI Capture Up Counter 1 Register"
|
|
in
|
|
newline
|
|
group.long 0x50++0x27
|
|
line.long 0x00 "RTICOMP0,RTI Compare 0 Register"
|
|
line.long 0x04 "RTIUDCP0,RTI Update Compare 0 Register"
|
|
line.long 0x08 "RTICOMP1,RTI Compare 1 Register"
|
|
line.long 0x0C "RTIUDCP1,RTI Update Compare 1 Register"
|
|
line.long 0x10 "RTICOMP2,RTI Compare 2 Register"
|
|
line.long 0x14 "RTIUDCP2,RTI Update Compare 2 Register"
|
|
line.long 0x18 "RTICOMP3,RTI Compare 3 Register"
|
|
line.long 0x1C "RTIUDCP3,RTI Update Compare 3 Register"
|
|
line.long 0x20 "RTITBLCOMP,RTI Timebase Low Compare Register"
|
|
line.long 0x24 "RTITBHCOMP,RTI Timebase High Compare Register"
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "RTISETINTENA,RTI Set Interrupt Enable Register"
|
|
bitfld.long 0x00 11. " SETDMA3 ,Set compare DMA request 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " SETDMA2 ,Set compare DMA request 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " SETDMA1 ,Set compare DMA request 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SETDMA0 ,Set compare DMA request 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "RTICLEARINTENA,RTI Clear Interrupt Enable Register"
|
|
eventfld.long 0x04 11. " CLEARDMA3 ,Clear compare DMA request 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 10. " CLEARDMA2 ,Clear compare DMA request 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 9. " CLEARDMA1 ,Clear compare DMA request 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 8. " CLEARDMA0 ,Clear compare DMA request 0" "No interrupt,Interrupt"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RTIINTENA_SET/CLR,RTI Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " OVL1INT ,Free running counter 1 overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " OVL0INT ,Free running counter 1 overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " TBINT ,Timebase interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INT3 ,Compare interrupt 3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " INT2 ,Compare interrupt 2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " INT1 ,Compare interrupt 1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " INT0 ,Compare interrupt 0" "No interrupt,Interrupt"
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Register"
|
|
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DWDPRLD ,Digital watchdog preload value"
|
|
line.long 0x08 "RTIWDSTATUS,Watchdog Status Register"
|
|
eventfld.long 0x08 5. " DWWD_ST ,Windowed watchdog status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 4. " END_TIME_VIOL ,Windowed watchdog end time violation status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 3. " START_TIME_VIOL ,Windowed watchdog start time violation status" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 2. " KEY_ST ,Watchdog key status" "No wrong key,Wrong key"
|
|
eventfld.long 0x08 1. " DWD_ST ,DWD status" "No reset,Reset"
|
|
line.long 0x0C "RTIWDKEY,RTI Watchdog Key Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " WDKEY ,Watchdog key"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "RTIDWDCNTR,RTI Digital Watchdog Down Counter Register"
|
|
hexmask.long 0x00 0.--24. 1. " DWDCNTR ,DWD down counter"
|
|
group.long 0xA4++0x1B
|
|
line.long 0x00 "RTIWWDRXNCTRL,Digital Windowed Watchdog Reaction Control Register"
|
|
bitfld.long 0x00 0.--3. " WWDRXN ,The DWWD reaction" "Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Non-maskable interrupt,Reset,Reset,Reset,Reset,Reset"
|
|
line.long 0x04 "RTIWWDSIZECTRL,Digital Windowed Watchdog Window Size Control Register"
|
|
line.long 0x08 "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable Register"
|
|
bitfld.long 0x08 24.--27. " INTCLRENABLE3 ,Enable the auto-clear functionality on the compare 3 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 16.--19. " INTCLRENABLE2 ,Enable the auto-clear functionality on the compare 2 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 8.--11. " INTCLRENABLE1 ,Enable the auto-clear functionality on the compare 1 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 0.--3. " INTCLRENABLE0 ,Enable the auto-clear functionality on the compare 0 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x0C "RTICOMP0CLR,RTI Compare 0 Clear Register"
|
|
line.long 0x10 "RTICOMP1CLR,RTI Compare 1 Clear Register"
|
|
line.long 0x14 "RTICOMP2CLR,RTI Compare 2 Clear Register"
|
|
line.long 0x18 "RTICOMP3CLR,RTI Compare 3 Clear Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTI2"
|
|
base ad:0x500F0000
|
|
width 19.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "RTIGCTRL,RTI Global Control Register"
|
|
bitfld.long 0x00 16.--19. " NTUSEL ,Select NTU signal" "NTU0,,,,,NTU1,,,,,NTU2,,,,,NTU3"
|
|
bitfld.long 0x00 15. " COS ,Continue on suspend" "Stopped,Running"
|
|
bitfld.long 0x00 1. " CNT1EN ,Counter 1 enable" "Stopped,Running"
|
|
bitfld.long 0x00 0. " CNT0EN ,Counter 0 enable" "Stopped,Running"
|
|
line.long 0x04 "RTITBCTRL,RTI Timebase Control Register"
|
|
bitfld.long 0x04 1. " INC ,Increment free running counter 0" "Not incremented,Incremented"
|
|
bitfld.long 0x04 0. " TBEXT ,Timebase external" "RTIUC0,NTU"
|
|
line.long 0x08 "RTICAPCTRL,RTI Capture Control Register"
|
|
bitfld.long 0x08 1. " CAPCNTR1 ,Capture counter 1" "Source 0,Source 1"
|
|
bitfld.long 0x08 0. " CAPCNTR0 ,Capture counter 0" "Source 0,Source 1"
|
|
line.long 0x0C "RTICOMPCTRL,RTI Compare Control Register"
|
|
bitfld.long 0x0C 12. " COMPSEL3 ,Compare select 3" "RTIFRC0,RTIFRC1"
|
|
bitfld.long 0x0C 8. " COMPSEL2 ,Compare select 2" "RTIFRC0,RTIFRC1"
|
|
bitfld.long 0x0C 4. " COMPSEL1 ,Compare select 1" "RTIFRC0,RTIFRC1"
|
|
bitfld.long 0x0C 0. " COMPSEL0 ,Compare select 0" "RTIFRC0,RTIFRC1"
|
|
line.long 0x10 "RTIFRC0,RTI Free Running Counter 0 Register"
|
|
line.long 0x14 "RTIUC0,RTI Up Counter 0 Register"
|
|
line.long 0x18 "RTICPUC0,RTI Compare Up Counter 0 Register"
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RTICAFRC0,RTI Capture Free Running Counter 0 Register"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RTICAUC0,RTI Capture Up Counter 0 Register"
|
|
in
|
|
newline
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "RTIFRC1,RTI Free Running Counter 1 Register"
|
|
line.long 0x04 "RTIUC1,RTI Up Counter 1 Register"
|
|
line.long 0x08 "RTICPUC1,RTI Compare Up Counter 1 Register"
|
|
newline
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "RTICAFRC1,RTI Capture Free Running Counter 1 Register"
|
|
in
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "RTICAUC1,RTI Capture Up Counter 1 Register"
|
|
in
|
|
newline
|
|
group.long 0x50++0x27
|
|
line.long 0x00 "RTICOMP0,RTI Compare 0 Register"
|
|
line.long 0x04 "RTIUDCP0,RTI Update Compare 0 Register"
|
|
line.long 0x08 "RTICOMP1,RTI Compare 1 Register"
|
|
line.long 0x0C "RTIUDCP1,RTI Update Compare 1 Register"
|
|
line.long 0x10 "RTICOMP2,RTI Compare 2 Register"
|
|
line.long 0x14 "RTIUDCP2,RTI Update Compare 2 Register"
|
|
line.long 0x18 "RTICOMP3,RTI Compare 3 Register"
|
|
line.long 0x1C "RTIUDCP3,RTI Update Compare 3 Register"
|
|
line.long 0x20 "RTITBLCOMP,RTI Timebase Low Compare Register"
|
|
line.long 0x24 "RTITBHCOMP,RTI Timebase High Compare Register"
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "RTISETINTENA,RTI Set Interrupt Enable Register"
|
|
bitfld.long 0x00 11. " SETDMA3 ,Set compare DMA request 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " SETDMA2 ,Set compare DMA request 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " SETDMA1 ,Set compare DMA request 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SETDMA0 ,Set compare DMA request 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "RTICLEARINTENA,RTI Clear Interrupt Enable Register"
|
|
eventfld.long 0x04 11. " CLEARDMA3 ,Clear compare DMA request 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 10. " CLEARDMA2 ,Clear compare DMA request 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 9. " CLEARDMA1 ,Clear compare DMA request 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 8. " CLEARDMA0 ,Clear compare DMA request 0" "No interrupt,Interrupt"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RTIINTENA_SET/CLR,RTI Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " OVL1INT ,Free running counter 1 overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " OVL0INT ,Free running counter 1 overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " TBINT ,Timebase interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INT3 ,Compare interrupt 3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " INT2 ,Compare interrupt 2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " INT1 ,Compare interrupt 1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " INT0 ,Compare interrupt 0" "No interrupt,Interrupt"
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Register"
|
|
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DWDPRLD ,Digital watchdog preload value"
|
|
line.long 0x08 "RTIWDSTATUS,Watchdog Status Register"
|
|
eventfld.long 0x08 5. " DWWD_ST ,Windowed watchdog status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 4. " END_TIME_VIOL ,Windowed watchdog end time violation status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 3. " START_TIME_VIOL ,Windowed watchdog start time violation status" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 2. " KEY_ST ,Watchdog key status" "No wrong key,Wrong key"
|
|
eventfld.long 0x08 1. " DWD_ST ,DWD status" "No reset,Reset"
|
|
line.long 0x0C "RTIWDKEY,RTI Watchdog Key Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " WDKEY ,Watchdog key"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "RTIDWDCNTR,RTI Digital Watchdog Down Counter Register"
|
|
hexmask.long 0x00 0.--24. 1. " DWDCNTR ,DWD down counter"
|
|
group.long 0xA4++0x1B
|
|
line.long 0x00 "RTIWWDRXNCTRL,Digital Windowed Watchdog Reaction Control Register"
|
|
bitfld.long 0x00 0.--3. " WWDRXN ,The DWWD reaction" "Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Non-maskable interrupt,Reset,Reset,Reset,Reset,Reset"
|
|
line.long 0x04 "RTIWWDSIZECTRL,Digital Windowed Watchdog Window Size Control Register"
|
|
line.long 0x08 "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable Register"
|
|
bitfld.long 0x08 24.--27. " INTCLRENABLE3 ,Enable the auto-clear functionality on the compare 3 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 16.--19. " INTCLRENABLE2 ,Enable the auto-clear functionality on the compare 2 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 8.--11. " INTCLRENABLE1 ,Enable the auto-clear functionality on the compare 1 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 0.--3. " INTCLRENABLE0 ,Enable the auto-clear functionality on the compare 0 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x0C "RTICOMP0CLR,RTI Compare 0 Clear Register"
|
|
line.long 0x10 "RTICOMP1CLR,RTI Compare 1 Clear Register"
|
|
line.long 0x14 "RTICOMP2CLR,RTI Compare 2 Clear Register"
|
|
line.long 0x18 "RTICOMP3CLR,RTI Compare 3 Clear Register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "RTI-A"
|
|
base ad:0xFFFFFC00
|
|
width 19.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "RTIGCTRL,RTI Global Control Register"
|
|
bitfld.long 0x00 16.--19. " NTUSEL ,Select NTU signal" "NTU0,,,,,NTU1,,,,,NTU2,,,,,NTU3"
|
|
bitfld.long 0x00 15. " COS ,Continue on suspend" "Stopped,Running"
|
|
bitfld.long 0x00 1. " CNT1EN ,Counter 1 enable" "Stopped,Running"
|
|
bitfld.long 0x00 0. " CNT0EN ,Counter 0 enable" "Stopped,Running"
|
|
line.long 0x04 "RTITBCTRL,RTI Timebase Control Register"
|
|
bitfld.long 0x04 1. " INC ,Increment free running counter 0" "Not incremented,Incremented"
|
|
bitfld.long 0x04 0. " TBEXT ,Timebase external" "RTIUC0,NTU"
|
|
line.long 0x08 "RTICAPCTRL,RTI Capture Control Register"
|
|
bitfld.long 0x08 1. " CAPCNTR1 ,Capture counter 1" "Source 0,Source 1"
|
|
bitfld.long 0x08 0. " CAPCNTR0 ,Capture counter 0" "Source 0,Source 1"
|
|
line.long 0x0C "RTICOMPCTRL,RTI Compare Control Register"
|
|
bitfld.long 0x0C 12. " COMPSEL3 ,Compare select 3" "RTIFRC0,RTIFRC1"
|
|
bitfld.long 0x0C 8. " COMPSEL2 ,Compare select 2" "RTIFRC0,RTIFRC1"
|
|
bitfld.long 0x0C 4. " COMPSEL1 ,Compare select 1" "RTIFRC0,RTIFRC1"
|
|
bitfld.long 0x0C 0. " COMPSEL0 ,Compare select 0" "RTIFRC0,RTIFRC1"
|
|
line.long 0x10 "RTIFRC0,RTI Free Running Counter 0 Register"
|
|
line.long 0x14 "RTIUC0,RTI Up Counter 0 Register"
|
|
line.long 0x18 "RTICPUC0,RTI Compare Up Counter 0 Register"
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RTICAFRC0,RTI Capture Free Running Counter 0 Register"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RTICAUC0,RTI Capture Up Counter 0 Register"
|
|
in
|
|
newline
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "RTIFRC1,RTI Free Running Counter 1 Register"
|
|
line.long 0x04 "RTIUC1,RTI Up Counter 1 Register"
|
|
line.long 0x08 "RTICPUC1,RTI Compare Up Counter 1 Register"
|
|
newline
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "RTICAFRC1,RTI Capture Free Running Counter 1 Register"
|
|
in
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "RTICAUC1,RTI Capture Up Counter 1 Register"
|
|
in
|
|
newline
|
|
group.long 0x50++0x27
|
|
line.long 0x00 "RTICOMP0,RTI Compare 0 Register"
|
|
line.long 0x04 "RTIUDCP0,RTI Update Compare 0 Register"
|
|
line.long 0x08 "RTICOMP1,RTI Compare 1 Register"
|
|
line.long 0x0C "RTIUDCP1,RTI Update Compare 1 Register"
|
|
line.long 0x10 "RTICOMP2,RTI Compare 2 Register"
|
|
line.long 0x14 "RTIUDCP2,RTI Update Compare 2 Register"
|
|
line.long 0x18 "RTICOMP3,RTI Compare 3 Register"
|
|
line.long 0x1C "RTIUDCP3,RTI Update Compare 3 Register"
|
|
line.long 0x20 "RTITBLCOMP,RTI Timebase Low Compare Register"
|
|
line.long 0x24 "RTITBHCOMP,RTI Timebase High Compare Register"
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "RTISETINTENA,RTI Set Interrupt Enable Register"
|
|
bitfld.long 0x00 11. " SETDMA3 ,Set compare DMA request 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " SETDMA2 ,Set compare DMA request 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " SETDMA1 ,Set compare DMA request 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SETDMA0 ,Set compare DMA request 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "RTICLEARINTENA,RTI Clear Interrupt Enable Register"
|
|
eventfld.long 0x04 11. " CLEARDMA3 ,Clear compare DMA request 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 10. " CLEARDMA2 ,Clear compare DMA request 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 9. " CLEARDMA1 ,Clear compare DMA request 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 8. " CLEARDMA0 ,Clear compare DMA request 0" "No interrupt,Interrupt"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RTIINTENA_SET/CLR,RTI Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " OVL1INT ,Free running counter 1 overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " OVL0INT ,Free running counter 1 overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " TBINT ,Timebase interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INT3 ,Compare interrupt 3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " INT2 ,Compare interrupt 2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " INT1 ,Compare interrupt 1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " INT0 ,Compare interrupt 0" "No interrupt,Interrupt"
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Register"
|
|
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DWDPRLD ,Digital watchdog preload value"
|
|
line.long 0x08 "RTIWDSTATUS,Watchdog Status Register"
|
|
eventfld.long 0x08 5. " DWWD_ST ,Windowed watchdog status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 4. " END_TIME_VIOL ,Windowed watchdog end time violation status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 3. " START_TIME_VIOL ,Windowed watchdog start time violation status" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 2. " KEY_ST ,Watchdog key status" "No wrong key,Wrong key"
|
|
eventfld.long 0x08 1. " DWD_ST ,DWD status" "No reset,Reset"
|
|
line.long 0x0C "RTIWDKEY,RTI Watchdog Key Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " WDKEY ,Watchdog key"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "RTIDWDCNTR,RTI Digital Watchdog Down Counter Register"
|
|
hexmask.long 0x00 0.--24. 1. " DWDCNTR ,DWD down counter"
|
|
group.long 0xA4++0x1B
|
|
line.long 0x00 "RTIWWDRXNCTRL,Digital Windowed Watchdog Reaction Control Register"
|
|
bitfld.long 0x00 0.--3. " WWDRXN ,The DWWD reaction" "Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Non-maskable interrupt,Reset,Reset,Reset,Reset,Reset"
|
|
line.long 0x04 "RTIWWDSIZECTRL,Digital Windowed Watchdog Window Size Control Register"
|
|
line.long 0x08 "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable Register"
|
|
bitfld.long 0x08 24.--27. " INTCLRENABLE3 ,Enable the auto-clear functionality on the compare 3 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 16.--19. " INTCLRENABLE2 ,Enable the auto-clear functionality on the compare 2 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 8.--11. " INTCLRENABLE1 ,Enable the auto-clear functionality on the compare 1 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 0.--3. " INTCLRENABLE0 ,Enable the auto-clear functionality on the compare 0 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x0C "RTICOMP0CLR,RTI Compare 0 Clear Register"
|
|
line.long 0x10 "RTICOMP1CLR,RTI Compare 1 Clear Register"
|
|
line.long 0x14 "RTICOMP2CLR,RTI Compare 2 Clear Register"
|
|
line.long 0x18 "RTICOMP3CLR,RTI Compare 3 Clear Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTI-B/WDT"
|
|
base ad:0xFFFFEE00
|
|
width 19.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "RTIGCTRL,RTI Global Control Register"
|
|
bitfld.long 0x00 16.--19. " NTUSEL ,Select NTU signal" "NTU0,,,,,NTU1,,,,,NTU2,,,,,NTU3"
|
|
bitfld.long 0x00 15. " COS ,Continue on suspend" "Stopped,Running"
|
|
bitfld.long 0x00 1. " CNT1EN ,Counter 1 enable" "Stopped,Running"
|
|
bitfld.long 0x00 0. " CNT0EN ,Counter 0 enable" "Stopped,Running"
|
|
line.long 0x04 "RTITBCTRL,RTI Timebase Control Register"
|
|
bitfld.long 0x04 1. " INC ,Increment free running counter 0" "Not incremented,Incremented"
|
|
bitfld.long 0x04 0. " TBEXT ,Timebase external" "RTIUC0,NTU"
|
|
line.long 0x08 "RTICAPCTRL,RTI Capture Control Register"
|
|
bitfld.long 0x08 1. " CAPCNTR1 ,Capture counter 1" "Source 0,Source 1"
|
|
bitfld.long 0x08 0. " CAPCNTR0 ,Capture counter 0" "Source 0,Source 1"
|
|
line.long 0x0C "RTICOMPCTRL,RTI Compare Control Register"
|
|
bitfld.long 0x0C 12. " COMPSEL3 ,Compare select 3" "RTIFRC0,RTIFRC1"
|
|
bitfld.long 0x0C 8. " COMPSEL2 ,Compare select 2" "RTIFRC0,RTIFRC1"
|
|
bitfld.long 0x0C 4. " COMPSEL1 ,Compare select 1" "RTIFRC0,RTIFRC1"
|
|
bitfld.long 0x0C 0. " COMPSEL0 ,Compare select 0" "RTIFRC0,RTIFRC1"
|
|
line.long 0x10 "RTIFRC0,RTI Free Running Counter 0 Register"
|
|
line.long 0x14 "RTIUC0,RTI Up Counter 0 Register"
|
|
line.long 0x18 "RTICPUC0,RTI Compare Up Counter 0 Register"
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RTICAFRC0,RTI Capture Free Running Counter 0 Register"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RTICAUC0,RTI Capture Up Counter 0 Register"
|
|
in
|
|
newline
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "RTIFRC1,RTI Free Running Counter 1 Register"
|
|
line.long 0x04 "RTIUC1,RTI Up Counter 1 Register"
|
|
line.long 0x08 "RTICPUC1,RTI Compare Up Counter 1 Register"
|
|
newline
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "RTICAFRC1,RTI Capture Free Running Counter 1 Register"
|
|
in
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "RTICAUC1,RTI Capture Up Counter 1 Register"
|
|
in
|
|
newline
|
|
group.long 0x50++0x27
|
|
line.long 0x00 "RTICOMP0,RTI Compare 0 Register"
|
|
line.long 0x04 "RTIUDCP0,RTI Update Compare 0 Register"
|
|
line.long 0x08 "RTICOMP1,RTI Compare 1 Register"
|
|
line.long 0x0C "RTIUDCP1,RTI Update Compare 1 Register"
|
|
line.long 0x10 "RTICOMP2,RTI Compare 2 Register"
|
|
line.long 0x14 "RTIUDCP2,RTI Update Compare 2 Register"
|
|
line.long 0x18 "RTICOMP3,RTI Compare 3 Register"
|
|
line.long 0x1C "RTIUDCP3,RTI Update Compare 3 Register"
|
|
line.long 0x20 "RTITBLCOMP,RTI Timebase Low Compare Register"
|
|
line.long 0x24 "RTITBHCOMP,RTI Timebase High Compare Register"
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "RTISETINTENA,RTI Set Interrupt Enable Register"
|
|
bitfld.long 0x00 11. " SETDMA3 ,Set compare DMA request 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " SETDMA2 ,Set compare DMA request 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " SETDMA1 ,Set compare DMA request 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SETDMA0 ,Set compare DMA request 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "RTICLEARINTENA,RTI Clear Interrupt Enable Register"
|
|
eventfld.long 0x04 11. " CLEARDMA3 ,Clear compare DMA request 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 10. " CLEARDMA2 ,Clear compare DMA request 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 9. " CLEARDMA1 ,Clear compare DMA request 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 8. " CLEARDMA0 ,Clear compare DMA request 0" "No interrupt,Interrupt"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RTIINTENA_SET/CLR,RTI Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " OVL1INT ,Free running counter 1 overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " OVL0INT ,Free running counter 1 overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " TBINT ,Timebase interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INT3 ,Compare interrupt 3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " INT2 ,Compare interrupt 2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " INT1 ,Compare interrupt 1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " INT0 ,Compare interrupt 0" "No interrupt,Interrupt"
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Register"
|
|
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DWDPRLD ,Digital watchdog preload value"
|
|
line.long 0x08 "RTIWDSTATUS,Watchdog Status Register"
|
|
eventfld.long 0x08 5. " DWWD_ST ,Windowed watchdog status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 4. " END_TIME_VIOL ,Windowed watchdog end time violation status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 3. " START_TIME_VIOL ,Windowed watchdog start time violation status" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 2. " KEY_ST ,Watchdog key status" "No wrong key,Wrong key"
|
|
eventfld.long 0x08 1. " DWD_ST ,DWD status" "No reset,Reset"
|
|
line.long 0x0C "RTIWDKEY,RTI Watchdog Key Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " WDKEY ,Watchdog key"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "RTIDWDCNTR,RTI Digital Watchdog Down Counter Register"
|
|
hexmask.long 0x00 0.--24. 1. " DWDCNTR ,DWD down counter"
|
|
group.long 0xA4++0x1B
|
|
line.long 0x00 "RTIWWDRXNCTRL,Digital Windowed Watchdog Reaction Control Register"
|
|
bitfld.long 0x00 0.--3. " WWDRXN ,The DWWD reaction" "Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Non-maskable interrupt,Reset,Reset,Reset,Reset,Reset"
|
|
line.long 0x04 "RTIWWDSIZECTRL,Digital Windowed Watchdog Window Size Control Register"
|
|
line.long 0x08 "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable Register"
|
|
bitfld.long 0x08 24.--27. " INTCLRENABLE3 ,Enable the auto-clear functionality on the compare 3 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 16.--19. " INTCLRENABLE2 ,Enable the auto-clear functionality on the compare 2 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 8.--11. " INTCLRENABLE1 ,Enable the auto-clear functionality on the compare 1 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 0.--3. " INTCLRENABLE0 ,Enable the auto-clear functionality on the compare 0 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x0C "RTICOMP0CLR,RTI Compare 0 Clear Register"
|
|
line.long 0x10 "RTICOMP1CLR,RTI Compare 1 Clear Register"
|
|
line.long 0x14 "RTICOMP2CLR,RTI Compare 2 Clear Register"
|
|
line.long 0x18 "RTICOMP3CLR,RTI Compare 3 Clear Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "GIO (General Purpose I/0)"
|
|
tree "IRQ Function Registers"
|
|
base ad:0xFFF7BC00
|
|
width 13.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "GCR,GIO Reset Register"
|
|
bitfld.long 0x00 0. " RESET ,GIO reset" "No reset,Reset"
|
|
line.long 0x04 "PWDN,Power Down Mode Register"
|
|
bitfld.long 0x04 0. " GIOPWDN ,GIO operation mode" "Normal operation,Power down mode"
|
|
newline
|
|
line.long 0x08 "INTDET,Interrupt Detection Register"
|
|
bitfld.long 0x08 31. " GIOINTDET_3[7] ,GIOD7 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 30. " [6] ,GIOD6 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 29. " [5] ,GIOD5 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 28. " [4] ,GIOD4 interrupt detection select" "Falling/Rising,Both"
|
|
newline
|
|
bitfld.long 0x08 27. " [3] ,GIOD3 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 26. " [2] ,GIOD2 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 25. " [1] ,GIOD1 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 24. " [0] ,GIOD0 interrupt detection select" "Falling/Rising,Both"
|
|
newline
|
|
bitfld.long 0x08 23. " GIOINTDET_2[7] ,GIOC7 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 22. " [6] ,GIOC6 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 21. " [5] ,GIOC5 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 20. " [4] ,GIOC4 interrupt detection select" "Falling/Rising,Both"
|
|
newline
|
|
bitfld.long 0x08 19. " [3] ,GIOC3 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 18. " [2] ,GIOC2 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 17. " [1] ,GIOC1 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 16. " [0] ,GIOC0 interrupt detection select" "Falling/Rising,Both"
|
|
newline
|
|
bitfld.long 0x08 15. " GIOINTDET_1[7] ,GIOB7 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 14. " [6] ,GIOB6 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 13. " [5] ,GIOB5 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 12. " [4] ,GIOB4 interrupt detection select" "Falling/Rising,Both"
|
|
newline
|
|
bitfld.long 0x08 11. " [3] ,GIOB3 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 10. " [2] ,GIOB2 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 9. " [1] ,GIOB1 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 8. " [0] ,GIOB0 interrupt detection select" "Falling/Rising,Both"
|
|
newline
|
|
bitfld.long 0x08 7. " GIOINTDET_0[7] ,GIOA7 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 6. " [6] ,GIOA6 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 5. " [5] ,GIOA5 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 4. " [4] ,GIOA4 interrupt detection select" "Falling/Rising,Both"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,GIOA3 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 2. " [2] ,GIOA2 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 1. " [1] ,GIOA1 interrupt detection select" "Falling/Rising,Both"
|
|
bitfld.long 0x08 0. " [0] ,GIOA0 interrupt detection select" "Falling/Rising,Both"
|
|
line.long 0x0C "POL,Interrupt Polarity Register"
|
|
bitfld.long 0x0C 31. " GIOPOL_3[7] ,GIOD7 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 30. " [6] ,GIOD6 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 29. " [5] ,GIOD5 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 28. " [4] ,GIOD4 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
newline
|
|
bitfld.long 0x0C 27. " [3] ,GIOD3 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 26. " [2] ,GIOD2 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 25. " [1] ,GIOD1 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 24. " [0] ,GIOD0 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
newline
|
|
bitfld.long 0x0C 23. " GIOPOL_2[7] ,GIOC7 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 22. " [6] ,GIOC6 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 21. " [5] ,GIOC5 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 20. " [4] ,GIOC4 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
newline
|
|
bitfld.long 0x0C 19. " [3] ,GIOC3 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 18. " [2] ,GIOC2 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 17. " [1] ,GIOC1 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 16. " [0] ,GIOC0 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
newline
|
|
bitfld.long 0x0C 15. " GIOPOL_1[7] ,GIOB7 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 14. " [6] ,GIOB6 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 13. " [5] ,GIOB5 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 12. " [4] ,GIOB4 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
newline
|
|
bitfld.long 0x0C 11. " [3] ,GIOB3 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 10. " [2] ,GIOB2 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 9. " [1] ,GIOB1 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 8. " [0] ,GIOB0 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
newline
|
|
bitfld.long 0x0C 7. " GIOPOL_0[7] ,GIOA7 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 6. " [6] ,GIOA6 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 5. " [5] ,GIOA5 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 4. " [4] ,GIOA4 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
newline
|
|
bitfld.long 0x0C 3. " [3] ,GIOA3 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 2. " [2] ,GIOA2 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 1. " [1] ,GIOA1 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
bitfld.long 0x0C 0. " [0] ,GIOA0 interrupt polarity select (User-privilege/low power mode)" "Falling/Low,Rising/High"
|
|
newline
|
|
line.long 0x10 "ENA_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x14 31. " GIOENA3[7] ,GIOD7 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x14 30. " [6] ,GIOD6 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x14 29. " [5] ,GIOD5 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x14 28. " [4] ,GIOD4 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 27. 0x10 27. 0x14 27. " [3] ,GIOD3 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x14 26. " [2] ,GIOD2 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 25. 0x10 25. 0x14 25. " [1] ,GIOD1 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x14 24. " [0] ,GIOD0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 23. 0x10 23. 0x14 23. " GIOENA2[7] ,GIOC7 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x14 22. " [6] ,GIOC6 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x14 21. " [5] ,GIOC5 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x14 20. " [4] ,GIOC4 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 19. 0x10 19. 0x14 19. " [3] ,GIOC3 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x14 18. " [2] ,GIOC2 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x14 17. " [1] ,GIOC1 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x14 16. " [0] ,GIOC0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 15. 0x10 15. 0x14 15. " GIOENA1[7] ,GIOB7 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x14 14. " [6] ,GIOB6 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 13. 0x10 13. 0x14 13. " [5] ,GIOB5 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x14 12. " [4] ,GIOB4 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 11. 0x10 11. 0x14 11. " [3] ,GIOB3 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x14 10. " [2] ,GIOB2 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x14 9. " [1] ,GIOB1 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x14 8. " [0] ,GIOB0 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 7. 0x10 7. 0x14 7. " GIOENA0[7] ,GIOA7 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x14 6. " [6] ,GIOA6 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x14 5. " [5] ,GIOA5 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x14 4. " [4] ,GIOA4 interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x10 3. 0x10 3. 0x14 3. " [3] ,GIOA3 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x14 2. " [2] ,GIOA2 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 1. 0x10 1. 0x14 1. " [1] ,GIOA1 interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x14 0. " [0] ,GIOA0 interrupt enable" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "LVL_SET/CLR,Interrupt Priority Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " GIOLVL3[7] ,GIOD7 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [6] ,GIOD6 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [5] ,GIOD5 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [4] ,GIOD4 interrupt priority" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [3] ,GIOD3 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [2] ,GIOD2 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [1] ,GIOD1 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [0] ,GIOD0 interrupt priority" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " GIOLVL2[7] ,GIOC7 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [6] ,GIOC6 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [5] ,GIOC5 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [4] ,GIOC4 interrupt priority" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [3] ,GIOC3 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [2] ,GIOC2 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [1] ,GIOC1 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [0] ,GIOC0 interrupt priority" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " GIOLVL1[7] ,GIOB7 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [6] ,GIOB6 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [5] ,GIOB5 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [4] ,GIOB4 interrupt priority" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [3] ,GIOB3 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [2] ,GIOB2 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [1] ,GIOB1 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [0] ,GIOB0 interrupt priority" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " GIOLVL0[7] ,GIOA7 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,GIOA6 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,GIOA5 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,GIOA4 interrupt priority" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,GIOA3 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,GIOA2 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,GIOA1 interrupt priority" "Low,High"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,GIOA0 interrupt priority" "Low,High"
|
|
newline
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FLG,Interrupt Flag Register"
|
|
eventfld.long 0x00 31. " GIOFLG_3[7] ,GIOD7 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " [6] ,GIOD6 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 29. " [5] ,GIOD5 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " [4] ,GIOD4 flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 27. " [3] ,GIOD3 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " [2] ,GIOD2 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " [1] ,GIOD1 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " [0] ,GIOD0 flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 23. " GIOFLG_2[7] ,GIOC7 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " [6] ,GIOC6 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " [5] ,GIOC5 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " [4] ,GIOC4 flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 19. " [3] ,GIOC3 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " [2] ,GIOC2 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " [1] ,GIOC1 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " [0] ,GIOC0 flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 15. " GIOFLG_1[7] ,GIOB7 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " [6] ,GIOB6 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " [5] ,GIOB5 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " [4] ,GIOB4 flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 11. " [3] ,GIOB3 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [2] ,GIOB2 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " [1] ,GIOB1 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " [0] ,GIOB0 flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 7. " GIOFLG_0[7] ,GIOA7 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " [6] ,GIOA6 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " [5] ,GIOA5 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,GIOA4 flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 3. " [3] ,GIOA3 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,GIOA2 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " [1] ,GIOA1 flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " [0] ,GIOA0 flag" "No interrupt,Interrupt"
|
|
newline
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "OFFA,Index Bits For Currently Pending High-Priority Interrupt Register A"
|
|
in
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "OFFB,Index Bits For Currently Pending High-Priority Interrupt Register B"
|
|
in
|
|
newline
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "EMUA,GIO Emulation Register A"
|
|
bitfld.long 0x00 0.--5. " GIOEMUA ,GIO emulation A bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "EMUB,GIO Emulation Register B"
|
|
bitfld.long 0x04 0.--5. " GIOEMUB ,GIO emulation B bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "I/O Function Registers"
|
|
tree "GPIO_A"
|
|
base ad:0xFFF7BC34
|
|
width 18.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DIRA,GIOA Data Direction Register"
|
|
bitfld.long 0x00 7. " GIODIR[7] ,GIO data direction 7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,GIO data direction 6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,GIO data direction 5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,GIO data direction 4" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO data direction 3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,GIO data direction 2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,GIO data direction 1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,GIO data direction 0" "Input,Output"
|
|
line.long 0x04 "DINA,GIOA Data Input Register"
|
|
bitfld.long 0x04 7. " GIODIN[7] ,GIO data input 7" "Low,High"
|
|
bitfld.long 0x04 6. " [6] ,GIO data input 6" "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,GIO data input 5" "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,GIO data input 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,GIO data input 3" "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,GIO data input 2" "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,GIO data input 1" "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,GIO data input 0" "Low,High"
|
|
newline
|
|
line.long 0x08 "DOUTA_SET/CLR,GIOA Data Output Register"
|
|
setclrfld.long 0x08 7. 0x0C 7. 0x10 7. " GIODOUT[7] ,GIO data output 7" "Low,High"
|
|
setclrfld.long 0x08 6. 0x0C 6. 0x10 6. " [6] ,GIO data output 6" "Low,High"
|
|
setclrfld.long 0x08 5. 0x0C 5. 0x10 5. " [5] ,GIO data output 5" "Low,High"
|
|
setclrfld.long 0x08 4. 0x0C 4. 0x10 4. " [4] ,GIO data output 4" "Low,High"
|
|
newline
|
|
setclrfld.long 0x08 3. 0x0C 3. 0x10 3. " [3] ,GIO data output 3" "Low,High"
|
|
setclrfld.long 0x08 2. 0x0C 2. 0x10 2. " [2] ,GIO data output 2" "Low,High"
|
|
setclrfld.long 0x08 1. 0x0C 1. 0x10 1. " [1] ,GIO data output 1" "Low,High"
|
|
setclrfld.long 0x08 0. 0x0C 0. 0x10 0. " [0] ,GIO data output 0" "Low,High"
|
|
newline
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "PDRA,GIOA Open Drain Register"
|
|
bitfld.long 0x00 7. " GIOPDR[7] ,GIO open drain enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,GIO open drain enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,GIO open drain enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,GIO open drain enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO open drain enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,GIO open drain enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,GIO open drain enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,GIO open drain enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "PULDISA,GIOA Pull Disable Register"
|
|
bitfld.long 0x04 7. " GIOPULDIS[7] ,GIO pull disable 7" "No,Yes"
|
|
bitfld.long 0x04 6. " [6] ,GIO pull disable 6" "No,Yes"
|
|
bitfld.long 0x04 5. " [5] ,GIO pull disable 5" "No,Yes"
|
|
bitfld.long 0x04 4. " [4] ,GIO pull disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,GIO pull disable 3" "No,Yes"
|
|
bitfld.long 0x04 2. " [2] ,GIO pull disable 2" "No,Yes"
|
|
bitfld.long 0x04 1. " [1] ,GIO pull disable 1" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,GIO pull disable 0" "No,Yes"
|
|
line.long 0x08 "PSLA,GIOA Pull Select Register"
|
|
bitfld.long 0x08 7. " GIOPSL[7] ,GIO pull select 7" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 6. " [6] ,GIO pull select 6" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 5. " [5] ,GIO pull select 5" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 4. " [4] ,GIO pull select 4" "Pull-down,Pull-up"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,GIO pull select 3" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 2. " [2] ,GIO pull select 2" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 1. " [1] ,GIO pull select 1" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 0. " [0] ,GIO pull select 0" "Pull-down,Pull-up"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO_B"
|
|
base ad:0xFFF7BC54
|
|
width 18.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DIRB,GIOB Data Direction Register"
|
|
bitfld.long 0x00 7. " GIODIR[7] ,GIO data direction 7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,GIO data direction 6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,GIO data direction 5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,GIO data direction 4" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO data direction 3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,GIO data direction 2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,GIO data direction 1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,GIO data direction 0" "Input,Output"
|
|
line.long 0x04 "DINB,GIOB Data Input Register"
|
|
bitfld.long 0x04 7. " GIODIN[7] ,GIO data input 7" "Low,High"
|
|
bitfld.long 0x04 6. " [6] ,GIO data input 6" "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,GIO data input 5" "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,GIO data input 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,GIO data input 3" "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,GIO data input 2" "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,GIO data input 1" "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,GIO data input 0" "Low,High"
|
|
newline
|
|
line.long 0x08 "DOUTB_SET/CLR,GIOB Data Output Register"
|
|
setclrfld.long 0x08 7. 0x0C 7. 0x10 7. " GIODOUT[7] ,GIO data output 7" "Low,High"
|
|
setclrfld.long 0x08 6. 0x0C 6. 0x10 6. " [6] ,GIO data output 6" "Low,High"
|
|
setclrfld.long 0x08 5. 0x0C 5. 0x10 5. " [5] ,GIO data output 5" "Low,High"
|
|
setclrfld.long 0x08 4. 0x0C 4. 0x10 4. " [4] ,GIO data output 4" "Low,High"
|
|
newline
|
|
setclrfld.long 0x08 3. 0x0C 3. 0x10 3. " [3] ,GIO data output 3" "Low,High"
|
|
setclrfld.long 0x08 2. 0x0C 2. 0x10 2. " [2] ,GIO data output 2" "Low,High"
|
|
setclrfld.long 0x08 1. 0x0C 1. 0x10 1. " [1] ,GIO data output 1" "Low,High"
|
|
setclrfld.long 0x08 0. 0x0C 0. 0x10 0. " [0] ,GIO data output 0" "Low,High"
|
|
newline
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "PDRB,GIOB Open Drain Register"
|
|
bitfld.long 0x00 7. " GIOPDR[7] ,GIO open drain enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,GIO open drain enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,GIO open drain enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,GIO open drain enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO open drain enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,GIO open drain enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,GIO open drain enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,GIO open drain enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "PULDISB,GIOB Pull Disable Register"
|
|
bitfld.long 0x04 7. " GIOPULDIS[7] ,GIO pull disable 7" "No,Yes"
|
|
bitfld.long 0x04 6. " [6] ,GIO pull disable 6" "No,Yes"
|
|
bitfld.long 0x04 5. " [5] ,GIO pull disable 5" "No,Yes"
|
|
bitfld.long 0x04 4. " [4] ,GIO pull disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,GIO pull disable 3" "No,Yes"
|
|
bitfld.long 0x04 2. " [2] ,GIO pull disable 2" "No,Yes"
|
|
bitfld.long 0x04 1. " [1] ,GIO pull disable 1" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,GIO pull disable 0" "No,Yes"
|
|
line.long 0x08 "PSLB,GIOB Pull Select Register"
|
|
bitfld.long 0x08 7. " GIOPSL[7] ,GIO pull select 7" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 6. " [6] ,GIO pull select 6" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 5. " [5] ,GIO pull select 5" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 4. " [4] ,GIO pull select 4" "Pull-down,Pull-up"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,GIO pull select 3" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 2. " [2] ,GIO pull select 2" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 1. " [1] ,GIO pull select 1" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 0. " [0] ,GIO pull select 0" "Pull-down,Pull-up"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO_C"
|
|
base ad:0xFFF7BC74
|
|
width 18.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DIRC,GIOC Data Direction Register"
|
|
bitfld.long 0x00 7. " GIODIR[7] ,GIO data direction 7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,GIO data direction 6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,GIO data direction 5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,GIO data direction 4" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO data direction 3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,GIO data direction 2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,GIO data direction 1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,GIO data direction 0" "Input,Output"
|
|
line.long 0x04 "DINC,GIOC Data Input Register"
|
|
bitfld.long 0x04 7. " GIODIN[7] ,GIO data input 7" "Low,High"
|
|
bitfld.long 0x04 6. " [6] ,GIO data input 6" "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,GIO data input 5" "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,GIO data input 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,GIO data input 3" "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,GIO data input 2" "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,GIO data input 1" "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,GIO data input 0" "Low,High"
|
|
newline
|
|
line.long 0x08 "DOUTC_SET/CLR,GIOC Data Output Register"
|
|
setclrfld.long 0x08 7. 0x0C 7. 0x10 7. " GIODOUT[7] ,GIO data output 7" "Low,High"
|
|
setclrfld.long 0x08 6. 0x0C 6. 0x10 6. " [6] ,GIO data output 6" "Low,High"
|
|
setclrfld.long 0x08 5. 0x0C 5. 0x10 5. " [5] ,GIO data output 5" "Low,High"
|
|
setclrfld.long 0x08 4. 0x0C 4. 0x10 4. " [4] ,GIO data output 4" "Low,High"
|
|
newline
|
|
setclrfld.long 0x08 3. 0x0C 3. 0x10 3. " [3] ,GIO data output 3" "Low,High"
|
|
setclrfld.long 0x08 2. 0x0C 2. 0x10 2. " [2] ,GIO data output 2" "Low,High"
|
|
setclrfld.long 0x08 1. 0x0C 1. 0x10 1. " [1] ,GIO data output 1" "Low,High"
|
|
setclrfld.long 0x08 0. 0x0C 0. 0x10 0. " [0] ,GIO data output 0" "Low,High"
|
|
newline
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "PDRC,GIOC Open Drain Register"
|
|
bitfld.long 0x00 7. " GIOPDR[7] ,GIO open drain enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,GIO open drain enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,GIO open drain enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,GIO open drain enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO open drain enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,GIO open drain enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,GIO open drain enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,GIO open drain enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "PULDISC,GIOC Pull Disable Register"
|
|
bitfld.long 0x04 7. " GIOPULDIS[7] ,GIO pull disable 7" "No,Yes"
|
|
bitfld.long 0x04 6. " [6] ,GIO pull disable 6" "No,Yes"
|
|
bitfld.long 0x04 5. " [5] ,GIO pull disable 5" "No,Yes"
|
|
bitfld.long 0x04 4. " [4] ,GIO pull disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,GIO pull disable 3" "No,Yes"
|
|
bitfld.long 0x04 2. " [2] ,GIO pull disable 2" "No,Yes"
|
|
bitfld.long 0x04 1. " [1] ,GIO pull disable 1" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,GIO pull disable 0" "No,Yes"
|
|
line.long 0x08 "PSLC,GIOC Pull Select Register"
|
|
bitfld.long 0x08 7. " GIOPSL[7] ,GIO pull select 7" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 6. " [6] ,GIO pull select 6" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 5. " [5] ,GIO pull select 5" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 4. " [4] ,GIO pull select 4" "Pull-down,Pull-up"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,GIO pull select 3" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 2. " [2] ,GIO pull select 2" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 1. " [1] ,GIO pull select 1" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 0. " [0] ,GIO pull select 0" "Pull-down,Pull-up"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO_D"
|
|
base ad:0xFFF7BC94
|
|
width 18.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DIRD,GIOD Data Direction Register"
|
|
bitfld.long 0x00 7. " GIODIR[7] ,GIO data direction 7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,GIO data direction 6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,GIO data direction 5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,GIO data direction 4" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO data direction 3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,GIO data direction 2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,GIO data direction 1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,GIO data direction 0" "Input,Output"
|
|
line.long 0x04 "DIND,GIOD Data Input Register"
|
|
bitfld.long 0x04 7. " GIODIN[7] ,GIO data input 7" "Low,High"
|
|
bitfld.long 0x04 6. " [6] ,GIO data input 6" "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,GIO data input 5" "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,GIO data input 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,GIO data input 3" "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,GIO data input 2" "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,GIO data input 1" "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,GIO data input 0" "Low,High"
|
|
newline
|
|
line.long 0x08 "DOUTD_SET/CLR,GIOD Data Output Register"
|
|
setclrfld.long 0x08 7. 0x0C 7. 0x10 7. " GIODOUT[7] ,GIO data output 7" "Low,High"
|
|
setclrfld.long 0x08 6. 0x0C 6. 0x10 6. " [6] ,GIO data output 6" "Low,High"
|
|
setclrfld.long 0x08 5. 0x0C 5. 0x10 5. " [5] ,GIO data output 5" "Low,High"
|
|
setclrfld.long 0x08 4. 0x0C 4. 0x10 4. " [4] ,GIO data output 4" "Low,High"
|
|
newline
|
|
setclrfld.long 0x08 3. 0x0C 3. 0x10 3. " [3] ,GIO data output 3" "Low,High"
|
|
setclrfld.long 0x08 2. 0x0C 2. 0x10 2. " [2] ,GIO data output 2" "Low,High"
|
|
setclrfld.long 0x08 1. 0x0C 1. 0x10 1. " [1] ,GIO data output 1" "Low,High"
|
|
setclrfld.long 0x08 0. 0x0C 0. 0x10 0. " [0] ,GIO data output 0" "Low,High"
|
|
newline
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "PDRD,GIOD Open Drain Register"
|
|
bitfld.long 0x00 7. " GIOPDR[7] ,GIO open drain enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,GIO open drain enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,GIO open drain enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,GIO open drain enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO open drain enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,GIO open drain enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,GIO open drain enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,GIO open drain enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "PULDISD,GIOD Pull Disable Register"
|
|
bitfld.long 0x04 7. " GIOPULDIS[7] ,GIO pull disable 7" "No,Yes"
|
|
bitfld.long 0x04 6. " [6] ,GIO pull disable 6" "No,Yes"
|
|
bitfld.long 0x04 5. " [5] ,GIO pull disable 5" "No,Yes"
|
|
bitfld.long 0x04 4. " [4] ,GIO pull disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,GIO pull disable 3" "No,Yes"
|
|
bitfld.long 0x04 2. " [2] ,GIO pull disable 2" "No,Yes"
|
|
bitfld.long 0x04 1. " [1] ,GIO pull disable 1" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,GIO pull disable 0" "No,Yes"
|
|
line.long 0x08 "PSLD,GIOD Pull Select Register"
|
|
bitfld.long 0x08 7. " GIOPSL[7] ,GIO pull select 7" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 6. " [6] ,GIO pull select 6" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 5. " [5] ,GIO pull select 5" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 4. " [4] ,GIO pull select 4" "Pull-down,Pull-up"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,GIO pull select 3" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 2. " [2] ,GIO pull select 2" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 1. " [1] ,GIO pull select 1" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 0. " [0] ,GIO pull select 0" "Pull-down,Pull-up"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO_E"
|
|
base ad:0xFFF7BCB4
|
|
width 18.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DIRE,GIOE Data Direction Register"
|
|
bitfld.long 0x00 7. " GIODIR[7] ,GIO data direction 7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,GIO data direction 6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,GIO data direction 5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,GIO data direction 4" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO data direction 3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,GIO data direction 2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,GIO data direction 1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,GIO data direction 0" "Input,Output"
|
|
line.long 0x04 "DINE,GIOE Data Input Register"
|
|
bitfld.long 0x04 7. " GIODIN[7] ,GIO data input 7" "Low,High"
|
|
bitfld.long 0x04 6. " [6] ,GIO data input 6" "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,GIO data input 5" "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,GIO data input 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,GIO data input 3" "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,GIO data input 2" "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,GIO data input 1" "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,GIO data input 0" "Low,High"
|
|
newline
|
|
line.long 0x08 "DOUTE_SET/CLR,GIOE Data Output Register"
|
|
setclrfld.long 0x08 7. 0x0C 7. 0x10 7. " GIODOUT[7] ,GIO data output 7" "Low,High"
|
|
setclrfld.long 0x08 6. 0x0C 6. 0x10 6. " [6] ,GIO data output 6" "Low,High"
|
|
setclrfld.long 0x08 5. 0x0C 5. 0x10 5. " [5] ,GIO data output 5" "Low,High"
|
|
setclrfld.long 0x08 4. 0x0C 4. 0x10 4. " [4] ,GIO data output 4" "Low,High"
|
|
newline
|
|
setclrfld.long 0x08 3. 0x0C 3. 0x10 3. " [3] ,GIO data output 3" "Low,High"
|
|
setclrfld.long 0x08 2. 0x0C 2. 0x10 2. " [2] ,GIO data output 2" "Low,High"
|
|
setclrfld.long 0x08 1. 0x0C 1. 0x10 1. " [1] ,GIO data output 1" "Low,High"
|
|
setclrfld.long 0x08 0. 0x0C 0. 0x10 0. " [0] ,GIO data output 0" "Low,High"
|
|
newline
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "PDRE,GIOE Open Drain Register"
|
|
bitfld.long 0x00 7. " GIOPDR[7] ,GIO open drain enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,GIO open drain enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,GIO open drain enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,GIO open drain enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO open drain enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,GIO open drain enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,GIO open drain enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,GIO open drain enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "PULDISE,GIOE Pull Disable Register"
|
|
bitfld.long 0x04 7. " GIOPULDIS[7] ,GIO pull disable 7" "No,Yes"
|
|
bitfld.long 0x04 6. " [6] ,GIO pull disable 6" "No,Yes"
|
|
bitfld.long 0x04 5. " [5] ,GIO pull disable 5" "No,Yes"
|
|
bitfld.long 0x04 4. " [4] ,GIO pull disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,GIO pull disable 3" "No,Yes"
|
|
bitfld.long 0x04 2. " [2] ,GIO pull disable 2" "No,Yes"
|
|
bitfld.long 0x04 1. " [1] ,GIO pull disable 1" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,GIO pull disable 0" "No,Yes"
|
|
line.long 0x08 "PSLE,GIOE Pull Select Register"
|
|
bitfld.long 0x08 7. " GIOPSL[7] ,GIO pull select 7" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 6. " [6] ,GIO pull select 6" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 5. " [5] ,GIO pull select 5" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 4. " [4] ,GIO pull select 4" "Pull-down,Pull-up"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,GIO pull select 3" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 2. " [2] ,GIO pull select 2" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 1. " [1] ,GIO pull select 1" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 0. " [0] ,GIO pull select 0" "Pull-down,Pull-up"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO_F"
|
|
base ad:0xFFF7BCD4
|
|
width 18.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DIRF,GIOF Data Direction Register"
|
|
bitfld.long 0x00 7. " GIODIR[7] ,GIO data direction 7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,GIO data direction 6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,GIO data direction 5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,GIO data direction 4" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO data direction 3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,GIO data direction 2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,GIO data direction 1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,GIO data direction 0" "Input,Output"
|
|
line.long 0x04 "DINF,GIOF Data Input Register"
|
|
bitfld.long 0x04 7. " GIODIN[7] ,GIO data input 7" "Low,High"
|
|
bitfld.long 0x04 6. " [6] ,GIO data input 6" "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,GIO data input 5" "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,GIO data input 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,GIO data input 3" "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,GIO data input 2" "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,GIO data input 1" "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,GIO data input 0" "Low,High"
|
|
newline
|
|
line.long 0x08 "DOUTF_SET/CLR,GIOF Data Output Register"
|
|
setclrfld.long 0x08 7. 0x0C 7. 0x10 7. " GIODOUT[7] ,GIO data output 7" "Low,High"
|
|
setclrfld.long 0x08 6. 0x0C 6. 0x10 6. " [6] ,GIO data output 6" "Low,High"
|
|
setclrfld.long 0x08 5. 0x0C 5. 0x10 5. " [5] ,GIO data output 5" "Low,High"
|
|
setclrfld.long 0x08 4. 0x0C 4. 0x10 4. " [4] ,GIO data output 4" "Low,High"
|
|
newline
|
|
setclrfld.long 0x08 3. 0x0C 3. 0x10 3. " [3] ,GIO data output 3" "Low,High"
|
|
setclrfld.long 0x08 2. 0x0C 2. 0x10 2. " [2] ,GIO data output 2" "Low,High"
|
|
setclrfld.long 0x08 1. 0x0C 1. 0x10 1. " [1] ,GIO data output 1" "Low,High"
|
|
setclrfld.long 0x08 0. 0x0C 0. 0x10 0. " [0] ,GIO data output 0" "Low,High"
|
|
newline
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "PDRF,GIOF Open Drain Register"
|
|
bitfld.long 0x00 7. " GIOPDR[7] ,GIO open drain enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,GIO open drain enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,GIO open drain enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,GIO open drain enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO open drain enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,GIO open drain enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,GIO open drain enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,GIO open drain enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "PULDISF,GIOF Pull Disable Register"
|
|
bitfld.long 0x04 7. " GIOPULDIS[7] ,GIO pull disable 7" "No,Yes"
|
|
bitfld.long 0x04 6. " [6] ,GIO pull disable 6" "No,Yes"
|
|
bitfld.long 0x04 5. " [5] ,GIO pull disable 5" "No,Yes"
|
|
bitfld.long 0x04 4. " [4] ,GIO pull disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,GIO pull disable 3" "No,Yes"
|
|
bitfld.long 0x04 2. " [2] ,GIO pull disable 2" "No,Yes"
|
|
bitfld.long 0x04 1. " [1] ,GIO pull disable 1" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,GIO pull disable 0" "No,Yes"
|
|
line.long 0x08 "PSLF,GIOF Pull Select Register"
|
|
bitfld.long 0x08 7. " GIOPSL[7] ,GIO pull select 7" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 6. " [6] ,GIO pull select 6" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 5. " [5] ,GIO pull select 5" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 4. " [4] ,GIO pull select 4" "Pull-down,Pull-up"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,GIO pull select 3" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 2. " [2] ,GIO pull select 2" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 1. " [1] ,GIO pull select 1" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 0. " [0] ,GIO pull select 0" "Pull-down,Pull-up"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO_G"
|
|
base ad:0xFFF7BCF4
|
|
width 18.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DIRG,GIOG Data Direction Register"
|
|
bitfld.long 0x00 7. " GIODIR[7] ,GIO data direction 7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,GIO data direction 6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,GIO data direction 5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,GIO data direction 4" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO data direction 3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,GIO data direction 2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,GIO data direction 1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,GIO data direction 0" "Input,Output"
|
|
line.long 0x04 "DING,GIOG Data Input Register"
|
|
bitfld.long 0x04 7. " GIODIN[7] ,GIO data input 7" "Low,High"
|
|
bitfld.long 0x04 6. " [6] ,GIO data input 6" "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,GIO data input 5" "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,GIO data input 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,GIO data input 3" "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,GIO data input 2" "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,GIO data input 1" "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,GIO data input 0" "Low,High"
|
|
newline
|
|
line.long 0x08 "DOUTG_SET/CLR,GIOG Data Output Register"
|
|
setclrfld.long 0x08 7. 0x0C 7. 0x10 7. " GIODOUT[7] ,GIO data output 7" "Low,High"
|
|
setclrfld.long 0x08 6. 0x0C 6. 0x10 6. " [6] ,GIO data output 6" "Low,High"
|
|
setclrfld.long 0x08 5. 0x0C 5. 0x10 5. " [5] ,GIO data output 5" "Low,High"
|
|
setclrfld.long 0x08 4. 0x0C 4. 0x10 4. " [4] ,GIO data output 4" "Low,High"
|
|
newline
|
|
setclrfld.long 0x08 3. 0x0C 3. 0x10 3. " [3] ,GIO data output 3" "Low,High"
|
|
setclrfld.long 0x08 2. 0x0C 2. 0x10 2. " [2] ,GIO data output 2" "Low,High"
|
|
setclrfld.long 0x08 1. 0x0C 1. 0x10 1. " [1] ,GIO data output 1" "Low,High"
|
|
setclrfld.long 0x08 0. 0x0C 0. 0x10 0. " [0] ,GIO data output 0" "Low,High"
|
|
newline
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "PDRG,GIOG Open Drain Register"
|
|
bitfld.long 0x00 7. " GIOPDR[7] ,GIO open drain enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,GIO open drain enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,GIO open drain enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,GIO open drain enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO open drain enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,GIO open drain enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,GIO open drain enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,GIO open drain enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "PULDISG,GIOG Pull Disable Register"
|
|
bitfld.long 0x04 7. " GIOPULDIS[7] ,GIO pull disable 7" "No,Yes"
|
|
bitfld.long 0x04 6. " [6] ,GIO pull disable 6" "No,Yes"
|
|
bitfld.long 0x04 5. " [5] ,GIO pull disable 5" "No,Yes"
|
|
bitfld.long 0x04 4. " [4] ,GIO pull disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,GIO pull disable 3" "No,Yes"
|
|
bitfld.long 0x04 2. " [2] ,GIO pull disable 2" "No,Yes"
|
|
bitfld.long 0x04 1. " [1] ,GIO pull disable 1" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,GIO pull disable 0" "No,Yes"
|
|
line.long 0x08 "PSLG,GIOG Pull Select Register"
|
|
bitfld.long 0x08 7. " GIOPSL[7] ,GIO pull select 7" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 6. " [6] ,GIO pull select 6" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 5. " [5] ,GIO pull select 5" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 4. " [4] ,GIO pull select 4" "Pull-down,Pull-up"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,GIO pull select 3" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 2. " [2] ,GIO pull select 2" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 1. " [1] ,GIO pull select 1" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 0. " [0] ,GIO pull select 0" "Pull-down,Pull-up"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO_H"
|
|
base ad:0xFFF7BD14
|
|
width 18.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DIRH,GIOH Data Direction Register"
|
|
bitfld.long 0x00 7. " GIODIR[7] ,GIO data direction 7" "Input,Output"
|
|
bitfld.long 0x00 6. " [6] ,GIO data direction 6" "Input,Output"
|
|
bitfld.long 0x00 5. " [5] ,GIO data direction 5" "Input,Output"
|
|
bitfld.long 0x00 4. " [4] ,GIO data direction 4" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO data direction 3" "Input,Output"
|
|
bitfld.long 0x00 2. " [2] ,GIO data direction 2" "Input,Output"
|
|
bitfld.long 0x00 1. " [1] ,GIO data direction 1" "Input,Output"
|
|
bitfld.long 0x00 0. " [0] ,GIO data direction 0" "Input,Output"
|
|
line.long 0x04 "DINH,GIOH Data Input Register"
|
|
bitfld.long 0x04 7. " GIODIN[7] ,GIO data input 7" "Low,High"
|
|
bitfld.long 0x04 6. " [6] ,GIO data input 6" "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,GIO data input 5" "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,GIO data input 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,GIO data input 3" "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,GIO data input 2" "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,GIO data input 1" "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,GIO data input 0" "Low,High"
|
|
newline
|
|
line.long 0x08 "DOUTH_SET/CLR,GIOH Data Output Register"
|
|
setclrfld.long 0x08 7. 0x0C 7. 0x10 7. " GIODOUT[7] ,GIO data output 7" "Low,High"
|
|
setclrfld.long 0x08 6. 0x0C 6. 0x10 6. " [6] ,GIO data output 6" "Low,High"
|
|
setclrfld.long 0x08 5. 0x0C 5. 0x10 5. " [5] ,GIO data output 5" "Low,High"
|
|
setclrfld.long 0x08 4. 0x0C 4. 0x10 4. " [4] ,GIO data output 4" "Low,High"
|
|
newline
|
|
setclrfld.long 0x08 3. 0x0C 3. 0x10 3. " [3] ,GIO data output 3" "Low,High"
|
|
setclrfld.long 0x08 2. 0x0C 2. 0x10 2. " [2] ,GIO data output 2" "Low,High"
|
|
setclrfld.long 0x08 1. 0x0C 1. 0x10 1. " [1] ,GIO data output 1" "Low,High"
|
|
setclrfld.long 0x08 0. 0x0C 0. 0x10 0. " [0] ,GIO data output 0" "Low,High"
|
|
newline
|
|
group.long 0x14++0x0B
|
|
line.long 0x00 "PDRH,GIOH Open Drain Register"
|
|
bitfld.long 0x00 7. " GIOPDR[7] ,GIO open drain enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,GIO open drain enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,GIO open drain enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,GIO open drain enable 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO open drain enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,GIO open drain enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,GIO open drain enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,GIO open drain enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "PULDISH,GIOH Pull Disable Register"
|
|
bitfld.long 0x04 7. " GIOPULDIS[7] ,GIO pull disable 7" "No,Yes"
|
|
bitfld.long 0x04 6. " [6] ,GIO pull disable 6" "No,Yes"
|
|
bitfld.long 0x04 5. " [5] ,GIO pull disable 5" "No,Yes"
|
|
bitfld.long 0x04 4. " [4] ,GIO pull disable 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,GIO pull disable 3" "No,Yes"
|
|
bitfld.long 0x04 2. " [2] ,GIO pull disable 2" "No,Yes"
|
|
bitfld.long 0x04 1. " [1] ,GIO pull disable 1" "No,Yes"
|
|
bitfld.long 0x04 0. " [0] ,GIO pull disable 0" "No,Yes"
|
|
line.long 0x08 "PSLH,GIOH Pull Select Register"
|
|
bitfld.long 0x08 7. " GIOPSL[7] ,GIO pull select 7" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 6. " [6] ,GIO pull select 6" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 5. " [5] ,GIO pull select 5" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 4. " [4] ,GIO pull select 4" "Pull-down,Pull-up"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,GIO pull select 3" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 2. " [2] ,GIO pull select 2" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 1. " [1] ,GIO pull select 1" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 0. " [0] ,GIO pull select 0" "Pull-down,Pull-up"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "Slew Rate Registers"
|
|
base ad:0xFFF7BD34
|
|
width 6.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SRCA,GIO Slew Rate Select Register"
|
|
bitfld.long 0x00 7. " GIOSRC[7] ,GIO slew rate control 7" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,GIO slew rate control 6" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " [5] ,GIO slew rate control 5" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,GIO slew rate control 4" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO slew rate control 3" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,GIO slew rate control 2" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " [1] ,GIO slew rate control 1" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,GIO slew rate control 0" "Not selected,Selected"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "SRCB,GIO Slew Rate Select Register"
|
|
bitfld.long 0x00 7. " GIOSRC[7] ,GIO slew rate control 7" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,GIO slew rate control 6" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " [5] ,GIO slew rate control 5" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,GIO slew rate control 4" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO slew rate control 3" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,GIO slew rate control 2" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " [1] ,GIO slew rate control 1" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,GIO slew rate control 0" "Not selected,Selected"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "SRCC,GIO Slew Rate Select Register"
|
|
bitfld.long 0x00 7. " GIOSRC[7] ,GIO slew rate control 7" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,GIO slew rate control 6" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " [5] ,GIO slew rate control 5" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,GIO slew rate control 4" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO slew rate control 3" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,GIO slew rate control 2" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " [1] ,GIO slew rate control 1" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,GIO slew rate control 0" "Not selected,Selected"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "SRCD,GIO Slew Rate Select Register"
|
|
bitfld.long 0x00 7. " GIOSRC[7] ,GIO slew rate control 7" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,GIO slew rate control 6" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " [5] ,GIO slew rate control 5" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,GIO slew rate control 4" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO slew rate control 3" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,GIO slew rate control 2" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " [1] ,GIO slew rate control 1" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,GIO slew rate control 0" "Not selected,Selected"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SRCE,GIO Slew Rate Select Register"
|
|
bitfld.long 0x00 7. " GIOSRC[7] ,GIO slew rate control 7" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,GIO slew rate control 6" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " [5] ,GIO slew rate control 5" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,GIO slew rate control 4" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO slew rate control 3" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,GIO slew rate control 2" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " [1] ,GIO slew rate control 1" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,GIO slew rate control 0" "Not selected,Selected"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SRCF,GIO Slew Rate Select Register"
|
|
bitfld.long 0x00 7. " GIOSRC[7] ,GIO slew rate control 7" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,GIO slew rate control 6" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " [5] ,GIO slew rate control 5" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,GIO slew rate control 4" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO slew rate control 3" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,GIO slew rate control 2" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " [1] ,GIO slew rate control 1" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,GIO slew rate control 0" "Not selected,Selected"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SRCG,GIO Slew Rate Select Register"
|
|
bitfld.long 0x00 7. " GIOSRC[7] ,GIO slew rate control 7" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,GIO slew rate control 6" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " [5] ,GIO slew rate control 5" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,GIO slew rate control 4" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO slew rate control 3" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,GIO slew rate control 2" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " [1] ,GIO slew rate control 1" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,GIO slew rate control 0" "Not selected,Selected"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SRCH,GIO Slew Rate Select Register"
|
|
bitfld.long 0x00 7. " GIOSRC[7] ,GIO slew rate control 7" "Not selected,Selected"
|
|
bitfld.long 0x00 6. " [6] ,GIO slew rate control 6" "Not selected,Selected"
|
|
bitfld.long 0x00 5. " [5] ,GIO slew rate control 5" "Not selected,Selected"
|
|
bitfld.long 0x00 4. " [4] ,GIO slew rate control 4" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,GIO slew rate control 3" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " [2] ,GIO slew rate control 2" "Not selected,Selected"
|
|
bitfld.long 0x00 1. " [1] ,GIO slew rate control 1" "Not selected,Selected"
|
|
bitfld.long 0x00 0. " [0] ,GIO slew rate control 0" "Not selected,Selected"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "MAILBOX (Mailbox)"
|
|
tree "BSS_MBOX4MSS"
|
|
base ad:0xF0608000
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INT_MASK_SET/CLR,INT_MASK Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " MAILBOX_ACK_INT_MASK ,Mailbox acknowledge interrupt mask" "Unmasked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " MAILBOX_INT_MASK ,Mailbox interrupt mask" "Unmasked,Masked"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "INT_STS_CLR,INT_STS_CLR Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_STS_CLR ,Acknowledge interrupt status register clear" "Clear,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_CLR ,Interrupt status register clear" "Clear,Clear"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "INT_ACK,INT_ACK Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "INT_TRIG,INT_TRIG Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_TRIG ,Indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_TRIG ,Trigger interrupt and indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "INT_STS_MASKED,INT_STS_MASKED Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_MASKED ,Current status of mailbox empty interrupt if it is not masked" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_MASKED ,Current status of mailbox full interrupt if it is not masked" "No interrupt,Interrupt"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "INT_STS_RAW,INT_STS_RAW Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_RAW ,Current status of mailbox empty interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_RAW ,Current status of mailbox full interrupt" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("AWR1642")||cpuis("AWR1642-CORE1")||cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
tree "BSS_MBOX4GEM"
|
|
base ad:0xF0608100
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INT_MASK_SET/CLR,INT_MASK Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " MAILBOX_ACK_INT_MASK ,Mailbox acknowledge interrupt mask" "Unmasked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " MAILBOX_INT_MASK ,Mailbox interrupt mask" "Unmasked,Masked"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "INT_STS_CLR,INT_STS_CLR Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_STS_CLR ,Acknowledge interrupt status register clear" "Clear,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_CLR ,Interrupt status register clear" "Clear,Clear"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "INT_ACK,INT_ACK Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "INT_TRIG,INT_TRIG Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_TRIG ,Indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_TRIG ,Trigger interrupt and indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "INT_STS_MASKED,INT_STS_MASKED Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_MASKED ,Current status of mailbox empty interrupt if it is not masked" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_MASKED ,Current status of mailbox full interrupt if it is not masked" "No interrupt,Interrupt"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "INT_STS_RAW,INT_STS_RAW Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_RAW ,Current status of mailbox empty interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_RAW ,Current status of mailbox full interrupt" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GEM_MBOX4BSS"
|
|
base ad:0xF0608200
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INT_MASK_SET/CLR,INT_MASK Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " MAILBOX_ACK_INT_MASK ,Mailbox acknowledge interrupt mask" "Unmasked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " MAILBOX_INT_MASK ,Mailbox interrupt mask" "Unmasked,Masked"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "INT_STS_CLR,INT_STS_CLR Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_STS_CLR ,Acknowledge interrupt status register clear" "Clear,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_CLR ,Interrupt status register clear" "Clear,Clear"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "INT_ACK,INT_ACK Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "INT_TRIG,INT_TRIG Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_TRIG ,Indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_TRIG ,Trigger interrupt and indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "INT_STS_MASKED,INT_STS_MASKED Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_MASKED ,Current status of mailbox empty interrupt if it is not masked" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_MASKED ,Current status of mailbox full interrupt if it is not masked" "No interrupt,Interrupt"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "INT_STS_RAW,INT_STS_RAW Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_RAW ,Current status of mailbox empty interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_RAW ,Current status of mailbox full interrupt" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MSS_MBOX4GEM"
|
|
base ad:0xF0608300
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INT_MASK_SET/CLR,INT_MASK Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " MAILBOX_ACK_INT_MASK ,Mailbox acknowledge interrupt mask" "Unmasked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " MAILBOX_INT_MASK ,Mailbox interrupt mask" "Unmasked,Masked"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "INT_STS_CLR,INT_STS_CLR Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_STS_CLR ,Acknowledge interrupt status register clear" "Clear,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_CLR ,Interrupt status register clear" "Clear,Clear"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "INT_ACK,INT_ACK Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "INT_TRIG,INT_TRIG Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_TRIG ,Indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_TRIG ,Trigger interrupt and indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "INT_STS_MASKED,INT_STS_MASKED Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_MASKED ,Current status of mailbox empty interrupt if it is not masked" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_MASKED ,Current status of mailbox full interrupt if it is not masked" "No interrupt,Interrupt"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "INT_STS_RAW,INT_STS_RAW Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_RAW ,Current status of mailbox empty interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_RAW ,Current status of mailbox full interrupt" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GEM_MBOX4MSS"
|
|
base ad:0xF0608400
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INT_MASK_SET/CLR,INT_MASK Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " MAILBOX_ACK_INT_MASK ,Mailbox acknowledge interrupt mask" "Unmasked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " MAILBOX_INT_MASK ,Mailbox interrupt mask" "Unmasked,Masked"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "INT_STS_CLR,INT_STS_CLR Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_STS_CLR ,Acknowledge interrupt status register clear" "Clear,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_CLR ,Interrupt status register clear" "Clear,Clear"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "INT_ACK,INT_ACK Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "INT_TRIG,INT_TRIG Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_TRIG ,Indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_TRIG ,Trigger interrupt and indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "INT_STS_MASKED,INT_STS_MASKED Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_MASKED ,Current status of mailbox empty interrupt if it is not masked" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_MASKED ,Current status of mailbox full interrupt if it is not masked" "No interrupt,Interrupt"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "INT_STS_RAW,INT_STS_RAW Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_RAW ,Current status of mailbox empty interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_RAW ,Current status of mailbox full interrupt" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "MSS_MBOX4BSS"
|
|
base ad:0xF0608600
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INT_MASK_SET/CLR,INT_MASK Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " MAILBOX_ACK_INT_MASK ,Mailbox acknowledge interrupt mask" "Unmasked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " MAILBOX_INT_MASK ,Mailbox interrupt mask" "Unmasked,Masked"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "INT_STS_CLR,INT_STS_CLR Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_STS_CLR ,Acknowledge interrupt status register clear" "Clear,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_CLR ,Interrupt status register clear" "Clear,Clear"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "INT_ACK,INT_ACK Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "INT_TRIG,INT_TRIG Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_TRIG ,Indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_TRIG ,Trigger interrupt and indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "INT_STS_MASKED,INT_STS_MASKED Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_MASKED ,Current status of mailbox empty interrupt if it is not masked" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_MASKED ,Current status of mailbox full interrupt if it is not masked" "No interrupt,Interrupt"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "INT_STS_RAW,INT_STS_RAW Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_RAW ,Current status of mailbox empty interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_RAW ,Current status of mailbox full interrupt" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("AWR1642"))||(cpuis("AWR1642-CORE1"))||cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
tree.open "DMM (Data Modification Module)"
|
|
tree "DMM-2"
|
|
base ad:0xFCFFF600
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GLBCTRL,Global Control Register"
|
|
rbitfld.long 0x00 24. " BUSY ,Busy" "Not received,Received"
|
|
bitfld.long 0x00 18. " CONTCLK ,Continuous DMMCLK output" "Suspended,Continue"
|
|
bitfld.long 0x00 17. " COS ,Continue on suspend" "Suspended,Continue"
|
|
newline
|
|
bitfld.long 0x00 16. " RESET ,Reset" "No reset,Reset"
|
|
bitfld.long 0x00 9.--10. " DDM_WIDTH ,Packet width in direct data mode" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 8. " TM_DMM ,Packet format" "Trace mode,Direct mode"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " ON/OFF ,DMM module receives data enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
if (((per.l(ad:0xFCFFF600))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "INT_SET/CLR,Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " PROG_BUFF ,Programmable buffer interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " EO_BUFF ,End of buffer interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " BUSERROR ,BMM bus error response" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " BUFF_OVF ,Write buffer overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SRC_OVF ,Source overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " DEST3_ERR ,Destination 3 error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " DEST2_ERR ,Destination 2 error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " DEST1_ERR ,Destination 1 error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " DEST0_ERR ,Destination 0 error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PACKET_ERR_INT ,Packet error interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "INT_SET/CLR,Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " DEST3REG2 ,Destination 3 region 2 interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " DEST3REG1 ,Destination 3 region 1 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " DEST2REG2 ,Destination 2 region 2 interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " DEST2REG1 ,Destination 2 region 1 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " DEST1REG2 ,Destination 1 region 2 interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " DEST1REG1 ,Destination 1 region 1 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " DEST0REG2 ,Destination 0 region 2 interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " DEST0REG1 ,Destination 0 region 1 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " BUSERROR ,BMM bus error response" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " BUFF_OVF ,Write buffer overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SRC_OVF ,Source overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " DEST3_ERR ,Destination 3 error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " DEST2_ERR ,Destination 2 error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " DEST1_ERR ,Destination 1 error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " DEST0_ERR ,Destination 0 error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PACKET_ERR_INT ,Packet error interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "INTLVL,Interrupt Level Register"
|
|
bitfld.long 0x00 17. " PROG_BUFF ,Programmable buffer interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 16. " EO_BUFF ,End of buffer interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 15. " DEST3REG2 ,Destination 3 region 2 interrupt level" "Level 0,Level 1"
|
|
newline
|
|
bitfld.long 0x00 14. " DEST3REG1 ,Destination 3 region 1 interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 13. " DEST2REG2 ,Destination 2 region 2 interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 12. " DEST2REG1 ,Destination 2 region 1 interrupt level" "Level 0,Level 1"
|
|
newline
|
|
bitfld.long 0x00 11. " DEST1REG2 ,Destination 1 region 2 interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 10. " DEST1REG1 ,Destination 1 region 1 interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 9. " DEST0REG2 ,Destination 0 region 2 interrupt level" "Level 0,Level 1"
|
|
newline
|
|
bitfld.long 0x00 8. " DEST0REG1 ,Destination 0 region 1 interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 7. " BUSERROR ,BMM bus error response" "Level 0,Level 1"
|
|
bitfld.long 0x00 6. " BUFF_OVF ,Write buffer overflow interrupt level" "Level 0,Level 1"
|
|
newline
|
|
bitfld.long 0x00 5. " SRC_OVF ,Source overflow interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 4. " DEST3_ERR ,Destination 3 error interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 3. " DEST2_ERR ,Destination 2 error interrupt level" "Level 0,Level 1"
|
|
newline
|
|
bitfld.long 0x00 2. " DEST1_ERR ,Destination 1 error interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 1. " DEST0_ERR ,Destination 0 error interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 0. " PACKET_ERR_INT ,Packet error interrupt level" "Level 0,Level 1"
|
|
line.long 0x04 "INTFLG,Interrupt Flag Register"
|
|
eventfld.long 0x04 17. " PROG_BUFF ,Programmable buffer interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 16. " EO_BUFF ,End of buffer interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 15. " DEST3REG2 ,Destination 3 region 2 interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 14. " DEST3REG1 ,Destination 3 region 1 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 13. " DEST2REG2 ,Destination 2 region 2 interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 12. " DEST2REG1 ,Destination 2 region 1 interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 11. " DEST1REG2 ,Destination 1 region 2 interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 10. " DEST1REG1 ,Destination 1 region 1 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 9. " DEST0REG2 ,Destination 0 region 2 interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 8. " DEST0REG1 ,Destination 0 region 1 interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 7. " BUSERROR ,BMM bus error response" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " BUFF_OVF ,Write buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 5. " SRC_OVF ,Source overflow interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 4. " DEST3_ERR ,Destination 3 error interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " DEST2_ERR ,Destination 2 error interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " DEST1_ERR ,Destination 1 error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 1. " DEST0_ERR ,Destination 0 error interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 0. " PACKET_ERR_INT ,Packet error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
width 18.
|
|
group.long 0x14++0x0F
|
|
line.long 0x00 "OFF1,Interrupt Offset 1 Register"
|
|
bitfld.long 0x00 0.--4. " OFFSET ,Interrupt" "Phantom,Packet error,Destination 0 error,Destination 1 error,Destination 2 error,Destination 3 error,Source overflow,Buffer overflow,Bus error,Destination 0 region 1,Destination 0 region 2,Destination 1 region 1,Destination 1 region 2,Destination 2 region 1,Destination 2 region 2,Destination 3 region 1,Destination 3 region 2,End of buffer,Programmable buffer,?..."
|
|
line.long 0x04 "OFF2,Interrupt Offset 2 Register"
|
|
bitfld.long 0x04 0.--4. " OFFSET ,Interrupt" "Phantom,Packet error,Destination 0 error,Destination 1 error,Destination 2 error,Destination 3 error,Source overflow,Buffer overflow,Bus error,Destination 0 region 1,Destination 0 region 2,Destination 1 region 1,Destination 1 region 2,Destination 2 region 1,Destination 2 region 2,Destination 3 region 1,Destination 3 region 2,End of buffer,Programmable buffer,?..."
|
|
line.long 0x08 "DDMDEST,Direct Data Mode Destination Register"
|
|
line.long 0x0C "DDMBL,Direct Data Mode Blocksize Register"
|
|
bitfld.long 0x0C 0.--3. " BLOCKSIZE ,Block size [bytes]" "Disabled,32,64,128,256,512,1024,2048,4096,8192,16384,32768,?..."
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DDMPT,Direct Data Mode Pointer Register"
|
|
hexmask.long.word 0x00 0.--14. 0x01 " POINTER ,Pointer"
|
|
group.long 0x28++0x43
|
|
line.long 0x00 "INTPT,Direct Data Mode Interrupt Pointer Register"
|
|
hexmask.long.word 0x00 0.--14. 0x01 " INTPT ,Interrupt pointer"
|
|
line.long 0x04 "DEST0REG1,Destination 0 Region 1 Register"
|
|
hexmask.long.word 0x04 18.--31. 0x04 " BASEADDR ,Base address"
|
|
hexmask.long.tbyte 0x04 0.--17. 0x01 " BLOCKADDR ,Block address"
|
|
line.long 0x08 "DEST0BL1,Destination 0 Blocksize 1 Register"
|
|
bitfld.long 0x08 0.--3. " BLOCKSIZE ,Block size [bytes]" "Disabled,32,64,128,256,512,1024,2048,4096,8192,16384,32768,?..."
|
|
line.long 0x0C "DEST0REG2,Destination 0 Region 2 Register"
|
|
hexmask.long.word 0x0C 18.--31. 0x04 " BASEADDR ,Base address"
|
|
hexmask.long.tbyte 0x0C 0.--17. 0x01 " BLOCKADDR ,Block address"
|
|
line.long 0x10 "DEST0BL2,Destination 0 Blocksize 2 Register"
|
|
bitfld.long 0x10 0.--3. " BLOCKSIZE ,Block size [bytes]" "Disabled,32,64,128,256,512,1024,2048,4096,8192,16384,32768,?..."
|
|
line.long 0x14 "DEST1REG1,Destination 1 Region 1 Register"
|
|
hexmask.long.word 0x14 18.--31. 0x04 " BASEADDR ,Base address"
|
|
hexmask.long.tbyte 0x14 0.--17. 0x01 " BLOCKADDR ,Block address"
|
|
line.long 0x18 "DEST1BL1,Destination 1 Blocksize 1 Register"
|
|
bitfld.long 0x18 0.--3. " BLOCKSIZE ,Block size [bytes]" "Disabled,32,64,128,256,512,1024,2048,4096,8192,16384,32768,?..."
|
|
line.long 0x1C "DEST1REG2,Destination 1 Region 2 Register"
|
|
hexmask.long.word 0x1C 18.--31. 0x04 " BASEADDR ,Base address"
|
|
hexmask.long.tbyte 0x1C 0.--17. 0x01 " BLOCKADDR ,Block address"
|
|
line.long 0x20 "DEST1BL2,Destination 1 Blocksize 2 Register"
|
|
bitfld.long 0x20 0.--3. " BLOCKSIZE ,Block size [bytes]" "Disabled,32,64,128,256,512,1024,2048,4096,8192,16384,32768,?..."
|
|
line.long 0x24 "DEST2REG1,Destination 2 Region 1 Register"
|
|
hexmask.long.word 0x24 18.--31. 0x04 " BASEADDR ,Base address"
|
|
hexmask.long.tbyte 0x24 0.--17. 0x01 " BLOCKADDR ,Block address"
|
|
line.long 0x28 "DEST2BL1,Destination 2 Blocksize 1 Register"
|
|
bitfld.long 0x28 0.--3. " BLOCKSIZE ,Block size [bytes]" "Disabled,32,64,128,256,512,1024,2048,4096,8192,16384,32768,?..."
|
|
line.long 0x2C "DEST2REG2,Destination 2 Region 2 Register"
|
|
hexmask.long.word 0x2C 18.--31. 0x04 " BASEADDR ,Base address"
|
|
hexmask.long.tbyte 0x2C 0.--17. 0x01 " BLOCKADDR ,Block address"
|
|
line.long 0x30 "DEST2BL2,Destination 2 Blocksize 2 Register"
|
|
bitfld.long 0x30 0.--3. " BLOCKSIZE ,Block size [bytes]" "Disabled,32,64,128,256,512,1024,2048,4096,8192,16384,32768,?..."
|
|
line.long 0x34 "DEST3REG1,Destination 3 Region 1 Register"
|
|
hexmask.long.word 0x34 18.--31. 0x04 " BASEADDR ,Base address"
|
|
hexmask.long.tbyte 0x34 0.--17. 0x01 " BLOCKADDR ,Block address"
|
|
line.long 0x38 "DEST3BL1,Destination 3 Blocksize 1 Register"
|
|
bitfld.long 0x38 0.--3. " BLOCKSIZE ,Block size [bytes]" "Disabled,32,64,128,256,512,1024,2048,4096,8192,16384,32768,?..."
|
|
line.long 0x3C "DEST3REG2,Destination 3 Region 2 Register"
|
|
hexmask.long.word 0x3C 18.--31. 0x04 " BASEADDR ,Base address"
|
|
hexmask.long.tbyte 0x3C 0.--17. 0x01 " BLOCKADDR ,Block address"
|
|
line.long 0x40 "DEST3BL2,Destination 3 Blocksize 2 Register"
|
|
bitfld.long 0x40 0.--3. " BLOCKSIZE ,Block size [bytes]" "Disabled,32,64,128,256,512,1024,2048,4096,8192,16384,32768,?..."
|
|
newline
|
|
if (((per.l(ad:0xFCFFF600))&0x100000F)==0x0A)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PC0(FUNC),Pin Control 0 Register"
|
|
bitfld.long 0x00 18. " ENAFUNC ,Functional mode of DMMENA pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 17. " DATA15FUNC ,Functional mode of DMMDATA[15] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 16. " DATA14FUNC ,Functional mode of DMMDATA[14] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 15. " DATA13FUNC ,Functional mode of DMMDATA[13] pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x00 14. " DATA12FUNC ,Functional mode of DMMDATA[12] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 13. " DATA11FUNC ,Functional mode of DMMDATA[11] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 12. " DATA10FUNC ,Functional mode of DMMDATA[10] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 11. " DATA9FUNC ,Functional mode of DMMDATA[9] pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x00 10. " DATA8FUNC ,Functional mode of DMMDATA[8] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 9. " DATA7FUNC ,Functional mode of DMMDATA[7] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 8. " DATA6FUNC ,Functional mode of DMMDATA[6] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 7. " DATA5FUNC ,Functional mode of DMMDATA[5] pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x00 6. " DATA4FUNC ,Functional mode of DMMDATA[4] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 5. " DATA3FUNC ,Functional mode of DMMDATA[3] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 4. " DATA2FUNC ,Functional mode of DMMDATA[2] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 3. " DATA1FUNC ,Functional mode of DMMDATA[1] pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x00 2. " DATA0FUNC ,Functional mode of DMMDATA[0] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 1. " CLKFUNC ,Functional mode of DMMCLK pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 0. " SYNCFUNC ,Functional mode of DMMSYNC pin" "GIO mode,Functional mode"
|
|
else
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "PC0(FUNC),Pin Control 0 Register"
|
|
bitfld.long 0x00 18. " ENAFUNC ,Functional mode of DMMENA pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 17. " DATA15FUNC ,Functional mode of DMMDATA[15] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 16. " DATA14FUNC ,Functional mode of DMMDATA[14] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 15. " DATA13FUNC ,Functional mode of DMMDATA[13] pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x00 14. " DATA12FUNC ,Functional mode of DMMDATA[12] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 13. " DATA11FUNC ,Functional mode of DMMDATA[11] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 12. " DATA10FUNC ,Functional mode of DMMDATA[10] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 11. " DATA9FUNC ,Functional mode of DMMDATA[9] pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x00 10. " DATA8FUNC ,Functional mode of DMMDATA[8] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 9. " DATA7FUNC ,Functional mode of DMMDATA[7] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 8. " DATA6FUNC ,Functional mode of DMMDATA[6] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 7. " DATA5FUNC ,Functional mode of DMMDATA[5] pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x00 6. " DATA4FUNC ,Functional mode of DMMDATA[4] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 5. " DATA3FUNC ,Functional mode of DMMDATA[3] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 4. " DATA2FUNC ,Functional mode of DMMDATA[2] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 3. " DATA1FUNC ,Functional mode of DMMDATA[1] pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x00 2. " DATA0FUNC ,Functional mode of DMMDATA[0] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 1. " CLKFUNC ,Functional mode of DMMCLK pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 0. " SYNCFUNC ,Functional mode of DMMSYNC pin" "GIO mode,Functional mode"
|
|
endif
|
|
newline
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PC1(DIR),Pin Control 1 Register"
|
|
bitfld.long 0x00 18. " ENADIR ,Direction of DMMENA pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 17. " DATA15DIR ,Direction of DMMDATA[15] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 16. " DATA14DIR ,Direction of DMMDATA[14] pin (GIO mode)" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 15. " DATA13DIR ,Direction of DMMDATA[13] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 14. " DATA12DIR ,Direction of DMMDATA[12] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 13. " DATA11DIR ,Direction of DMMDATA[11] pin (GIO mode)" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 12. " DATA10DIR ,Direction of DMMDATA[10] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 11. " DATA9DIR ,Direction of DMMDATA[9] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 10. " DATA8DIR ,Direction of DMMDATA[8] pin (GIO mode)" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. " DATA7DIR ,Direction of DMMDATA[7] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 8. " DATA6DIR ,Direction of DMMDATA[6] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 7. " DATA5DIR ,Direction of DMMDATA[5] pin (GIO mode)" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " DATA4DIR ,Direction of DMMDATA[4] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 5. " DATA3DIR ,Direction of DMMDATA[3] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 4. " DATA2DIR ,Direction of DMMDATA[2] pin (GIO mode)" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " DATA1DIR ,Direction of DMMDATA[1] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 2. " DATA0DIR ,Direction of DMMDATA[0] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 1. " CLKDIR ,Direction of DMMCLK pin (GIO mode)" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " SYNCDIR ,Direction of DMMSYNC pin (GIO mode)" "Input,Output"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "PC2(DIN),Pin Control 2 Register"
|
|
bitfld.long 0x00 18. " ENAIN ,DMMENA input" "Low,High"
|
|
bitfld.long 0x00 17. " DATA15IN ,DMMDATA[15] input" "Low,High"
|
|
bitfld.long 0x00 16. " DATA14IN ,DMMDATA[14] input" "Low,High"
|
|
bitfld.long 0x00 15. " DATA13IN ,DMMDATA[13] input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. " DATA12IN ,DMMDATA[12] input" "Low,High"
|
|
bitfld.long 0x00 13. " DATA11IN ,DMMDATA[11] input" "Low,High"
|
|
bitfld.long 0x00 12. " DATA10IN ,DMMDATA[10] input" "Low,High"
|
|
bitfld.long 0x00 11. " DATA9IN ,DMMDATA[9] input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " DATA8IN ,DMMDATA[8] input" "Low,High"
|
|
bitfld.long 0x00 9. " DATA7IN ,DMMDATA[7] input" "Low,High"
|
|
bitfld.long 0x00 8. " DATA6IN ,DMMDATA[6] input" "Low,High"
|
|
bitfld.long 0x00 7. " DATA5IN ,DMMDATA[5] input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " DATA4IN ,DMMDATA[4] input" "Low,High"
|
|
bitfld.long 0x00 5. " DATA3IN ,DMMDATA[3] input" "Low,High"
|
|
bitfld.long 0x00 4. " DATA2IN ,DMMDATA[2] input" "Low,High"
|
|
bitfld.long 0x00 3. " DATA1IN ,DMMDATA[1] input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " DATA0IN ,DMMDATA[0] input" "Low,High"
|
|
bitfld.long 0x00 1. " CLKIN ,DMMCLK input" "Low,High"
|
|
bitfld.long 0x00 0. " SYNCIN ,DMMSYNC input" "Low,High"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PC3(OUT)_SET/CLR,Pin Control 3 Register"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " ENAOUT ,Output state of DMMENA pin" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DATA15OUT ,Output state of DMMDATA[15] pin" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " DATA14OUT ,Output state of DMMDATA[14] pin" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " DATA13OUT ,Output state of DMMDATA[13] pin" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " DATA12OUT ,Output state of DMMDATA[12] pin" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " DATA11OUT ,Output state of DMMDATA[11] pin" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " DATA10OUT ,Output state of DMMDATA[10] pin" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " DATA9OUT ,Output state of DMMDATA[9] pin" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " DATA8OUT ,Output state of DMMDATA[8] pin" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " DATA7OUT ,Output state of DMMDATA[7] pin" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " DATA6OUT ,Output state of DMMDATA[6] pin" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DATA5OUT ,Output state of DMMDATA[5] pin" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DATA4OUT ,Output state of DMMDATA[4] pin" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DATA3OUT ,Output state of DMMDATA[3] pin" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DATA2OUT ,Output state of DMMDATA[2] pin" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " DATA1OUT ,Output state of DMMDATA[1] pin" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DATA0OUT ,Output state of DMMDATA[0] pin" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CLKOUT ,Output state of DMMCLK pin" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SYNCOUT ,Output state of DMMSYNC pin" "Low,High"
|
|
group.long 0x84++0x0B
|
|
line.long 0x00 "PC6(PDR),Pin Control 6 Register"
|
|
bitfld.long 0x00 18. " ENAPDR ,ENAPDR open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DATA15PDR ,Open drain enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DATA14PDR ,Open drain enable 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " DATA13PDR ,Open drain enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DATA12PDR ,Open drain enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DATA11PDR ,Open drain enable 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " DATA10PDR ,Open drain enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DATA9PDR ,Open drain enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DATA8PDR ,Open drain enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " DATA7PDR ,Open drain enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DATA6PDR ,Open drain enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DATA5PDR ,Open drain enable 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " DATA4PDR ,Open drain enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DATA3PDR ,Open drain enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DATA2PDR ,Open drain enable 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " DATA1PDR ,Open drain enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DATA0PDR ,Open drain enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CLKPDR ,CLKPDR open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " SYNCPDR ,SYNCPDR open drain enable" "Disabled,Enabled"
|
|
line.long 0x04 "PC7(PDIS),Pin Control 7 Register"
|
|
bitfld.long 0x04 18. " ENAPDIS ,ENAPDIS pull disable" "No,Yes"
|
|
bitfld.long 0x04 17. " DATA15PDIS ,Pull disable 15" "No,Yes"
|
|
bitfld.long 0x04 16. " DATA14PDIS ,Pull disable 14" "No,Yes"
|
|
bitfld.long 0x04 15. " DATA13PDIS ,Pull disable 13" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 14. " DATA12PDIS ,Pull disable 12" "No,Yes"
|
|
bitfld.long 0x04 13. " DATA11PDIS ,Pull disable 11" "No,Yes"
|
|
bitfld.long 0x04 12. " DATA10PDIS ,Pull disable 10" "No,Yes"
|
|
bitfld.long 0x04 11. " DATA9PDIS ,Pull disable 9" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 10. " DATA8PDIS ,Pull disable 8" "No,Yes"
|
|
bitfld.long 0x04 9. " DATA7PDIS ,Pull disable 7" "No,Yes"
|
|
bitfld.long 0x04 8. " DATA6PDIS ,Pull disable 6" "No,Yes"
|
|
bitfld.long 0x04 7. " DATA5PDIS ,Pull disable 5" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 6. " DATA4PDIS ,Pull disable 4" "No,Yes"
|
|
bitfld.long 0x04 5. " DATA3PDIS ,Pull disable 3" "No,Yes"
|
|
bitfld.long 0x04 4. " DATA2PDIS ,Pull disable 2" "No,Yes"
|
|
bitfld.long 0x04 3. " DATA1PDIS ,Pull disable 1" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 2. " DATA0PDIS ,Pull disable 0" "No,Yes"
|
|
bitfld.long 0x04 1. " CLKPDIS ,CLKPDIS pull disable" "No,Yes"
|
|
bitfld.long 0x04 0. " SYNCPDIS ,SYNCPDIS pull disable" "No,Yes"
|
|
line.long 0x08 "PC8(PSEL),Pin Control 8 Register"
|
|
bitfld.long 0x08 18. " ENAPSEL ,ENAPSEL pull select" "Pull down,Pull up"
|
|
bitfld.long 0x08 17. " DATA15PSEL ,Pull select 15" "Pull down,Pull up"
|
|
bitfld.long 0x08 16. " DATA14PSEL ,Pull select 14" "Pull down,Pull up"
|
|
bitfld.long 0x08 15. " DATA13PSEL ,Pull select 13" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 14. " DATA12PSEL ,Pull select 12" "Pull down,Pull up"
|
|
bitfld.long 0x08 13. " DATA11PSEL ,Pull select 11" "Pull down,Pull up"
|
|
bitfld.long 0x08 12. " DATA10PSEL ,Pull select 10" "Pull down,Pull up"
|
|
bitfld.long 0x08 11. " DATA9PSEL ,Pull select 9" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 10. " DATA8PSEL ,Pull select 8" "Pull down,Pull up"
|
|
bitfld.long 0x08 9. " DATA7PSEL ,Pull select 7" "Pull down,Pull up"
|
|
bitfld.long 0x08 8. " DATA6PSEL ,Pull select 6" "Pull down,Pull up"
|
|
bitfld.long 0x08 7. " DATA5PSEL ,Pull select 5" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 6. " DATA4PSEL ,Pull select 4" "Pull down,Pull up"
|
|
bitfld.long 0x08 5. " DATA3PSEL ,Pull select 3" "Pull down,Pull up"
|
|
bitfld.long 0x08 4. " DATA2PSEL ,Pull select 2" "Pull down,Pull up"
|
|
bitfld.long 0x08 3. " DATA1PSEL ,Pull select 1" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 2. " DATA0PSEL ,Pull select 0" "Pull down,Pull up"
|
|
bitfld.long 0x08 1. " CLKPDSEL ,CLKPDSEL pull select" "Pull down,Pull up"
|
|
bitfld.long 0x08 0. " SYNCPSEL ,SYNCPSEL pull select" "Pull down,Pull up"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMM-1"
|
|
base ad:0xFCFFF700
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GLBCTRL,Global Control Register"
|
|
rbitfld.long 0x00 24. " BUSY ,Busy" "Not received,Received"
|
|
bitfld.long 0x00 18. " CONTCLK ,Continuous DMMCLK output" "Suspended,Continue"
|
|
bitfld.long 0x00 17. " COS ,Continue on suspend" "Suspended,Continue"
|
|
newline
|
|
bitfld.long 0x00 16. " RESET ,Reset" "No reset,Reset"
|
|
bitfld.long 0x00 9.--10. " DDM_WIDTH ,Packet width in direct data mode" "8 bits,16 bits,32 bits,?..."
|
|
bitfld.long 0x00 8. " TM_DMM ,Packet format" "Trace mode,Direct mode"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " ON/OFF ,DMM module receives data enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
if (((per.l(ad:0xFCFFF700))&0x100)==0x100)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "INT_SET/CLR,Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " PROG_BUFF ,Programmable buffer interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " EO_BUFF ,End of buffer interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " BUSERROR ,BMM bus error response" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " BUFF_OVF ,Write buffer overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SRC_OVF ,Source overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " DEST3_ERR ,Destination 3 error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " DEST2_ERR ,Destination 2 error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " DEST1_ERR ,Destination 1 error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " DEST0_ERR ,Destination 0 error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PACKET_ERR_INT ,Packet error interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "INT_SET/CLR,Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " DEST3REG2 ,Destination 3 region 2 interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " DEST3REG1 ,Destination 3 region 1 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " DEST2REG2 ,Destination 2 region 2 interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " DEST2REG1 ,Destination 2 region 1 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " DEST1REG2 ,Destination 1 region 2 interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " DEST1REG1 ,Destination 1 region 1 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " DEST0REG2 ,Destination 0 region 2 interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " DEST0REG1 ,Destination 0 region 1 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " BUSERROR ,BMM bus error response" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " BUFF_OVF ,Write buffer overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SRC_OVF ,Source overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " DEST3_ERR ,Destination 3 error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " DEST2_ERR ,Destination 2 error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " DEST1_ERR ,Destination 1 error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " DEST0_ERR ,Destination 0 error interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PACKET_ERR_INT ,Packet error interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "INTLVL,Interrupt Level Register"
|
|
bitfld.long 0x00 17. " PROG_BUFF ,Programmable buffer interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 16. " EO_BUFF ,End of buffer interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 15. " DEST3REG2 ,Destination 3 region 2 interrupt level" "Level 0,Level 1"
|
|
newline
|
|
bitfld.long 0x00 14. " DEST3REG1 ,Destination 3 region 1 interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 13. " DEST2REG2 ,Destination 2 region 2 interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 12. " DEST2REG1 ,Destination 2 region 1 interrupt level" "Level 0,Level 1"
|
|
newline
|
|
bitfld.long 0x00 11. " DEST1REG2 ,Destination 1 region 2 interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 10. " DEST1REG1 ,Destination 1 region 1 interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 9. " DEST0REG2 ,Destination 0 region 2 interrupt level" "Level 0,Level 1"
|
|
newline
|
|
bitfld.long 0x00 8. " DEST0REG1 ,Destination 0 region 1 interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 7. " BUSERROR ,BMM bus error response" "Level 0,Level 1"
|
|
bitfld.long 0x00 6. " BUFF_OVF ,Write buffer overflow interrupt level" "Level 0,Level 1"
|
|
newline
|
|
bitfld.long 0x00 5. " SRC_OVF ,Source overflow interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 4. " DEST3_ERR ,Destination 3 error interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 3. " DEST2_ERR ,Destination 2 error interrupt level" "Level 0,Level 1"
|
|
newline
|
|
bitfld.long 0x00 2. " DEST1_ERR ,Destination 1 error interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 1. " DEST0_ERR ,Destination 0 error interrupt level" "Level 0,Level 1"
|
|
bitfld.long 0x00 0. " PACKET_ERR_INT ,Packet error interrupt level" "Level 0,Level 1"
|
|
line.long 0x04 "INTFLG,Interrupt Flag Register"
|
|
eventfld.long 0x04 17. " PROG_BUFF ,Programmable buffer interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 16. " EO_BUFF ,End of buffer interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 15. " DEST3REG2 ,Destination 3 region 2 interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 14. " DEST3REG1 ,Destination 3 region 1 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 13. " DEST2REG2 ,Destination 2 region 2 interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 12. " DEST2REG1 ,Destination 2 region 1 interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 11. " DEST1REG2 ,Destination 1 region 2 interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 10. " DEST1REG1 ,Destination 1 region 1 interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 9. " DEST0REG2 ,Destination 0 region 2 interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 8. " DEST0REG1 ,Destination 0 region 1 interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 7. " BUSERROR ,BMM bus error response" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 6. " BUFF_OVF ,Write buffer overflow interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 5. " SRC_OVF ,Source overflow interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 4. " DEST3_ERR ,Destination 3 error interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " DEST2_ERR ,Destination 2 error interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " DEST1_ERR ,Destination 1 error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 1. " DEST0_ERR ,Destination 0 error interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 0. " PACKET_ERR_INT ,Packet error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
width 18.
|
|
group.long 0x14++0x0F
|
|
line.long 0x00 "OFF1,Interrupt Offset 1 Register"
|
|
bitfld.long 0x00 0.--4. " OFFSET ,Interrupt" "Phantom,Packet error,Destination 0 error,Destination 1 error,Destination 2 error,Destination 3 error,Source overflow,Buffer overflow,Bus error,Destination 0 region 1,Destination 0 region 2,Destination 1 region 1,Destination 1 region 2,Destination 2 region 1,Destination 2 region 2,Destination 3 region 1,Destination 3 region 2,End of buffer,Programmable buffer,?..."
|
|
line.long 0x04 "OFF2,Interrupt Offset 2 Register"
|
|
bitfld.long 0x04 0.--4. " OFFSET ,Interrupt" "Phantom,Packet error,Destination 0 error,Destination 1 error,Destination 2 error,Destination 3 error,Source overflow,Buffer overflow,Bus error,Destination 0 region 1,Destination 0 region 2,Destination 1 region 1,Destination 1 region 2,Destination 2 region 1,Destination 2 region 2,Destination 3 region 1,Destination 3 region 2,End of buffer,Programmable buffer,?..."
|
|
line.long 0x08 "DDMDEST,Direct Data Mode Destination Register"
|
|
line.long 0x0C "DDMBL,Direct Data Mode Blocksize Register"
|
|
bitfld.long 0x0C 0.--3. " BLOCKSIZE ,Block size [bytes]" "Disabled,32,64,128,256,512,1024,2048,4096,8192,16384,32768,?..."
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "DDMPT,Direct Data Mode Pointer Register"
|
|
hexmask.long.word 0x00 0.--14. 0x01 " POINTER ,Pointer"
|
|
group.long 0x28++0x43
|
|
line.long 0x00 "INTPT,Direct Data Mode Interrupt Pointer Register"
|
|
hexmask.long.word 0x00 0.--14. 0x01 " INTPT ,Interrupt pointer"
|
|
line.long 0x04 "DEST0REG1,Destination 0 Region 1 Register"
|
|
hexmask.long.word 0x04 18.--31. 0x04 " BASEADDR ,Base address"
|
|
hexmask.long.tbyte 0x04 0.--17. 0x01 " BLOCKADDR ,Block address"
|
|
line.long 0x08 "DEST0BL1,Destination 0 Blocksize 1 Register"
|
|
bitfld.long 0x08 0.--3. " BLOCKSIZE ,Block size [bytes]" "Disabled,32,64,128,256,512,1024,2048,4096,8192,16384,32768,?..."
|
|
line.long 0x0C "DEST0REG2,Destination 0 Region 2 Register"
|
|
hexmask.long.word 0x0C 18.--31. 0x04 " BASEADDR ,Base address"
|
|
hexmask.long.tbyte 0x0C 0.--17. 0x01 " BLOCKADDR ,Block address"
|
|
line.long 0x10 "DEST0BL2,Destination 0 Blocksize 2 Register"
|
|
bitfld.long 0x10 0.--3. " BLOCKSIZE ,Block size [bytes]" "Disabled,32,64,128,256,512,1024,2048,4096,8192,16384,32768,?..."
|
|
line.long 0x14 "DEST1REG1,Destination 1 Region 1 Register"
|
|
hexmask.long.word 0x14 18.--31. 0x04 " BASEADDR ,Base address"
|
|
hexmask.long.tbyte 0x14 0.--17. 0x01 " BLOCKADDR ,Block address"
|
|
line.long 0x18 "DEST1BL1,Destination 1 Blocksize 1 Register"
|
|
bitfld.long 0x18 0.--3. " BLOCKSIZE ,Block size [bytes]" "Disabled,32,64,128,256,512,1024,2048,4096,8192,16384,32768,?..."
|
|
line.long 0x1C "DEST1REG2,Destination 1 Region 2 Register"
|
|
hexmask.long.word 0x1C 18.--31. 0x04 " BASEADDR ,Base address"
|
|
hexmask.long.tbyte 0x1C 0.--17. 0x01 " BLOCKADDR ,Block address"
|
|
line.long 0x20 "DEST1BL2,Destination 1 Blocksize 2 Register"
|
|
bitfld.long 0x20 0.--3. " BLOCKSIZE ,Block size [bytes]" "Disabled,32,64,128,256,512,1024,2048,4096,8192,16384,32768,?..."
|
|
line.long 0x24 "DEST2REG1,Destination 2 Region 1 Register"
|
|
hexmask.long.word 0x24 18.--31. 0x04 " BASEADDR ,Base address"
|
|
hexmask.long.tbyte 0x24 0.--17. 0x01 " BLOCKADDR ,Block address"
|
|
line.long 0x28 "DEST2BL1,Destination 2 Blocksize 1 Register"
|
|
bitfld.long 0x28 0.--3. " BLOCKSIZE ,Block size [bytes]" "Disabled,32,64,128,256,512,1024,2048,4096,8192,16384,32768,?..."
|
|
line.long 0x2C "DEST2REG2,Destination 2 Region 2 Register"
|
|
hexmask.long.word 0x2C 18.--31. 0x04 " BASEADDR ,Base address"
|
|
hexmask.long.tbyte 0x2C 0.--17. 0x01 " BLOCKADDR ,Block address"
|
|
line.long 0x30 "DEST2BL2,Destination 2 Blocksize 2 Register"
|
|
bitfld.long 0x30 0.--3. " BLOCKSIZE ,Block size [bytes]" "Disabled,32,64,128,256,512,1024,2048,4096,8192,16384,32768,?..."
|
|
line.long 0x34 "DEST3REG1,Destination 3 Region 1 Register"
|
|
hexmask.long.word 0x34 18.--31. 0x04 " BASEADDR ,Base address"
|
|
hexmask.long.tbyte 0x34 0.--17. 0x01 " BLOCKADDR ,Block address"
|
|
line.long 0x38 "DEST3BL1,Destination 3 Blocksize 1 Register"
|
|
bitfld.long 0x38 0.--3. " BLOCKSIZE ,Block size [bytes]" "Disabled,32,64,128,256,512,1024,2048,4096,8192,16384,32768,?..."
|
|
line.long 0x3C "DEST3REG2,Destination 3 Region 2 Register"
|
|
hexmask.long.word 0x3C 18.--31. 0x04 " BASEADDR ,Base address"
|
|
hexmask.long.tbyte 0x3C 0.--17. 0x01 " BLOCKADDR ,Block address"
|
|
line.long 0x40 "DEST3BL2,Destination 3 Blocksize 2 Register"
|
|
bitfld.long 0x40 0.--3. " BLOCKSIZE ,Block size [bytes]" "Disabled,32,64,128,256,512,1024,2048,4096,8192,16384,32768,?..."
|
|
newline
|
|
if (((per.l(ad:0xFCFFF700))&0x100000F)==0x0A)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PC0(FUNC),Pin Control 0 Register"
|
|
bitfld.long 0x00 18. " ENAFUNC ,Functional mode of DMMENA pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 17. " DATA15FUNC ,Functional mode of DMMDATA[15] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 16. " DATA14FUNC ,Functional mode of DMMDATA[14] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 15. " DATA13FUNC ,Functional mode of DMMDATA[13] pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x00 14. " DATA12FUNC ,Functional mode of DMMDATA[12] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 13. " DATA11FUNC ,Functional mode of DMMDATA[11] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 12. " DATA10FUNC ,Functional mode of DMMDATA[10] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 11. " DATA9FUNC ,Functional mode of DMMDATA[9] pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x00 10. " DATA8FUNC ,Functional mode of DMMDATA[8] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 9. " DATA7FUNC ,Functional mode of DMMDATA[7] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 8. " DATA6FUNC ,Functional mode of DMMDATA[6] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 7. " DATA5FUNC ,Functional mode of DMMDATA[5] pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x00 6. " DATA4FUNC ,Functional mode of DMMDATA[4] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 5. " DATA3FUNC ,Functional mode of DMMDATA[3] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 4. " DATA2FUNC ,Functional mode of DMMDATA[2] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 3. " DATA1FUNC ,Functional mode of DMMDATA[1] pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x00 2. " DATA0FUNC ,Functional mode of DMMDATA[0] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 1. " CLKFUNC ,Functional mode of DMMCLK pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 0. " SYNCFUNC ,Functional mode of DMMSYNC pin" "GIO mode,Functional mode"
|
|
else
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "PC0(FUNC),Pin Control 0 Register"
|
|
bitfld.long 0x00 18. " ENAFUNC ,Functional mode of DMMENA pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 17. " DATA15FUNC ,Functional mode of DMMDATA[15] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 16. " DATA14FUNC ,Functional mode of DMMDATA[14] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 15. " DATA13FUNC ,Functional mode of DMMDATA[13] pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x00 14. " DATA12FUNC ,Functional mode of DMMDATA[12] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 13. " DATA11FUNC ,Functional mode of DMMDATA[11] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 12. " DATA10FUNC ,Functional mode of DMMDATA[10] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 11. " DATA9FUNC ,Functional mode of DMMDATA[9] pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x00 10. " DATA8FUNC ,Functional mode of DMMDATA[8] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 9. " DATA7FUNC ,Functional mode of DMMDATA[7] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 8. " DATA6FUNC ,Functional mode of DMMDATA[6] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 7. " DATA5FUNC ,Functional mode of DMMDATA[5] pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x00 6. " DATA4FUNC ,Functional mode of DMMDATA[4] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 5. " DATA3FUNC ,Functional mode of DMMDATA[3] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 4. " DATA2FUNC ,Functional mode of DMMDATA[2] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 3. " DATA1FUNC ,Functional mode of DMMDATA[1] pin" "GIO mode,Functional mode"
|
|
newline
|
|
bitfld.long 0x00 2. " DATA0FUNC ,Functional mode of DMMDATA[0] pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 1. " CLKFUNC ,Functional mode of DMMCLK pin" "GIO mode,Functional mode"
|
|
bitfld.long 0x00 0. " SYNCFUNC ,Functional mode of DMMSYNC pin" "GIO mode,Functional mode"
|
|
endif
|
|
newline
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PC1(DIR),Pin Control 1 Register"
|
|
bitfld.long 0x00 18. " ENADIR ,Direction of DMMENA pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 17. " DATA15DIR ,Direction of DMMDATA[15] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 16. " DATA14DIR ,Direction of DMMDATA[14] pin (GIO mode)" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 15. " DATA13DIR ,Direction of DMMDATA[13] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 14. " DATA12DIR ,Direction of DMMDATA[12] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 13. " DATA11DIR ,Direction of DMMDATA[11] pin (GIO mode)" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 12. " DATA10DIR ,Direction of DMMDATA[10] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 11. " DATA9DIR ,Direction of DMMDATA[9] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 10. " DATA8DIR ,Direction of DMMDATA[8] pin (GIO mode)" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. " DATA7DIR ,Direction of DMMDATA[7] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 8. " DATA6DIR ,Direction of DMMDATA[6] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 7. " DATA5DIR ,Direction of DMMDATA[5] pin (GIO mode)" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 6. " DATA4DIR ,Direction of DMMDATA[4] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 5. " DATA3DIR ,Direction of DMMDATA[3] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 4. " DATA2DIR ,Direction of DMMDATA[2] pin (GIO mode)" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. " DATA1DIR ,Direction of DMMDATA[1] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 2. " DATA0DIR ,Direction of DMMDATA[0] pin (GIO mode)" "Input,Output"
|
|
bitfld.long 0x00 1. " CLKDIR ,Direction of DMMCLK pin (GIO mode)" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. " SYNCDIR ,Direction of DMMSYNC pin (GIO mode)" "Input,Output"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "PC2(DIN),Pin Control 2 Register"
|
|
bitfld.long 0x00 18. " ENAIN ,DMMENA input" "Low,High"
|
|
bitfld.long 0x00 17. " DATA15IN ,DMMDATA[15] input" "Low,High"
|
|
bitfld.long 0x00 16. " DATA14IN ,DMMDATA[14] input" "Low,High"
|
|
bitfld.long 0x00 15. " DATA13IN ,DMMDATA[13] input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. " DATA12IN ,DMMDATA[12] input" "Low,High"
|
|
bitfld.long 0x00 13. " DATA11IN ,DMMDATA[11] input" "Low,High"
|
|
bitfld.long 0x00 12. " DATA10IN ,DMMDATA[10] input" "Low,High"
|
|
bitfld.long 0x00 11. " DATA9IN ,DMMDATA[9] input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. " DATA8IN ,DMMDATA[8] input" "Low,High"
|
|
bitfld.long 0x00 9. " DATA7IN ,DMMDATA[7] input" "Low,High"
|
|
bitfld.long 0x00 8. " DATA6IN ,DMMDATA[6] input" "Low,High"
|
|
bitfld.long 0x00 7. " DATA5IN ,DMMDATA[5] input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " DATA4IN ,DMMDATA[4] input" "Low,High"
|
|
bitfld.long 0x00 5. " DATA3IN ,DMMDATA[3] input" "Low,High"
|
|
bitfld.long 0x00 4. " DATA2IN ,DMMDATA[2] input" "Low,High"
|
|
bitfld.long 0x00 3. " DATA1IN ,DMMDATA[1] input" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " DATA0IN ,DMMDATA[0] input" "Low,High"
|
|
bitfld.long 0x00 1. " CLKIN ,DMMCLK input" "Low,High"
|
|
bitfld.long 0x00 0. " SYNCIN ,DMMSYNC input" "Low,High"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PC3(OUT)_SET/CLR,Pin Control 3 Register"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " ENAOUT ,Output state of DMMENA pin" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DATA15OUT ,Output state of DMMDATA[15] pin" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " DATA14OUT ,Output state of DMMDATA[14] pin" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " DATA13OUT ,Output state of DMMDATA[13] pin" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " DATA12OUT ,Output state of DMMDATA[12] pin" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " DATA11OUT ,Output state of DMMDATA[11] pin" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " DATA10OUT ,Output state of DMMDATA[10] pin" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " DATA9OUT ,Output state of DMMDATA[9] pin" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " DATA8OUT ,Output state of DMMDATA[8] pin" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " DATA7OUT ,Output state of DMMDATA[7] pin" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " DATA6OUT ,Output state of DMMDATA[6] pin" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DATA5OUT ,Output state of DMMDATA[5] pin" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DATA4OUT ,Output state of DMMDATA[4] pin" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DATA3OUT ,Output state of DMMDATA[3] pin" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DATA2OUT ,Output state of DMMDATA[2] pin" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " DATA1OUT ,Output state of DMMDATA[1] pin" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DATA0OUT ,Output state of DMMDATA[0] pin" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CLKOUT ,Output state of DMMCLK pin" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SYNCOUT ,Output state of DMMSYNC pin" "Low,High"
|
|
group.long 0x84++0x0B
|
|
line.long 0x00 "PC6(PDR),Pin Control 6 Register"
|
|
bitfld.long 0x00 18. " ENAPDR ,ENAPDR open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DATA15PDR ,Open drain enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DATA14PDR ,Open drain enable 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " DATA13PDR ,Open drain enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DATA12PDR ,Open drain enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DATA11PDR ,Open drain enable 11" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " DATA10PDR ,Open drain enable 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " DATA9PDR ,Open drain enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DATA8PDR ,Open drain enable 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " DATA7PDR ,Open drain enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DATA6PDR ,Open drain enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DATA5PDR ,Open drain enable 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " DATA4PDR ,Open drain enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DATA3PDR ,Open drain enable 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DATA2PDR ,Open drain enable 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " DATA1PDR ,Open drain enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DATA0PDR ,Open drain enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CLKPDR ,CLKPDR open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " SYNCPDR ,SYNCPDR open drain enable" "Disabled,Enabled"
|
|
line.long 0x04 "PC7(PDIS),Pin Control 7 Register"
|
|
bitfld.long 0x04 18. " ENAPDIS ,ENAPDIS pull disable" "No,Yes"
|
|
bitfld.long 0x04 17. " DATA15PDIS ,Pull disable 15" "No,Yes"
|
|
bitfld.long 0x04 16. " DATA14PDIS ,Pull disable 14" "No,Yes"
|
|
bitfld.long 0x04 15. " DATA13PDIS ,Pull disable 13" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 14. " DATA12PDIS ,Pull disable 12" "No,Yes"
|
|
bitfld.long 0x04 13. " DATA11PDIS ,Pull disable 11" "No,Yes"
|
|
bitfld.long 0x04 12. " DATA10PDIS ,Pull disable 10" "No,Yes"
|
|
bitfld.long 0x04 11. " DATA9PDIS ,Pull disable 9" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 10. " DATA8PDIS ,Pull disable 8" "No,Yes"
|
|
bitfld.long 0x04 9. " DATA7PDIS ,Pull disable 7" "No,Yes"
|
|
bitfld.long 0x04 8. " DATA6PDIS ,Pull disable 6" "No,Yes"
|
|
bitfld.long 0x04 7. " DATA5PDIS ,Pull disable 5" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 6. " DATA4PDIS ,Pull disable 4" "No,Yes"
|
|
bitfld.long 0x04 5. " DATA3PDIS ,Pull disable 3" "No,Yes"
|
|
bitfld.long 0x04 4. " DATA2PDIS ,Pull disable 2" "No,Yes"
|
|
bitfld.long 0x04 3. " DATA1PDIS ,Pull disable 1" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 2. " DATA0PDIS ,Pull disable 0" "No,Yes"
|
|
bitfld.long 0x04 1. " CLKPDIS ,CLKPDIS pull disable" "No,Yes"
|
|
bitfld.long 0x04 0. " SYNCPDIS ,SYNCPDIS pull disable" "No,Yes"
|
|
line.long 0x08 "PC8(PSEL),Pin Control 8 Register"
|
|
bitfld.long 0x08 18. " ENAPSEL ,ENAPSEL pull select" "Pull down,Pull up"
|
|
bitfld.long 0x08 17. " DATA15PSEL ,Pull select 15" "Pull down,Pull up"
|
|
bitfld.long 0x08 16. " DATA14PSEL ,Pull select 14" "Pull down,Pull up"
|
|
bitfld.long 0x08 15. " DATA13PSEL ,Pull select 13" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 14. " DATA12PSEL ,Pull select 12" "Pull down,Pull up"
|
|
bitfld.long 0x08 13. " DATA11PSEL ,Pull select 11" "Pull down,Pull up"
|
|
bitfld.long 0x08 12. " DATA10PSEL ,Pull select 10" "Pull down,Pull up"
|
|
bitfld.long 0x08 11. " DATA9PSEL ,Pull select 9" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 10. " DATA8PSEL ,Pull select 8" "Pull down,Pull up"
|
|
bitfld.long 0x08 9. " DATA7PSEL ,Pull select 7" "Pull down,Pull up"
|
|
bitfld.long 0x08 8. " DATA6PSEL ,Pull select 6" "Pull down,Pull up"
|
|
bitfld.long 0x08 7. " DATA5PSEL ,Pull select 5" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 6. " DATA4PSEL ,Pull select 4" "Pull down,Pull up"
|
|
bitfld.long 0x08 5. " DATA3PSEL ,Pull select 3" "Pull down,Pull up"
|
|
bitfld.long 0x08 4. " DATA2PSEL ,Pull select 2" "Pull down,Pull up"
|
|
bitfld.long 0x08 3. " DATA1PSEL ,Pull select 1" "Pull down,Pull up"
|
|
newline
|
|
bitfld.long 0x08 2. " DATA0PSEL ,Pull select 0" "Pull down,Pull up"
|
|
bitfld.long 0x08 1. " CLKPDSEL ,CLKPDSEL pull select" "Pull down,Pull up"
|
|
bitfld.long 0x08 0. " SYNCPSEL ,SYNCPSEL pull select" "Pull down,Pull up"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "EPWM (Enhanced Pulse Width Modulator)"
|
|
tree "MSS_ETPWM1"
|
|
base ad:0xFCF78C00
|
|
width 24.
|
|
if (((per.l(ad:0xFCF78C00))&0x33)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/Status Register"
|
|
eventfld.long 0x00 18. " TBSTS_CTRMAX ,Time-base counter max latched status bit time-base counter maximum value" "Not reached,Reached"
|
|
eventfld.long 0x00 17. " TBSTS_SYNCI ,Input synchronization latched status bit external synchronization event" "Not occurred,Occurred"
|
|
newline
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
bitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
else
|
|
rbitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " TBCTL_FREE/SOFT ,Emulation mode bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
|
|
newline
|
|
bitfld.long 0x00 13. " TBCTL_PHSDIR ,Phase direction bit" "Count down,Count up"
|
|
bitfld.long 0x00 10.--12. " TBCTL_CLKDIV ,Time-base clock prescale bits" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
newline
|
|
bitfld.long 0x00 7.--9. " TBCTL_HSPCLKDIV ,High speed time-base clock prescale bits" "/1,/2,/4,/6,/8,/10,/12,/14"
|
|
bitfld.long 0x00 6. " TBCTL_SWFSYNC ,Software forced synchronization pulse" "No effect,Generated"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TBCTL_SYNCOSEL ,Synchronization output select" "EPWMxSYNC,CTR = 0,CTR = CMPB,Disabled"
|
|
bitfld.long 0x00 3. " TBCTL_PRDLD ,Active period register load from shadow register select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 2. " TBCTL_PHSEN ,Counter register load from phase register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TBCTL_CTRMODE ,Counter mode" "Up-count,Down-count,Up-down-count,Stop-freeze"
|
|
elif (((per.l(ad:0xFCF78C00))&0x30)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/Status Register"
|
|
eventfld.long 0x00 18. " TBSTS_CTRMAX ,Time-base counter max latched status bit time-base counter maximum value" "Not reached,Reached"
|
|
eventfld.long 0x00 17. " TBSTS_SYNCI ,Input synchronization latched status bit external synchronization event" "Not occurred,Occurred"
|
|
newline
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
bitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
else
|
|
rbitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " TBCTL_FREE/SOFT ,Emulation mode bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
|
|
newline
|
|
bitfld.long 0x00 10.--12. " TBCTL_CLKDIV ,Time-base clock prescale bits" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
newline
|
|
bitfld.long 0x00 7.--9. " TBCTL_HSPCLKDIV ,High speed time-base clock prescale bits" "/1,/2,/4,/6,/8,/10,/12,/14"
|
|
bitfld.long 0x00 6. " TBCTL_SWFSYNC ,Software forced synchronization pulse" "No effect,Generated"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TBCTL_SYNCOSEL ,Synchronization output select" "EPWMxSYNC,CTR = 0,CTR = CMPB,Disabled"
|
|
bitfld.long 0x00 3. " TBCTL_PRDLD ,Active period register load from shadow register select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 2. " TBCTL_PHSEN ,Counter register load from phase register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TBCTL_CTRMODE ,Counter mode" "Up-count,Down-count,Up-down-count,Stop-freeze"
|
|
elif (((per.l(ad:0xFCF78C00))&0x03)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/Status Register"
|
|
eventfld.long 0x00 18. " TBSTS_CTRMAX ,Time-base counter max latched status bit time-base counter maximum value" "Not reached,Reached"
|
|
eventfld.long 0x00 17. " TBSTS_SYNCI ,Input synchronization latched status bit external synchronization event" "Not occurred,Occurred"
|
|
newline
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
bitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
else
|
|
rbitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " TBCTL_FREE/SOFT ,Emulation mode bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
|
|
newline
|
|
bitfld.long 0x00 13. " TBCTL_PHSDIR ,Phase direction bit" "Count down,Count up"
|
|
bitfld.long 0x00 10.--12. " TBCTL_CLKDIV ,Time-base clock prescale bits" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
newline
|
|
bitfld.long 0x00 7.--9. " TBCTL_HSPCLKDIV ,High speed time-base clock prescale bits" "/1,/2,/4,/6,/8,/10,/12,/14"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TBCTL_SYNCOSEL ,Synchronization output select" "EPWMxSYNC,CTR = 0,CTR = CMPB,Disabled"
|
|
bitfld.long 0x00 3. " TBCTL_PRDLD ,Active period register load from shadow register select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 2. " TBCTL_PHSEN ,Counter register load from phase register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TBCTL_CTRMODE ,Counter mode" "Up-count,Down-count,Up-down-count,Stop-freeze"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/Status Register"
|
|
eventfld.long 0x00 18. " TBSTS_CTRMAX ,Time-base counter max latched status bit time-base counter maximum value" "Not reached,Reached"
|
|
eventfld.long 0x00 17. " TBSTS_SYNCI ,Input synchronization latched status bit external synchronization event" "Not occurred,Occurred"
|
|
newline
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
bitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
else
|
|
rbitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " TBCTL_FREE/SOFT ,Emulation mode bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
|
|
newline
|
|
bitfld.long 0x00 10.--12. " TBCTL_CLKDIV ,Time-base clock prescale bits" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
newline
|
|
bitfld.long 0x00 7.--9. " TBCTL_HSPCLKDIV ,High speed time-base clock prescale bits" "/1,/2,/4,/6,/8,/10,/12,/14"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TBCTL_SYNCOSEL ,Synchronization output select" "EPWMxSYNC,CTR = 0,CTR = CMPB,Disabled"
|
|
bitfld.long 0x00 3. " TBCTL_PRDLD ,Active period register load from shadow register select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 2. " TBCTL_PHSEN ,Counter register load from phase register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TBCTL_CTRMODE ,Counter mode" "Up-count,Down-count,Up-down-count,Stop-freeze"
|
|
endif
|
|
group.long 0x04++0x3B
|
|
line.long 0x00 "TBPHS,Time-Base Phase Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TBPHS ,Time-base phase"
|
|
line.long 0x04 "TBCTR_TBPRD,Time-Base Counter Register/Period Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " TBPRD ,Time-base period"
|
|
hexmask.long.word 0x04 0.--15. 1. " TBCTR ,Time-base counter"
|
|
line.long 0x08 "CMPCTL,Counter-Compare Control Register"
|
|
bitfld.long 0x08 25. " SHDWBFULL ,Counter-compare B CMPB shadow register full status flag" "Not full,Full"
|
|
bitfld.long 0x08 24. " SHDWAFULL ,Counter-compare A CMPA shadow register full status flag" "Not full,Full"
|
|
newline
|
|
bitfld.long 0x08 22. " SHDWBMODE ,Counter-compare B" "Shadow mode,Immediate mode"
|
|
bitfld.long 0x08 20. " SHDWAMODE ,Counter-compare A CMPA register operating mode" "Shadow mode,Immediate mode"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " LOADBMODE ,Active Counter-Compare B CMPB load from shadow select mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
|
|
bitfld.long 0x08 16.--17. " LOADAMODE ,Active Counter-Compare A CMPA load from shadow select mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
|
|
line.long 0x0C "CMPA,Counter-Compare A Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " CMPA ,Counter-Compare A"
|
|
line.long 0x10 "CMPB_AQCTLA,Counter-Compare B Register/Action-Qualifier Control Register For Output A (ePWMxA)"
|
|
bitfld.long 0x10 26.--27. " AQCTLA_CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle"
|
|
bitfld.long 0x10 24.--25. " AQCTLA_CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle"
|
|
newline
|
|
bitfld.long 0x10 22.--23. " AQCTLA_CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle"
|
|
bitfld.long 0x10 20.--21. " AQCTLA_CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle"
|
|
newline
|
|
bitfld.long 0x10 18.--19. " AQCTLA_PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggle"
|
|
bitfld.long 0x10 16.--17. " AQCTLA_ZRO ,Action when counter equals 0" "Disabled,Clear,Set,Toggle"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. " CMPB ,Counter-compare B"
|
|
line.long 0x14 "AQCTLB_AQSFRC,Action-Qualifier Control Register For Output B (ePWMxB)/Action-Qualifier Software Force Register"
|
|
bitfld.long 0x14 22.--23. " AQSFRC_RLDCSF ,AQCSFRC active register reload from shadow options" "0,Period,0/Period,Immediately"
|
|
bitfld.long 0x14 21. " AQSFRC_OTSFB ,One-time software forced event on output B" "No effect,Event"
|
|
newline
|
|
bitfld.long 0x14 19.--20. " AQSFRC_ACTSFB ,Action when One-time software force B is invoked" "No effect,Clear,Set,Toggle"
|
|
bitfld.long 0x14 18. " AQSFRC_OTSFA ,One-time software forced event on output A" "No effect,Forced event"
|
|
newline
|
|
bitfld.long 0x14 16.--17. " AQSFRC_ACTSFA ,Action when One-time software force A is invoked" "No effect,Clear,Set,Toggle"
|
|
bitfld.long 0x14 10.--11. " AQCTLB_CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x14 8.--9. " AQCTLB_CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
|
|
bitfld.long 0x14 6.--7. " AQCTLB_CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x14 4.--5. " AQCTLB_CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
|
|
bitfld.long 0x14 2.--3. " AQCTLB_PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x14 0.--1. " AQCTLB_ZRO ,Action when counter equals 0" "Disabled,Cleared,Set,Toggled"
|
|
line.long 0x18 "AQCSFRC_DBCTL,Dead-Band Generator Control Register/Action-Qualifier Continuous S/W Force Register Set"
|
|
bitfld.long 0x18 31. " DBCTL_HALFCYCLE ,Half cycle clocking enable bit" "Full cycle,Half cycle"
|
|
bitfld.long 0x18 20.--21. " DBCTL_IN_MODE ,Dead band input mode control" "EPWMxA falling/rising edge,EPWMxB rising/EPWMxA falling edge,EPWMxA rising/EPWMxB falling edge,EPWMxB rising/falling edge"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DBCTL_POLSEL ,Polarity select control" "Active high,Active low complementary,Active high complementary,Active low"
|
|
bitfld.long 0x18 16.--17. " DBCTL_OUT_MODE ,Dead-band output mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 2.--3. " AQCSFRC_CSFB ,Continuous software force on output B" "Forced disabled,Continued low,Continued high,Software forced disabled"
|
|
bitfld.long 0x18 0.--1. " AQCSFRC_CSFA ,Continuous software force on output A" "Forced disabled,Continued low,Continued high,Software forced disabled"
|
|
line.long 0x1C "DBRED_DBFED,Dead-Band Generator Rising Edge Delay Count Register/Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.long.word 0x1C 16.--25. 1. " DBFED_DEL ,Falling edge delay count"
|
|
hexmask.long.word 0x1C 0.--9. 1. " DBRED_DEL ,Rising edge delay count"
|
|
line.long 0x20 "TZSEL_TZDCSEL,Trip Zone Digital Compare Select Register/Trip-Zone Select Register"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
bitfld.long 0x20 25.--27. " TZDCSEL_DCBEVT2 ,Digital compare output B event 2 selection [DCBH/DCBL]" "Disabled,LOW/-,HIGH/-,-/LOW,-/HIGH,LOW/HIGH,?..."
|
|
bitfld.long 0x20 22.--24. " TZDCSEL_DCBEVT1 ,Digital compare output B event 1 selection [DCBH/DCBL]" "Disabled,LOW/-,HIGH/-,-/LOW,-/HIGH,LOW/HIGH,?..."
|
|
newline
|
|
bitfld.long 0x20 19.--21. " TZDCSEL_DCAEVT2 ,Digital compare output A event 2 selection [DCAH/DCAL]" "Disabled,LOW/-,HIGH/-,-/LOW,-/HIGH,LOW/HIGH,?..."
|
|
bitfld.long 0x20 16.--18. " TZDCSEL_DCAEVT1 ,Digital compare output A event 1 selection [DCAH/DCAL]" "Disabled,LOW/-,HIGH/-,-/LOW,-/HIGH,LOW/HIGH,?..."
|
|
else
|
|
bitfld.long 0x20 25.--27. " TZDCSEL_DCBEVT2 ,Digital compare output B event 2 selection" "Disabled,DCBH=LOW_DCBL=?,DCBH=HIGH,DCBL=?,DCBL=LOW_DCBH=?,DCBL=HIGH,DCBH=?,DCBL=HIGH_DCBH=LOW"
|
|
bitfld.long 0x20 22.--24. " TZDCSEL_DCBEVT1 ,Digital compare output B event 1 selection" "Disabled,DCBH=LOW_DCBL=?,DCBH=HIGH,DCBL=?,DCBL=LOW_DCBH=?,DCBL=HIGH,DCBH=?,DCBL=HIGH_DCBH=LOW"
|
|
newline
|
|
bitfld.long 0x20 19.--21. " TZDCSEL_DCAEVT2 ,Digital compare output A event 2 selection" "Disabled,DCAH=LOW/DCAL=?,DCAH=HIGH,DCAL=?,DCAL=LOW/DCAH=?,DCAL=HIGH,DCAH=?,DCAL=HIGH/DCAH=LOW"
|
|
bitfld.long 0x20 16.--18. " TZDCSEL_DCAEVT1 ,Digital compare output A event 1 selection" "Disabled,DCAH=LOW/DCAL=?,DCAH=HIGH,DCAL=?,DCAL=LOW/DCAH=?,DCAL=HIGH,DCAH=?,DCAL=HIGH/DCAH=LOW"
|
|
endif
|
|
newline
|
|
bitfld.long 0x20 15. " TZSEL_DCBEVT1 ,Digital compare output B event 1 select" "Disabled,Enabled"
|
|
bitfld.long 0x20 14. " TZSEL_DCAEVT1 ,Digital compare output A event 1 select" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 13. " TZSEL_OSHT6 ,Use TZ6 as One-shot trip source for ePWM" "Disabled,Enabled"
|
|
bitfld.long 0x20 12. " TZSEL_OSHT5 ,Use TZ5 as One-shot trip source for ePWM" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 11. " TZSEL_OSHT4 ,Use TZ4 as One-shot trip source for ePWM" "Disabled,Enabled"
|
|
bitfld.long 0x20 10. " TZSEL_OSHT3 ,Use TZ3 as One-shot trip source for ePWM" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 9. " TZSEL_OSHT2 ,Use TZ2 as One-shot trip source for ePWM" "Disabled,Enabled"
|
|
bitfld.long 0x20 8. " TZSEL_OSHT1 ,Use TZ1 as One-shot trip source for ePWM" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 7. " TZSEL_DCBEVT2 ,Digital compare output B event 2" "Disabled,Enabled"
|
|
bitfld.long 0x20 6. " TZSEL_DCAEVT2 ,Digital compare output A event 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 5. " TZSEL_CBC6 ,Trip-zone 6" "Disabled,Enabled"
|
|
bitfld.long 0x20 4. " TZSEL_CBC5 ,Trip-zone 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 3. " TZSEL_CBC4 ,Trip-zone 4" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " TZSEL_CBC3 ,Trip-zone 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 1. " TZSEL_CBC2 ,Trip-zone 2" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " TZSEL_CBC1 ,Trip-zone 1" "Disabled,Enabled"
|
|
line.long 0x24 "TZCTL_TZEINT,Trip-Zone Control Register/Trip-Zone Enable Interrupt Register"
|
|
bitfld.long 0x24 22. " TZEINT_DCBEVT2 ,Digital comparator output B event 2" "Disabled,Enabled"
|
|
bitfld.long 0x24 21. " TZEINT_DCBEVT1 ,Digital comparator output B event 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 20. " TZEINT_DCAEVT2 ,Digital comparator output A event 2" "Disabled,Enabled"
|
|
bitfld.long 0x24 19. " TZEINT_DCAEVT1 ,Digital comparator output A event 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 18. " TZEINT_OST ,Trip-zone One-Shot interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 17. " TZEINT_CBC ,Trip-zone Cycle-by-Cycle interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 10.--11. " TZCTL_DCBEVT2 ,Digital compare output B event 2 action on ePWMxB" "High-impedance,Forced high,Forced low,Disabled"
|
|
bitfld.long 0x24 8.--9. " TZCTL_DCBEVT1 ,Digital compare output B event 1 action on ePWMxB" "High-impedance,Forced high,Forced low,Disabled"
|
|
newline
|
|
bitfld.long 0x24 6.--7. " TZCTL_DCAEVT2 ,Digital compare output A event 2 action on ePWMxA" "High-impedance,Forced high,Forced low,Disabled"
|
|
bitfld.long 0x24 4.--5. " TZCTL_DCAEVT1 ,Digital compare output A event 1 action on ePWMxA" "High-impedance,Forced high,Forced low,Disabled"
|
|
newline
|
|
bitfld.long 0x24 2.--3. " TZCTL_TZB ,Action on output ePWMxB" "High-impedance,Forced high,Forced low,Disabled"
|
|
bitfld.long 0x24 0.--1. " TZCTL_TZA ,Action on output ePWMxA" "High-impedance,Forced high,Forced low,Disabled"
|
|
line.long 0x28 "TZFLG_TZ_SET/CLR,Trip-Zone Flag Register/Trip-Zone Set/Clear Register"
|
|
setclrfld.long 0x28 6. 0x2C 6. 0x28 22. " DCBEVT2 ,Digital comparator output B event 2 interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x28 5. 0x2C 5. 0x28 21. " DCBEVT1 ,Digital comparator output B event 1 interrupt" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x28 4. 0x2C 4. 0x28 20. " DCAEVT2 ,Digital comparator output A event 2 interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x28 3. 0x2C 3. 0x28 19. " DCAEVT1 ,Digital comparator output A event 1 interrupt" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x28 2. 0x2C 2. 0x28 18. " OST ,Trip-zone one-Shot interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x28 1. 0x2C 1. 0x28 17. " CBC ,Trip-zone cycle-by-cycle interrupt" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x28 0. 0x2C 0. 0x28 16. " INT ,Latched trip interrupt status flag" "Not generated,Generated"
|
|
line.long 0x2C "TZFRC_ETSEL,Trip-Zone Force Register/Event-Trigger Selection Register"
|
|
bitfld.long 0x2C 31. " ETSEL_SOCBEN ,Enable the ADC start of conversion B ePWMxSOCB pulse" "Disabled,Enabled"
|
|
bitfld.long 0x2C 28.--30. " ETSEL_SOCBSEL ,ePWMxSOCB selection options" "DCBEVT1_soc,TBCTR=0,TBCTR=period,TBCTR=0/period,TBCTR=CMPA timer INC,TBCTR=CMPA,TBCTR=CMPB timer INC,TBCTR=CMPB"
|
|
newline
|
|
bitfld.long 0x2C 27. " ETSEL_SOCAEN ,Enable the ADC start of conversion A ePWMxSOCA pulse" "Disabled,Enabled"
|
|
bitfld.long 0x2C 24.--26. " ETSEL_SOCASEL ,ePWMxSOCA selection options" "DCBEVT1_soc,TBCTR=0,TBCTR=period,TBCTR=0/period,TBCTR=CMPA timer INC,TBCTR=CMPA,TBCTR=CMPB timer INC,TBCTR=CMPB"
|
|
newline
|
|
bitfld.long 0x2C 19. " ETSEL_INTEN ,Enable ePWM interrupt ePWMx_INT generation" "Disabled,Enabled"
|
|
bitfld.long 0x2C 16.--18. " ETSEL_INTSEL ,ePWM interrupt ePWMx_INT selection options" ",TBCTR=0,TBCTR=period,TBCTR=0/period,TBCTR=CMPA timer INC,TBCTR=CMPA,TBCTR=CMPB timer INC,TBCTR=CMPB"
|
|
newline
|
|
bitfld.long 0x2C 6. " TZFRC_DCBEVT2 ,Force flag for digital compare output B event 2" "Not forced,Forced"
|
|
bitfld.long 0x2C 5. " TZFRC_DCBEVT1 ,Force flag for digital compare output B event 1" "Not forced,Forced"
|
|
newline
|
|
bitfld.long 0x2C 4. " TZFRC_DCAEVT2 ,Force flag for digital compare output A event 2" "Not forced,Forced"
|
|
bitfld.long 0x2C 3. " TZFRC_DCAEVT1 ,Force flag for digital compare output A event 1" "Not forced,Forced"
|
|
newline
|
|
bitfld.long 0x2C 2. " TZFRC_OST ,Force a one-shot trip event via software 0" "Not forced,Forced"
|
|
bitfld.long 0x2C 1. " TZFRC_CBC ,Force a cycle-by-cycle trip event via software 0" "Not forced,Forced"
|
|
line.long 0x30 "ETPS_ETFLG,Event-Trigger Pre-Scale Register/Event-Trigger Flag Register"
|
|
bitfld.long 0x30 19. " ETFLG_SOCB ,Latched ePWM ADC start-of-conversion B ePWMxSOCB status flag" "Not occurred,Occurred"
|
|
bitfld.long 0x30 18. " ETFLG_SOCA ,Latched ePWM ADC start-of-conversion A ePWMxSOCA status flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x30 16. " ETFLG_INT ,Latched ePWM interrupt ePWMx_INT status flag" "Not occurred,Occurred"
|
|
bitfld.long 0x30 14.--15. " ETPS_SOCBCNT ,ePWM ADC start-of-conversion B event ePWMxSOCB counter register" "No events,1 event,2 events,3 events"
|
|
newline
|
|
bitfld.long 0x30 12.--13. " ETPS_SOCBPRD ,ePWM ADC start-of-conversion B event ePWMxSOCB period select" "Disabled,1st event,2nd event,3rd event"
|
|
bitfld.long 0x30 10.--11. " ETPS_SOCACNT ,ePWM ADC start-of-conversion A event ePWMxSOCA counter register" "No events,1 event,2 events,3 events"
|
|
newline
|
|
bitfld.long 0x30 8.--9. " ETPS_SOCAPRD ,ePWM ADC start-of-conversion A event ePWMxSOCA period select" "Disabled,1st event,2nd event,3rd event"
|
|
bitfld.long 0x30 2.--3. " ETPS_INTCNT ,ePWM interrupt event ePWMx_INT counter register" "No events,1 event,2 events,3 events"
|
|
newline
|
|
bitfld.long 0x30 0.--1. " ETPS_INTPRD ,ePWM interrupt ePWMx_INT period select" "Disabled,1st event,2nd event,3rd event"
|
|
line.long 0x34 "ETCLR_ETFRC,Event-Trigger Clear Register/Event-Trigger Force Register"
|
|
bitfld.long 0x34 19. " ETFRC_SOCB ,SOCB force bit" "No effect,Forced"
|
|
bitfld.long 0x34 18. " ETFRC_SOCA ,SOCA force bit" "No effect,Forced"
|
|
newline
|
|
bitfld.long 0x34 16. " ETFRC_INT ,INT force bit" "No effect,Forced"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
eventfld.long 0x34 3. " ETCLR_SOCB ,ePWM ADC start-of-conversion B ePWMxSOCB flag clear bit" "No effect,Cleared"
|
|
newline
|
|
eventfld.long 0x34 2. " ETCLR_SOCA ,ePWM ADC start-of-conversion A ePWMxSOCB flag clear bit" "No effect,Cleared"
|
|
eventfld.long 0x34 0. " ETCLR_INT ,ePWM interrupt ePWMx_INT flag clear bit" "No effect,Cleared"
|
|
else
|
|
bitfld.long 0x34 3. " ETCLR_SOCB ,ePWM ADC start-of-Conversion B ePWMxSOCB flag clear bit" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x34 2. " ETCLR_SOCA ,ePWM ADC start-of-conversion A ePWMxSOCB flag clear bit" "No effect,Cleared"
|
|
bitfld.long 0x34 0. " ETCLR_INT ,ePWM interrupt ePWMx_INT flag clear bit" "No effect,Cleared"
|
|
endif
|
|
line.long 0x38 "PCCTL,PWM-Chopper Control Register"
|
|
bitfld.long 0x38 8.--10. " CHPDUTY ,Chopping clock duty cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,?..."
|
|
bitfld.long 0x38 5.--7. " CHPFREQ ,Chopping clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
newline
|
|
bitfld.long 0x38 1.--4. " OSHTWTH ,One-Shot pulse width" "1 x VCLK3 / 8 wide,2 x VCLK3 / 8 wide,3 x VCLK3 / 8 wide,4 x VCLK3 / 8 wide,5 x VCLK3 / 8 wide,6 x VCLK3 / 8 wide,7 x VCLK3 / 8 wide,8 x VCLK3 / 8 wide,9 x VCLK3 / 8 wide,10 x VCLK3 / 8 wide,11 x VCLK3 / 8 wide,12 x VCLK3 / 8 wide,13 x VCLK3 / 8 wide,14 x VCLK3 / 8 wide,15 x VCLK3 / 8 wide,16 x VCLK3 / 8 wide"
|
|
bitfld.long 0x38 0. " CHPEN ,PWM-chopping enable" "Disabled,Enabled"
|
|
group.long 0x60++0x13
|
|
line.long 0x00 "DCTRIPSEL_DCACTL,Digital Compare Trip Select Register/Digital Compare A Control Register"
|
|
bitfld.long 0x00 25. " DCACTL_EVT2FRC_SYNCSEL ,DCAEVT2 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 24. " DCACTL_EVT2SRCSEL ,DCAEVT2 source signal select" "DCAEVT2,DCEVTFILT"
|
|
newline
|
|
bitfld.long 0x00 19. " DCACTL_EVT1SYNCE ,DCAEVT1 SYNC generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DCACTL_EVT1SOCE ,DCAEVT1 SOC generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " DCACTL_EVT1FRC_SYNCSEL ,DCAEVT1 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 16. " DCACTL_EVT1SRCSEL ,DCAEVT1 source signal select" "DCAEVT,DCEVTFILT"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " DCTRIPSEL_DCBLCOMPSEL ,Digital compare B low input select" "TZ1 input,TZ2 input,TZ3 input,?..."
|
|
bitfld.long 0x00 8.--11. " DCTRIPSEL_DCBHCOMPSEL ,Digital compare B high input select" "TZ1 input,TZ2 input,TZ3 input,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " DCTRIPSEL/DCALCOMPSEL ,Digital compare A low input select" "TZ1 input,TZ2 input,TZ3 input,?..."
|
|
bitfld.long 0x00 0.--3. " DCTRIPSEL/DCAHCOMPSEL ,Digital compare A high input select" "TZ1 input,TZ2 input,TZ3 input,?..."
|
|
line.long 0x04 "DCBCTL_DCFCTL,Digital Compare B Control Register/Digital Compare Filter Control Register"
|
|
bitfld.long 0x04 20.--21. " DCFCTL_PULSESEL ,Pulse select for blanking & capture alignment" "TBCTR = TBPRD,TBCTR = 0,?..."
|
|
bitfld.long 0x04 19. " DCFCTL_BLANKINV ,Blanking window inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x04 18. " DCFCTL_BLANKE ,Blanking window enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--17. " DCFCTL_SRCSEL ,Filter block signal source select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2"
|
|
newline
|
|
bitfld.long 0x04 9. " DCBCTL_EVT2FRC_SYNCSEL ,DCBEVT2 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.long 0x04 8. " DCBCTL_EVT2SRCSEL ,DCBEVT2 source signal select" "DCBEVT2,DCEVTFILT"
|
|
newline
|
|
bitfld.long 0x04 3. " DCBCTL_EVT1SYNCE ,DCBEVT1 SYNC generation" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " DCBCTL_EVT1SOCE ,DCBEVT1 SOC generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " DCBCTL_EVT1FRC_SYNCSEL ,DCBEVT1 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.long 0x04 0. " DCBCTL_EVT1SRCSEL ,DCBEVT1 source signal select" "DCBEVT1,DCEVTFILT"
|
|
line.long 0x08 "DCCAPCTL_DCFOFFSET,Digital Compare Capture Control Register/Digital Compare Filter Offset Register"
|
|
hexmask.long.word 0x08 16.--31. 0x01 " DCFOFFSET_OFFSET ,Blanking window offset"
|
|
bitfld.long 0x08 1. " DCCAPCTL_SHDWMODE ,TBCTR counter capture shadow select mode" "Shadow mode,Active mode"
|
|
newline
|
|
bitfld.long 0x08 0. " DCCAPCTL_CAPE ,TBCTR counter capture enable" "Disabled,Enabled"
|
|
line.long 0x0C "DCFOFFSETCNT_DCFWINDOW,Digital Compare Filter Offset Counter Register/Digital Compare Filter Window Register"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " DCFWINDOW_WINDOW ,Blanking window width"
|
|
hexmask.long.word 0x0C 0.--15. 0x01 " DCFOFFSETCNT_OFFSETCNT ,Blanking offset counter"
|
|
line.long 0x10 "DCFWINDOWCNT_DCCAP,Digital Compare Filter Window Counter Register/Digital Compare Counter Capture Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " DCCAP ,Digital compare time-base counter capture"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DCFWINDOWCNT ,Blanking window counter"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MSS_ETPWM2"
|
|
base ad:0xFCF78D00
|
|
width 24.
|
|
if (((per.l(ad:0xFCF78D00))&0x33)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/Status Register"
|
|
eventfld.long 0x00 18. " TBSTS_CTRMAX ,Time-base counter max latched status bit time-base counter maximum value" "Not reached,Reached"
|
|
eventfld.long 0x00 17. " TBSTS_SYNCI ,Input synchronization latched status bit external synchronization event" "Not occurred,Occurred"
|
|
newline
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
bitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
else
|
|
rbitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " TBCTL_FREE/SOFT ,Emulation mode bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
|
|
newline
|
|
bitfld.long 0x00 13. " TBCTL_PHSDIR ,Phase direction bit" "Count down,Count up"
|
|
bitfld.long 0x00 10.--12. " TBCTL_CLKDIV ,Time-base clock prescale bits" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
newline
|
|
bitfld.long 0x00 7.--9. " TBCTL_HSPCLKDIV ,High speed time-base clock prescale bits" "/1,/2,/4,/6,/8,/10,/12,/14"
|
|
bitfld.long 0x00 6. " TBCTL_SWFSYNC ,Software forced synchronization pulse" "No effect,Generated"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TBCTL_SYNCOSEL ,Synchronization output select" "EPWMxSYNC,CTR = 0,CTR = CMPB,Disabled"
|
|
bitfld.long 0x00 3. " TBCTL_PRDLD ,Active period register load from shadow register select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 2. " TBCTL_PHSEN ,Counter register load from phase register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TBCTL_CTRMODE ,Counter mode" "Up-count,Down-count,Up-down-count,Stop-freeze"
|
|
elif (((per.l(ad:0xFCF78D00))&0x30)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/Status Register"
|
|
eventfld.long 0x00 18. " TBSTS_CTRMAX ,Time-base counter max latched status bit time-base counter maximum value" "Not reached,Reached"
|
|
eventfld.long 0x00 17. " TBSTS_SYNCI ,Input synchronization latched status bit external synchronization event" "Not occurred,Occurred"
|
|
newline
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
bitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
else
|
|
rbitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " TBCTL_FREE/SOFT ,Emulation mode bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
|
|
newline
|
|
bitfld.long 0x00 10.--12. " TBCTL_CLKDIV ,Time-base clock prescale bits" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
newline
|
|
bitfld.long 0x00 7.--9. " TBCTL_HSPCLKDIV ,High speed time-base clock prescale bits" "/1,/2,/4,/6,/8,/10,/12,/14"
|
|
bitfld.long 0x00 6. " TBCTL_SWFSYNC ,Software forced synchronization pulse" "No effect,Generated"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TBCTL_SYNCOSEL ,Synchronization output select" "EPWMxSYNC,CTR = 0,CTR = CMPB,Disabled"
|
|
bitfld.long 0x00 3. " TBCTL_PRDLD ,Active period register load from shadow register select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 2. " TBCTL_PHSEN ,Counter register load from phase register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TBCTL_CTRMODE ,Counter mode" "Up-count,Down-count,Up-down-count,Stop-freeze"
|
|
elif (((per.l(ad:0xFCF78D00))&0x03)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/Status Register"
|
|
eventfld.long 0x00 18. " TBSTS_CTRMAX ,Time-base counter max latched status bit time-base counter maximum value" "Not reached,Reached"
|
|
eventfld.long 0x00 17. " TBSTS_SYNCI ,Input synchronization latched status bit external synchronization event" "Not occurred,Occurred"
|
|
newline
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
bitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
else
|
|
rbitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " TBCTL_FREE/SOFT ,Emulation mode bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
|
|
newline
|
|
bitfld.long 0x00 13. " TBCTL_PHSDIR ,Phase direction bit" "Count down,Count up"
|
|
bitfld.long 0x00 10.--12. " TBCTL_CLKDIV ,Time-base clock prescale bits" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
newline
|
|
bitfld.long 0x00 7.--9. " TBCTL_HSPCLKDIV ,High speed time-base clock prescale bits" "/1,/2,/4,/6,/8,/10,/12,/14"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TBCTL_SYNCOSEL ,Synchronization output select" "EPWMxSYNC,CTR = 0,CTR = CMPB,Disabled"
|
|
bitfld.long 0x00 3. " TBCTL_PRDLD ,Active period register load from shadow register select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 2. " TBCTL_PHSEN ,Counter register load from phase register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TBCTL_CTRMODE ,Counter mode" "Up-count,Down-count,Up-down-count,Stop-freeze"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/Status Register"
|
|
eventfld.long 0x00 18. " TBSTS_CTRMAX ,Time-base counter max latched status bit time-base counter maximum value" "Not reached,Reached"
|
|
eventfld.long 0x00 17. " TBSTS_SYNCI ,Input synchronization latched status bit external synchronization event" "Not occurred,Occurred"
|
|
newline
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
bitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
else
|
|
rbitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " TBCTL_FREE/SOFT ,Emulation mode bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
|
|
newline
|
|
bitfld.long 0x00 10.--12. " TBCTL_CLKDIV ,Time-base clock prescale bits" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
newline
|
|
bitfld.long 0x00 7.--9. " TBCTL_HSPCLKDIV ,High speed time-base clock prescale bits" "/1,/2,/4,/6,/8,/10,/12,/14"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TBCTL_SYNCOSEL ,Synchronization output select" "EPWMxSYNC,CTR = 0,CTR = CMPB,Disabled"
|
|
bitfld.long 0x00 3. " TBCTL_PRDLD ,Active period register load from shadow register select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 2. " TBCTL_PHSEN ,Counter register load from phase register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TBCTL_CTRMODE ,Counter mode" "Up-count,Down-count,Up-down-count,Stop-freeze"
|
|
endif
|
|
group.long 0x04++0x3B
|
|
line.long 0x00 "TBPHS,Time-Base Phase Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TBPHS ,Time-base phase"
|
|
line.long 0x04 "TBCTR_TBPRD,Time-Base Counter Register/Period Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " TBPRD ,Time-base period"
|
|
hexmask.long.word 0x04 0.--15. 1. " TBCTR ,Time-base counter"
|
|
line.long 0x08 "CMPCTL,Counter-Compare Control Register"
|
|
bitfld.long 0x08 25. " SHDWBFULL ,Counter-compare B CMPB shadow register full status flag" "Not full,Full"
|
|
bitfld.long 0x08 24. " SHDWAFULL ,Counter-compare A CMPA shadow register full status flag" "Not full,Full"
|
|
newline
|
|
bitfld.long 0x08 22. " SHDWBMODE ,Counter-compare B" "Shadow mode,Immediate mode"
|
|
bitfld.long 0x08 20. " SHDWAMODE ,Counter-compare A CMPA register operating mode" "Shadow mode,Immediate mode"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " LOADBMODE ,Active Counter-Compare B CMPB load from shadow select mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
|
|
bitfld.long 0x08 16.--17. " LOADAMODE ,Active Counter-Compare A CMPA load from shadow select mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
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line.long 0x0C "CMPA,Counter-Compare A Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " CMPA ,Counter-Compare A"
|
|
line.long 0x10 "CMPB_AQCTLA,Counter-Compare B Register/Action-Qualifier Control Register For Output A (ePWMxA)"
|
|
bitfld.long 0x10 26.--27. " AQCTLA_CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle"
|
|
bitfld.long 0x10 24.--25. " AQCTLA_CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle"
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|
newline
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bitfld.long 0x10 22.--23. " AQCTLA_CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle"
|
|
bitfld.long 0x10 20.--21. " AQCTLA_CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle"
|
|
newline
|
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bitfld.long 0x10 18.--19. " AQCTLA_PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggle"
|
|
bitfld.long 0x10 16.--17. " AQCTLA_ZRO ,Action when counter equals 0" "Disabled,Clear,Set,Toggle"
|
|
newline
|
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hexmask.long.word 0x10 0.--15. 1. " CMPB ,Counter-compare B"
|
|
line.long 0x14 "AQCTLB_AQSFRC,Action-Qualifier Control Register For Output B (ePWMxB)/Action-Qualifier Software Force Register"
|
|
bitfld.long 0x14 22.--23. " AQSFRC_RLDCSF ,AQCSFRC active register reload from shadow options" "0,Period,0/Period,Immediately"
|
|
bitfld.long 0x14 21. " AQSFRC_OTSFB ,One-time software forced event on output B" "No effect,Event"
|
|
newline
|
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bitfld.long 0x14 19.--20. " AQSFRC_ACTSFB ,Action when One-time software force B is invoked" "No effect,Clear,Set,Toggle"
|
|
bitfld.long 0x14 18. " AQSFRC_OTSFA ,One-time software forced event on output A" "No effect,Forced event"
|
|
newline
|
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bitfld.long 0x14 16.--17. " AQSFRC_ACTSFA ,Action when One-time software force A is invoked" "No effect,Clear,Set,Toggle"
|
|
bitfld.long 0x14 10.--11. " AQCTLB_CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
|
|
newline
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bitfld.long 0x14 8.--9. " AQCTLB_CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
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bitfld.long 0x14 6.--7. " AQCTLB_CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
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newline
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bitfld.long 0x14 4.--5. " AQCTLB_CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
|
|
bitfld.long 0x14 2.--3. " AQCTLB_PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled"
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|
newline
|
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bitfld.long 0x14 0.--1. " AQCTLB_ZRO ,Action when counter equals 0" "Disabled,Cleared,Set,Toggled"
|
|
line.long 0x18 "AQCSFRC_DBCTL,Dead-Band Generator Control Register/Action-Qualifier Continuous S/W Force Register Set"
|
|
bitfld.long 0x18 31. " DBCTL_HALFCYCLE ,Half cycle clocking enable bit" "Full cycle,Half cycle"
|
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bitfld.long 0x18 20.--21. " DBCTL_IN_MODE ,Dead band input mode control" "EPWMxA falling/rising edge,EPWMxB rising/EPWMxA falling edge,EPWMxA rising/EPWMxB falling edge,EPWMxB rising/falling edge"
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newline
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bitfld.long 0x18 18.--19. " DBCTL_POLSEL ,Polarity select control" "Active high,Active low complementary,Active high complementary,Active low"
|
|
bitfld.long 0x18 16.--17. " DBCTL_OUT_MODE ,Dead-band output mode" "0,1,2,3"
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newline
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bitfld.long 0x18 2.--3. " AQCSFRC_CSFB ,Continuous software force on output B" "Forced disabled,Continued low,Continued high,Software forced disabled"
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|
bitfld.long 0x18 0.--1. " AQCSFRC_CSFA ,Continuous software force on output A" "Forced disabled,Continued low,Continued high,Software forced disabled"
|
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line.long 0x1C "DBRED_DBFED,Dead-Band Generator Rising Edge Delay Count Register/Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.long.word 0x1C 16.--25. 1. " DBFED_DEL ,Falling edge delay count"
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hexmask.long.word 0x1C 0.--9. 1. " DBRED_DEL ,Rising edge delay count"
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line.long 0x20 "TZSEL_TZDCSEL,Trip Zone Digital Compare Select Register/Trip-Zone Select Register"
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sif cpuis("AWR1843*")||cpuis("AWR6843*")
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bitfld.long 0x20 25.--27. " TZDCSEL_DCBEVT2 ,Digital compare output B event 2 selection [DCBH/DCBL]" "Disabled,LOW/-,HIGH/-,-/LOW,-/HIGH,LOW/HIGH,?..."
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bitfld.long 0x20 22.--24. " TZDCSEL_DCBEVT1 ,Digital compare output B event 1 selection [DCBH/DCBL]" "Disabled,LOW/-,HIGH/-,-/LOW,-/HIGH,LOW/HIGH,?..."
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newline
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bitfld.long 0x20 19.--21. " TZDCSEL_DCAEVT2 ,Digital compare output A event 2 selection [DCAH/DCAL]" "Disabled,LOW/-,HIGH/-,-/LOW,-/HIGH,LOW/HIGH,?..."
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bitfld.long 0x20 16.--18. " TZDCSEL_DCAEVT1 ,Digital compare output A event 1 selection [DCAH/DCAL]" "Disabled,LOW/-,HIGH/-,-/LOW,-/HIGH,LOW/HIGH,?..."
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else
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bitfld.long 0x20 25.--27. " TZDCSEL_DCBEVT2 ,Digital compare output B event 2 selection" "Disabled,DCBH=LOW_DCBL=?,DCBH=HIGH,DCBL=?,DCBL=LOW_DCBH=?,DCBL=HIGH,DCBH=?,DCBL=HIGH_DCBH=LOW"
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bitfld.long 0x20 22.--24. " TZDCSEL_DCBEVT1 ,Digital compare output B event 1 selection" "Disabled,DCBH=LOW_DCBL=?,DCBH=HIGH,DCBL=?,DCBL=LOW_DCBH=?,DCBL=HIGH,DCBH=?,DCBL=HIGH_DCBH=LOW"
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newline
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bitfld.long 0x20 19.--21. " TZDCSEL_DCAEVT2 ,Digital compare output A event 2 selection" "Disabled,DCAH=LOW/DCAL=?,DCAH=HIGH,DCAL=?,DCAL=LOW/DCAH=?,DCAL=HIGH,DCAH=?,DCAL=HIGH/DCAH=LOW"
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bitfld.long 0x20 16.--18. " TZDCSEL_DCAEVT1 ,Digital compare output A event 1 selection" "Disabled,DCAH=LOW/DCAL=?,DCAH=HIGH,DCAL=?,DCAL=LOW/DCAH=?,DCAL=HIGH,DCAH=?,DCAL=HIGH/DCAH=LOW"
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|
endif
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newline
|
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bitfld.long 0x20 15. " TZSEL_DCBEVT1 ,Digital compare output B event 1 select" "Disabled,Enabled"
|
|
bitfld.long 0x20 14. " TZSEL_DCAEVT1 ,Digital compare output A event 1 select" "Disabled,Enabled"
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newline
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bitfld.long 0x20 13. " TZSEL_OSHT6 ,Use TZ6 as One-shot trip source for ePWM" "Disabled,Enabled"
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bitfld.long 0x20 12. " TZSEL_OSHT5 ,Use TZ5 as One-shot trip source for ePWM" "Disabled,Enabled"
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newline
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bitfld.long 0x20 11. " TZSEL_OSHT4 ,Use TZ4 as One-shot trip source for ePWM" "Disabled,Enabled"
|
|
bitfld.long 0x20 10. " TZSEL_OSHT3 ,Use TZ3 as One-shot trip source for ePWM" "Disabled,Enabled"
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|
newline
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bitfld.long 0x20 9. " TZSEL_OSHT2 ,Use TZ2 as One-shot trip source for ePWM" "Disabled,Enabled"
|
|
bitfld.long 0x20 8. " TZSEL_OSHT1 ,Use TZ1 as One-shot trip source for ePWM" "Disabled,Enabled"
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newline
|
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bitfld.long 0x20 7. " TZSEL_DCBEVT2 ,Digital compare output B event 2" "Disabled,Enabled"
|
|
bitfld.long 0x20 6. " TZSEL_DCAEVT2 ,Digital compare output A event 2" "Disabled,Enabled"
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newline
|
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bitfld.long 0x20 5. " TZSEL_CBC6 ,Trip-zone 6" "Disabled,Enabled"
|
|
bitfld.long 0x20 4. " TZSEL_CBC5 ,Trip-zone 5" "Disabled,Enabled"
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|
newline
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bitfld.long 0x20 3. " TZSEL_CBC4 ,Trip-zone 4" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " TZSEL_CBC3 ,Trip-zone 3" "Disabled,Enabled"
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|
newline
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bitfld.long 0x20 1. " TZSEL_CBC2 ,Trip-zone 2" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " TZSEL_CBC1 ,Trip-zone 1" "Disabled,Enabled"
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|
line.long 0x24 "TZCTL_TZEINT,Trip-Zone Control Register/Trip-Zone Enable Interrupt Register"
|
|
bitfld.long 0x24 22. " TZEINT_DCBEVT2 ,Digital comparator output B event 2" "Disabled,Enabled"
|
|
bitfld.long 0x24 21. " TZEINT_DCBEVT1 ,Digital comparator output B event 1" "Disabled,Enabled"
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|
newline
|
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bitfld.long 0x24 20. " TZEINT_DCAEVT2 ,Digital comparator output A event 2" "Disabled,Enabled"
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|
bitfld.long 0x24 19. " TZEINT_DCAEVT1 ,Digital comparator output A event 1" "Disabled,Enabled"
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newline
|
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bitfld.long 0x24 18. " TZEINT_OST ,Trip-zone One-Shot interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 17. " TZEINT_CBC ,Trip-zone Cycle-by-Cycle interrupt enable" "Disabled,Enabled"
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newline
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bitfld.long 0x24 10.--11. " TZCTL_DCBEVT2 ,Digital compare output B event 2 action on ePWMxB" "High-impedance,Forced high,Forced low,Disabled"
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bitfld.long 0x24 8.--9. " TZCTL_DCBEVT1 ,Digital compare output B event 1 action on ePWMxB" "High-impedance,Forced high,Forced low,Disabled"
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newline
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bitfld.long 0x24 6.--7. " TZCTL_DCAEVT2 ,Digital compare output A event 2 action on ePWMxA" "High-impedance,Forced high,Forced low,Disabled"
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bitfld.long 0x24 4.--5. " TZCTL_DCAEVT1 ,Digital compare output A event 1 action on ePWMxA" "High-impedance,Forced high,Forced low,Disabled"
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newline
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bitfld.long 0x24 2.--3. " TZCTL_TZB ,Action on output ePWMxB" "High-impedance,Forced high,Forced low,Disabled"
|
|
bitfld.long 0x24 0.--1. " TZCTL_TZA ,Action on output ePWMxA" "High-impedance,Forced high,Forced low,Disabled"
|
|
line.long 0x28 "TZFLG_TZ_SET/CLR,Trip-Zone Flag Register/Trip-Zone Set/Clear Register"
|
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setclrfld.long 0x28 6. 0x2C 6. 0x28 22. " DCBEVT2 ,Digital comparator output B event 2 interrupt" "Not occurred,Occurred"
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setclrfld.long 0x28 5. 0x2C 5. 0x28 21. " DCBEVT1 ,Digital comparator output B event 1 interrupt" "Not occurred,Occurred"
|
|
newline
|
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setclrfld.long 0x28 4. 0x2C 4. 0x28 20. " DCAEVT2 ,Digital comparator output A event 2 interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x28 3. 0x2C 3. 0x28 19. " DCAEVT1 ,Digital comparator output A event 1 interrupt" "Not occurred,Occurred"
|
|
newline
|
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setclrfld.long 0x28 2. 0x2C 2. 0x28 18. " OST ,Trip-zone one-Shot interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x28 1. 0x2C 1. 0x28 17. " CBC ,Trip-zone cycle-by-cycle interrupt" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x28 0. 0x2C 0. 0x28 16. " INT ,Latched trip interrupt status flag" "Not generated,Generated"
|
|
line.long 0x2C "TZFRC_ETSEL,Trip-Zone Force Register/Event-Trigger Selection Register"
|
|
bitfld.long 0x2C 31. " ETSEL_SOCBEN ,Enable the ADC start of conversion B ePWMxSOCB pulse" "Disabled,Enabled"
|
|
bitfld.long 0x2C 28.--30. " ETSEL_SOCBSEL ,ePWMxSOCB selection options" "DCBEVT1_soc,TBCTR=0,TBCTR=period,TBCTR=0/period,TBCTR=CMPA timer INC,TBCTR=CMPA,TBCTR=CMPB timer INC,TBCTR=CMPB"
|
|
newline
|
|
bitfld.long 0x2C 27. " ETSEL_SOCAEN ,Enable the ADC start of conversion A ePWMxSOCA pulse" "Disabled,Enabled"
|
|
bitfld.long 0x2C 24.--26. " ETSEL_SOCASEL ,ePWMxSOCA selection options" "DCBEVT1_soc,TBCTR=0,TBCTR=period,TBCTR=0/period,TBCTR=CMPA timer INC,TBCTR=CMPA,TBCTR=CMPB timer INC,TBCTR=CMPB"
|
|
newline
|
|
bitfld.long 0x2C 19. " ETSEL_INTEN ,Enable ePWM interrupt ePWMx_INT generation" "Disabled,Enabled"
|
|
bitfld.long 0x2C 16.--18. " ETSEL_INTSEL ,ePWM interrupt ePWMx_INT selection options" ",TBCTR=0,TBCTR=period,TBCTR=0/period,TBCTR=CMPA timer INC,TBCTR=CMPA,TBCTR=CMPB timer INC,TBCTR=CMPB"
|
|
newline
|
|
bitfld.long 0x2C 6. " TZFRC_DCBEVT2 ,Force flag for digital compare output B event 2" "Not forced,Forced"
|
|
bitfld.long 0x2C 5. " TZFRC_DCBEVT1 ,Force flag for digital compare output B event 1" "Not forced,Forced"
|
|
newline
|
|
bitfld.long 0x2C 4. " TZFRC_DCAEVT2 ,Force flag for digital compare output A event 2" "Not forced,Forced"
|
|
bitfld.long 0x2C 3. " TZFRC_DCAEVT1 ,Force flag for digital compare output A event 1" "Not forced,Forced"
|
|
newline
|
|
bitfld.long 0x2C 2. " TZFRC_OST ,Force a one-shot trip event via software 0" "Not forced,Forced"
|
|
bitfld.long 0x2C 1. " TZFRC_CBC ,Force a cycle-by-cycle trip event via software 0" "Not forced,Forced"
|
|
line.long 0x30 "ETPS_ETFLG,Event-Trigger Pre-Scale Register/Event-Trigger Flag Register"
|
|
bitfld.long 0x30 19. " ETFLG_SOCB ,Latched ePWM ADC start-of-conversion B ePWMxSOCB status flag" "Not occurred,Occurred"
|
|
bitfld.long 0x30 18. " ETFLG_SOCA ,Latched ePWM ADC start-of-conversion A ePWMxSOCA status flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x30 16. " ETFLG_INT ,Latched ePWM interrupt ePWMx_INT status flag" "Not occurred,Occurred"
|
|
bitfld.long 0x30 14.--15. " ETPS_SOCBCNT ,ePWM ADC start-of-conversion B event ePWMxSOCB counter register" "No events,1 event,2 events,3 events"
|
|
newline
|
|
bitfld.long 0x30 12.--13. " ETPS_SOCBPRD ,ePWM ADC start-of-conversion B event ePWMxSOCB period select" "Disabled,1st event,2nd event,3rd event"
|
|
bitfld.long 0x30 10.--11. " ETPS_SOCACNT ,ePWM ADC start-of-conversion A event ePWMxSOCA counter register" "No events,1 event,2 events,3 events"
|
|
newline
|
|
bitfld.long 0x30 8.--9. " ETPS_SOCAPRD ,ePWM ADC start-of-conversion A event ePWMxSOCA period select" "Disabled,1st event,2nd event,3rd event"
|
|
bitfld.long 0x30 2.--3. " ETPS_INTCNT ,ePWM interrupt event ePWMx_INT counter register" "No events,1 event,2 events,3 events"
|
|
newline
|
|
bitfld.long 0x30 0.--1. " ETPS_INTPRD ,ePWM interrupt ePWMx_INT period select" "Disabled,1st event,2nd event,3rd event"
|
|
line.long 0x34 "ETCLR_ETFRC,Event-Trigger Clear Register/Event-Trigger Force Register"
|
|
bitfld.long 0x34 19. " ETFRC_SOCB ,SOCB force bit" "No effect,Forced"
|
|
bitfld.long 0x34 18. " ETFRC_SOCA ,SOCA force bit" "No effect,Forced"
|
|
newline
|
|
bitfld.long 0x34 16. " ETFRC_INT ,INT force bit" "No effect,Forced"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
eventfld.long 0x34 3. " ETCLR_SOCB ,ePWM ADC start-of-conversion B ePWMxSOCB flag clear bit" "No effect,Cleared"
|
|
newline
|
|
eventfld.long 0x34 2. " ETCLR_SOCA ,ePWM ADC start-of-conversion A ePWMxSOCB flag clear bit" "No effect,Cleared"
|
|
eventfld.long 0x34 0. " ETCLR_INT ,ePWM interrupt ePWMx_INT flag clear bit" "No effect,Cleared"
|
|
else
|
|
bitfld.long 0x34 3. " ETCLR_SOCB ,ePWM ADC start-of-Conversion B ePWMxSOCB flag clear bit" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x34 2. " ETCLR_SOCA ,ePWM ADC start-of-conversion A ePWMxSOCB flag clear bit" "No effect,Cleared"
|
|
bitfld.long 0x34 0. " ETCLR_INT ,ePWM interrupt ePWMx_INT flag clear bit" "No effect,Cleared"
|
|
endif
|
|
line.long 0x38 "PCCTL,PWM-Chopper Control Register"
|
|
bitfld.long 0x38 8.--10. " CHPDUTY ,Chopping clock duty cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,?..."
|
|
bitfld.long 0x38 5.--7. " CHPFREQ ,Chopping clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
newline
|
|
bitfld.long 0x38 1.--4. " OSHTWTH ,One-Shot pulse width" "1 x VCLK3 / 8 wide,2 x VCLK3 / 8 wide,3 x VCLK3 / 8 wide,4 x VCLK3 / 8 wide,5 x VCLK3 / 8 wide,6 x VCLK3 / 8 wide,7 x VCLK3 / 8 wide,8 x VCLK3 / 8 wide,9 x VCLK3 / 8 wide,10 x VCLK3 / 8 wide,11 x VCLK3 / 8 wide,12 x VCLK3 / 8 wide,13 x VCLK3 / 8 wide,14 x VCLK3 / 8 wide,15 x VCLK3 / 8 wide,16 x VCLK3 / 8 wide"
|
|
bitfld.long 0x38 0. " CHPEN ,PWM-chopping enable" "Disabled,Enabled"
|
|
group.long 0x60++0x13
|
|
line.long 0x00 "DCTRIPSEL_DCACTL,Digital Compare Trip Select Register/Digital Compare A Control Register"
|
|
bitfld.long 0x00 25. " DCACTL_EVT2FRC_SYNCSEL ,DCAEVT2 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 24. " DCACTL_EVT2SRCSEL ,DCAEVT2 source signal select" "DCAEVT2,DCEVTFILT"
|
|
newline
|
|
bitfld.long 0x00 19. " DCACTL_EVT1SYNCE ,DCAEVT1 SYNC generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DCACTL_EVT1SOCE ,DCAEVT1 SOC generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " DCACTL_EVT1FRC_SYNCSEL ,DCAEVT1 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 16. " DCACTL_EVT1SRCSEL ,DCAEVT1 source signal select" "DCAEVT,DCEVTFILT"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " DCTRIPSEL_DCBLCOMPSEL ,Digital compare B low input select" "TZ1 input,TZ2 input,TZ3 input,?..."
|
|
bitfld.long 0x00 8.--11. " DCTRIPSEL_DCBHCOMPSEL ,Digital compare B high input select" "TZ1 input,TZ2 input,TZ3 input,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " DCTRIPSEL/DCALCOMPSEL ,Digital compare A low input select" "TZ1 input,TZ2 input,TZ3 input,?..."
|
|
bitfld.long 0x00 0.--3. " DCTRIPSEL/DCAHCOMPSEL ,Digital compare A high input select" "TZ1 input,TZ2 input,TZ3 input,?..."
|
|
line.long 0x04 "DCBCTL_DCFCTL,Digital Compare B Control Register/Digital Compare Filter Control Register"
|
|
bitfld.long 0x04 20.--21. " DCFCTL_PULSESEL ,Pulse select for blanking & capture alignment" "TBCTR = TBPRD,TBCTR = 0,?..."
|
|
bitfld.long 0x04 19. " DCFCTL_BLANKINV ,Blanking window inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x04 18. " DCFCTL_BLANKE ,Blanking window enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--17. " DCFCTL_SRCSEL ,Filter block signal source select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2"
|
|
newline
|
|
bitfld.long 0x04 9. " DCBCTL_EVT2FRC_SYNCSEL ,DCBEVT2 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.long 0x04 8. " DCBCTL_EVT2SRCSEL ,DCBEVT2 source signal select" "DCBEVT2,DCEVTFILT"
|
|
newline
|
|
bitfld.long 0x04 3. " DCBCTL_EVT1SYNCE ,DCBEVT1 SYNC generation" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " DCBCTL_EVT1SOCE ,DCBEVT1 SOC generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " DCBCTL_EVT1FRC_SYNCSEL ,DCBEVT1 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.long 0x04 0. " DCBCTL_EVT1SRCSEL ,DCBEVT1 source signal select" "DCBEVT1,DCEVTFILT"
|
|
line.long 0x08 "DCCAPCTL_DCFOFFSET,Digital Compare Capture Control Register/Digital Compare Filter Offset Register"
|
|
hexmask.long.word 0x08 16.--31. 0x01 " DCFOFFSET_OFFSET ,Blanking window offset"
|
|
bitfld.long 0x08 1. " DCCAPCTL_SHDWMODE ,TBCTR counter capture shadow select mode" "Shadow mode,Active mode"
|
|
newline
|
|
bitfld.long 0x08 0. " DCCAPCTL_CAPE ,TBCTR counter capture enable" "Disabled,Enabled"
|
|
line.long 0x0C "DCFOFFSETCNT_DCFWINDOW,Digital Compare Filter Offset Counter Register/Digital Compare Filter Window Register"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " DCFWINDOW_WINDOW ,Blanking window width"
|
|
hexmask.long.word 0x0C 0.--15. 0x01 " DCFOFFSETCNT_OFFSETCNT ,Blanking offset counter"
|
|
line.long 0x10 "DCFWINDOWCNT_DCCAP,Digital Compare Filter Window Counter Register/Digital Compare Counter Capture Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " DCCAP ,Digital compare time-base counter capture"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DCFWINDOWCNT ,Blanking window counter"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MSS_ETPWM3"
|
|
base ad:0xFCF78E00
|
|
width 24.
|
|
if (((per.l(ad:0xFCF78E00))&0x33)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/Status Register"
|
|
eventfld.long 0x00 18. " TBSTS_CTRMAX ,Time-base counter max latched status bit time-base counter maximum value" "Not reached,Reached"
|
|
eventfld.long 0x00 17. " TBSTS_SYNCI ,Input synchronization latched status bit external synchronization event" "Not occurred,Occurred"
|
|
newline
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
bitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
else
|
|
rbitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " TBCTL_FREE/SOFT ,Emulation mode bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
|
|
newline
|
|
bitfld.long 0x00 13. " TBCTL_PHSDIR ,Phase direction bit" "Count down,Count up"
|
|
bitfld.long 0x00 10.--12. " TBCTL_CLKDIV ,Time-base clock prescale bits" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
newline
|
|
bitfld.long 0x00 7.--9. " TBCTL_HSPCLKDIV ,High speed time-base clock prescale bits" "/1,/2,/4,/6,/8,/10,/12,/14"
|
|
bitfld.long 0x00 6. " TBCTL_SWFSYNC ,Software forced synchronization pulse" "No effect,Generated"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TBCTL_SYNCOSEL ,Synchronization output select" "EPWMxSYNC,CTR = 0,CTR = CMPB,Disabled"
|
|
bitfld.long 0x00 3. " TBCTL_PRDLD ,Active period register load from shadow register select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 2. " TBCTL_PHSEN ,Counter register load from phase register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TBCTL_CTRMODE ,Counter mode" "Up-count,Down-count,Up-down-count,Stop-freeze"
|
|
elif (((per.l(ad:0xFCF78E00))&0x30)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/Status Register"
|
|
eventfld.long 0x00 18. " TBSTS_CTRMAX ,Time-base counter max latched status bit time-base counter maximum value" "Not reached,Reached"
|
|
eventfld.long 0x00 17. " TBSTS_SYNCI ,Input synchronization latched status bit external synchronization event" "Not occurred,Occurred"
|
|
newline
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
bitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
else
|
|
rbitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " TBCTL_FREE/SOFT ,Emulation mode bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
|
|
newline
|
|
bitfld.long 0x00 10.--12. " TBCTL_CLKDIV ,Time-base clock prescale bits" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
newline
|
|
bitfld.long 0x00 7.--9. " TBCTL_HSPCLKDIV ,High speed time-base clock prescale bits" "/1,/2,/4,/6,/8,/10,/12,/14"
|
|
bitfld.long 0x00 6. " TBCTL_SWFSYNC ,Software forced synchronization pulse" "No effect,Generated"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TBCTL_SYNCOSEL ,Synchronization output select" "EPWMxSYNC,CTR = 0,CTR = CMPB,Disabled"
|
|
bitfld.long 0x00 3. " TBCTL_PRDLD ,Active period register load from shadow register select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 2. " TBCTL_PHSEN ,Counter register load from phase register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TBCTL_CTRMODE ,Counter mode" "Up-count,Down-count,Up-down-count,Stop-freeze"
|
|
elif (((per.l(ad:0xFCF78E00))&0x03)==0x02)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/Status Register"
|
|
eventfld.long 0x00 18. " TBSTS_CTRMAX ,Time-base counter max latched status bit time-base counter maximum value" "Not reached,Reached"
|
|
eventfld.long 0x00 17. " TBSTS_SYNCI ,Input synchronization latched status bit external synchronization event" "Not occurred,Occurred"
|
|
newline
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
bitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
else
|
|
rbitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " TBCTL_FREE/SOFT ,Emulation mode bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
|
|
newline
|
|
bitfld.long 0x00 13. " TBCTL_PHSDIR ,Phase direction bit" "Count down,Count up"
|
|
bitfld.long 0x00 10.--12. " TBCTL_CLKDIV ,Time-base clock prescale bits" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
newline
|
|
bitfld.long 0x00 7.--9. " TBCTL_HSPCLKDIV ,High speed time-base clock prescale bits" "/1,/2,/4,/6,/8,/10,/12,/14"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TBCTL_SYNCOSEL ,Synchronization output select" "EPWMxSYNC,CTR = 0,CTR = CMPB,Disabled"
|
|
bitfld.long 0x00 3. " TBCTL_PRDLD ,Active period register load from shadow register select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 2. " TBCTL_PHSEN ,Counter register load from phase register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TBCTL_CTRMODE ,Counter mode" "Up-count,Down-count,Up-down-count,Stop-freeze"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/Status Register"
|
|
eventfld.long 0x00 18. " TBSTS_CTRMAX ,Time-base counter max latched status bit time-base counter maximum value" "Not reached,Reached"
|
|
eventfld.long 0x00 17. " TBSTS_SYNCI ,Input synchronization latched status bit external synchronization event" "Not occurred,Occurred"
|
|
newline
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
bitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
else
|
|
rbitfld.long 0x00 16. " TBSTS_CTRDIR ,Time-base counter direction status bit" "Down,Up"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 14.--15. " TBCTL_FREE/SOFT ,Emulation mode bits" "Stop after timer INC or DEC,Stop after whole cycle,Free run,Free run"
|
|
newline
|
|
bitfld.long 0x00 10.--12. " TBCTL_CLKDIV ,Time-base clock prescale bits" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
newline
|
|
bitfld.long 0x00 7.--9. " TBCTL_HSPCLKDIV ,High speed time-base clock prescale bits" "/1,/2,/4,/6,/8,/10,/12,/14"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " TBCTL_SYNCOSEL ,Synchronization output select" "EPWMxSYNC,CTR = 0,CTR = CMPB,Disabled"
|
|
bitfld.long 0x00 3. " TBCTL_PRDLD ,Active period register load from shadow register select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x00 2. " TBCTL_PHSEN ,Counter register load from phase register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " TBCTL_CTRMODE ,Counter mode" "Up-count,Down-count,Up-down-count,Stop-freeze"
|
|
endif
|
|
group.long 0x04++0x3B
|
|
line.long 0x00 "TBPHS,Time-Base Phase Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TBPHS ,Time-base phase"
|
|
line.long 0x04 "TBCTR_TBPRD,Time-Base Counter Register/Period Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " TBPRD ,Time-base period"
|
|
hexmask.long.word 0x04 0.--15. 1. " TBCTR ,Time-base counter"
|
|
line.long 0x08 "CMPCTL,Counter-Compare Control Register"
|
|
bitfld.long 0x08 25. " SHDWBFULL ,Counter-compare B CMPB shadow register full status flag" "Not full,Full"
|
|
bitfld.long 0x08 24. " SHDWAFULL ,Counter-compare A CMPA shadow register full status flag" "Not full,Full"
|
|
newline
|
|
bitfld.long 0x08 22. " SHDWBMODE ,Counter-compare B" "Shadow mode,Immediate mode"
|
|
bitfld.long 0x08 20. " SHDWAMODE ,Counter-compare A CMPA register operating mode" "Shadow mode,Immediate mode"
|
|
newline
|
|
bitfld.long 0x08 18.--19. " LOADBMODE ,Active Counter-Compare B CMPB load from shadow select mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
|
|
bitfld.long 0x08 16.--17. " LOADAMODE ,Active Counter-Compare A CMPA load from shadow select mode" "CTR=0,CTR=PRD,CTR=0/CTR=PRD,Freeze"
|
|
line.long 0x0C "CMPA,Counter-Compare A Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " CMPA ,Counter-Compare A"
|
|
line.long 0x10 "CMPB_AQCTLA,Counter-Compare B Register/Action-Qualifier Control Register For Output A (ePWMxA)"
|
|
bitfld.long 0x10 26.--27. " AQCTLA_CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Clear,Set,Toggle"
|
|
bitfld.long 0x10 24.--25. " AQCTLA_CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Clear,Set,Toggle"
|
|
newline
|
|
bitfld.long 0x10 22.--23. " AQCTLA_CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Clear,Set,Toggle"
|
|
bitfld.long 0x10 20.--21. " AQCTLA_CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Clear,Set,Toggle"
|
|
newline
|
|
bitfld.long 0x10 18.--19. " AQCTLA_PRD ,Action when the counter equals the period" "Disabled,Clear,Set,Toggle"
|
|
bitfld.long 0x10 16.--17. " AQCTLA_ZRO ,Action when counter equals 0" "Disabled,Clear,Set,Toggle"
|
|
newline
|
|
hexmask.long.word 0x10 0.--15. 1. " CMPB ,Counter-compare B"
|
|
line.long 0x14 "AQCTLB_AQSFRC,Action-Qualifier Control Register For Output B (ePWMxB)/Action-Qualifier Software Force Register"
|
|
bitfld.long 0x14 22.--23. " AQSFRC_RLDCSF ,AQCSFRC active register reload from shadow options" "0,Period,0/Period,Immediately"
|
|
bitfld.long 0x14 21. " AQSFRC_OTSFB ,One-time software forced event on output B" "No effect,Event"
|
|
newline
|
|
bitfld.long 0x14 19.--20. " AQSFRC_ACTSFB ,Action when One-time software force B is invoked" "No effect,Clear,Set,Toggle"
|
|
bitfld.long 0x14 18. " AQSFRC_OTSFA ,One-time software forced event on output A" "No effect,Forced event"
|
|
newline
|
|
bitfld.long 0x14 16.--17. " AQSFRC_ACTSFA ,Action when One-time software force A is invoked" "No effect,Clear,Set,Toggle"
|
|
bitfld.long 0x14 10.--11. " AQCTLB_CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x14 8.--9. " AQCTLB_CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
|
|
bitfld.long 0x14 6.--7. " AQCTLB_CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x14 4.--5. " AQCTLB_CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled"
|
|
bitfld.long 0x14 2.--3. " AQCTLB_PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled"
|
|
newline
|
|
bitfld.long 0x14 0.--1. " AQCTLB_ZRO ,Action when counter equals 0" "Disabled,Cleared,Set,Toggled"
|
|
line.long 0x18 "AQCSFRC_DBCTL,Dead-Band Generator Control Register/Action-Qualifier Continuous S/W Force Register Set"
|
|
bitfld.long 0x18 31. " DBCTL_HALFCYCLE ,Half cycle clocking enable bit" "Full cycle,Half cycle"
|
|
bitfld.long 0x18 20.--21. " DBCTL_IN_MODE ,Dead band input mode control" "EPWMxA falling/rising edge,EPWMxB rising/EPWMxA falling edge,EPWMxA rising/EPWMxB falling edge,EPWMxB rising/falling edge"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DBCTL_POLSEL ,Polarity select control" "Active high,Active low complementary,Active high complementary,Active low"
|
|
bitfld.long 0x18 16.--17. " DBCTL_OUT_MODE ,Dead-band output mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 2.--3. " AQCSFRC_CSFB ,Continuous software force on output B" "Forced disabled,Continued low,Continued high,Software forced disabled"
|
|
bitfld.long 0x18 0.--1. " AQCSFRC_CSFA ,Continuous software force on output A" "Forced disabled,Continued low,Continued high,Software forced disabled"
|
|
line.long 0x1C "DBRED_DBFED,Dead-Band Generator Rising Edge Delay Count Register/Dead-Band Generator Falling Edge Delay Count Register"
|
|
hexmask.long.word 0x1C 16.--25. 1. " DBFED_DEL ,Falling edge delay count"
|
|
hexmask.long.word 0x1C 0.--9. 1. " DBRED_DEL ,Rising edge delay count"
|
|
line.long 0x20 "TZSEL_TZDCSEL,Trip Zone Digital Compare Select Register/Trip-Zone Select Register"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
bitfld.long 0x20 25.--27. " TZDCSEL_DCBEVT2 ,Digital compare output B event 2 selection [DCBH/DCBL]" "Disabled,LOW/-,HIGH/-,-/LOW,-/HIGH,LOW/HIGH,?..."
|
|
bitfld.long 0x20 22.--24. " TZDCSEL_DCBEVT1 ,Digital compare output B event 1 selection [DCBH/DCBL]" "Disabled,LOW/-,HIGH/-,-/LOW,-/HIGH,LOW/HIGH,?..."
|
|
newline
|
|
bitfld.long 0x20 19.--21. " TZDCSEL_DCAEVT2 ,Digital compare output A event 2 selection [DCAH/DCAL]" "Disabled,LOW/-,HIGH/-,-/LOW,-/HIGH,LOW/HIGH,?..."
|
|
bitfld.long 0x20 16.--18. " TZDCSEL_DCAEVT1 ,Digital compare output A event 1 selection [DCAH/DCAL]" "Disabled,LOW/-,HIGH/-,-/LOW,-/HIGH,LOW/HIGH,?..."
|
|
else
|
|
bitfld.long 0x20 25.--27. " TZDCSEL_DCBEVT2 ,Digital compare output B event 2 selection" "Disabled,DCBH=LOW_DCBL=?,DCBH=HIGH,DCBL=?,DCBL=LOW_DCBH=?,DCBL=HIGH,DCBH=?,DCBL=HIGH_DCBH=LOW"
|
|
bitfld.long 0x20 22.--24. " TZDCSEL_DCBEVT1 ,Digital compare output B event 1 selection" "Disabled,DCBH=LOW_DCBL=?,DCBH=HIGH,DCBL=?,DCBL=LOW_DCBH=?,DCBL=HIGH,DCBH=?,DCBL=HIGH_DCBH=LOW"
|
|
newline
|
|
bitfld.long 0x20 19.--21. " TZDCSEL_DCAEVT2 ,Digital compare output A event 2 selection" "Disabled,DCAH=LOW/DCAL=?,DCAH=HIGH,DCAL=?,DCAL=LOW/DCAH=?,DCAL=HIGH,DCAH=?,DCAL=HIGH/DCAH=LOW"
|
|
bitfld.long 0x20 16.--18. " TZDCSEL_DCAEVT1 ,Digital compare output A event 1 selection" "Disabled,DCAH=LOW/DCAL=?,DCAH=HIGH,DCAL=?,DCAL=LOW/DCAH=?,DCAL=HIGH,DCAH=?,DCAL=HIGH/DCAH=LOW"
|
|
endif
|
|
newline
|
|
bitfld.long 0x20 15. " TZSEL_DCBEVT1 ,Digital compare output B event 1 select" "Disabled,Enabled"
|
|
bitfld.long 0x20 14. " TZSEL_DCAEVT1 ,Digital compare output A event 1 select" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 13. " TZSEL_OSHT6 ,Use TZ6 as One-shot trip source for ePWM" "Disabled,Enabled"
|
|
bitfld.long 0x20 12. " TZSEL_OSHT5 ,Use TZ5 as One-shot trip source for ePWM" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 11. " TZSEL_OSHT4 ,Use TZ4 as One-shot trip source for ePWM" "Disabled,Enabled"
|
|
bitfld.long 0x20 10. " TZSEL_OSHT3 ,Use TZ3 as One-shot trip source for ePWM" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 9. " TZSEL_OSHT2 ,Use TZ2 as One-shot trip source for ePWM" "Disabled,Enabled"
|
|
bitfld.long 0x20 8. " TZSEL_OSHT1 ,Use TZ1 as One-shot trip source for ePWM" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 7. " TZSEL_DCBEVT2 ,Digital compare output B event 2" "Disabled,Enabled"
|
|
bitfld.long 0x20 6. " TZSEL_DCAEVT2 ,Digital compare output A event 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 5. " TZSEL_CBC6 ,Trip-zone 6" "Disabled,Enabled"
|
|
bitfld.long 0x20 4. " TZSEL_CBC5 ,Trip-zone 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 3. " TZSEL_CBC4 ,Trip-zone 4" "Disabled,Enabled"
|
|
bitfld.long 0x20 2. " TZSEL_CBC3 ,Trip-zone 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x20 1. " TZSEL_CBC2 ,Trip-zone 2" "Disabled,Enabled"
|
|
bitfld.long 0x20 0. " TZSEL_CBC1 ,Trip-zone 1" "Disabled,Enabled"
|
|
line.long 0x24 "TZCTL_TZEINT,Trip-Zone Control Register/Trip-Zone Enable Interrupt Register"
|
|
bitfld.long 0x24 22. " TZEINT_DCBEVT2 ,Digital comparator output B event 2" "Disabled,Enabled"
|
|
bitfld.long 0x24 21. " TZEINT_DCBEVT1 ,Digital comparator output B event 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 20. " TZEINT_DCAEVT2 ,Digital comparator output A event 2" "Disabled,Enabled"
|
|
bitfld.long 0x24 19. " TZEINT_DCAEVT1 ,Digital comparator output A event 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 18. " TZEINT_OST ,Trip-zone One-Shot interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 17. " TZEINT_CBC ,Trip-zone Cycle-by-Cycle interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 10.--11. " TZCTL_DCBEVT2 ,Digital compare output B event 2 action on ePWMxB" "High-impedance,Forced high,Forced low,Disabled"
|
|
bitfld.long 0x24 8.--9. " TZCTL_DCBEVT1 ,Digital compare output B event 1 action on ePWMxB" "High-impedance,Forced high,Forced low,Disabled"
|
|
newline
|
|
bitfld.long 0x24 6.--7. " TZCTL_DCAEVT2 ,Digital compare output A event 2 action on ePWMxA" "High-impedance,Forced high,Forced low,Disabled"
|
|
bitfld.long 0x24 4.--5. " TZCTL_DCAEVT1 ,Digital compare output A event 1 action on ePWMxA" "High-impedance,Forced high,Forced low,Disabled"
|
|
newline
|
|
bitfld.long 0x24 2.--3. " TZCTL_TZB ,Action on output ePWMxB" "High-impedance,Forced high,Forced low,Disabled"
|
|
bitfld.long 0x24 0.--1. " TZCTL_TZA ,Action on output ePWMxA" "High-impedance,Forced high,Forced low,Disabled"
|
|
line.long 0x28 "TZFLG_TZ_SET/CLR,Trip-Zone Flag Register/Trip-Zone Set/Clear Register"
|
|
setclrfld.long 0x28 6. 0x2C 6. 0x28 22. " DCBEVT2 ,Digital comparator output B event 2 interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x28 5. 0x2C 5. 0x28 21. " DCBEVT1 ,Digital comparator output B event 1 interrupt" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x28 4. 0x2C 4. 0x28 20. " DCAEVT2 ,Digital comparator output A event 2 interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x28 3. 0x2C 3. 0x28 19. " DCAEVT1 ,Digital comparator output A event 1 interrupt" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x28 2. 0x2C 2. 0x28 18. " OST ,Trip-zone one-Shot interrupt" "Not occurred,Occurred"
|
|
setclrfld.long 0x28 1. 0x2C 1. 0x28 17. " CBC ,Trip-zone cycle-by-cycle interrupt" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x28 0. 0x2C 0. 0x28 16. " INT ,Latched trip interrupt status flag" "Not generated,Generated"
|
|
line.long 0x2C "TZFRC_ETSEL,Trip-Zone Force Register/Event-Trigger Selection Register"
|
|
bitfld.long 0x2C 31. " ETSEL_SOCBEN ,Enable the ADC start of conversion B ePWMxSOCB pulse" "Disabled,Enabled"
|
|
bitfld.long 0x2C 28.--30. " ETSEL_SOCBSEL ,ePWMxSOCB selection options" "DCBEVT1_soc,TBCTR=0,TBCTR=period,TBCTR=0/period,TBCTR=CMPA timer INC,TBCTR=CMPA,TBCTR=CMPB timer INC,TBCTR=CMPB"
|
|
newline
|
|
bitfld.long 0x2C 27. " ETSEL_SOCAEN ,Enable the ADC start of conversion A ePWMxSOCA pulse" "Disabled,Enabled"
|
|
bitfld.long 0x2C 24.--26. " ETSEL_SOCASEL ,ePWMxSOCA selection options" "DCBEVT1_soc,TBCTR=0,TBCTR=period,TBCTR=0/period,TBCTR=CMPA timer INC,TBCTR=CMPA,TBCTR=CMPB timer INC,TBCTR=CMPB"
|
|
newline
|
|
bitfld.long 0x2C 19. " ETSEL_INTEN ,Enable ePWM interrupt ePWMx_INT generation" "Disabled,Enabled"
|
|
bitfld.long 0x2C 16.--18. " ETSEL_INTSEL ,ePWM interrupt ePWMx_INT selection options" ",TBCTR=0,TBCTR=period,TBCTR=0/period,TBCTR=CMPA timer INC,TBCTR=CMPA,TBCTR=CMPB timer INC,TBCTR=CMPB"
|
|
newline
|
|
bitfld.long 0x2C 6. " TZFRC_DCBEVT2 ,Force flag for digital compare output B event 2" "Not forced,Forced"
|
|
bitfld.long 0x2C 5. " TZFRC_DCBEVT1 ,Force flag for digital compare output B event 1" "Not forced,Forced"
|
|
newline
|
|
bitfld.long 0x2C 4. " TZFRC_DCAEVT2 ,Force flag for digital compare output A event 2" "Not forced,Forced"
|
|
bitfld.long 0x2C 3. " TZFRC_DCAEVT1 ,Force flag for digital compare output A event 1" "Not forced,Forced"
|
|
newline
|
|
bitfld.long 0x2C 2. " TZFRC_OST ,Force a one-shot trip event via software 0" "Not forced,Forced"
|
|
bitfld.long 0x2C 1. " TZFRC_CBC ,Force a cycle-by-cycle trip event via software 0" "Not forced,Forced"
|
|
line.long 0x30 "ETPS_ETFLG,Event-Trigger Pre-Scale Register/Event-Trigger Flag Register"
|
|
bitfld.long 0x30 19. " ETFLG_SOCB ,Latched ePWM ADC start-of-conversion B ePWMxSOCB status flag" "Not occurred,Occurred"
|
|
bitfld.long 0x30 18. " ETFLG_SOCA ,Latched ePWM ADC start-of-conversion A ePWMxSOCA status flag" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x30 16. " ETFLG_INT ,Latched ePWM interrupt ePWMx_INT status flag" "Not occurred,Occurred"
|
|
bitfld.long 0x30 14.--15. " ETPS_SOCBCNT ,ePWM ADC start-of-conversion B event ePWMxSOCB counter register" "No events,1 event,2 events,3 events"
|
|
newline
|
|
bitfld.long 0x30 12.--13. " ETPS_SOCBPRD ,ePWM ADC start-of-conversion B event ePWMxSOCB period select" "Disabled,1st event,2nd event,3rd event"
|
|
bitfld.long 0x30 10.--11. " ETPS_SOCACNT ,ePWM ADC start-of-conversion A event ePWMxSOCA counter register" "No events,1 event,2 events,3 events"
|
|
newline
|
|
bitfld.long 0x30 8.--9. " ETPS_SOCAPRD ,ePWM ADC start-of-conversion A event ePWMxSOCA period select" "Disabled,1st event,2nd event,3rd event"
|
|
bitfld.long 0x30 2.--3. " ETPS_INTCNT ,ePWM interrupt event ePWMx_INT counter register" "No events,1 event,2 events,3 events"
|
|
newline
|
|
bitfld.long 0x30 0.--1. " ETPS_INTPRD ,ePWM interrupt ePWMx_INT period select" "Disabled,1st event,2nd event,3rd event"
|
|
line.long 0x34 "ETCLR_ETFRC,Event-Trigger Clear Register/Event-Trigger Force Register"
|
|
bitfld.long 0x34 19. " ETFRC_SOCB ,SOCB force bit" "No effect,Forced"
|
|
bitfld.long 0x34 18. " ETFRC_SOCA ,SOCA force bit" "No effect,Forced"
|
|
newline
|
|
bitfld.long 0x34 16. " ETFRC_INT ,INT force bit" "No effect,Forced"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
eventfld.long 0x34 3. " ETCLR_SOCB ,ePWM ADC start-of-conversion B ePWMxSOCB flag clear bit" "No effect,Cleared"
|
|
newline
|
|
eventfld.long 0x34 2. " ETCLR_SOCA ,ePWM ADC start-of-conversion A ePWMxSOCB flag clear bit" "No effect,Cleared"
|
|
eventfld.long 0x34 0. " ETCLR_INT ,ePWM interrupt ePWMx_INT flag clear bit" "No effect,Cleared"
|
|
else
|
|
bitfld.long 0x34 3. " ETCLR_SOCB ,ePWM ADC start-of-Conversion B ePWMxSOCB flag clear bit" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x34 2. " ETCLR_SOCA ,ePWM ADC start-of-conversion A ePWMxSOCB flag clear bit" "No effect,Cleared"
|
|
bitfld.long 0x34 0. " ETCLR_INT ,ePWM interrupt ePWMx_INT flag clear bit" "No effect,Cleared"
|
|
endif
|
|
line.long 0x38 "PCCTL,PWM-Chopper Control Register"
|
|
bitfld.long 0x38 8.--10. " CHPDUTY ,Chopping clock duty cycle" "1/8,2/8,3/8,4/8,5/8,6/8,7/8,?..."
|
|
bitfld.long 0x38 5.--7. " CHPFREQ ,Chopping clock frequency" "/1,/2,/3,/4,/5,/6,/7,/8"
|
|
newline
|
|
bitfld.long 0x38 1.--4. " OSHTWTH ,One-Shot pulse width" "1 x VCLK3 / 8 wide,2 x VCLK3 / 8 wide,3 x VCLK3 / 8 wide,4 x VCLK3 / 8 wide,5 x VCLK3 / 8 wide,6 x VCLK3 / 8 wide,7 x VCLK3 / 8 wide,8 x VCLK3 / 8 wide,9 x VCLK3 / 8 wide,10 x VCLK3 / 8 wide,11 x VCLK3 / 8 wide,12 x VCLK3 / 8 wide,13 x VCLK3 / 8 wide,14 x VCLK3 / 8 wide,15 x VCLK3 / 8 wide,16 x VCLK3 / 8 wide"
|
|
bitfld.long 0x38 0. " CHPEN ,PWM-chopping enable" "Disabled,Enabled"
|
|
group.long 0x60++0x13
|
|
line.long 0x00 "DCTRIPSEL_DCACTL,Digital Compare Trip Select Register/Digital Compare A Control Register"
|
|
bitfld.long 0x00 25. " DCACTL_EVT2FRC_SYNCSEL ,DCAEVT2 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 24. " DCACTL_EVT2SRCSEL ,DCAEVT2 source signal select" "DCAEVT2,DCEVTFILT"
|
|
newline
|
|
bitfld.long 0x00 19. " DCACTL_EVT1SYNCE ,DCAEVT1 SYNC generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DCACTL_EVT1SOCE ,DCAEVT1 SOC generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " DCACTL_EVT1FRC_SYNCSEL ,DCAEVT1 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 16. " DCACTL_EVT1SRCSEL ,DCAEVT1 source signal select" "DCAEVT,DCEVTFILT"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " DCTRIPSEL_DCBLCOMPSEL ,Digital compare B low input select" "TZ1 input,TZ2 input,TZ3 input,?..."
|
|
bitfld.long 0x00 8.--11. " DCTRIPSEL_DCBHCOMPSEL ,Digital compare B high input select" "TZ1 input,TZ2 input,TZ3 input,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " DCTRIPSEL/DCALCOMPSEL ,Digital compare A low input select" "TZ1 input,TZ2 input,TZ3 input,?..."
|
|
bitfld.long 0x00 0.--3. " DCTRIPSEL/DCAHCOMPSEL ,Digital compare A high input select" "TZ1 input,TZ2 input,TZ3 input,?..."
|
|
line.long 0x04 "DCBCTL_DCFCTL,Digital Compare B Control Register/Digital Compare Filter Control Register"
|
|
bitfld.long 0x04 20.--21. " DCFCTL_PULSESEL ,Pulse select for blanking & capture alignment" "TBCTR = TBPRD,TBCTR = 0,?..."
|
|
bitfld.long 0x04 19. " DCFCTL_BLANKINV ,Blanking window inversion" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x04 18. " DCFCTL_BLANKE ,Blanking window enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16.--17. " DCFCTL_SRCSEL ,Filter block signal source select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2"
|
|
newline
|
|
bitfld.long 0x04 9. " DCBCTL_EVT2FRC_SYNCSEL ,DCBEVT2 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.long 0x04 8. " DCBCTL_EVT2SRCSEL ,DCBEVT2 source signal select" "DCBEVT2,DCEVTFILT"
|
|
newline
|
|
bitfld.long 0x04 3. " DCBCTL_EVT1SYNCE ,DCBEVT1 SYNC generation" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " DCBCTL_EVT1SOCE ,DCBEVT1 SOC generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " DCBCTL_EVT1FRC_SYNCSEL ,DCBEVT1 force synchronization signal select" "Synchronous,Asynchronous"
|
|
bitfld.long 0x04 0. " DCBCTL_EVT1SRCSEL ,DCBEVT1 source signal select" "DCBEVT1,DCEVTFILT"
|
|
line.long 0x08 "DCCAPCTL_DCFOFFSET,Digital Compare Capture Control Register/Digital Compare Filter Offset Register"
|
|
hexmask.long.word 0x08 16.--31. 0x01 " DCFOFFSET_OFFSET ,Blanking window offset"
|
|
bitfld.long 0x08 1. " DCCAPCTL_SHDWMODE ,TBCTR counter capture shadow select mode" "Shadow mode,Active mode"
|
|
newline
|
|
bitfld.long 0x08 0. " DCCAPCTL_CAPE ,TBCTR counter capture enable" "Disabled,Enabled"
|
|
line.long 0x0C "DCFOFFSETCNT_DCFWINDOW,Digital Compare Filter Offset Counter Register/Digital Compare Filter Window Register"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " DCFWINDOW_WINDOW ,Blanking window width"
|
|
hexmask.long.word 0x0C 0.--15. 0x01 " DCFOFFSETCNT_OFFSETCNT ,Blanking offset counter"
|
|
line.long 0x10 "DCFWINDOWCNT_DCCAP,Digital Compare Filter Window Counter Register/Digital Compare Counter Capture Register"
|
|
hexmask.long.word 0x10 16.--31. 1. " DCCAP ,Digital compare time-base counter capture"
|
|
hexmask.long.byte 0x10 0.--7. 1. " DCFWINDOWCNT ,Blanking window counter"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif !cpuis("AWR1843*")&&!cpuis("AWR6843*")
|
|
tree "DCAN (Controller Area Network)"
|
|
base ad:0xFFF7DC00
|
|
width 14.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,DCAN Control Register"
|
|
bitfld.long 0x00 25. " WUBA ,Automatic wake up on bus activity when in local power-down mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PDR ,Request for local low power-down mode" "Not requested,Requested"
|
|
bitfld.long 0x00 20. " DE3 ,Enable DMA request line for IF3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " DE2 ,Enable DMA request line for IF2" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DE1 ,Enable DMA request line for IF1" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " IE1 ,Interrupt line 1 enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 16. " INITDBG ,Internal init state while debug access" "Not debug,Debug"
|
|
bitfld.long 0x00 15. " SWR ,Software reset enable" "No reset,Reset"
|
|
bitfld.long 0x00 10.--13. " PMD ,ECC on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " ABO ,Auto-Bus-On enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " IDS ,Interruption debug support enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TEST ,Test mode enable" "Normal operation,Test mode"
|
|
newline
|
|
bitfld.long 0x00 6. " CCE ,Configuration change enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DAR ,Disable automatic retransmission" "No,Yes"
|
|
bitfld.long 0x00 3. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " SIE ,Status change interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " IE0 ,Interrupt line 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " INIT ,Initialization" "Normal operation,Initialization"
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "ES,Error And Status Register"
|
|
in
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ERRC,Error Counter Register"
|
|
bitfld.long 0x00 15. " RP ,Receive error passive" "Not reached,Reached"
|
|
hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive error counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit error counter"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "BTR,Bit Timing Register"
|
|
rbitfld.long 0x00 16.--19. " BRPE ,Baud rate prescaler extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--14. " TSEG2 ,Time segment after the sample point" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. " TSEG1 ,Time segment before the sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " SJW ,Synchronization jump width" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " BRP ,Baud rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "INT,Interrupt Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " INT1ID ,Interrupt 1 identifier"
|
|
hexmask.long.word 0x00 0.--15. 1. " INT0ID ,Interrupt identifier"
|
|
if (((per.l(ad:0xFFF7DC00))&0x80)==0x80)
|
|
if (((per.l(ad:0xFFF7DC00+0x14))&0x10)==0x00)
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM direct access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External loopback mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX ,Control of CAN_TX pin" "Normal operation,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loopback mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent mode" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM direct access enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX ,Control of CAN_TX pin" "Normal operation,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loopback mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent mode" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xFFF7DC00+0x14))&0x10)==0x00)
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM direct access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EXL ,External loopback mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX ,Control of CAN_TX pin" "Normal operation,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loopback mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent mode" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TEST,Test Register"
|
|
bitfld.long 0x00 9. " RDA ,RAM direct access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " RX ,Receive pin" "Dominant,Recessive"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " TX ,Control of CAN_TX pin" "Normal operation,Sample point,Dominant,Recessive"
|
|
bitfld.long 0x00 4. " LBACK ,Loopback mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SILENT ,Silent mode" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
rgroup.long 0x1C++0x07
|
|
line.long 0x00 "PERR,Parity Error Code Register"
|
|
bitfld.long 0x00 8.--10. " WORD_NUMBER ,Word number where parity error has been detected" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message object number where parity error has been detected"
|
|
line.long 0x04 "REV_ID,Core Revision ID Register"
|
|
group.long 0x24++0x0F
|
|
line.long 0x00 "ECCDIAG,ECC Diagnostic Register"
|
|
bitfld.long 0x00 0.--3. " ECC_DIAG ,SECDED diagnostic mode enable/disable" ",,,,,Enabled,,,,,Disabled,?..."
|
|
line.long 0x04 "ECCDIAG_STAT,ECC Diagnostic Status Register"
|
|
bitfld.long 0x04 8. " DEFLG_DIAG ,Double bit error flag diagnostic" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " SEFLG_DIAG ,Single bit error flag diagnostic" "Not detected,Detected"
|
|
line.long 0x08 "ECC_CS,ECC Control And Status Register"
|
|
bitfld.long 0x08 24.--27. " SBE_EVT_EN ,Enable/disable SECDED single bit error event" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 16.--19. " ECCMODE ,Enable/disable SECDED single bit error correction" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 8. " DEFLG ,Double bit error flag" "Not detected,Detected"
|
|
newline
|
|
bitfld.long 0x08 0. " SEFLG ,Single bit error flag" "Not detected,Detected"
|
|
line.long 0x0C "ECC_SERR,ECC Single Bit Error Code Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " MSG_NUM ,Message object number where ECC single bit error has been detected"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ABOTR,Auto-Bus-On Time Register"
|
|
newline
|
|
rgroup.long 0x84++0x5F
|
|
line.long 0x00 "TXRQ_X,Transmission Request X Register"
|
|
bitfld.long 0x00 15. " TXRQSTREG8[1] ,Transmission request bit for message objects 121-128" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [0] ,Transmission request bit for message objects 113-120" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 13. " TXRQSTREG7[1] ,Transmission request bit for message objects 105-112" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [0] ,Transmission request bit for message objects 97-104" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 11. " TXRQSTREG6[1] ,Transmission request bit for message objects 89-96" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [0] ,Transmission request bit for message objects 81-88" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 9. " TXRQSTREG5[1] ,Transmission request bit for message objects 73-80" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [0] ,Transmission request bit for message objects 65-72" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " TXRQSTREG4[1] ,Transmission request bit for message objects 57-64" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [0] ,Transmission request bit for message objects 49-56" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 5. " TXRQSTREG3[1] ,Transmission request bit for message objects 41-48" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [0] ,Transmission request bit for message objects 33-40" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 3. " TXRQSTREG2[1] ,Transmission request bit for message objects 25-32" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [0] ,Transmission request bit for message objects 17-24" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 1. " TXRQSTREG1[1] ,Transmission request bit for message objects 9-16" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Transmission request bit for message objects 1-8" "Not requested,Requested"
|
|
line.long 0x04 "TXRQ12,Transmission Request Register"
|
|
bitfld.long 0x04 31. " TXRQS[32] ,Transmission request bit for message object 32" "Not requested,Requested"
|
|
bitfld.long 0x04 30. " [31] ,Transmission request bit for message object 31" "Not requested,Requested"
|
|
bitfld.long 0x04 29. " [30] ,Transmission request bit for message object 30" "Not requested,Requested"
|
|
bitfld.long 0x04 28. " [29] ,Transmission request bit for message object 29" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 27. " [28] ,Transmission request bit for message object 28" "Not requested,Requested"
|
|
bitfld.long 0x04 26. " [27] ,Transmission request bit for message object 27" "Not requested,Requested"
|
|
bitfld.long 0x04 25. " [26] ,Transmission request bit for message object 26" "Not requested,Requested"
|
|
bitfld.long 0x04 24. " [25] ,Transmission request bit for message object 25" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 23. " [24] ,Transmission request bit for message object 24" "Not requested,Requested"
|
|
bitfld.long 0x04 22. " [23] ,Transmission request bit for message object 23" "Not requested,Requested"
|
|
bitfld.long 0x04 21. " [22] ,Transmission request bit for message object 22" "Not requested,Requested"
|
|
bitfld.long 0x04 20. " [21] ,Transmission request bit for message object 21" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 19. " [20] ,Transmission request bit for message object 20" "Not requested,Requested"
|
|
bitfld.long 0x04 18. " [19] ,Transmission request bit for message object 19" "Not requested,Requested"
|
|
bitfld.long 0x04 17. " [18] ,Transmission request bit for message object 18" "Not requested,Requested"
|
|
bitfld.long 0x04 16. " [17] ,Transmission request bit for message object 17" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 15. " [16] ,Transmission request bit for message object 16" "Not requested,Requested"
|
|
bitfld.long 0x04 14. " [15] ,Transmission request bit for message object 15" "Not requested,Requested"
|
|
bitfld.long 0x04 13. " [14] ,Transmission request bit for message object 14" "Not requested,Requested"
|
|
bitfld.long 0x04 12. " [13] ,Transmission request bit for message object 13" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 11. " [12] ,Transmission request bit for message object 12" "Not requested,Requested"
|
|
bitfld.long 0x04 10. " [11] ,Transmission request bit for message object 11" "Not requested,Requested"
|
|
bitfld.long 0x04 9. " [10] ,Transmission request bit for message object 10" "Not requested,Requested"
|
|
bitfld.long 0x04 8. " [9] ,Transmission request bit for message object 9" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 7. " [8] ,Transmission request bit for message object 8" "Not requested,Requested"
|
|
bitfld.long 0x04 6. " [7] ,Transmission request bit for message object 7" "Not requested,Requested"
|
|
bitfld.long 0x04 5. " [6] ,Transmission request bit for message object 6" "Not requested,Requested"
|
|
bitfld.long 0x04 4. " [5] ,Transmission request bit for message object 5" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x04 3. " [4] ,Transmission request bit for message object 4" "Not requested,Requested"
|
|
bitfld.long 0x04 2. " [3] ,Transmission request bit for message object 3" "Not requested,Requested"
|
|
bitfld.long 0x04 1. " [2] ,Transmission request bit for message object 2" "Not requested,Requested"
|
|
bitfld.long 0x04 0. " [1] ,Transmission request bit for message object 1" "Not requested,Requested"
|
|
line.long 0x08 "TXRQ34,Transmission Request Register"
|
|
bitfld.long 0x08 31. " TXRQS[64] ,Transmission request bit for message object 64" "Not requested,Requested"
|
|
bitfld.long 0x08 30. " [63] ,Transmission request bit for message object 63" "Not requested,Requested"
|
|
bitfld.long 0x08 29. " [62] ,Transmission request bit for message object 62" "Not requested,Requested"
|
|
bitfld.long 0x08 28. " [61] ,Transmission request bit for message object 61" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 27. " [60] ,Transmission request bit for message object 60" "Not requested,Requested"
|
|
bitfld.long 0x08 26. " [59] ,Transmission request bit for message object 59" "Not requested,Requested"
|
|
bitfld.long 0x08 25. " [58] ,Transmission request bit for message object 58" "Not requested,Requested"
|
|
bitfld.long 0x08 24. " [57] ,Transmission request bit for message object 57" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 23. " [56] ,Transmission request bit for message object 56" "Not requested,Requested"
|
|
bitfld.long 0x08 22. " [55] ,Transmission request bit for message object 55" "Not requested,Requested"
|
|
bitfld.long 0x08 21. " [54] ,Transmission request bit for message object 54" "Not requested,Requested"
|
|
bitfld.long 0x08 20. " [53] ,Transmission request bit for message object 53" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 19. " [52] ,Transmission request bit for message object 52" "Not requested,Requested"
|
|
bitfld.long 0x08 18. " [51] ,Transmission request bit for message object 51" "Not requested,Requested"
|
|
bitfld.long 0x08 17. " [50] ,Transmission request bit for message object 50" "Not requested,Requested"
|
|
bitfld.long 0x08 16. " [49] ,Transmission request bit for message object 49" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 15. " [48] ,Transmission request bit for message object 48" "Not requested,Requested"
|
|
bitfld.long 0x08 14. " [47] ,Transmission request bit for message object 47" "Not requested,Requested"
|
|
bitfld.long 0x08 13. " [46] ,Transmission request bit for message object 46" "Not requested,Requested"
|
|
bitfld.long 0x08 12. " [45] ,Transmission request bit for message object 45" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 11. " [44] ,Transmission request bit for message object 44" "Not requested,Requested"
|
|
bitfld.long 0x08 10. " [43] ,Transmission request bit for message object 43" "Not requested,Requested"
|
|
bitfld.long 0x08 9. " [42] ,Transmission request bit for message object 42" "Not requested,Requested"
|
|
bitfld.long 0x08 8. " [41] ,Transmission request bit for message object 41" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 7. " [40] ,Transmission request bit for message object 40" "Not requested,Requested"
|
|
bitfld.long 0x08 6. " [39] ,Transmission request bit for message object 39" "Not requested,Requested"
|
|
bitfld.long 0x08 5. " [38] ,Transmission request bit for message object 38" "Not requested,Requested"
|
|
bitfld.long 0x08 4. " [37] ,Transmission request bit for message object 37" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x08 3. " [36] ,Transmission request bit for message object 36" "Not requested,Requested"
|
|
bitfld.long 0x08 2. " [35] ,Transmission request bit for message object 35" "Not requested,Requested"
|
|
bitfld.long 0x08 1. " [34] ,Transmission request bit for message object 34" "Not requested,Requested"
|
|
bitfld.long 0x08 0. " [33] ,Transmission request bit for message object 33" "Not requested,Requested"
|
|
line.long 0x0C "TXRQ56,Transmission Request Register"
|
|
bitfld.long 0x0C 31. " TXRQS[96] ,Transmission request bit for message object 96" "Not requested,Requested"
|
|
bitfld.long 0x0C 30. " [95] ,Transmission request bit for message object 95" "Not requested,Requested"
|
|
bitfld.long 0x0C 29. " [94] ,Transmission request bit for message object 94" "Not requested,Requested"
|
|
bitfld.long 0x0C 28. " [93] ,Transmission request bit for message object 93" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 27. " [92] ,Transmission request bit for message object 92" "Not requested,Requested"
|
|
bitfld.long 0x0C 26. " [91] ,Transmission request bit for message object 91" "Not requested,Requested"
|
|
bitfld.long 0x0C 25. " [90] ,Transmission request bit for message object 90" "Not requested,Requested"
|
|
bitfld.long 0x0C 24. " [89] ,Transmission request bit for message object 89" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 23. " [88] ,Transmission request bit for message object 88" "Not requested,Requested"
|
|
bitfld.long 0x0C 22. " [87] ,Transmission request bit for message object 87" "Not requested,Requested"
|
|
bitfld.long 0x0C 21. " [86] ,Transmission request bit for message object 86" "Not requested,Requested"
|
|
bitfld.long 0x0C 20. " [85] ,Transmission request bit for message object 85" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 19. " [84] ,Transmission request bit for message object 84" "Not requested,Requested"
|
|
bitfld.long 0x0C 18. " [83] ,Transmission request bit for message object 83" "Not requested,Requested"
|
|
bitfld.long 0x0C 17. " [82] ,Transmission request bit for message object 82" "Not requested,Requested"
|
|
bitfld.long 0x0C 16. " [81] ,Transmission request bit for message object 81" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 15. " [80] ,Transmission request bit for message object 80" "Not requested,Requested"
|
|
bitfld.long 0x0C 14. " [79] ,Transmission request bit for message object 79" "Not requested,Requested"
|
|
bitfld.long 0x0C 13. " [78] ,Transmission request bit for message object 78" "Not requested,Requested"
|
|
bitfld.long 0x0C 12. " [77] ,Transmission request bit for message object 77" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 11. " [76] ,Transmission request bit for message object 76" "Not requested,Requested"
|
|
bitfld.long 0x0C 10. " [75] ,Transmission request bit for message object 75" "Not requested,Requested"
|
|
bitfld.long 0x0C 9. " [74] ,Transmission request bit for message object 74" "Not requested,Requested"
|
|
bitfld.long 0x0C 8. " [73] ,Transmission request bit for message object 73" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 7. " [72] ,Transmission request bit for message object 72" "Not requested,Requested"
|
|
bitfld.long 0x0C 6. " [71] ,Transmission request bit for message object 71" "Not requested,Requested"
|
|
bitfld.long 0x0C 5. " [70] ,Transmission request bit for message object 70" "Not requested,Requested"
|
|
bitfld.long 0x0C 4. " [69] ,Transmission request bit for message object 69" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x0C 3. " [68] ,Transmission request bit for message object 68" "Not requested,Requested"
|
|
bitfld.long 0x0C 2. " [67] ,Transmission request bit for message object 67" "Not requested,Requested"
|
|
bitfld.long 0x0C 1. " [66] ,Transmission request bit for message object 66" "Not requested,Requested"
|
|
bitfld.long 0x0C 0. " [65] ,Transmission request bit for message object 65" "Not requested,Requested"
|
|
line.long 0x10 "TXRQ78,Transmission Request Register"
|
|
bitfld.long 0x10 31. " TXRQS[128] ,Transmission request bit for message object 128" "Not requested,Requested"
|
|
bitfld.long 0x10 30. " [127] ,Transmission request bit for message object 127" "Not requested,Requested"
|
|
bitfld.long 0x10 29. " [126] ,Transmission request bit for message object 126" "Not requested,Requested"
|
|
bitfld.long 0x10 28. " [125] ,Transmission request bit for message object 125" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 27. " [124] ,Transmission request bit for message object 124" "Not requested,Requested"
|
|
bitfld.long 0x10 26. " [123] ,Transmission request bit for message object 123" "Not requested,Requested"
|
|
bitfld.long 0x10 25. " [122] ,Transmission request bit for message object 122" "Not requested,Requested"
|
|
bitfld.long 0x10 24. " [121] ,Transmission request bit for message object 121" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 23. " [120] ,Transmission request bit for message object 120" "Not requested,Requested"
|
|
bitfld.long 0x10 22. " [119] ,Transmission request bit for message object 119" "Not requested,Requested"
|
|
bitfld.long 0x10 21. " [118] ,Transmission request bit for message object 118" "Not requested,Requested"
|
|
bitfld.long 0x10 20. " [117] ,Transmission request bit for message object 117" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 19. " [116] ,Transmission request bit for message object 116" "Not requested,Requested"
|
|
bitfld.long 0x10 18. " [115] ,Transmission request bit for message object 115" "Not requested,Requested"
|
|
bitfld.long 0x10 17. " [114] ,Transmission request bit for message object 114" "Not requested,Requested"
|
|
bitfld.long 0x10 16. " [113] ,Transmission request bit for message object 113" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 15. " [112] ,Transmission request bit for message object 112" "Not requested,Requested"
|
|
bitfld.long 0x10 14. " [111] ,Transmission request bit for message object 111" "Not requested,Requested"
|
|
bitfld.long 0x10 13. " [110] ,Transmission request bit for message object 110" "Not requested,Requested"
|
|
bitfld.long 0x10 12. " [109] ,Transmission request bit for message object 109" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 11. " [108] ,Transmission request bit for message object 108" "Not requested,Requested"
|
|
bitfld.long 0x10 10. " [107] ,Transmission request bit for message object 107" "Not requested,Requested"
|
|
bitfld.long 0x10 9. " [106] ,Transmission request bit for message object 106" "Not requested,Requested"
|
|
bitfld.long 0x10 8. " [105] ,Transmission request bit for message object 105" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 7. " [104] ,Transmission request bit for message object 104" "Not requested,Requested"
|
|
bitfld.long 0x10 6. " [103] ,Transmission request bit for message object 103" "Not requested,Requested"
|
|
bitfld.long 0x10 5. " [102] ,Transmission request bit for message object 102" "Not requested,Requested"
|
|
bitfld.long 0x10 4. " [101] ,Transmission request bit for message object 101" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x10 3. " [100] ,Transmission request bit for message object 100" "Not requested,Requested"
|
|
bitfld.long 0x10 2. " [99] ,Transmission request bit for message object 99" "Not requested,Requested"
|
|
bitfld.long 0x10 1. " [98] ,Transmission request bit for message object 98" "Not requested,Requested"
|
|
bitfld.long 0x10 0. " [97] ,Transmission request bit for message object 97" "Not requested,Requested"
|
|
line.long 0x14 "NWDAT_X,New Data X Register"
|
|
bitfld.long 0x14 15. " NEWDATREG8[1] ,New data bit for message objects 121-128" "Not written,Written"
|
|
bitfld.long 0x14 14. " [0] ,New data bit for message objects 113-120" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x14 13. " NEWDATREG7[1] ,New data bit for message objects 105-112" "Not written,Written"
|
|
bitfld.long 0x14 12. " [0] ,New data bit for message objects 97-104" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x14 11. " NEWDATREG6[1] ,New data bit for message objects 89-96" "Not written,Written"
|
|
bitfld.long 0x14 10. " [0] ,New data bit for message objects 81-88" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x14 9. " NEWDATREG5[1] ,New data bit for message objects 73-80" "Not written,Written"
|
|
bitfld.long 0x14 8. " [0] ,New data bit for message objects 65-72" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x14 7. " NEWDATREG4[1] ,New data bit for message objects 57-64" "Not written,Written"
|
|
bitfld.long 0x14 6. " [0] ,New data bit for message objects 49-56" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x14 5. " NEWDATREG3[1] ,New data bit for message objects 41-48" "Not written,Written"
|
|
bitfld.long 0x14 4. " [0] ,New data bit for message objects 33-40" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x14 3. " NEWDATREG2[1] ,New data bit for message objects 25-32" "Not written,Written"
|
|
bitfld.long 0x14 2. " [0] ,New data bit for message objects 17-24" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x14 1. " NEWDATREG1[1] ,New data bit for message objects 9-16" "Not written,Written"
|
|
bitfld.long 0x14 0. " [0] ,New data bit for message objects 1-8" "Not written,Written"
|
|
line.long 0x18 "NWDAT12,New Data Register"
|
|
bitfld.long 0x18 31. " NEWDAT[32] ,New data bit for message object 32" "Not written,Written"
|
|
bitfld.long 0x18 30. " [31] ,New data bit for message object 31" "Not written,Written"
|
|
bitfld.long 0x18 29. " [30] ,New data bit for message object 30" "Not written,Written"
|
|
bitfld.long 0x18 28. " [29] ,New data bit for message object 29" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x18 27. " [28] ,New data bit for message object 28" "Not written,Written"
|
|
bitfld.long 0x18 26. " [27] ,New data bit for message object 27" "Not written,Written"
|
|
bitfld.long 0x18 25. " [26] ,New data bit for message object 26" "Not written,Written"
|
|
bitfld.long 0x18 24. " [25] ,New data bit for message object 25" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x18 23. " [24] ,New data bit for message object 24" "Not written,Written"
|
|
bitfld.long 0x18 22. " [23] ,New data bit for message object 23" "Not written,Written"
|
|
bitfld.long 0x18 21. " [22] ,New data bit for message object 22" "Not written,Written"
|
|
bitfld.long 0x18 20. " [21] ,New data bit for message object 21" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x18 19. " [20] ,New data bit for message object 20" "Not written,Written"
|
|
bitfld.long 0x18 18. " [19] ,New data bit for message object 19" "Not written,Written"
|
|
bitfld.long 0x18 17. " [18] ,New data bit for message object 18" "Not written,Written"
|
|
bitfld.long 0x18 16. " [17] ,New data bit for message object 17" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x18 15. " [16] ,New data bit for message object 16" "Not written,Written"
|
|
bitfld.long 0x18 14. " [15] ,New data bit for message object 15" "Not written,Written"
|
|
bitfld.long 0x18 13. " [14] ,New data bit for message object 14" "Not written,Written"
|
|
bitfld.long 0x18 12. " [13] ,New data bit for message object 13" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x18 11. " [12] ,New data bit for message object 12" "Not written,Written"
|
|
bitfld.long 0x18 10. " [11] ,New data bit for message object 11" "Not written,Written"
|
|
bitfld.long 0x18 9. " [10] ,New data bit for message object 10" "Not written,Written"
|
|
bitfld.long 0x18 8. " [9] ,New data bit for message object 9" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x18 7. " [8] ,New data bit for message object 8" "Not written,Written"
|
|
bitfld.long 0x18 6. " [7] ,New data bit for message object 7" "Not written,Written"
|
|
bitfld.long 0x18 5. " [6] ,New data bit for message object 6" "Not written,Written"
|
|
bitfld.long 0x18 4. " [5] ,New data bit for message object 5" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x18 3. " [4] ,New data bit for message object 4" "Not written,Written"
|
|
bitfld.long 0x18 2. " [3] ,New data bit for message object 3" "Not written,Written"
|
|
bitfld.long 0x18 1. " [2] ,New data bit for message object 2" "Not written,Written"
|
|
bitfld.long 0x18 0. " [1] ,New data bit for message object 1" "Not written,Written"
|
|
line.long 0x1C "NWDAT34,New Data Register"
|
|
bitfld.long 0x1C 31. " NEWDAT[64] ,New data bit for message object 64" "Not written,Written"
|
|
bitfld.long 0x1C 30. " [63] ,New data bit for message object 63" "Not written,Written"
|
|
bitfld.long 0x1C 29. " [62] ,New data bit for message object 62" "Not written,Written"
|
|
bitfld.long 0x1C 28. " [61] ,New data bit for message object 61" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x1C 27. " [60] ,New data bit for message object 60" "Not written,Written"
|
|
bitfld.long 0x1C 26. " [59] ,New data bit for message object 59" "Not written,Written"
|
|
bitfld.long 0x1C 25. " [58] ,New data bit for message object 58" "Not written,Written"
|
|
bitfld.long 0x1C 24. " [57] ,New data bit for message object 57" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x1C 23. " [56] ,New data bit for message object 56" "Not written,Written"
|
|
bitfld.long 0x1C 22. " [55] ,New data bit for message object 55" "Not written,Written"
|
|
bitfld.long 0x1C 21. " [54] ,New data bit for message object 54" "Not written,Written"
|
|
bitfld.long 0x1C 20. " [53] ,New data bit for message object 53" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x1C 19. " [52] ,New data bit for message object 52" "Not written,Written"
|
|
bitfld.long 0x1C 18. " [51] ,New data bit for message object 51" "Not written,Written"
|
|
bitfld.long 0x1C 17. " [50] ,New data bit for message object 50" "Not written,Written"
|
|
bitfld.long 0x1C 16. " [49] ,New data bit for message object 49" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x1C 15. " [48] ,New data bit for message object 48" "Not written,Written"
|
|
bitfld.long 0x1C 14. " [47] ,New data bit for message object 47" "Not written,Written"
|
|
bitfld.long 0x1C 13. " [46] ,New data bit for message object 46" "Not written,Written"
|
|
bitfld.long 0x1C 12. " [45] ,New data bit for message object 45" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x1C 11. " [44] ,New data bit for message object 44" "Not written,Written"
|
|
bitfld.long 0x1C 10. " [43] ,New data bit for message object 43" "Not written,Written"
|
|
bitfld.long 0x1C 9. " [42] ,New data bit for message object 42" "Not written,Written"
|
|
bitfld.long 0x1C 8. " [41] ,New data bit for message object 41" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x1C 7. " [40] ,New data bit for message object 40" "Not written,Written"
|
|
bitfld.long 0x1C 6. " [39] ,New data bit for message object 39" "Not written,Written"
|
|
bitfld.long 0x1C 5. " [38] ,New data bit for message object 38" "Not written,Written"
|
|
bitfld.long 0x1C 4. " [37] ,New data bit for message object 37" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x1C 3. " [36] ,New data bit for message object 68" "Not written,Written"
|
|
bitfld.long 0x1C 2. " [35] ,New data bit for message object 67" "Not written,Written"
|
|
bitfld.long 0x1C 1. " [34] ,New data bit for message object 66" "Not written,Written"
|
|
bitfld.long 0x1C 0. " [33] ,New data bit for message object 65" "Not written,Written"
|
|
line.long 0x20 "NWDAT56,New Data Register"
|
|
bitfld.long 0x20 31. " NEWDAT[96] ,New data bit for message object 96" "Not written,Written"
|
|
bitfld.long 0x20 30. " [95] ,New data bit for message object 95" "Not written,Written"
|
|
bitfld.long 0x20 29. " [94] ,New data bit for message object 94" "Not written,Written"
|
|
bitfld.long 0x20 28. " [93] ,New data bit for message object 93" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x20 27. " [92] ,New data bit for message object 92" "Not written,Written"
|
|
bitfld.long 0x20 26. " [91] ,New data bit for message object 91" "Not written,Written"
|
|
bitfld.long 0x20 25. " [90] ,New data bit for message object 90" "Not written,Written"
|
|
bitfld.long 0x20 24. " [89] ,New data bit for message object 89" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x20 23. " [88] ,New data bit for message object 88" "Not written,Written"
|
|
bitfld.long 0x20 22. " [87] ,New data bit for message object 87" "Not written,Written"
|
|
bitfld.long 0x20 21. " [86] ,New data bit for message object 86" "Not written,Written"
|
|
bitfld.long 0x20 20. " [85] ,New data bit for message object 85" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x20 19. " [84] ,New data bit for message object 84" "Not written,Written"
|
|
bitfld.long 0x20 18. " [83] ,New data bit for message object 83" "Not written,Written"
|
|
bitfld.long 0x20 17. " [82] ,New data bit for message object 82" "Not written,Written"
|
|
bitfld.long 0x20 16. " [81] ,New data bit for message object 81" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x20 15. " [80] ,New data bit for message object 80" "Not written,Written"
|
|
bitfld.long 0x20 14. " [79] ,New data bit for message object 79" "Not written,Written"
|
|
bitfld.long 0x20 13. " [78] ,New data bit for message object 78" "Not written,Written"
|
|
bitfld.long 0x20 12. " [77] ,New data bit for message object 77" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x20 11. " [76] ,New data bit for message object 76" "Not written,Written"
|
|
bitfld.long 0x20 10. " [75] ,New data bit for message object 75" "Not written,Written"
|
|
bitfld.long 0x20 9. " [74] ,New data bit for message object 74" "Not written,Written"
|
|
bitfld.long 0x20 8. " [73] ,New data bit for message object 73" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x20 7. " [72] ,New data bit for message object 72" "Not written,Written"
|
|
bitfld.long 0x20 6. " [71] ,New data bit for message object 71" "Not written,Written"
|
|
bitfld.long 0x20 5. " [70] ,New data bit for message object 70" "Not written,Written"
|
|
bitfld.long 0x20 4. " [69] ,New data bit for message object 69" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x20 3. " [68] ,New data bit for message object 68" "Not written,Written"
|
|
bitfld.long 0x20 2. " [67] ,New data bit for message object 67" "Not written,Written"
|
|
bitfld.long 0x20 1. " [66] ,New data bit for message object 66" "Not written,Written"
|
|
bitfld.long 0x20 0. " [65] ,New data bit for message object 65" "Not written,Written"
|
|
line.long 0x24 "NWDAT78,New Data Register"
|
|
bitfld.long 0x24 31. " NEWDAT[128] ,New data bit for message object 128" "Not written,Written"
|
|
bitfld.long 0x24 30. " [127] ,New data bit for message object 127" "Not written,Written"
|
|
bitfld.long 0x24 29. " [126] ,New data bit for message object 126" "Not written,Written"
|
|
bitfld.long 0x24 28. " [125] ,New data bit for message object 125" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x24 27. " [124] ,New data bit for message object 124" "Not written,Written"
|
|
bitfld.long 0x24 26. " [123] ,New data bit for message object 123" "Not written,Written"
|
|
bitfld.long 0x24 25. " [122] ,New data bit for message object 122" "Not written,Written"
|
|
bitfld.long 0x24 24. " [121] ,New data bit for message object 121" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x24 23. " [120] ,New data bit for message object 120" "Not written,Written"
|
|
bitfld.long 0x24 22. " [119] ,New data bit for message object 119" "Not written,Written"
|
|
bitfld.long 0x24 21. " [118] ,New data bit for message object 118" "Not written,Written"
|
|
bitfld.long 0x24 20. " [117] ,New data bit for message object 117" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x24 19. " [116] ,New data bit for message object 116" "Not written,Written"
|
|
bitfld.long 0x24 18. " [115] ,New data bit for message object 115" "Not written,Written"
|
|
bitfld.long 0x24 17. " [114] ,New data bit for message object 114" "Not written,Written"
|
|
bitfld.long 0x24 16. " [113] ,New data bit for message object 113" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x24 15. " [112] ,New data bit for message object 112" "Not written,Written"
|
|
bitfld.long 0x24 14. " [111] ,New data bit for message object 111" "Not written,Written"
|
|
bitfld.long 0x24 13. " [110] ,New data bit for message object 110" "Not written,Written"
|
|
bitfld.long 0x24 12. " [109] ,New data bit for message object 109" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x24 11. " [108] ,New data bit for message object 108" "Not written,Written"
|
|
bitfld.long 0x24 10. " [107] ,New data bit for message object 107" "Not written,Written"
|
|
bitfld.long 0x24 9. " [106] ,New data bit for message object 106" "Not written,Written"
|
|
bitfld.long 0x24 8. " [105] ,New data bit for message object 105" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x24 7. " [104] ,New data bit for message object 104" "Not written,Written"
|
|
bitfld.long 0x24 6. " [103] ,New data bit for message object 103" "Not written,Written"
|
|
bitfld.long 0x24 5. " [102] ,New data bit for message object 102" "Not written,Written"
|
|
bitfld.long 0x24 4. " [101] ,New data bit for message object 101" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x24 3. " [100] ,New data bit for message object 100" "Not written,Written"
|
|
bitfld.long 0x24 2. " [99] ,New data bit for message object 99" "Not written,Written"
|
|
bitfld.long 0x24 1. " [98] ,New data bit for message object 98" "Not written,Written"
|
|
bitfld.long 0x24 0. " [97] ,New data bit for message object 97" "Not written,Written"
|
|
line.long 0x28 "INTPND_X,Interrupt Pending X Register"
|
|
bitfld.long 0x28 15. " INTPNDREG8[1] ,Interrupt pending for message objects 121-128" "Not pending,Pending"
|
|
bitfld.long 0x28 14. " [0] ,Interrupt pending for message objects 113-120" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x28 13. " INTPNDREG7[1] ,Interrupt pending for message objects 105-112" "Not pending,Pending"
|
|
bitfld.long 0x28 12. " [0] ,Interrupt pending for message objects 97-104" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x28 11. " INTPNDREG6[1] ,Interrupt pending for message objects 89-96" "Not pending,Pending"
|
|
bitfld.long 0x28 10. " [0] ,Interrupt pending for message objects 81-88" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x28 9. " INTPNDREG5[1] ,Interrupt pending for message objects 73-80" "Not pending,Pending"
|
|
bitfld.long 0x28 8. " [0] ,Interrupt pending for message objects 65-72" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x28 7. " INTPNDREG4[1] ,Interrupt pending for message objects 57-64" "Not pending,Pending"
|
|
bitfld.long 0x28 6. " [0] ,Interrupt pending for message objects 49-56" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x28 5. " INTPNDREG3[1] ,Interrupt pending for message objects 41-48" "Not pending,Pending"
|
|
bitfld.long 0x28 4. " [0] ,Interrupt pending for message objects 33-40" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x28 3. " INTPNDREG2[1] ,Interrupt pending for message objects 25-32" "Not pending,Pending"
|
|
bitfld.long 0x28 2. " [0] ,Interrupt pending for message objects 17-24" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x28 1. " INTPNDREG1[1] ,Interrupt pending for message objects 9-16" "Not pending,Pending"
|
|
bitfld.long 0x28 0. " [0] ,Interrupt pending for message objects 1-8" "Not pending,Pending"
|
|
line.long 0x2C "INTPND12,Interrupt Pending Register"
|
|
bitfld.long 0x2C 31. " INTPND[32] ,Interrupt pending for message object 32" "Not pending,Pending"
|
|
bitfld.long 0x2C 30. " [31] ,Interrupt pending for message object 31" "Not pending,Pending"
|
|
bitfld.long 0x2C 29. " [30] ,Interrupt pending for message object 30" "Not pending,Pending"
|
|
bitfld.long 0x2C 28. " [29] ,Interrupt pending for message object 29" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x2C 27. " [28] ,Interrupt pending for message object 28" "Not pending,Pending"
|
|
bitfld.long 0x2C 26. " [27] ,Interrupt pending for message object 27" "Not pending,Pending"
|
|
bitfld.long 0x2C 25. " [26] ,Interrupt pending for message object 26" "Not pending,Pending"
|
|
bitfld.long 0x2C 24. " [25] ,Interrupt pending for message object 25" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x2C 23. " [24] ,Interrupt pending for message object 24" "Not pending,Pending"
|
|
bitfld.long 0x2C 22. " [23] ,Interrupt pending for message object 23" "Not pending,Pending"
|
|
bitfld.long 0x2C 21. " [22] ,Interrupt pending for message object 22" "Not pending,Pending"
|
|
bitfld.long 0x2C 20. " [21] ,Interrupt pending for message object 21" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x2C 19. " [20] ,Interrupt pending for message object 20" "Not pending,Pending"
|
|
bitfld.long 0x2C 18. " [19] ,Interrupt pending for message object 19" "Not pending,Pending"
|
|
bitfld.long 0x2C 17. " [18] ,Interrupt pending for message object 18" "Not pending,Pending"
|
|
bitfld.long 0x2C 16. " [17] ,Interrupt pending for message object 17" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x2C 15. " [16] ,Interrupt pending for message object 16" "Not pending,Pending"
|
|
bitfld.long 0x2C 14. " [15] ,Interrupt pending for message object 15" "Not pending,Pending"
|
|
bitfld.long 0x2C 13. " [14] ,Interrupt pending for message object 14" "Not pending,Pending"
|
|
bitfld.long 0x2C 12. " [13] ,Interrupt pending for message object 13" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x2C 11. " [12] ,Interrupt pending for message object 12" "Not pending,Pending"
|
|
bitfld.long 0x2C 10. " [11] ,Interrupt pending for message object 11" "Not pending,Pending"
|
|
bitfld.long 0x2C 9. " [10] ,Interrupt pending for message object 10" "Not pending,Pending"
|
|
bitfld.long 0x2C 8. " [9] ,Interrupt pending for message object 9" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x2C 7. " [8] ,Interrupt pending for message object 8" "Not pending,Pending"
|
|
bitfld.long 0x2C 6. " [7] ,Interrupt pending for message object 7" "Not pending,Pending"
|
|
bitfld.long 0x2C 5. " [6] ,Interrupt pending for message object 6" "Not pending,Pending"
|
|
bitfld.long 0x2C 4. " [5] ,Interrupt pending for message object 5" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x2C 3. " [4] ,Interrupt pending for message object 4" "Not pending,Pending"
|
|
bitfld.long 0x2C 2. " [3] ,Interrupt pending for message object 3" "Not pending,Pending"
|
|
bitfld.long 0x2C 1. " [2] ,Interrupt pending for message object 2" "Not pending,Pending"
|
|
bitfld.long 0x2C 0. " [1] ,Interrupt pending for message object 1" "Not pending,Pending"
|
|
line.long 0x30 "INTPND34,Interrupt Pending Register"
|
|
bitfld.long 0x30 31. " INTPND[64] ,Interrupt pending for message object 64" "Not pending,Pending"
|
|
bitfld.long 0x30 30. " [63] ,Interrupt pending for message object 63" "Not pending,Pending"
|
|
bitfld.long 0x30 29. " [62] ,Interrupt pending for message object 62" "Not pending,Pending"
|
|
bitfld.long 0x30 28. " [61] ,Interrupt pending for message object 61" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x30 27. " [60] ,Interrupt pending for message object 60" "Not pending,Pending"
|
|
bitfld.long 0x30 26. " [59] ,Interrupt pending for message object 59" "Not pending,Pending"
|
|
bitfld.long 0x30 25. " [58] ,Interrupt pending for message object 58" "Not pending,Pending"
|
|
bitfld.long 0x30 24. " [57] ,Interrupt pending for message object 57" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x30 23. " [56] ,Interrupt pending for message object 56" "Not pending,Pending"
|
|
bitfld.long 0x30 22. " [55] ,Interrupt pending for message object 55" "Not pending,Pending"
|
|
bitfld.long 0x30 21. " [54] ,Interrupt pending for message object 54" "Not pending,Pending"
|
|
bitfld.long 0x30 20. " [53] ,Interrupt pending for message object 53" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x30 19. " [52] ,Interrupt pending for message object 52" "Not pending,Pending"
|
|
bitfld.long 0x30 18. " [51] ,Interrupt pending for message object 51" "Not pending,Pending"
|
|
bitfld.long 0x30 17. " [50] ,Interrupt pending for message object 50" "Not pending,Pending"
|
|
bitfld.long 0x30 16. " [49] ,Interrupt pending for message object 49" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x30 15. " [48] ,Interrupt pending for message object 48" "Not pending,Pending"
|
|
bitfld.long 0x30 14. " [47] ,Interrupt pending for message object 47" "Not pending,Pending"
|
|
bitfld.long 0x30 13. " [46] ,Interrupt pending for message object 46" "Not pending,Pending"
|
|
bitfld.long 0x30 12. " [45] ,Interrupt pending for message object 45" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x30 11. " [44] ,Interrupt pending for message object 44" "Not pending,Pending"
|
|
bitfld.long 0x30 10. " [43] ,Interrupt pending for message object 43" "Not pending,Pending"
|
|
bitfld.long 0x30 9. " [42] ,Interrupt pending for message object 42" "Not pending,Pending"
|
|
bitfld.long 0x30 8. " [41] ,Interrupt pending for message object 41" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x30 7. " [40] ,Interrupt pending for message object 40" "Not pending,Pending"
|
|
bitfld.long 0x30 6. " [39] ,Interrupt pending for message object 39" "Not pending,Pending"
|
|
bitfld.long 0x30 5. " [38] ,Interrupt pending for message object 38" "Not pending,Pending"
|
|
bitfld.long 0x30 4. " [37] ,Interrupt pending for message object 37" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x30 3. " [36] ,Interrupt pending for message object 68" "Not pending,Pending"
|
|
bitfld.long 0x30 2. " [35] ,Interrupt pending for message object 67" "Not pending,Pending"
|
|
bitfld.long 0x30 1. " [34] ,Interrupt pending for message object 66" "Not pending,Pending"
|
|
bitfld.long 0x30 0. " [33] ,Interrupt pending for message object 65" "Not pending,Pending"
|
|
line.long 0x34 "INTPND56,Interrupt Pending Register"
|
|
bitfld.long 0x34 31. " INTPND[96] ,Interrupt pending for message object 96" "Not pending,Pending"
|
|
bitfld.long 0x34 30. " [95] ,Interrupt pending for message object 95" "Not pending,Pending"
|
|
bitfld.long 0x34 29. " [94] ,Interrupt pending for message object 94" "Not pending,Pending"
|
|
bitfld.long 0x34 28. " [93] ,Interrupt pending for message object 93" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x34 27. " [92] ,Interrupt pending for message object 92" "Not pending,Pending"
|
|
bitfld.long 0x34 26. " [91] ,Interrupt pending for message object 91" "Not pending,Pending"
|
|
bitfld.long 0x34 25. " [90] ,Interrupt pending for message object 90" "Not pending,Pending"
|
|
bitfld.long 0x34 24. " [89] ,Interrupt pending for message object 89" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x34 23. " [88] ,Interrupt pending for message object 88" "Not pending,Pending"
|
|
bitfld.long 0x34 22. " [87] ,Interrupt pending for message object 87" "Not pending,Pending"
|
|
bitfld.long 0x34 21. " [86] ,Interrupt pending for message object 86" "Not pending,Pending"
|
|
bitfld.long 0x34 20. " [85] ,Interrupt pending for message object 85" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x34 19. " [84] ,Interrupt pending for message object 84" "Not pending,Pending"
|
|
bitfld.long 0x34 18. " [83] ,Interrupt pending for message object 83" "Not pending,Pending"
|
|
bitfld.long 0x34 17. " [82] ,Interrupt pending for message object 82" "Not pending,Pending"
|
|
bitfld.long 0x34 16. " [81] ,Interrupt pending for message object 81" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x34 15. " [80] ,Interrupt pending for message object 80" "Not pending,Pending"
|
|
bitfld.long 0x34 14. " [79] ,Interrupt pending for message object 79" "Not pending,Pending"
|
|
bitfld.long 0x34 13. " [78] ,Interrupt pending for message object 78" "Not pending,Pending"
|
|
bitfld.long 0x34 12. " [77] ,Interrupt pending for message object 77" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x34 11. " [76] ,Interrupt pending for message object 76" "Not pending,Pending"
|
|
bitfld.long 0x34 10. " [75] ,Interrupt pending for message object 75" "Not pending,Pending"
|
|
bitfld.long 0x34 9. " [74] ,Interrupt pending for message object 74" "Not pending,Pending"
|
|
bitfld.long 0x34 8. " [73] ,Interrupt pending for message object 73" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x34 7. " [72] ,Interrupt pending for message object 72" "Not pending,Pending"
|
|
bitfld.long 0x34 6. " [71] ,Interrupt pending for message object 71" "Not pending,Pending"
|
|
bitfld.long 0x34 5. " [70] ,Interrupt pending for message object 70" "Not pending,Pending"
|
|
bitfld.long 0x34 4. " [69] ,Interrupt pending for message object 69" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x34 3. " [68] ,Interrupt pending for message object 68" "Not pending,Pending"
|
|
bitfld.long 0x34 2. " [67] ,Interrupt pending for message object 67" "Not pending,Pending"
|
|
bitfld.long 0x34 1. " [66] ,Interrupt pending for message object 66" "Not pending,Pending"
|
|
bitfld.long 0x34 0. " [65] ,Interrupt pending for message object 65" "Not pending,Pending"
|
|
line.long 0x38 "INTPND78,Interrupt Pending Register"
|
|
bitfld.long 0x38 31. " INTPND[128] ,Interrupt pending for message object 128" "Not pending,Pending"
|
|
bitfld.long 0x38 30. " [127] ,Interrupt pending for message object 127" "Not pending,Pending"
|
|
bitfld.long 0x38 29. " [126] ,Interrupt pending for message object 126" "Not pending,Pending"
|
|
bitfld.long 0x38 28. " [125] ,Interrupt pending for message object 125" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x38 27. " [124] ,Interrupt pending for message object 124" "Not pending,Pending"
|
|
bitfld.long 0x38 26. " [123] ,Interrupt pending for message object 123" "Not pending,Pending"
|
|
bitfld.long 0x38 25. " [122] ,Interrupt pending for message object 122" "Not pending,Pending"
|
|
bitfld.long 0x38 24. " [121] ,Interrupt pending for message object 121" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x38 23. " [120] ,Interrupt pending for message object 120" "Not pending,Pending"
|
|
bitfld.long 0x38 22. " [119] ,Interrupt pending for message object 119" "Not pending,Pending"
|
|
bitfld.long 0x38 21. " [118] ,Interrupt pending for message object 118" "Not pending,Pending"
|
|
bitfld.long 0x38 20. " [117] ,Interrupt pending for message object 117" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x38 19. " [116] ,Interrupt pending for message object 116" "Not pending,Pending"
|
|
bitfld.long 0x38 18. " [115] ,Interrupt pending for message object 115" "Not pending,Pending"
|
|
bitfld.long 0x38 17. " [114] ,Interrupt pending for message object 114" "Not pending,Pending"
|
|
bitfld.long 0x38 16. " [113] ,Interrupt pending for message object 113" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x38 15. " [112] ,Interrupt pending for message object 112" "Not pending,Pending"
|
|
bitfld.long 0x38 14. " [111] ,Interrupt pending for message object 111" "Not pending,Pending"
|
|
bitfld.long 0x38 13. " [110] ,Interrupt pending for message object 110" "Not pending,Pending"
|
|
bitfld.long 0x38 12. " [109] ,Interrupt pending for message object 109" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x38 11. " [108] ,Interrupt pending for message object 108" "Not pending,Pending"
|
|
bitfld.long 0x38 10. " [107] ,Interrupt pending for message object 107" "Not pending,Pending"
|
|
bitfld.long 0x38 9. " [106] ,Interrupt pending for message object 106" "Not pending,Pending"
|
|
bitfld.long 0x38 8. " [105] ,Interrupt pending for message object 105" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x38 7. " [104] ,Interrupt pending for message object 104" "Not pending,Pending"
|
|
bitfld.long 0x38 6. " [103] ,Interrupt pending for message object 103" "Not pending,Pending"
|
|
bitfld.long 0x38 5. " [102] ,Interrupt pending for message object 102" "Not pending,Pending"
|
|
bitfld.long 0x38 4. " [101] ,Interrupt pending for message object 101" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x38 3. " [100] ,Interrupt pending for message object 100" "Not pending,Pending"
|
|
bitfld.long 0x38 2. " [99] ,Interrupt pending for message object 99" "Not pending,Pending"
|
|
bitfld.long 0x38 1. " [98] ,Interrupt pending for message object 98" "Not pending,Pending"
|
|
bitfld.long 0x38 0. " [97] ,Interrupt pending for message object 97" "Not pending,Pending"
|
|
line.long 0x3C "MSGVAL_X,Message Valid X Register"
|
|
bitfld.long 0x3C 15. " MSGVALREG8[1] ,Message valid for message objects 121-128" "Not valid,Valid"
|
|
bitfld.long 0x3C 14. " [0] ,Message valid for message objects 113-120" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x3C 13. " MSGVALREG7[1] ,Message valid for message objects 105-112" "Not valid,Valid"
|
|
bitfld.long 0x3C 12. " [0] ,Message valid for message objects 97-104" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x3C 11. " MSGVALREG6[1] ,Message valid for message objects 89-96" "Not valid,Valid"
|
|
bitfld.long 0x3C 10. " [0] ,Message valid for message objects 81-88" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x3C 9. " MSGVALREG5[1] ,Message valid for message objects 73-80" "Not valid,Valid"
|
|
bitfld.long 0x3C 8. " [0] ,Message valid for message objects 65-72" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x3C 7. " MSGVALREG4[1] ,Message valid for message objects 57-64" "Not valid,Valid"
|
|
bitfld.long 0x3C 6. " [0] ,Message valid for message objects 49-56" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x3C 5. " MSGVALREG3[1] ,Message valid for message objects 41-48" "Not valid,Valid"
|
|
bitfld.long 0x3C 4. " [0] ,Message valid for message objects 33-40" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x3C 3. " MSGVALREG2[1] ,Message valid for message objects 25-32" "Not valid,Valid"
|
|
bitfld.long 0x3C 2. " [0] ,Message valid for message objects 17-24" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x3C 1. " MSGVALREG1[1] ,Message valid for message objects 9-16" "Not valid,Valid"
|
|
bitfld.long 0x3C 0. " [0] ,Message valid for message objects 1-8" "Not valid,Valid"
|
|
line.long 0x40 "MSGVAL12,Message Valid Register"
|
|
bitfld.long 0x40 31. " MSGVAL[32] ,Message valid for message object 32" "Not valid,Valid"
|
|
bitfld.long 0x40 30. " [31] ,Message valid for message object 31" "Not valid,Valid"
|
|
bitfld.long 0x40 29. " [30] ,Message valid for message object 30" "Not valid,Valid"
|
|
bitfld.long 0x40 28. " [29] ,Message valid for message object 29" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x40 27. " [28] ,Message valid for message object 28" "Not valid,Valid"
|
|
bitfld.long 0x40 26. " [27] ,Message valid for message object 27" "Not valid,Valid"
|
|
bitfld.long 0x40 25. " [26] ,Message valid for message object 26" "Not valid,Valid"
|
|
bitfld.long 0x40 24. " [25] ,Message valid for message object 25" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x40 23. " [24] ,Message valid for message object 24" "Not valid,Valid"
|
|
bitfld.long 0x40 22. " [23] ,Message valid for message object 23" "Not valid,Valid"
|
|
bitfld.long 0x40 21. " [22] ,Message valid for message object 22" "Not valid,Valid"
|
|
bitfld.long 0x40 20. " [21] ,Message valid for message object 21" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x40 19. " [20] ,Message valid for message object 20" "Not valid,Valid"
|
|
bitfld.long 0x40 18. " [19] ,Message valid for message object 19" "Not valid,Valid"
|
|
bitfld.long 0x40 17. " [18] ,Message valid for message object 18" "Not valid,Valid"
|
|
bitfld.long 0x40 16. " [17] ,Message valid for message object 17" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x40 15. " [16] ,Message valid for message object 16" "Not valid,Valid"
|
|
bitfld.long 0x40 14. " [15] ,Message valid for message object 15" "Not valid,Valid"
|
|
bitfld.long 0x40 13. " [14] ,Message valid for message object 14" "Not valid,Valid"
|
|
bitfld.long 0x40 12. " [13] ,Message valid for message object 13" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x40 11. " [12] ,Message valid for message object 12" "Not valid,Valid"
|
|
bitfld.long 0x40 10. " [11] ,Message valid for message object 11" "Not valid,Valid"
|
|
bitfld.long 0x40 9. " [10] ,Message valid for message object 10" "Not valid,Valid"
|
|
bitfld.long 0x40 8. " [9] ,Message valid for message object 9" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x40 7. " [8] ,Message valid for message object 8" "Not valid,Valid"
|
|
bitfld.long 0x40 6. " [7] ,Message valid for message object 7" "Not valid,Valid"
|
|
bitfld.long 0x40 5. " [6] ,Message valid for message object 6" "Not valid,Valid"
|
|
bitfld.long 0x40 4. " [5] ,Message valid for message object 5" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x40 3. " [4] ,Message valid for message object 4" "Not valid,Valid"
|
|
bitfld.long 0x40 2. " [3] ,Message valid for message object 3" "Not valid,Valid"
|
|
bitfld.long 0x40 1. " [2] ,Message valid for message object 2" "Not valid,Valid"
|
|
bitfld.long 0x40 0. " [1] ,Message valid for message object 1" "Not valid,Valid"
|
|
line.long 0x44 "MSGVAL34,Message Valid Register"
|
|
bitfld.long 0x44 31. " MSGVAL[64] ,Message valid for message object 64" "Not valid,Valid"
|
|
bitfld.long 0x44 30. " [63] ,Message valid for message object 63" "Not valid,Valid"
|
|
bitfld.long 0x44 29. " [62] ,Message valid for message object 62" "Not valid,Valid"
|
|
bitfld.long 0x44 28. " [61] ,Message valid for message object 61" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x44 27. " [60] ,Message valid for message object 60" "Not valid,Valid"
|
|
bitfld.long 0x44 26. " [59] ,Message valid for message object 59" "Not valid,Valid"
|
|
bitfld.long 0x44 25. " [58] ,Message valid for message object 58" "Not valid,Valid"
|
|
bitfld.long 0x44 24. " [57] ,Message valid for message object 57" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x44 23. " [56] ,Message valid for message object 56" "Not valid,Valid"
|
|
bitfld.long 0x44 22. " [55] ,Message valid for message object 55" "Not valid,Valid"
|
|
bitfld.long 0x44 21. " [54] ,Message valid for message object 54" "Not valid,Valid"
|
|
bitfld.long 0x44 20. " [53] ,Message valid for message object 53" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x44 19. " [52] ,Message valid for message object 52" "Not valid,Valid"
|
|
bitfld.long 0x44 18. " [51] ,Message valid for message object 51" "Not valid,Valid"
|
|
bitfld.long 0x44 17. " [50] ,Message valid for message object 50" "Not valid,Valid"
|
|
bitfld.long 0x44 16. " [49] ,Message valid for message object 49" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x44 15. " [48] ,Message valid for message object 48" "Not valid,Valid"
|
|
bitfld.long 0x44 14. " [47] ,Message valid for message object 47" "Not valid,Valid"
|
|
bitfld.long 0x44 13. " [46] ,Message valid for message object 46" "Not valid,Valid"
|
|
bitfld.long 0x44 12. " [45] ,Message valid for message object 45" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x44 11. " [44] ,Message valid for message object 44" "Not valid,Valid"
|
|
bitfld.long 0x44 10. " [43] ,Message valid for message object 43" "Not valid,Valid"
|
|
bitfld.long 0x44 9. " [42] ,Message valid for message object 42" "Not valid,Valid"
|
|
bitfld.long 0x44 8. " [41] ,Message valid for message object 41" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x44 7. " [40] ,Message valid for message object 40" "Not valid,Valid"
|
|
bitfld.long 0x44 6. " [39] ,Message valid for message object 39" "Not valid,Valid"
|
|
bitfld.long 0x44 5. " [38] ,Message valid for message object 38" "Not valid,Valid"
|
|
bitfld.long 0x44 4. " [37] ,Message valid for message object 37" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x44 3. " [36] ,Message valid for message object 68" "Not valid,Valid"
|
|
bitfld.long 0x44 2. " [35] ,Message valid for message object 67" "Not valid,Valid"
|
|
bitfld.long 0x44 1. " [34] ,Message valid for message object 66" "Not valid,Valid"
|
|
bitfld.long 0x44 0. " [33] ,Message valid for message object 65" "Not valid,Valid"
|
|
line.long 0x48 "MSGVAL56,Message Valid Register"
|
|
bitfld.long 0x48 31. " MSGVAL[96] ,Message valid for message object 96" "Not valid,Valid"
|
|
bitfld.long 0x48 30. " [95] ,Message valid for message object 95" "Not valid,Valid"
|
|
bitfld.long 0x48 29. " [94] ,Message valid for message object 94" "Not valid,Valid"
|
|
bitfld.long 0x48 28. " [93] ,Message valid for message object 93" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x48 27. " [92] ,Message valid for message object 92" "Not valid,Valid"
|
|
bitfld.long 0x48 26. " [91] ,Message valid for message object 91" "Not valid,Valid"
|
|
bitfld.long 0x48 25. " [90] ,Message valid for message object 90" "Not valid,Valid"
|
|
bitfld.long 0x48 24. " [89] ,Message valid for message object 89" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x48 23. " [88] ,Message valid for message object 88" "Not valid,Valid"
|
|
bitfld.long 0x48 22. " [87] ,Message valid for message object 87" "Not valid,Valid"
|
|
bitfld.long 0x48 21. " [86] ,Message valid for message object 86" "Not valid,Valid"
|
|
bitfld.long 0x48 20. " [85] ,Message valid for message object 85" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x48 19. " [84] ,Message valid for message object 84" "Not valid,Valid"
|
|
bitfld.long 0x48 18. " [83] ,Message valid for message object 83" "Not valid,Valid"
|
|
bitfld.long 0x48 17. " [82] ,Message valid for message object 82" "Not valid,Valid"
|
|
bitfld.long 0x48 16. " [81] ,Message valid for message object 81" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x48 15. " [80] ,Message valid for message object 80" "Not valid,Valid"
|
|
bitfld.long 0x48 14. " [79] ,Message valid for message object 79" "Not valid,Valid"
|
|
bitfld.long 0x48 13. " [78] ,Message valid for message object 78" "Not valid,Valid"
|
|
bitfld.long 0x48 12. " [77] ,Message valid for message object 77" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x48 11. " [76] ,Message valid for message object 76" "Not valid,Valid"
|
|
bitfld.long 0x48 10. " [75] ,Message valid for message object 75" "Not valid,Valid"
|
|
bitfld.long 0x48 9. " [74] ,Message valid for message object 74" "Not valid,Valid"
|
|
bitfld.long 0x48 8. " [73] ,Message valid for message object 73" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x48 7. " [72] ,Message valid for message object 72" "Not valid,Valid"
|
|
bitfld.long 0x48 6. " [71] ,Message valid for message object 71" "Not valid,Valid"
|
|
bitfld.long 0x48 5. " [70] ,Message valid for message object 70" "Not valid,Valid"
|
|
bitfld.long 0x48 4. " [69] ,Message valid for message object 69" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x48 3. " [68] ,Message valid for message object 68" "Not valid,Valid"
|
|
bitfld.long 0x48 2. " [67] ,Message valid for message object 67" "Not valid,Valid"
|
|
bitfld.long 0x48 1. " [66] ,Message valid for message object 66" "Not valid,Valid"
|
|
bitfld.long 0x48 0. " [65] ,Message valid for message object 65" "Not valid,Valid"
|
|
line.long 0x4C "MSGVAL78,Message Valid Register"
|
|
bitfld.long 0x4C 31. " MSGVAL[128] ,Message valid for message object 128" "Not valid,Valid"
|
|
bitfld.long 0x4C 30. " [127] ,Message valid for message object 127" "Not valid,Valid"
|
|
bitfld.long 0x4C 29. " [126] ,Message valid for message object 126" "Not valid,Valid"
|
|
bitfld.long 0x4C 28. " [125] ,Message valid for message object 125" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x4C 27. " [124] ,Message valid for message object 124" "Not valid,Valid"
|
|
bitfld.long 0x4C 26. " [123] ,Message valid for message object 123" "Not valid,Valid"
|
|
bitfld.long 0x4C 25. " [122] ,Message valid for message object 122" "Not valid,Valid"
|
|
bitfld.long 0x4C 24. " [121] ,Message valid for message object 121" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x4C 23. " [120] ,Message valid for message object 120" "Not valid,Valid"
|
|
bitfld.long 0x4C 22. " [119] ,Message valid for message object 119" "Not valid,Valid"
|
|
bitfld.long 0x4C 21. " [118] ,Message valid for message object 118" "Not valid,Valid"
|
|
bitfld.long 0x4C 20. " [117] ,Message valid for message object 117" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x4C 19. " [116] ,Message valid for message object 116" "Not valid,Valid"
|
|
bitfld.long 0x4C 18. " [115] ,Message valid for message object 115" "Not valid,Valid"
|
|
bitfld.long 0x4C 17. " [114] ,Message valid for message object 114" "Not valid,Valid"
|
|
bitfld.long 0x4C 16. " [113] ,Message valid for message object 113" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x4C 15. " [112] ,Message valid for message object 112" "Not valid,Valid"
|
|
bitfld.long 0x4C 14. " [111] ,Message valid for message object 111" "Not valid,Valid"
|
|
bitfld.long 0x4C 13. " [110] ,Message valid for message object 110" "Not valid,Valid"
|
|
bitfld.long 0x4C 12. " [109] ,Message valid for message object 109" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x4C 11. " [108] ,Message valid for message object 108" "Not valid,Valid"
|
|
bitfld.long 0x4C 10. " [107] ,Message valid for message object 107" "Not valid,Valid"
|
|
bitfld.long 0x4C 9. " [106] ,Message valid for message object 106" "Not valid,Valid"
|
|
bitfld.long 0x4C 8. " [105] ,Message valid for message object 105" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x4C 7. " [104] ,Message valid for message object 104" "Not valid,Valid"
|
|
bitfld.long 0x4C 6. " [103] ,Message valid for message object 103" "Not valid,Valid"
|
|
bitfld.long 0x4C 5. " [102] ,Message valid for message object 102" "Not valid,Valid"
|
|
bitfld.long 0x4C 4. " [101] ,Message valid for message object 101" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x4C 3. " [100] ,Message valid for message object 100" "Not valid,Valid"
|
|
bitfld.long 0x4C 2. " [99] ,Message valid for message object 99" "Not valid,Valid"
|
|
bitfld.long 0x4C 1. " [98] ,Message valid for message object 98" "Not valid,Valid"
|
|
bitfld.long 0x4C 0. " [97] ,Message valid for message object 97" "Not valid,Valid"
|
|
line.long 0x50 "INTMUX12,Interrupt Multiplexer Register"
|
|
bitfld.long 0x50 31. " INTMUX[32] ,INTPND interrupt line for message object 32" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 30. " [31] ,INTPND interrupt line for message object 31" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 29. " [30] ,INTPND interrupt line for message object 30" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 28. " [29] ,INTPND interrupt line for message object 29" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x50 27. " [28] ,INTPND interrupt line for message object 28" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 26. " [27] ,INTPND interrupt line for message object 27" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 25. " [26] ,INTPND interrupt line for message object 26" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 24. " [25] ,INTPND interrupt line for message object 25" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x50 23. " [24] ,INTPND interrupt line for message object 24" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 22. " [23] ,INTPND interrupt line for message object 23" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 21. " [22] ,INTPND interrupt line for message object 22" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 20. " [21] ,INTPND interrupt line for message object 21" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x50 19. " [20] ,INTPND interrupt line for message object 20" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 18. " [19] ,INTPND interrupt line for message object 19" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 17. " [18] ,INTPND interrupt line for message object 18" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 16. " [17] ,INTPND interrupt line for message object 17" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x50 15. " [16] ,INTPND interrupt line for message object 16" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 14. " [15] ,INTPND interrupt line for message object 15" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 13. " [14] ,INTPND interrupt line for message object 14" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 12. " [13] ,INTPND interrupt line for message object 13" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x50 11. " [12] ,INTPND interrupt line for message object 12" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 10. " [11] ,INTPND interrupt line for message object 11" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 9. " [10] ,INTPND interrupt line for message object 10" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 8. " [9] ,INTPND interrupt line for message object 9" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x50 7. " [8] ,INTPND interrupt line for message object 8" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 6. " [7] ,INTPND interrupt line for message object 7" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 5. " [6] ,INTPND interrupt line for message object 6" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 4. " [5] ,INTPND interrupt line for message object 5" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x50 3. " [4] ,INTPND interrupt line for message object 4" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 2. " [3] ,INTPND interrupt line for message object 3" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 1. " [2] ,INTPND interrupt line for message object 2" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x50 0. " [1] ,INTPND interrupt line for message object 1" "DCAN0INT,DCAN1INT"
|
|
line.long 0x54 "INTMUX34,Interrupt Multiplexer Register"
|
|
bitfld.long 0x54 31. " INTMUX[64] ,INTPND interrupt line for message object 64" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 30. " [63] ,INTPND interrupt line for message object 63" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 29. " [62] ,INTPND interrupt line for message object 62" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 28. " [61] ,INTPND interrupt line for message object 61" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x54 27. " [60] ,INTPND interrupt line for message object 60" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 26. " [59] ,INTPND interrupt line for message object 59" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 25. " [58] ,INTPND interrupt line for message object 58" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 24. " [57] ,INTPND interrupt line for message object 57" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x54 23. " [56] ,INTPND interrupt line for message object 56" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 22. " [55] ,INTPND interrupt line for message object 55" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 21. " [54] ,INTPND interrupt line for message object 54" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 20. " [53] ,INTPND interrupt line for message object 53" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x54 19. " [52] ,INTPND interrupt line for message object 52" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 18. " [51] ,INTPND interrupt line for message object 51" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 17. " [50] ,INTPND interrupt line for message object 50" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 16. " [49] ,INTPND interrupt line for message object 49" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x54 15. " [48] ,INTPND interrupt line for message object 48" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 14. " [47] ,INTPND interrupt line for message object 47" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 13. " [46] ,INTPND interrupt line for message object 46" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 12. " [45] ,INTPND interrupt line for message object 45" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x54 11. " [44] ,INTPND interrupt line for message object 44" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 10. " [43] ,INTPND interrupt line for message object 43" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 9. " [42] ,INTPND interrupt line for message object 42" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 8. " [41] ,INTPND interrupt line for message object 41" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x54 7. " [40] ,INTPND interrupt line for message object 40" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 6. " [39] ,INTPND interrupt line for message object 39" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 5. " [38] ,INTPND interrupt line for message object 38" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 4. " [37] ,INTPND interrupt line for message object 37" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x54 3. " [36] ,INTPND interrupt line for message object 68" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 2. " [35] ,INTPND interrupt line for message object 67" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 1. " [34] ,INTPND interrupt line for message object 66" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x54 0. " [33] ,INTPND interrupt line for message object 65" "DCAN0INT,DCAN1INT"
|
|
line.long 0x58 "INTMUX56,Interrupt Multiplexer Register"
|
|
bitfld.long 0x58 31. " INTMUX[96] ,INTPND interrupt line for message object 96" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 30. " [95] ,INTPND interrupt line for message object 95" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 29. " [94] ,INTPND interrupt line for message object 94" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 28. " [93] ,INTPND interrupt line for message object 93" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x58 27. " [92] ,INTPND interrupt line for message object 92" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 26. " [91] ,INTPND interrupt line for message object 91" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 25. " [90] ,INTPND interrupt line for message object 90" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 24. " [89] ,INTPND interrupt line for message object 89" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x58 23. " [88] ,INTPND interrupt line for message object 88" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 22. " [87] ,INTPND interrupt line for message object 87" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 21. " [86] ,INTPND interrupt line for message object 86" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 20. " [85] ,INTPND interrupt line for message object 85" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x58 19. " [84] ,INTPND interrupt line for message object 84" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 18. " [83] ,INTPND interrupt line for message object 83" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 17. " [82] ,INTPND interrupt line for message object 82" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 16. " [81] ,INTPND interrupt line for message object 81" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x58 15. " [80] ,INTPND interrupt line for message object 80" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 14. " [79] ,INTPND interrupt line for message object 79" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 13. " [78] ,INTPND interrupt line for message object 78" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 12. " [77] ,INTPND interrupt line for message object 77" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x58 11. " [76] ,INTPND interrupt line for message object 76" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 10. " [75] ,INTPND interrupt line for message object 75" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 9. " [74] ,INTPND interrupt line for message object 74" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 8. " [73] ,INTPND interrupt line for message object 73" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x58 7. " [72] ,INTPND interrupt line for message object 72" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 6. " [71] ,INTPND interrupt line for message object 71" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 5. " [70] ,INTPND interrupt line for message object 70" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 4. " [69] ,INTPND interrupt line for message object 69" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x58 3. " [68] ,INTPND interrupt line for message object 68" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 2. " [67] ,INTPND interrupt line for message object 67" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 1. " [66] ,INTPND interrupt line for message object 66" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x58 0. " [65] ,INTPND interrupt line for message object 65" "DCAN0INT,DCAN1INT"
|
|
line.long 0x5C "INTMUX78,Interrupt Multiplexer Register"
|
|
bitfld.long 0x5C 31. " INTMUX[128] ,INTPND interrupt line for message object 128" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 30. " [127] ,INTPND interrupt line for message object 127" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 29. " [126] ,INTPND interrupt line for message object 126" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 28. " [125] ,INTPND interrupt line for message object 125" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x5C 27. " [124] ,INTPND interrupt line for message object 124" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 26. " [123] ,INTPND interrupt line for message object 123" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 25. " [122] ,INTPND interrupt line for message object 122" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 24. " [121] ,INTPND interrupt line for message object 121" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x5C 23. " [120] ,INTPND interrupt line for message object 120" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 22. " [119] ,INTPND interrupt line for message object 119" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 21. " [118] ,INTPND interrupt line for message object 118" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 20. " [117] ,INTPND interrupt line for message object 117" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x5C 19. " [116] ,INTPND interrupt line for message object 116" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 18. " [115] ,INTPND interrupt line for message object 115" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 17. " [114] ,INTPND interrupt line for message object 114" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 16. " [113] ,INTPND interrupt line for message object 113" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x5C 15. " [112] ,INTPND interrupt line for message object 112" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 14. " [111] ,INTPND interrupt line for message object 111" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 13. " [110] ,INTPND interrupt line for message object 110" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 12. " [109] ,INTPND interrupt line for message object 109" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x5C 11. " [108] ,INTPND interrupt line for message object 108" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 10. " [107] ,INTPND interrupt line for message object 107" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 9. " [106] ,INTPND interrupt line for message object 106" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 8. " [105] ,INTPND interrupt line for message object 105" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x5C 7. " [104] ,INTPND interrupt line for message object 104" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 6. " [103] ,INTPND interrupt line for message object 103" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 5. " [102] ,INTPND interrupt line for message object 102" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 4. " [101] ,INTPND interrupt line for message object 101" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
bitfld.long 0x5C 3. " [100] ,INTPND interrupt line for message object 100" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 2. " [99] ,INTPND interrupt line for message object 99" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 1. " [98] ,INTPND interrupt line for message object 98" "DCAN0INT,DCAN1INT"
|
|
bitfld.long 0x5C 0. " [97] ,INTPND interrupt line for message object 97" "DCAN0INT,DCAN1INT"
|
|
newline
|
|
if (((per.l(ad:0xFFF7DC00+0x100))&0x800000)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IF1CMD,IF1 Command Register"
|
|
bitfld.long 0x00 23. " WR_RD ,Write/read" "Read,Write"
|
|
bitfld.long 0x00 22. " MASK ,Access mask bits" "Not changed,Transferred"
|
|
bitfld.long 0x00 21. " ARB ,Access arbitration bits" "Not changed,Transferred"
|
|
bitfld.long 0x00 20. " CONTROL ,Access control bits" "Not changed,Transferred"
|
|
newline
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear interrupt pending bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 18. " TXRQST_NEWDAT ,Access transmission request bit" "Not changed,Cleared"
|
|
bitfld.long 0x00 17. " DATA_A ,Access data bytes" "Not changed,Transferred"
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Not changed,Transferred"
|
|
newline
|
|
bitfld.long 0x00 15. " BUSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1 update" "Independent,Requested"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Number of message object in message RAM which is used for data transfer"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IF1CMD,IF1 Command Register"
|
|
bitfld.long 0x00 23. " WR_RD ,Write/read" "Read,Write"
|
|
bitfld.long 0x00 22. " MASK ,Access mask bits" "Not changed,Transferred"
|
|
bitfld.long 0x00 21. " ARB ,Access arbitration bits" "Not changed,Transferred"
|
|
bitfld.long 0x00 20. " CONTROL ,Access control bits" "Not changed,Transferred"
|
|
newline
|
|
bitfld.long 0x00 18. " TXRQST_NEWDAT ,Access transmission request bit" "CONTROL bit,Set"
|
|
bitfld.long 0x00 17. " DATA_A ,Access data bytes" "Not changed,Transferred"
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Not changed,Transferred"
|
|
newline
|
|
bitfld.long 0x00 15. " BUSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1 update" "Independent,Requested"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Number of message object in message RAM which is used for data transfer"
|
|
endif
|
|
group.long (0x100+0x04)++0x3
|
|
line.long 0x00 "IF1MSK,IF1 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask extended identifier" "Not used,Used"
|
|
bitfld.long 0x00 30. " MDIR ,Mask message direction" "Not used,Used"
|
|
hexmask.long 0x00 0.--28. 1. " MSK ,Identifier mask"
|
|
if (((per.l(ad:0xFFF7DC00+0x100+0x08))&0x40000000)==0x40000000)
|
|
group.long (0x100+0x08)++0x3
|
|
line.long 0x00 "IF1ARB,IF1 Arbitration Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,Message identifier"
|
|
else
|
|
group.long (0x100+0x08)++0x3
|
|
line.long 0x00 "IF1ARB,IF1 Arbitration Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit"
|
|
hexmask.long.word 0x00 18.--28. 1. " ID ,Message identifier"
|
|
endif
|
|
group.long (0x100+0x0C)++0x0B
|
|
line.long 0x00 "IF1MCTL,IF1 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New data" "Not written,Written"
|
|
bitfld.long 0x00 14. " MSGLST ,Message lost (only valid for message objects with direction = receive)" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Ignored,Used"
|
|
newline
|
|
bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " EOB ,End of block" "0,1"
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
|
|
line.long 0x04 "IF1DATA,IF1 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA_3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA_2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA_1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA_0 ,Data byte 0"
|
|
line.long 0x08 "IF1DATB,IF1 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA_7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA_6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA_5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA_4 ,Data byte 4"
|
|
if (((per.l(ad:0xFFF7DC00+0x120))&0x800000)==0x00)
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "IF2CMD,IF2 Command Register"
|
|
bitfld.long 0x00 23. " WR_RD ,Write/read" "Read,Write"
|
|
bitfld.long 0x00 22. " MASK ,Access mask bits" "Not changed,Transferred"
|
|
bitfld.long 0x00 21. " ARB ,Access arbitration bits" "Not changed,Transferred"
|
|
bitfld.long 0x00 20. " CONTROL ,Access control bits" "Not changed,Transferred"
|
|
newline
|
|
bitfld.long 0x00 19. " CLRINTPND ,Clear interrupt pending bit" "Not cleared,Cleared"
|
|
bitfld.long 0x00 18. " TXRQST_NEWDAT ,Access transmission request bit" "Not changed,Cleared"
|
|
bitfld.long 0x00 17. " DATA_A ,Access data bytes" "Not changed,Transferred"
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Not changed,Transferred"
|
|
newline
|
|
bitfld.long 0x00 15. " BUSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF2 update" "Independent,Requested"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Number of message object in message RAM which is used for data transfer"
|
|
else
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "IF2CMD,IF2 Command Register"
|
|
bitfld.long 0x00 23. " WR_RD ,Write/read" "Read,Write"
|
|
bitfld.long 0x00 22. " MASK ,Access mask bits" "Not changed,Transferred"
|
|
bitfld.long 0x00 21. " ARB ,Access arbitration bits" "Not changed,Transferred"
|
|
bitfld.long 0x00 20. " CONTROL ,Access control bits" "Not changed,Transferred"
|
|
newline
|
|
bitfld.long 0x00 18. " TXRQST_NEWDAT ,Access transmission request bit" "CONTROL bit,Set"
|
|
bitfld.long 0x00 17. " DATA_A ,Access data bytes" "Not changed,Transferred"
|
|
bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Not changed,Transferred"
|
|
newline
|
|
bitfld.long 0x00 15. " BUSY ,Busy flag" "Not busy,Busy"
|
|
bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF2 update" "Independent,Requested"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Number of message object in message RAM which is used for data transfer"
|
|
endif
|
|
group.long (0x120+0x04)++0x3
|
|
line.long 0x00 "IF2MSK,IF2 Mask Register"
|
|
bitfld.long 0x00 31. " MXTD ,Mask extended identifier" "Not used,Used"
|
|
bitfld.long 0x00 30. " MDIR ,Mask message direction" "Not used,Used"
|
|
hexmask.long 0x00 0.--28. 1. " MSK ,Identifier mask"
|
|
if (((per.l(ad:0xFFF7DC00+0x120+0x08))&0x40000000)==0x40000000)
|
|
group.long (0x120+0x08)++0x3
|
|
line.long 0x00 "IF2ARB,IF2 Arbitration Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,Message identifier"
|
|
else
|
|
group.long (0x120+0x08)++0x3
|
|
line.long 0x00 "IF2ARB,IF2 Arbitration Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit"
|
|
hexmask.long.word 0x00 18.--28. 1. " ID ,Message identifier"
|
|
endif
|
|
group.long (0x120+0x0C)++0x0B
|
|
line.long 0x00 "IF2MCTL,IF2 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New data" "Not written,Written"
|
|
bitfld.long 0x00 14. " MSGLST ,Message lost (only valid for message objects with direction = receive)" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Ignored,Used"
|
|
newline
|
|
bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " EOB ,End of block" "0,1"
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
|
|
line.long 0x04 "IF2DATA,IF2 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA_3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA_2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA_1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA_0 ,Data byte 0"
|
|
line.long 0x08 "IF2DATB,IF2 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA_7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA_6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA_5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA_4 ,Data byte 4"
|
|
newline
|
|
group.long 0x140++0x07
|
|
line.long 0x00 "IF3OBS,IF3 Observation Register"
|
|
rbitfld.long 0x00 15. " IF3_UPD ,IF3 update data" "Not updated,Updated"
|
|
rbitfld.long 0x00 12. " IF3_SDB ,IF3 status of data B read access" "Read out,Not read out"
|
|
rbitfld.long 0x00 11. " IF3_SDA ,IF3 status of data B read access" "Read out,Not read out"
|
|
rbitfld.long 0x00 10. " IF3_SC ,IF3 status of control bits read access" "Read out,Not read out"
|
|
newline
|
|
rbitfld.long 0x00 9. " IF3_SA ,IF3 status of arbitration data read access" "Read out,Not read out"
|
|
rbitfld.long 0x00 8. " IF3_SM ,IF3 status of mask data read access" "Read out,Not read out"
|
|
bitfld.long 0x00 4. " DATAB ,Data B read observation" "Not to be read,To be read"
|
|
newline
|
|
bitfld.long 0x00 3. " DATAA ,Data A read observation" "Not to be read,To be read"
|
|
bitfld.long 0x00 2. " CTRL ,Ctrl read observation" "Not to be read,To be read"
|
|
bitfld.long 0x00 1. " ARB ,Arbitration data read observation" "Not to be read,To be read"
|
|
bitfld.long 0x00 0. " MASK ,Mask data read observation" "Not to be read,To be read"
|
|
line.long 0x04 "IF3MSK,IF3 Mask Register"
|
|
rbitfld.long 0x04 31. " MXTD ,Mask extended identifier" "Not used,Used"
|
|
rbitfld.long 0x04 30. " MDIR ,Mask message direction" "Not used,Used"
|
|
hexmask.long 0x04 0.--28. 1. " MSK ,Identifier mask"
|
|
if (((per.l(ad:0xFFF7DC00+0x148))&0x40000000)==0x40000000)
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "IF3ARB,IF3 Arbitration Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit"
|
|
hexmask.long 0x00 0.--28. 1. " ID ,Message identifier"
|
|
else
|
|
rgroup.long 0x148++0x03
|
|
line.long 0x00 "IF3ARB,IF$2 Arbitration Register"
|
|
bitfld.long 0x00 31. " MSGVAL ,Message valid" "Not valid,Valid"
|
|
bitfld.long 0x00 30. " XTD ,Extended identifier" "Standard,Extended"
|
|
bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit"
|
|
hexmask.long.word 0x00 18.--28. 1. " ID ,Message identifier"
|
|
endif
|
|
rgroup.long 0x14C++0x0B
|
|
line.long 0x00 "IF3MCTL,IF3 Message Control Register"
|
|
bitfld.long 0x00 15. " NEWDAT ,New data" "Not written,Written"
|
|
bitfld.long 0x00 14. " MSGLST ,Message lost" "Not lost,Lost"
|
|
bitfld.long 0x00 13. " INTPND ,Interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " UMASK ,Use acceptance mask" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x00 11. " TXIE ,Transmit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RXIE ,Receive interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RMTEN ,Remote enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TXRQST ,Transmit request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " EOB ,End of block" "0,1"
|
|
bitfld.long 0x00 0.--3. " DLC ,Data length code" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8"
|
|
line.long 0x04 "IF3DATA,IF3 Data A Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA_3 ,Data byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA_2 ,Data byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA_1 ,Data byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA_0 ,Data byte 0"
|
|
line.long 0x08 "IF3DATB,IF3 Data B Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA_7 ,Data byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA_6 ,Data byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA_5 ,Data byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA_4 ,Data byte 4"
|
|
group.long 0x160++0x0F
|
|
line.long 0x00 "IF3UPD12,Update Enable Register"
|
|
bitfld.long 0x00 31. " IF3UPDEN[32] ,IF3 update enable for message object 32" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [31] ,IF3 update enable for message object 31" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [30] ,IF3 update enable for message object 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [29] ,IF3 update enable for message object 29" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [28] ,IF3 update enable for message object 28" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [27] ,IF3 update enable for message object 27" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [26] ,IF3 update enable for message object 26" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [25] ,IF3 update enable for message object 25" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [24] ,IF3 update enable for message object 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [23] ,IF3 update enable for message object 23" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [22] ,IF3 update enable for message object 22" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [21] ,IF3 update enable for message object 21" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [20] ,IF3 update enable for message object 20" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [19] ,IF3 update enable for message object 19" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [18] ,IF3 update enable for message object 18" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [17] ,IF3 update enable for message object 17" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [16] ,IF3 update enable for message object 16" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [15] ,IF3 update enable for message object 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [14] ,IF3 update enable for message object 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [13] ,IF3 update enable for message object 13" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [12] ,IF3 update enable for message object 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [11] ,IF3 update enable for message object 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [10] ,IF3 update enable for message object 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [9] ,IF3 update enable for message object 9" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [8] ,IF3 update enable for message object 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [7] ,IF3 update enable for message object 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [6] ,IF3 update enable for message object 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [5] ,IF3 update enable for message object 5" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [4] ,IF3 update enable for message object 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [3] ,IF3 update enable for message object 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [2] ,IF3 update enable for message object 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [1] ,IF3 update enable for message object 1" "Disabled,Enabled"
|
|
line.long 0x04 "IF3UPD34,Update Enable Register"
|
|
bitfld.long 0x04 31. " IF3UPDEN[64] ,IF3 update enable for message object 64" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [63] ,IF3 update enable for message object 63" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [62] ,IF3 update enable for message object 62" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [61] ,IF3 update enable for message object 61" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 27. " [60] ,IF3 update enable for message object 60" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [59] ,IF3 update enable for message object 59" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [58] ,IF3 update enable for message object 58" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [57] ,IF3 update enable for message object 57" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 23. " [56] ,IF3 update enable for message object 56" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [55] ,IF3 update enable for message object 55" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [54] ,IF3 update enable for message object 54" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [53] ,IF3 update enable for message object 53" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " [52] ,IF3 update enable for message object 52" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [51] ,IF3 update enable for message object 51" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [50] ,IF3 update enable for message object 50" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [49] ,IF3 update enable for message object 49" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " [48] ,IF3 update enable for message object 48" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [47] ,IF3 update enable for message object 47" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [46] ,IF3 update enable for message object 46" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [45] ,IF3 update enable for message object 45" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [44] ,IF3 update enable for message object 44" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [43] ,IF3 update enable for message object 43" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [42] ,IF3 update enable for message object 42" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [41] ,IF3 update enable for message object 41" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " [40] ,IF3 update enable for message object 40" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [39] ,IF3 update enable for message object 39" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [38] ,IF3 update enable for message object 38" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [37] ,IF3 update enable for message object 37" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " [36] ,IF3 update enable for message object 68" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [35] ,IF3 update enable for message object 67" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [34] ,IF3 update enable for message object 66" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [33] ,IF3 update enable for message object 65" "Disabled,Enabled"
|
|
line.long 0x08 "IF3UPD56,Update Enable Register"
|
|
bitfld.long 0x08 31. " IF3UPDEN[96] ,IF3 update enable for message object 96" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " [95] ,IF3 update enable for message object 95" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " [94] ,IF3 update enable for message object 94" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " [93] ,IF3 update enable for message object 93" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 27. " [92] ,IF3 update enable for message object 92" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " [91] ,IF3 update enable for message object 91" "Disabled,Enabled"
|
|
bitfld.long 0x08 25. " [90] ,IF3 update enable for message object 90" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " [89] ,IF3 update enable for message object 89" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 23. " [88] ,IF3 update enable for message object 88" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " [87] ,IF3 update enable for message object 87" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " [86] ,IF3 update enable for message object 86" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " [85] ,IF3 update enable for message object 85" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 19. " [84] ,IF3 update enable for message object 84" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " [83] ,IF3 update enable for message object 83" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " [82] ,IF3 update enable for message object 82" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " [81] ,IF3 update enable for message object 81" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 15. " [80] ,IF3 update enable for message object 80" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " [79] ,IF3 update enable for message object 79" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " [78] ,IF3 update enable for message object 78" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " [77] ,IF3 update enable for message object 77" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 11. " [76] ,IF3 update enable for message object 76" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [75] ,IF3 update enable for message object 75" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [74] ,IF3 update enable for message object 74" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [73] ,IF3 update enable for message object 73" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " [72] ,IF3 update enable for message object 72" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [71] ,IF3 update enable for message object 71" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [70] ,IF3 update enable for message object 70" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [69] ,IF3 update enable for message object 69" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 3. " [68] ,IF3 update enable for message object 68" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [67] ,IF3 update enable for message object 67" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [66] ,IF3 update enable for message object 66" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [65] ,IF3 update enable for message object 65" "Disabled,Enabled"
|
|
line.long 0x0C "IF3UPD78,Update Enable Register"
|
|
bitfld.long 0x0C 31. " IF3UPDEN[128] ,IF3 update enable for message object 128" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [127] ,IF3 update enable for message object 127" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [126] ,IF3 update enable for message object 126" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [125] ,IF3 update enable for message object 125" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 27. " [124] ,IF3 update enable for message object 124" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " [123] ,IF3 update enable for message object 123" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [122] ,IF3 update enable for message object 122" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [121] ,IF3 update enable for message object 121" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 23. " [120] ,IF3 update enable for message object 120" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [119] ,IF3 update enable for message object 119" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " [118] ,IF3 update enable for message object 118" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [117] ,IF3 update enable for message object 117" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 19. " [116] ,IF3 update enable for message object 116" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [115] ,IF3 update enable for message object 115" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [114] ,IF3 update enable for message object 114" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " [113] ,IF3 update enable for message object 113" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 15. " [112] ,IF3 update enable for message object 112" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " [111] ,IF3 update enable for message object 111" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " [110] ,IF3 update enable for message object 110" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " [109] ,IF3 update enable for message object 109" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 11. " [108] ,IF3 update enable for message object 108" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " [107] ,IF3 update enable for message object 107" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " [106] ,IF3 update enable for message object 106" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " [105] ,IF3 update enable for message object 105" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 7. " [104] ,IF3 update enable for message object 104" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [103] ,IF3 update enable for message object 103" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [102] ,IF3 update enable for message object 102" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [101] ,IF3 update enable for message object 101" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 3. " [100] ,IF3 update enable for message object 100" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " [99] ,IF3 update enable for message object 99" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [98] ,IF3 update enable for message object 98" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [97] ,IF3 update enable for message object 97" "Disabled,Enabled"
|
|
if (((per.l(ad:0xFFF7DC00+0x1E0))&0x08)==0x00)
|
|
if (((per.l(ad:0xFFF7DC00+0x1E0))&0x04)==0x00)
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "TIOC,TX I/O Control Register"
|
|
bitfld.long 0x00 18. " PU ,CAN_TX pull up/pull down select" "Pull down,Pull up"
|
|
bitfld.long 0x00 17. " PD ,CAN_TX pull disable" "No,Yes"
|
|
bitfld.long 0x00 16. " OD ,CAN_TX open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " FUNC ,CAN_TX function" "GIO,Functional"
|
|
bitfld.long 0x00 2. " DIR ,CAN_TX data direction" "Input,Output"
|
|
newline
|
|
rbitfld.long 0x00 0. " IN ,CAN_TX data in" "Low,High"
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "TIOC,TX I/O Control Register"
|
|
bitfld.long 0x00 16. " OD ,CAN_TX open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " FUNC ,CAN_TX function" "GIO,Functional"
|
|
bitfld.long 0x00 2. " DIR ,CAN_TX data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " OUT ,CAN_TX data out write" "Low,High"
|
|
newline
|
|
rbitfld.long 0x00 0. " IN ,CAN_TX data in" "Low,High"
|
|
endif
|
|
else
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "TIOC,TX I/O Control Register"
|
|
newline
|
|
bitfld.long 0x00 3. " FUNC ,CAN_TX function" "GIO,Functional"
|
|
newline
|
|
rbitfld.long 0x00 0. " IN ,CAN_TX data in" "Low,High"
|
|
endif
|
|
if (((per.l(ad:0xFFF7DC00+0x1E4))&0x08)==0x00)
|
|
if (((per.l(ad:0xFFF7DC00+0x1E4))&0x04)==0x00)
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "RIOC,RX I/O Control Register"
|
|
bitfld.long 0x00 18. " PU ,CAN_RX pull up/pull down select" "Pull down,Pull up"
|
|
bitfld.long 0x00 17. " PD ,CAN_RX pull disable" "No,Yes"
|
|
bitfld.long 0x00 16. " OD ,CAN_RX open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " FUNC ,CAN_RX function" "GIO,Functional"
|
|
bitfld.long 0x00 2. " DIR ,CAN_RX data direction" "Input,Output"
|
|
newline
|
|
rbitfld.long 0x00 0. " IN ,CAN_RX data in" "Low,High"
|
|
else
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "RIOC,RX I/O Control Register"
|
|
bitfld.long 0x00 16. " OD ,CAN_RX open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " FUNC ,CAN_RX function" "GIO,Functional"
|
|
bitfld.long 0x00 2. " DIR ,CAN_RX data direction" "Input,Output"
|
|
bitfld.long 0x00 1. " OUT ,CAN_RX data out write" "Low,High"
|
|
newline
|
|
rbitfld.long 0x00 0. " IN ,CAN_RX data in" "Low,High"
|
|
endif
|
|
else
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "RIOC,RX I/O Control Register"
|
|
newline
|
|
bitfld.long 0x00 3. " FUNC ,CAN_RX function" "GIO,Functional"
|
|
newline
|
|
rbitfld.long 0x00 0. " IN ,CAN_RX data in" "Low,High"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif cpuis("AWR1642*")||cpuis("AWR1843*")
|
|
tree.open "MCAN (Modular Controller Area Network)"
|
|
tree "CAN-FD Module Configuration"
|
|
base ad:0xFFF7C800
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "PID,MCANSS_PID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID register scheme" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " BU ,Business Unit" ",,Processors,?..."
|
|
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID ,Module ID"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major revision" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " MINOR ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL,MCANSS_CTRL Register"
|
|
bitfld.long 0x00 6. " EXT_TS_CNTR_EN ,External timestamp counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AUTOWAKEUP ,Automatic wakeup enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " WAKEUPREQEN ,Wakeup request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EMUEN ,Emulation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " EMUFACK ,Emulation fast ACK" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CLKFACK ,Clock fast ACK" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RESET ,Initiates a soft reset" "No reset,Reset"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "STAT,MCANSS_STAT Register"
|
|
bitfld.long 0x00 2. " ENABLE_FDOE ,Enable FDOE configuration" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MMI_DONE ,Memory initialization status" "In progress,Done"
|
|
bitfld.long 0x00 0. " RESET_STS ,Reset status" "No reset,Reset"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ICS,Interrupt Clear Shadow Register"
|
|
eventfld.long 0x00 0. " ICS ,External timestamp counter overflow interrupt status" "No interrupt,Interrupt"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "IRS,Interrupt Raw Status Register"
|
|
bitfld.long 0x00 0. " IRS ,External timestamp counter overflow interrupt status" "No interrupt,Interrupt"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IECS,Interrupt Enable Clear Shadow Register"
|
|
eventfld.long 0x00 0. " IECS ,External timestamp counter overflow interrupt status" "No interrupt,Interrupt"
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "IE,Interrupt Enable Register"
|
|
bitfld.long 0x00 0. " IE ,External timestamp counter overflow interrupt" "Disabled,Enabled"
|
|
line.long 0x04 "IES,Interrupt Enable Status Register"
|
|
bitfld.long 0x04 0. " IES ,External timestamp counter overflow interrupt" "Low,High"
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "EOI,End Of Interrupt Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EOI ,Pulse output corresponding to interrupt from EOI register"
|
|
line.long 0x04 "EXT_TS_PS,External Timestamp Prescaler Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " PRESCALE ,Pulse output corresponding to interrupt from EOI register"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "EXT_TS_USIC,External Timestamp Unserviced Interrupts Counter Register"
|
|
bitfld.long 0x00 0.--4. " EXT_TS_INTR_CNTR ,Number of unserviced rollover interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ECC_EOI,ECC End Of Interrupt Register"
|
|
eventfld.long 0x00 8. " ECC_EOI ,ECC end of interrupt" "Low,High"
|
|
rgroup.long 0x200++0x0B
|
|
line.long 0x00 "CREL,MCAN_CREL Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " MON ,Time stamp month"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DAY ,Time stamp day"
|
|
line.long 0x04 "ENDN,MCAN_ENDN Register"
|
|
line.long 0x08 "CUST,MCAN_CUST Register"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "DBTP,Data Bit Timing And Prescaler Register"
|
|
bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " DBRP ,Data baud rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before smaple point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " DSJW ,Data resynchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0xFFF7C800+0x218))&0x80)==0x80)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "TEST,MCAN_TEST Register"
|
|
rbitfld.long 0x00 7. " RX ,Actual value of MCAN_RX pin" "Low,High"
|
|
bitfld.long 0x00 5.--6. " TX ,MCAN_TX pin output function" "0,1,2,3"
|
|
bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x210++0x03
|
|
line.long 0x00 "TEST,MCAN_TEST Register"
|
|
bitfld.long 0x00 7. " RX ,Actual value of MCAN_RX pin" "Low,High"
|
|
bitfld.long 0x00 5.--6. " TX ,MCAN_TX pin output function" "0,1,2,3"
|
|
bitfld.long 0x00 4. " LBCK ,Loop back mode" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x214++0x1B
|
|
line.long 0x00 "RWD,MCAN_RWD Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog counter value"
|
|
line.long 0x04 "CCCR,MCAN_CCCR Register"
|
|
bitfld.long 0x04 14. " TXP ,Transmit pause" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " PXHD ,Protocol exception handling disable" "No,Yes"
|
|
bitfld.long 0x04 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 8. " FDOE ,FD operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " TEST ,Test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DAR ,Disable automatic retransmission" "No,Yes"
|
|
bitfld.long 0x04 5. " MON ,Bus monitoring mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " CSR ,Clock stop request" "Not requested,Requested"
|
|
rbitfld.long 0x04 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x04 2. " ASM ,Restricted operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CCE ,Configuration change enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " INIT ,Start software initialization" "Not started,Started"
|
|
line.long 0x08 "NBTP,Nominal Bit Timing And Prescaler Register"
|
|
hexmask.long.byte 0x08 25.--31. 1. " NSJW ,Nominal resynchronization jump width"
|
|
hexmask.long.word 0x08 16.--24. 1. " NBRP ,Nominal baud rate prescaler"
|
|
hexmask.long.byte 0x08 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x08 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point"
|
|
line.long 0x0C "TSCC,MCAN_TSCC Register"
|
|
bitfld.long 0x0C 16.--19. " TCP ,Timestamp counter prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--1. " TSS ,Timestamp select" "0,1,2,3"
|
|
line.long 0x10 "TSCV,MCAN_TSCV Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TSC ,Timestamp counter"
|
|
line.long 0x14 "TOCC,MCAN_TOCC Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " TOP ,Timeout period"
|
|
bitfld.long 0x14 1.--2. " TOS ,Timeout select" "0,1,2,3"
|
|
bitfld.long 0x14 0. " ETOC ,Enable timeout counter" "Disabled,Enabled"
|
|
line.long 0x18 "TOCV,MCAN_TOCV Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " TOC ,Timeout counter"
|
|
rgroup.long 0x240++0x07
|
|
line.long 0x00 "ECR,MCAN_ECR Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CEL ,CAN error logging"
|
|
bitfld.long 0x00 15. " RP ,Receive error passive" "No,Yes"
|
|
hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive error counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit error counter"
|
|
line.long 0x04 "PSR,MCAN_PSR Register"
|
|
hexmask.long.byte 0x04 16.--22. 1. " TDCV ,Transmitter delay compensation value"
|
|
bitfld.long 0x04 14. " PXE ,Protocol exception event" "Not occurred,Occurred"
|
|
bitfld.long 0x04 13. " RFDF ,Received a CAN FD message" "Not received,Received"
|
|
bitfld.long 0x04 12. " RBRS ,BRS flag of last received CAN FD message" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 11. " RESI ,ESI flag of last received CAN FD Message" "Low,High"
|
|
bitfld.long 0x04 8.--10. " DLEC ,Data phase last error code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 7. " BO ,BUS_OFF status" "Low,High"
|
|
bitfld.long 0x04 6. " EW ,Warning status" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 5. " EP ,Error passive" "Low,High"
|
|
bitfld.long 0x04 3.--4. " ACT ,Activity" "0,1,2,3"
|
|
bitfld.long 0x04 0.--2. " LEC ,Last error code" "0,1,2,3,4,5,6,7"
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "TDCR,MCAN_TDCR Register"
|
|
hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length"
|
|
group.long 0x250++0x0F
|
|
line.long 0x00 "IR,Interrupt Register"
|
|
bitfld.long 0x00 29. " ARA ,Access to reserved address" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " PED ,Protocol error in data phase" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " PEA ,Protocol error in arbitration phase" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " WDI ,Watchdog interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 25. " BO ,BUS_OFF status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " EW ,Warning status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " EP ,Error passive" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " ELO ,Error logging overflow" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 21. " BEU ,Bit error uncorrected" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " BEC ,Bit error corrected" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " DRX ,Message stored to dedicated Rx buffer" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " TOO ,Timeout occurred" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 17. " MRAF ,Message RAM access failure" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " TSW ,Timestamp wraparound" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " TEFL ,Tx event FIFO element lost" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " TEFF ,Tx event FIFO full" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 13. " TEFW ,Tx event FIFO watermark reached" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " TEFN ,Tx event FIFO new entry" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " TFE ,Tx FIFO empty" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " TCF ,Transmission cancellation finished" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " TC ,Transmission complete" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " HPM ,High priority message" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " RF1L ,Rx FIFO 1 message lost" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RF1F ,Rx FIFO 1 full" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 5. " RF1W ,Rx FIFO 1 watermark reached" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " RF1N ,Rx FIFO 1 new message" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " RF0L ,Rx FIFO 0 message lost" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RF0F ,Rx FIFO 0 Full" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 1. " RF0W ,Rx FIFO 0 watermark reached" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RF0N ,Rx FIFO 0 new message" "No interrupt,Interrupt"
|
|
line.long 0x04 "IE,Interrupt Enable Register"
|
|
bitfld.long 0x04 29. " ARAE ,Access to reserved address enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " PEDE ,Protocol error in data phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " PEAE ,Protocol error in arbitration phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " WDIE ,Watchdog interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " BOE ,BUS_OFF status enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " EWE ,Warning status enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " EPE ,Error passive enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ELOE ,Error logging overflow enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 21. " BEUE ,Bit error uncorrected enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " BECE ,Bit error corrected enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " DRXE ,Message stored to dedicated Rx buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " TOOE ,Timeout occurred enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 17. " MRAFE ,Message RAM access failure enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " TSWE ,Timestamp wraparound enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " TEFLE ,Tx event FIFO element lost enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " TEFFE ,Tx event FIFO full enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " TEFWE ,Tx event FIFO watermark reached enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " TEFNE ,Tx event FIFO new entry enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " TFEE ,Tx FIFO empty enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " TCFE ,Transmission cancellation finished enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 9. " TCE ,Transmission complete enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " HPME ,High priority message enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " RF1LE ,Rx FIFO 1 message lost enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RF1FE ,Rx FIFO 1 full enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 5. " RF1WE ,Rx FIFO 1 watermark reached enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RF1NE ,Rx FIFO 1 new message enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " RF0LE ,Rx FIFO 0 message lost enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RF0FE ,Rx FIFO 0 full enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " RF0WE ,Rx FIFO 0 watermark reached enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RF0NE ,Rx FIFO 0 new message enable" "Disabled,Enabled"
|
|
line.long 0x08 "ILS,Interrupt Line Select Register"
|
|
bitfld.long 0x08 29. " ARAL ,Access to reserved address interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 28. " PEDL ,Protocol error in data phase interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 27. " PEAL ,Protocol error in arbitration phase interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 26. " WDIL ,Watchdog interrupt interrupt line" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 25. " BOL ,BUS_OFF status interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 24. " EWL ,Warning status interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 23. " EPL ,Error passive interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 22. " ELOL ,Error logging overflow interrupt line" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 21. " BEUL ,Bit error uncorrected interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 20. " BECL ,Bit error corrected interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 19. " DRXL ,Message stored to dedicated Rx buffer interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 18. " TOOL ,Timeout occurred interrupt Line" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 17. " MRAFL ,Message RAM access failure interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 16. " TSWL ,Timestamp wraparound interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 15. " TEFLL ,Tx event FIFO element lost interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 14. " TEFFL ,Tx event FIFO full interrupt line" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 13. " TEFWL ,Tx event FIFO watermark reached interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 12. " TEFNL ,Tx event FIFO new entry interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 11. " TFEL ,Tx FIFO empty interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 10. " TCFL ,Transmission cancellation finished interrupt line" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 9. " TCL ,Transmission complete interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 8. " HPML ,High priority message interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 7. " RF1LL ,Rx FIFO 1 message lost interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 6. " RF1FL ,Rx FIFO 1 full interrupt line" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 5. " RF1WL ,Rx FIFO 1 watermark reached interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 4. " RF1NL ,Rx FIFO 1 new message interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 3. " RF0LL ,Rx FIFO 0 message lost interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 2. " RF0FL ,Rx FIFO 0 full interrupt line" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " RF0WL ,Rx FIFO 0 watermark reached interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 0. " RF0NL ,Rx FIFO 0 new message interrupt line" "INT0,INT1"
|
|
line.long 0x0C "ILE,Interrupt Line Enable Register"
|
|
bitfld.long 0x0C 1. " EINT1 ,Enable interrupt line 1" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " EINT0 ,Enable interrupt line 0" "Disabled,Enabled"
|
|
group.long 0x280++0x0B
|
|
line.long 0x00 "GFC,Global Filter Configuration Register"
|
|
bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "0,1,2,3"
|
|
bitfld.long 0x00 1. " RRFS ,Reject remote frames standard" "Not rejected,Rejected"
|
|
bitfld.long 0x00 0. " RRFE ,Reject remote frames extended" "Not rejected,Rejected"
|
|
line.long 0x04 "SIDFC,Standard ID Filter Configuration Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " LSS_S ,List size standard"
|
|
hexmask.long.word 0x04 2.--15. 0x04 " FLSSA_S ,Filter list standard start address"
|
|
line.long 0x08 "XIDFC,MCAN_XIDFC Register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " LSS_X ,List size standard"
|
|
hexmask.long.word 0x08 2.--15. 0x04 " FLSSA_X ,Filter list standard start address"
|
|
group.long 0x290++0x13
|
|
line.long 0x00 "XIDAM,MCAN_XIDAM Register"
|
|
hexmask.long 0x00 0.--28. 1. " EIDM ,Extended ID mask"
|
|
line.long 0x04 "HPMS,High Priority Message Status Register"
|
|
bitfld.long 0x04 15. " FLST ,Filter list" "0,1"
|
|
hexmask.long.byte 0x04 8.--14. 1. " FIDX ,Filter index"
|
|
bitfld.long 0x04 6.--7. " MSI ,Message storage indicator" "0,1,2,3"
|
|
bitfld.long 0x04 0.--5. " BIDX ,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "NDAT1,MCAN_NDAT1 Register"
|
|
line.long 0x0C "NDAT2,MCAN_NDAT2 Register"
|
|
line.long 0x10 "RXF0C,MCAN_RXF0C Register"
|
|
bitfld.long 0x10 31. " F0OM ,Rx FIFO 0 operation mode" "Blocking,Overwrite"
|
|
hexmask.long.byte 0x10 24.--30. 1. " F0WM ,Rx FIFO 0 watermark"
|
|
hexmask.long.word 0x10 15.--22. 1. " F0S ,Rx FIFO 0 size"
|
|
hexmask.long.word 0x10 2.--14. 0x04 " F0SA ,Rx FIFO 0 start address"
|
|
rgroup.long 0x2A4++0x03
|
|
line.long 0x00 "RXF0S,Rx FIFO 0 Status Register"
|
|
bitfld.long 0x00 25. " RF0L ,Rx FIFO 0 message lost" "Not lost,Lost"
|
|
bitfld.long 0x00 24. " F0F ,Rx FIFO 0 Full" "Not full,Full"
|
|
hexmask.long.byte 0x00 16.--21. 1. " F0PI ,Rx FIFO 0 put index"
|
|
bitfld.long 0x00 8.--13. " F0GI ,Rx FIFO 0 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " F0FL ,Rx FIFO 0 fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x2A8++0x0B
|
|
line.long 0x00 "RXF0A,MCAN_RXF0A Register"
|
|
bitfld.long 0x00 0.--5. " F0AI ,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "RXBC,MCAN_RXBC Register"
|
|
hexmask.long.word 0x04 2.--15. 0x04 " RBSA ,Rx buffer start address"
|
|
line.long 0x08 "RXF1C,MCAN_RXF1C Register"
|
|
bitfld.long 0x08 31. " F1OM ,Rx FIFO 1 operation mode" "Blocking,Overwrite"
|
|
hexmask.long.byte 0x08 24.--30. 1. " F1WM ,Rx FIFO 1 watermark"
|
|
hexmask.long.word 0x08 15.--22. 1. " F1S ,Rx FIFO 1 size"
|
|
hexmask.long.word 0x08 2.--14. 0x04 " F1SA ,Rx FIFO 1 start address"
|
|
rgroup.long 0x2B4++0x03
|
|
line.long 0x00 "RXF1S,Rx FIFO 1 Status Register"
|
|
bitfld.long 0x00 25. " RF1L ,Rx FIFO 1 Message Lost" "Not lost,Lost"
|
|
bitfld.long 0x00 24. " F1F ,Rx FIFO 1 Full" "Not full,Full"
|
|
hexmask.long.byte 0x00 16.--21. 1. " F1PI ,Rx FIFO 1 put index"
|
|
bitfld.long 0x00 8.--13. " F1GI ,Rx FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " F1FL ,Rx FIFO 1 fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x2B8++0x07
|
|
line.long 0x00 "RXF1A,MCAN_RXF1A Register"
|
|
bitfld.long 0x00 0.--5. " F1AI ,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "RXESC,MCAN_RXESC Register"
|
|
bitfld.long 0x04 8.--10. " RBDS ,Rx Buffer data field size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 4.--6. " F1DS ,Rx FIFO 1 data field size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " F0DS ,Rx FIFO 0 data field Size" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2C0++0x07
|
|
line.long 0x00 "TXBC,MCAN_TXBC Register"
|
|
bitfld.long 0x00 30. " TFQM ,Tx FIFO/queue mode" "FIFO,Queue"
|
|
bitfld.long 0x00 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " TBSA ,Tx buffers start address"
|
|
line.long 0x04 "TXFQS,Tx FIFO/Queue Status Register"
|
|
bitfld.long 0x04 21. " TFQF ,Tx FIFO/queue full" "Not full,Full"
|
|
bitfld.long 0x04 16.--20. " TFQPI ,Tx FIFO/queue put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 8.--12. " TFGI ,Tx queue get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--5. " TFFL ,Tx FIFO free level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "TXESC,MCAN_TXESC Register"
|
|
bitfld.long 0x00 0.--2. " TBDS ,Tx buffer data field size" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2CC++0x03
|
|
line.long 0x00 "TXBRP,Tx Buffer Request Pending Register"
|
|
bitfld.long 0x00 31. " TRP[31] ,Tx buffer 31 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " [30] ,Tx buffer 30 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " [29] ,Tx buffer 29 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " [28] ,Tx buffer 28 transmission request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Tx buffer 27 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " [26] ,Tx buffer 26 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " [25] ,Tx buffer 25 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " [24] ,Tx buffer 24 transmission request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Tx buffer 23 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " [22] ,Tx buffer 22 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " [21] ,Tx buffer 21 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " [20] ,Tx buffer 20 transmission request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Tx buffer 19 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " [18] ,Tx buffer 18 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " [17] ,Tx buffer 17 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " [16] ,Tx buffer 16 transmission request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Tx buffer 15 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Tx buffer 14 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Tx buffer 13 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Tx buffer 12 transmission request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Tx buffer 11 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Tx buffer 10 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Tx buffer 9 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " [8] ,Tx buffer 8 transmission request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Tx buffer 7 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " [6] ,Tx buffer 6 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " [5] ,Tx buffer 5 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Tx buffer 4 transmission request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Tx buffer 3 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " [2] ,Tx buffer 2 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " [1] ,Tx buffer 1 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Tx buffer 0 transmission request pending" "Not pending,Pending"
|
|
if (((per.l(ad:0xFFF7C800+0x218))&0x02)==0x00)
|
|
group.long 0x2D0++0x07
|
|
line.long 0x00 "TXBAR,Tx Buffer Add Request Register"
|
|
bitfld.long 0x00 31. " AR[31] ,Add Tx buffer 31 request" "Not requested,Requested"
|
|
bitfld.long 0x00 30. " [30] ,Add Tx buffer 30 request" "Not requested,Requested"
|
|
bitfld.long 0x00 29. " [29] ,Add Tx buffer 29 request" "Not requested,Requested"
|
|
bitfld.long 0x00 28. " [28] ,Add Tx buffer 28 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Add Tx buffer 27 request" "Not requested,Requested"
|
|
bitfld.long 0x00 26. " [26] ,Add Tx buffer 26 request" "Not requested,Requested"
|
|
bitfld.long 0x00 25. " [25] ,Add Tx buffer 25 request" "Not requested,Requested"
|
|
bitfld.long 0x00 24. " [24] ,Add Tx buffer 24 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Add Tx buffer 23 request" "Not requested,Requested"
|
|
bitfld.long 0x00 22. " [22] ,Add Tx buffer 22 request" "Not requested,Requested"
|
|
bitfld.long 0x00 21. " [21] ,Add Tx buffer 21 request" "Not requested,Requested"
|
|
bitfld.long 0x00 20. " [20] ,Add Tx buffer 20 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Add Tx buffer 19 request" "Not requested,Requested"
|
|
bitfld.long 0x00 18. " [18] ,Add Tx buffer 18 request" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " [17] ,Add Tx buffer 17 request" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " [16] ,Add Tx buffer 16 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Add Tx buffer 15 request" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [14] ,Add Tx buffer 14 request" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " [13] ,Add Tx buffer 13 request" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [12] ,Add Tx buffer 12 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Add Tx buffer 11 request" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,Add Tx buffer 10 request" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " [9] ,Add Tx buffer 9 request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [8] ,Add Tx buffer 8 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Add Tx buffer 7 request" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Add Tx buffer 6 request" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,Add Tx buffer 5 request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Add Tx buffer 4 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Add Tx buffer 3 request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Add Tx buffer 2 request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Add Tx buffer 1 request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Add Tx buffer 0 request" "Not requested,Requested"
|
|
line.long 0x04 "TXBCR,Tx Buffer Cancellation Request Register"
|
|
bitfld.long 0x04 31. " CR[31] ,Cancel Tx buffer 31 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 30. " [30] ,Cancel Tx buffer 30 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 29. " [29] ,Cancel Tx buffer 29 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 28. " [28] ,Cancel Tx buffer 28 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 27. " [27] ,Cancel Tx buffer 27 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 26. " [26] ,Cancel Tx buffer 26 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 25. " [25] ,Cancel Tx buffer 25 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 24. " [24] ,Cancel Tx buffer 24 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 23. " [23] ,Cancel Tx buffer 23 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 22. " [22] ,Cancel Tx buffer 22 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 21. " [21] ,Cancel Tx buffer 21 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 20. " [20] ,Cancel Tx buffer 20 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Cancel Tx buffer 19 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 18. " [18] ,Cancel Tx buffer 18 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 17. " [17] ,Cancel Tx buffer 17 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 16. " [16] ,Cancel Tx buffer 16 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 15. " [15] ,Cancel Tx buffer 15 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 14. " [14] ,Cancel Tx buffer 14 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 13. " [13] ,Cancel Tx buffer 13 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 12. " [12] ,Cancel Tx buffer 12 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Cancel Tx buffer 11 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 10. " [10] ,Cancel Tx buffer 10 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 9. " [9] ,Cancel Tx buffer 9 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 8. " [8] ,Cancel Tx buffer 8 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Cancel Tx buffer 7 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 6. " [6] ,Cancel Tx buffer 6 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 5. " [5] ,Cancel Tx buffer 5 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 4. " [4] ,Cancel Tx buffer 4 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Cancel Tx buffer 3 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 2. " [2] ,Cancel Tx buffer 2 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 1. " [1] ,Cancel Tx buffer 1 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 0. " [0] ,Cancel Tx buffer 0 request" "Not cancelled,Cancelled"
|
|
else
|
|
rgroup.long 0x2D0++0x07
|
|
line.long 0x00 "TXBAR,Tx Buffer Add Request Register"
|
|
bitfld.long 0x00 31. " AR[31] ,Add Tx buffer 31 request" "Not requested,Requested"
|
|
bitfld.long 0x00 30. " [30] ,Add Tx buffer 30 request" "Not requested,Requested"
|
|
bitfld.long 0x00 29. " [29] ,Add Tx buffer 29 request" "Not requested,Requested"
|
|
bitfld.long 0x00 28. " [28] ,Add Tx buffer 28 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Add Tx buffer 27 request" "Not requested,Requested"
|
|
bitfld.long 0x00 26. " [26] ,Add Tx buffer 26 request" "Not requested,Requested"
|
|
bitfld.long 0x00 25. " [25] ,Add Tx buffer 25 request" "Not requested,Requested"
|
|
bitfld.long 0x00 24. " [24] ,Add Tx buffer 24 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Add Tx buffer 23 request" "Not requested,Requested"
|
|
bitfld.long 0x00 22. " [22] ,Add Tx buffer 22 request" "Not requested,Requested"
|
|
bitfld.long 0x00 21. " [21] ,Add Tx buffer 21 request" "Not requested,Requested"
|
|
bitfld.long 0x00 20. " [20] ,Add Tx buffer 20 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Add Tx buffer 19 request" "Not requested,Requested"
|
|
bitfld.long 0x00 18. " [18] ,Add Tx buffer 18 request" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " [17] ,Add Tx buffer 17 request" "Not requested,Requested"
|
|
bitfld.long 0x00 16. " [16] ,Add Tx buffer 16 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Add Tx buffer 15 request" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [14] ,Add Tx buffer 14 request" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " [13] ,Add Tx buffer 13 request" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [12] ,Add Tx buffer 12 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Add Tx buffer 11 request" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,Add Tx buffer 10 request" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " [9] ,Add Tx buffer 9 request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [8] ,Add Tx buffer 8 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Add Tx buffer 7 request" "Not requested,Requested"
|
|
bitfld.long 0x00 6. " [6] ,Add Tx buffer 6 request" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,Add Tx buffer 5 request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Add Tx buffer 4 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Add Tx buffer 3 request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Add Tx buffer 2 request" "Not requested,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Add Tx buffer 1 request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Add Tx buffer 0 request" "Not requested,Requested"
|
|
line.long 0x04 "TXBCR,Tx Buffer Cancellation Request Register"
|
|
bitfld.long 0x04 31. " CR[31] ,Cancel Tx buffer 31 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 30. " [30] ,Cancel Tx buffer 30 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 29. " [29] ,Cancel Tx buffer 29 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 28. " [28] ,Cancel Tx buffer 28 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 27. " [27] ,Cancel Tx buffer 27 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 26. " [26] ,Cancel Tx buffer 26 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 25. " [25] ,Cancel Tx buffer 25 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 24. " [24] ,Cancel Tx buffer 24 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 23. " [23] ,Cancel Tx buffer 23 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 22. " [22] ,Cancel Tx buffer 22 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 21. " [21] ,Cancel Tx buffer 21 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 20. " [20] ,Cancel Tx buffer 20 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Cancel Tx buffer 19 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 18. " [18] ,Cancel Tx buffer 18 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 17. " [17] ,Cancel Tx buffer 17 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 16. " [16] ,Cancel Tx buffer 16 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 15. " [15] ,Cancel Tx buffer 15 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 14. " [14] ,Cancel Tx buffer 14 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 13. " [13] ,Cancel Tx buffer 13 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 12. " [12] ,Cancel Tx buffer 12 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Cancel Tx buffer 11 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 10. " [10] ,Cancel Tx buffer 10 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 9. " [9] ,Cancel Tx buffer 9 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 8. " [8] ,Cancel Tx buffer 8 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Cancel Tx buffer 7 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 6. " [6] ,Cancel Tx buffer 6 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 5. " [5] ,Cancel Tx buffer 5 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 4. " [4] ,Cancel Tx buffer 4 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Cancel Tx buffer 3 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 2. " [2] ,Cancel Tx buffer 2 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 1. " [1] ,Cancel Tx buffer 1 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 0. " [0] ,Cancel Tx buffer 0 request" "Not cancelled,Cancelled"
|
|
endif
|
|
rgroup.long 0x2D8++0x07
|
|
line.long 0x00 "TXBTO,Tx Buffer Transmission Occurred Register"
|
|
bitfld.long 0x00 31. " TO[31] ,Tx buffer 31 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " [30] ,Tx buffer 30 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " [29] ,Tx buffer 29 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " [28] ,Tx buffer 28 transmission occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Tx buffer 27 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " [26] ,Tx buffer 26 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " [25] ,Tx buffer 25 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " [24] ,Tx buffer 24 transmission occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Tx buffer 23 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " [22] ,Tx buffer 22 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " [21] ,Tx buffer 21 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " [20] ,Tx buffer 20 transmission occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Tx buffer 19 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " [18] ,Tx buffer 18 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " [17] ,Tx buffer 17 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " [16] ,Tx buffer 16 transmission occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Tx buffer 15 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " [14] ,Tx buffer 14 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " [13] ,Tx buffer 13 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " [12] ,Tx buffer 12 transmission occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Tx buffer 11 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " [10] ,Tx buffer 10 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " [9] ,Tx buffer 9 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " [8] ,Tx buffer 8 transmission occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Tx buffer 7 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " [6] ,Tx buffer 6 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " [5] ,Tx buffer 5 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " [4] ,Tx buffer 4 transmission occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Tx buffer 3 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " [2] ,Tx buffer 2 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " [1] ,Tx buffer 1 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " [0] ,Tx buffer 0 transmission occurred" "Not occurred,Occurred"
|
|
line.long 0x04 "TXBCF,Tx Buffer Cancellation Finished Register"
|
|
bitfld.long 0x04 31. " CF[31] ,Tx buffer 31 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 30. " [30] ,Tx buffer 30 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 29. " [29] ,Tx buffer 29 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 28. " [28] ,Tx buffer 28 cancellation finished" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x04 27. " [27] ,Tx buffer 27 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 26. " [26] ,Tx buffer 26 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 25. " [25] ,Tx buffer 25 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 24. " [24] ,Tx buffer 24 cancellation finished" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x04 23. " [23] ,Tx buffer 23 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 22. " [22] ,Tx buffer 22 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 21. " [21] ,Tx buffer 21 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 20. " [20] ,Tx buffer 20 cancellation finished" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Tx buffer 19 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 18. " [18] ,Tx buffer 18 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 17. " [17] ,Tx buffer 17 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 16. " [16] ,Tx buffer 16 cancellation finished" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x04 15. " [15] ,Tx buffer 15 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 14. " [14] ,Tx buffer 14 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 13. " [13] ,Tx buffer 13 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 12. " [12] ,Tx buffer 12 cancellation finished" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Tx buffer 11 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 10. " [10] ,Tx buffer 10 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 9. " [9] ,Tx buffer 9 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 8. " [8] ,Tx buffer 8 cancellation finished" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Tx buffer 7 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 6. " [6] ,Tx buffer 6 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 5. " [5] ,Tx buffer 5 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 4. " [4] ,Tx buffer 4 cancellation finished" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Tx buffer 3 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 2. " [2] ,Tx buffer 2 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 1. " [1] ,Tx buffer 1 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 0. " [0] ,Tx buffer 0 cancellation finished" "Not finished,Finished"
|
|
group.long 0x2E0++0x07
|
|
line.long 0x00 "TXBTIE,MCAN_TXBTIE Register"
|
|
bitfld.long 0x00 31. " TIE[31] ,Tx buffer 31 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Tx buffer 30 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Tx buffer 29 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Tx buffer 28 transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Tx buffer 27 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Tx buffer 26 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Tx buffer 25 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Tx buffer 24 transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Tx buffer 23 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Tx buffer 22 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Tx buffer 21 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Tx buffer 20 transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Tx buffer 19 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Tx buffer 18 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Tx buffer 17 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Tx buffer 16 transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Tx buffer 15 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Tx buffer 14 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Tx buffer 13 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Tx buffer 12 transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Tx buffer 11 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Tx buffer 10 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Tx buffer 9 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Tx buffer 8 transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Tx buffer 7 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Tx buffer 6 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Tx buffer 5 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Tx buffer 4 transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Tx buffer 3 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Tx buffer 2 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Tx buffer 1 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Tx buffer 0 transmission interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "TXBCIE,MCAN_TXBCIE Register"
|
|
bitfld.long 0x04 31. " CFIE[31] ,Tx buffer 31 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [30] ,Tx buffer 30 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [29] ,Tx buffer 29 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [28] ,Tx buffer 28 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 27. " [27] ,Tx buffer 27 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [26] ,Tx buffer 26 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [25] ,Tx buffer 25 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [24] ,Tx buffer 24 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 23. " [23] ,Tx buffer 23 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [22] ,Tx buffer 22 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [21] ,Tx buffer 21 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [20] ,Tx buffer 20 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Tx buffer 19 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [18] ,Tx buffer 18 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [17] ,Tx buffer 17 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [16] ,Tx buffer 16 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " [15] ,Tx buffer 15 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [14] ,Tx buffer 14 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [13] ,Tx buffer 13 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [12] ,Tx buffer 12 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Tx buffer 11 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [10] ,Tx buffer 10 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [9] ,Tx buffer 9 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [8] ,Tx buffer 8 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Tx buffer 7 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [6] ,Tx buffer 6 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [5] ,Tx buffer 5 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [4] ,Tx buffer 4 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Tx buffer 3 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,Tx buffer 2 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [1] ,Tx buffer 1 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [0] ,Tx buffer 0 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "TXEFC,MCAN_TXEFC Register"
|
|
bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address"
|
|
rgroup.long 0x2F4++0x07
|
|
line.long 0x00 "TXEFS,Tx Event FIFO Status Register"
|
|
bitfld.long 0x00 25. " TEFL ,Tx Event FIFO element lost" "Not lost,Lost"
|
|
bitfld.long 0x00 24. " EFF ,Event FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 16.--20. " EFPI ,Event FIFO put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " EFGI ,Event FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " EFFL ,Event FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "TXEFA,MCAN_TXEFA Register"
|
|
bitfld.long 0x04 0.--4. " EFAI ,Event FIFO acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MCAN ECC Module"
|
|
base ad:0xFFF7A000
|
|
width 24.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "AGGR_REVISION,Aggregator Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " BU ,Bu" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID ,Module ID"
|
|
bitfld.long 0x00 11.--15. " REVRTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " REVMAJ ,Major version" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom version" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " REVMIN ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "VECTOR,ECC Vector Register"
|
|
rbitfld.long 0x00 24. " RD_SVBUS_DONE ,Status to indicate if read on serial VBUS is complete" "Not completed,Completed"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " RD_SVBUS_ADDR ,Read address"
|
|
bitfld.long 0x00 15. " RD_SVBUS ,Trigger a read on the serial VBUS" "Not triggered,Triggered"
|
|
hexmask.long.word 0x00 0.--10. 1. " ECC_VEC ,Value written to select the corresponding ECC RAM for control or status"
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "MISC_STATUS,Misc Status Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS ,Number of RAMS serviced by the ECC aggregator"
|
|
line.long 0x04 "WRAP_REVISION,ECC Wrapper Revision Register"
|
|
bitfld.long 0x04 30.--31. " W_SCHEME ,Scheme" "0,1,2,3"
|
|
bitfld.long 0x04 28.--29. " W_BU ,Bu" "0,1,2,3"
|
|
hexmask.long.word 0x04 16.--27. 1. " W_MODULE_ID ,Module ID"
|
|
bitfld.long 0x04 11.--15. " W_REVRTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x04 8.--10. " W_REVMAJ ,Major version" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 6.--7. " W_CUSTOM ,Custom version" "0,1,2,3"
|
|
group.long 0x14++0x0F
|
|
line.long 0x00 "CONTROL,ECC Control Register"
|
|
bitfld.long 0x00 6. " ERROR_ONCE ,Force error only once" "Not forced,Forced"
|
|
bitfld.long 0x00 5. " FORCE_N_ROW ,Force error on any RAM read" "Not forced,Forced"
|
|
bitfld.long 0x00 4. " FORCE_DED ,Force double bit error" "Not forced,Forced"
|
|
bitfld.long 0x00 3. " FORCE_SEC ,Force single bit error" "Not forced,Forced"
|
|
newline
|
|
bitfld.long 0x00 2. " EN_RMW ,Enable RMW" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ECC_CHK ,Enable ECC check" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ECC_EN ,Enable ECC" "Disabled,Enabled"
|
|
line.long 0x04 "ERR_CTRL1,ECC Error Control Register 1"
|
|
hexmask.long.word 0x04 16.--31. 1. " ECC_BIT1 ,Data bit that needs to be flipped when FORCE_SEC is set"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " ECC_ROW ,Row address where single or double-bit error needs to be applied"
|
|
line.long 0x08 "ERR_CTRL2,ECC Error Control Register 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " ECC_BIT2 ,Data bit that needs to be flipped if double bit error needs to be forced"
|
|
line.long 0x0C "ERR_STAT1,ECC Error Status Register 1"
|
|
hexmask.long.word 0x0C 16.--31. 0x01 " ECC_ROW ,Row address where the single or double-bit error has occurred"
|
|
bitfld.long 0x0C 9. " CLR_ECC_DED ,Clear double bit error status" "Not cleared,Cleared"
|
|
bitfld.long 0x0C 8. " CLR_ECC_SEC ,Clear single bit error status" "Not cleared,Cleared"
|
|
bitfld.long 0x0C 1. " ECC_DED ,Level double bit error status" "No error,Error"
|
|
newline
|
|
bitfld.long 0x0C 0. " ECC_SEC ,Level single bit error status" "No error,Error"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "ERR_STAT2,ECC Error Status Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " ECC_BIT2_STS ,Data bit that corresponds to the double-bit error"
|
|
hexmask.long.word 0x00 0.--15. 1. " ECC_BIT1_STS ,Data bit that corresponds to the single-bit error"
|
|
group.long 0x3C++0x07
|
|
line.long 0x00 "SEC_EOI_REG,Single Error Correction End Of Interrupt Register"
|
|
bitfld.long 0x00 0. " SEC_EOI_WR ,EOI register" "0,1"
|
|
line.long 0x04 "SEC_STATUS_REG0,Single Error Correction Interrupt Status Register"
|
|
bitfld.long 0x04 0. " SEC_PEND ,Interrupt pending status for MSGMEM_PEND" "Not pending,Pending"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SEC_ENABLE_SET/CLR,Single Error Correction Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x40 0. " SEC_EN ,MSGMEM_PEND interrupt enable" "Disabled,Enabled"
|
|
group.long 0x13C++0x07
|
|
line.long 0x00 "DED_EOI_REG,Dual Error Detection End Of Interrupt Register"
|
|
bitfld.long 0x00 0. " DED_EOI_WR ,EOI register" "0,1"
|
|
line.long 0x04 "DED_STATUS_REG0,Dual Error Detection Interrupt Status Register"
|
|
bitfld.long 0x04 0. " DED_PEND ,Interrupt pending status for MSGMEM_PEND" "Not pending,Pending"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "DED_ENABLE_SET/CLR,Dual Error Detection Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x40 0. " DED_EN ,MSGMEM_PEND interrupt enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
elif cpuis("AWR6843*")
|
|
tree.open "MCAN (Modular Controller Area Network)"
|
|
tree "CAN-FD Module Configuration"
|
|
base ad:0xFFF7C800
|
|
width 16.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SS_PID,Product ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID register scheme" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " BU ,Business Unit" ",,Processors,?..."
|
|
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID ,Module ID"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major revision" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " MINOR ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SS_CTRL,Control Register"
|
|
bitfld.long 0x00 6. " EXT_TS_CNTR_EN ,External timestamp counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AUTOWAKEUP ,Automatic wakeup enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " WAKEUPREGEN ,Wakeup request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DBGSUSP_FREE ,Debug suspend free" "Not freed,Freed"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SS_STAT,Status Register"
|
|
bitfld.long 0x00 2. " EN_FDOE ,Enable FDOE configuration" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MMI_DONE ,Memory initialization status" "In progress,Done"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SS_ICS,Interrupt Clear Shadow Register"
|
|
eventfld.long 0x00 0. " ICS ,External timestamp counter overflow interrupt status" "No interrupt,Interrupt"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SS_IRS,Interrupt Raw Status Register"
|
|
bitfld.long 0x00 0. " IRS ,External timestamp counter overflow interrupt status" "No interrupt,Interrupt"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SS_IECS,Interrupt Enable Clear Shadow Register"
|
|
eventfld.long 0x00 0. " IECS ,External timestamp counter overflow interrupt status" "No interrupt,Interrupt"
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "SS_IE,Interrupt Enable Register"
|
|
bitfld.long 0x00 0. " IE ,External timestamp counter overflow interrupt" "Disabled,Enabled"
|
|
line.long 0x04 "SS_IES,Interrupt Enable Status Register"
|
|
bitfld.long 0x04 0. " IES ,External timestamp counter overflow interrupt" "Low,High"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "SS_EOI,End Of Interrupt Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EOI ,Pulse output corresponding to interrupt from EOI register"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SS_EXT_TS_PS,External Timestamp Prescaler Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PRESCALE ,Pulse output corresponding to interrupt from EOI register"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SS_EXT_TS_USIC,External Timestamp Unserviced Interrupts Counter Register"
|
|
bitfld.long 0x00 0.--4. " EXT_TS_INTR_CNTR ,Number of unserviced rollover interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x200++0x0B
|
|
line.long 0x00 "CREL,Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MON ,Time stamp month"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " DAY ,Time stamp day"
|
|
line.long 0x04 "ENDN,Endianess Test Value Register"
|
|
line.long 0x08 "CUST,Custom Register"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "DBTP,Data Bit Timing And Prescaler Register"
|
|
bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " DBRP ,Data baud rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DSJW ,Data resynchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0xFFF7C800+0x218))&0x80)==0x80)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "TEST,Test Register"
|
|
rbitfld.long 0x00 7. " RX ,Receive pin" "Low,High"
|
|
bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "0,1,2,3"
|
|
bitfld.long 0x00 4. " LBCK ,Loop back mode enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x210++0x03
|
|
line.long 0x00 "TEST,Test Register"
|
|
bitfld.long 0x00 7. " RX ,Receive pin" "Low,High"
|
|
bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "0,1,2,3"
|
|
bitfld.long 0x00 4. " LBCK ,Loop back mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x214++0x1B
|
|
line.long 0x00 "RWD,Watchdog Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog counter value"
|
|
line.long 0x04 "CCCR,Command Completion Coalescing Register"
|
|
bitfld.long 0x04 14. " TXP ,Transmit pause" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " PXHD ,Protocol exception handling disable" "No,Yes"
|
|
bitfld.long 0x04 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " FDOE ,FD operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " TEST ,Test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DAR ,Disable automatic retransmission" "No,Yes"
|
|
bitfld.long 0x04 5. " MON ,Bus monitoring mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CSR ,Clock stop request" "Not requested,Requested"
|
|
rbitfld.long 0x04 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged"
|
|
newline
|
|
bitfld.long 0x04 2. " ASM ,Restricted operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CCE ,Configuration change enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " INIT ,Start software initialization" "Not started,Started"
|
|
line.long 0x08 "NBTP,Nominal Bit Timing And Prescaler Register"
|
|
hexmask.long.byte 0x08 25.--31. 1. " NSJW ,Nominal resynchronization jump width"
|
|
hexmask.long.word 0x08 16.--24. 1. " NBRP ,Nominal baud rate prescaler"
|
|
hexmask.long.byte 0x08 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x08 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point"
|
|
line.long 0x0C "TSCC,Timestamp Counter Control Register"
|
|
bitfld.long 0x0C 16.--19. " TCP ,Timestamp counter prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--1. " TSS ,Timestamp select" "0,1,2,3"
|
|
line.long 0x10 "TSCV,Timestamp Counter Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TSC ,Timestamp counter"
|
|
line.long 0x14 "TOCC,Timeout Counter Control Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " TOP ,Timeout period"
|
|
bitfld.long 0x14 1.--2. " TOS ,Timeout select" "0,1,2,3"
|
|
bitfld.long 0x14 0. " ETOC ,Enable timeout counter" "Disabled,Enabled"
|
|
line.long 0x18 "TOCV,Timeout Counter Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " TOC ,Timeout counter"
|
|
rgroup.long 0x240++0x07
|
|
line.long 0x00 "ECR,Error Counter Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CEL ,CAN error logging"
|
|
bitfld.long 0x00 15. " RP ,Receive error passive" "No,Yes"
|
|
hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive error counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit error counter"
|
|
line.long 0x04 "PSR,Packet Start Register"
|
|
hexmask.long.byte 0x04 16.--22. 1. " TDCV ,Transmitter delay compensation value"
|
|
bitfld.long 0x04 14. " PXE ,Protocol exception event" "Not occurred,Occurred"
|
|
bitfld.long 0x04 13. " RFDF ,Received a CAN FD message" "Not received,Received"
|
|
bitfld.long 0x04 12. " RBRS ,BRS flag of last received CAN FD message" "Low,High"
|
|
bitfld.long 0x04 11. " RESI ,ESI flag of last received CAN FD Message" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 8.--10. " DLEC ,Data phase last error code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 7. " BO ,BUS_OFF status" "Low,High"
|
|
bitfld.long 0x04 6. " EW ,Warning status" "Low,High"
|
|
bitfld.long 0x04 5. " EP ,Error passive" "Low,High"
|
|
bitfld.long 0x04 3.--4. " ACT ,Activity" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 0.--2. " LEC ,Last error code" "0,1,2,3,4,5,6,7"
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "TDCR,Transmitter Delay Compensation Register"
|
|
hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length"
|
|
group.long 0x250++0x0F
|
|
line.long 0x00 "IR,Interrupt Register"
|
|
bitfld.long 0x00 29. " ARA ,Access to reserved address" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " PED ,Protocol error in data phase" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " PEA ,Protocol error in arbitration phase" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " WDI ,Watchdog interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " BO ,BUS_OFF status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 24. " EW ,Warning status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " EP ,Error passive" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " ELO ,Error logging overflow" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " BEU ,Bit error uncorrected" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " BEC ,Bit error corrected" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 19. " DRX ,Message stored to dedicated Rx buffer" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " TOO ,Timeout occurred" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " MRAF ,Message RAM access failure" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " TSW ,Timestamp wraparound" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " TEFL ,Tx event FIFO element lost" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 14. " TEFF ,Tx event FIFO full" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " TEFW ,Tx event FIFO watermark reached" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " TEFN ,Tx event FIFO new entry" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " TFE ,Tx FIFO empty" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " TCF ,Transmission cancellation finished" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " TC ,Transmission complete" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " HPM ,High priority message" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " RF1L ,Rx FIFO 1 message lost" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RF1F ,Rx FIFO 1 full" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RF1W ,Rx FIFO 1 watermark reached" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 4. " RF1N ,Rx FIFO 1 new message" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " RF0L ,Rx FIFO 0 message lost" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RF0F ,Rx FIFO 0 Full" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RF0W ,Rx FIFO 0 watermark reached" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RF0N ,Rx FIFO 0 new message" "No interrupt,Interrupt"
|
|
line.long 0x04 "IE,Interrupt Enable Register"
|
|
bitfld.long 0x04 29. " ARAE ,Access to reserved address enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " PEDE ,Protocol error in data phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " PEAE ,Protocol error in arbitration phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " WDIE ,Watchdog interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " BOE ,BUS_OFF status enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 24. " EWE ,Warning status enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " EPE ,Error passive enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ELOE ,Error logging overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " BEUE ,Bit error uncorrected enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " BECE ,Bit error corrected enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " DRXE ,Message stored to dedicated Rx buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " TOOE ,Timeout occurred enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " MRAFE ,Message RAM access failure enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " TSWE ,Timestamp wraparound enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " TEFLE ,Tx event FIFO element lost enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 14. " TEFFE ,Tx event FIFO full enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " TEFWE ,Tx event FIFO watermark reached enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " TEFNE ,Tx event FIFO new entry enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " TFEE ,Tx FIFO empty enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " TCFE ,Transmission cancellation finished enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 9. " TCE ,Transmission complete enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " HPME ,High priority message enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " RF1LE ,Rx FIFO 1 message lost enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RF1FE ,Rx FIFO 1 full enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " RF1WE ,Rx FIFO 1 watermark reached enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " RF1NE ,Rx FIFO 1 new message enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " RF0LE ,Rx FIFO 0 message lost enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RF0FE ,Rx FIFO 0 full enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RF0WE ,Rx FIFO 0 watermark reached enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RF0NE ,Rx FIFO 0 new message enable" "Disabled,Enabled"
|
|
line.long 0x08 "ILS,Interrupt Line Select Register"
|
|
bitfld.long 0x08 29. " ARAL ,Access to reserved address interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 28. " PEDL ,Protocol error in data phase interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 27. " PEAL ,Protocol error in arbitration phase interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 26. " WDIL ,Watchdog interrupt interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 25. " BOL ,BUS_OFF status interrupt line" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 24. " EWL ,Warning status interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 23. " EPL ,Error passive interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 22. " ELOL ,Error logging overflow interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 21. " BEUL ,Bit error uncorrected interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 20. " BECL ,Bit error corrected interrupt line" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 19. " DRXL ,Message stored to dedicated Rx buffer interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 18. " TOOL ,Timeout occurred interrupt Line" "INT0,INT1"
|
|
bitfld.long 0x08 17. " MRAFL ,Message RAM access failure interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 16. " TSWL ,Timestamp wraparound interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 15. " TEFLL ,Tx event FIFO element lost interrupt line" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 14. " TEFFL ,Tx event FIFO full interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 13. " TEFWL ,Tx event FIFO watermark reached interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 12. " TEFNL ,Tx event FIFO new entry interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 11. " TFEL ,Tx FIFO empty interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 10. " TCFL ,Transmission cancellation finished interrupt line" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 9. " TCL ,Transmission complete interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 8. " HPML ,High priority message interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 7. " RF1LL ,Rx FIFO 1 message lost interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 6. " RF1FL ,Rx FIFO 1 full interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 5. " RF1WL ,Rx FIFO 1 watermark reached interrupt line" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 4. " RF1NL ,Rx FIFO 1 new message interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 3. " RF0LL ,Rx FIFO 0 message lost interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 2. " RF0FL ,Rx FIFO 0 full interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 1. " RF0WL ,Rx FIFO 0 watermark reached interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 0. " RF0NL ,Rx FIFO 0 new message interrupt line" "INT0,INT1"
|
|
line.long 0x0C "ILE,Interrupt Line Enable Register"
|
|
bitfld.long 0x0C 1. " EINT[1] ,Enable interrupt line 1" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [0] ,Enable interrupt line 0" "Disabled,Enabled"
|
|
group.long 0x280++0x0B
|
|
line.long 0x00 "GFC,Global Filter Configuration Register"
|
|
bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "0,1,2,3"
|
|
bitfld.long 0x00 1. " RRFS ,Reject remote frames standard" "Not rejected,Rejected"
|
|
bitfld.long 0x00 0. " RRFE ,Reject remote frames extended" "Not rejected,Rejected"
|
|
line.long 0x04 "SIDFC,Standard ID Filter Configuration Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " LSS_S ,List size standard"
|
|
hexmask.long.word 0x04 2.--15. 0x04 " FLSSA_S ,Filter list standard start address"
|
|
line.long 0x08 "XIDFC,Extended ID Filter Configuration Register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " LSS_X ,List size standard"
|
|
hexmask.long.word 0x08 2.--15. 0x04 " FLSSA_X ,Filter list standard start address"
|
|
group.long 0x290++0x13
|
|
line.long 0x00 "XIDAM,Extended Mask ID Register"
|
|
bitfld.long 0x00 28. " EIDM ,Extended ID mask 28" "0,1"
|
|
bitfld.long 0x00 27. ",Extended ID mask 27" "0,1"
|
|
bitfld.long 0x00 26. ",Extended ID mask 26" "0,1"
|
|
bitfld.long 0x00 25. ",Extended ID mask 25" "0,1"
|
|
bitfld.long 0x00 24. ",Extended ID mask 24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. ",Extended ID mask 23" "0,1"
|
|
bitfld.long 0x00 22. ",Extended ID mask 22" "0,1"
|
|
bitfld.long 0x00 21. ",Extended ID mask 21" "0,1"
|
|
bitfld.long 0x00 20. ",Extended ID mask 20" "0,1"
|
|
bitfld.long 0x00 19. ",Extended ID mask 19" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. ",Extended ID mask 18" "0,1"
|
|
bitfld.long 0x00 17. ",Extended ID mask 17" "0,1"
|
|
bitfld.long 0x00 16. ",Extended ID mask 16" "0,1"
|
|
bitfld.long 0x00 15. ",Extended ID mask 15" "0,1"
|
|
bitfld.long 0x00 14. ",Extended ID mask 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. ",Extended ID mask 13" "0,1"
|
|
bitfld.long 0x00 12. ",Extended ID mask 12" "0,1"
|
|
bitfld.long 0x00 11. ",Extended ID mask 11" "0,1"
|
|
bitfld.long 0x00 10. ",Extended ID mask 10" "0,1"
|
|
bitfld.long 0x00 9. ",Extended ID mask 9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. ",Extended ID mask 8" "0,1"
|
|
bitfld.long 0x00 7. ",Extended ID mask 7" "0,1"
|
|
bitfld.long 0x00 6. ",Extended ID mask 6" "0,1"
|
|
bitfld.long 0x00 5. ",Extended ID mask 5" "0,1"
|
|
bitfld.long 0x00 4. ",Extended ID mask 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. ",Extended ID mask 3" "0,1"
|
|
bitfld.long 0x00 2. ",Extended ID mask 2" "0,1"
|
|
bitfld.long 0x00 1. ",Extended ID mask 1" "0,1"
|
|
bitfld.long 0x00 0. ",Extended ID mask 0" "0,1"
|
|
line.long 0x04 "HPMS,High Priority Message Status Register"
|
|
bitfld.long 0x04 15. " FLST ,Filter list" "0,1"
|
|
hexmask.long.byte 0x04 8.--14. 1. " FIDX ,Filter index"
|
|
bitfld.long 0x04 6.--7. " MSI ,Message storage indicator" "0,1,2,3"
|
|
bitfld.long 0x04 0.--5. " BIDX ,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "NDAT1,New Data 1 Register"
|
|
line.long 0x0C "NDAT2,New Data 2 Register"
|
|
line.long 0x10 "RXF0C,Rx FIFO 0 Control Register"
|
|
bitfld.long 0x10 31. " F0OM ,Rx FIFO 0 operation mode" "Blocking,Overwrite"
|
|
hexmask.long.byte 0x10 24.--30. 1. " F0WM ,Rx FIFO 0 watermark"
|
|
hexmask.long.word 0x10 15.--22. 1. " F0S ,Rx FIFO 0 size"
|
|
hexmask.long.word 0x10 2.--14. 0x04 " F0SA ,Rx FIFO 0 start address"
|
|
rgroup.long 0x2A4++0x03
|
|
line.long 0x00 "RXF0S,Rx FIFO 0 Status Register"
|
|
bitfld.long 0x00 25. " RF0L ,Rx FIFO 0 message lost" "Not lost,Lost"
|
|
bitfld.long 0x00 24. " F0F ,Rx FIFO 0 full" "Not full,Full"
|
|
hexmask.long.byte 0x00 16.--21. 1. " F0PI ,Rx FIFO 0 put index"
|
|
bitfld.long 0x00 8.--13. " F0GI ,Rx FIFO 0 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " F0FL ,Rx FIFO 0 fill level"
|
|
group.long 0x2A8++0x0B
|
|
line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge Register"
|
|
bitfld.long 0x00 0.--5. " F0AI ,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "RXBC,Rx FIFO 0 Buffer Control Register"
|
|
hexmask.long.word 0x04 2.--15. 0x04 " RBSA ,Rx buffer start address"
|
|
line.long 0x08 "RXF1C,Rx FIFO 1 Control Register"
|
|
bitfld.long 0x08 31. " F1OM ,Rx FIFO 1 operation mode" "Blocking,Overwrite"
|
|
hexmask.long.byte 0x08 24.--30. 1. " F1WM ,Rx FIFO 1 watermark"
|
|
hexmask.long.word 0x08 15.--22. 1. " F1S ,Rx FIFO 1 size"
|
|
hexmask.long.word 0x08 2.--14. 0x04 " F1SA ,Rx FIFO 1 start address"
|
|
rgroup.long 0x2B4++0x03
|
|
line.long 0x00 "RXF1S,Rx FIFO 1 Status Register"
|
|
bitfld.long 0x00 25. " RF1L ,Rx FIFO 1 message lost" "Not lost,Lost"
|
|
bitfld.long 0x00 24. " F1F ,Rx FIFO 1 full" "Not full,Full"
|
|
hexmask.long.byte 0x00 16.--21. 1. " F1PI ,Rx FIFO 1 put index"
|
|
bitfld.long 0x00 8.--13. " F1GI ,Rx FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " F1FL ,Rx FIFO 1 fill level"
|
|
group.long 0x2B8++0x07
|
|
line.long 0x00 "RXF1A,Rx FIFO 0 Acknowledge Register"
|
|
bitfld.long 0x00 0.--5. " F1AI ,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "RXESC,Rx Size Control Register"
|
|
bitfld.long 0x04 8.--10. " RBDS ,Rx Buffer data field size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 4.--6. " F1DS ,Rx FIFO 1 data field size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " F0DS ,Rx FIFO 0 data field Size" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2C0++0x07
|
|
line.long 0x00 "TXBC,Tx Buffer Control Register"
|
|
bitfld.long 0x00 30. " TFQM ,Tx FIFO/queue mode" "FIFO,Queue"
|
|
bitfld.long 0x00 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " TBSA ,Tx buffers start address"
|
|
line.long 0x04 "TXFQS,Tx FIFO/Queue Status Register"
|
|
bitfld.long 0x04 21. " TFQF ,Tx FIFO/queue full" "Not full,Full"
|
|
bitfld.long 0x04 16.--20. " TFQPI ,Tx FIFO/queue put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 8.--12. " TFGI ,Tx queue get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--5. " TFFL ,Tx FIFO free level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "TXESC,Tx Buffer Size Control Register"
|
|
bitfld.long 0x00 0.--2. " TBDS ,Tx buffer data field size" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2CC++0x03
|
|
line.long 0x00 "TXBRP,Tx Buffer Request Pending Register"
|
|
bitfld.long 0x00 31. " TRP[31] ,Tx buffer 31 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " [30] ,Tx buffer 30 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " [29] ,Tx buffer 29 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " [28] ,Tx buffer 28 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " [27] ,Tx buffer 27 transmission request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Tx buffer 26 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " [25] ,Tx buffer 25 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " [24] ,Tx buffer 24 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " [23] ,Tx buffer 23 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " [22] ,Tx buffer 22 transmission request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Tx buffer 21 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " [20] ,Tx buffer 20 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " [19] ,Tx buffer 19 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " [18] ,Tx buffer 18 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " [17] ,Tx buffer 17 transmission request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Tx buffer 16 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " [15] ,Tx buffer 15 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Tx buffer 14 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Tx buffer 13 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Tx buffer 12 transmission request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Tx buffer 11 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Tx buffer 10 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Tx buffer 9 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " [8] ,Tx buffer 8 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " [7] ,Tx buffer 7 transmission request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Tx buffer 6 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " [5] ,Tx buffer 5 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Tx buffer 4 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " [3] ,Tx buffer 3 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " [2] ,Tx buffer 2 transmission request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Tx buffer 1 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Tx buffer 0 transmission request pending" "Not pending,Pending"
|
|
if (((per.l(ad:0xFFF7C800+0x218))&0x02)==0x00)
|
|
group.long 0x2D0++0x07
|
|
line.long 0x00 "TXBAR,Tx Buffer Add Request Register"
|
|
bitfld.long 0x00 31. " AR[31] ,Add Tx buffer 31 request" "Not requested,Requested"
|
|
bitfld.long 0x00 30. " [30] ,Add Tx buffer 30 request" "Not requested,Requested"
|
|
bitfld.long 0x00 29. " [29] ,Add Tx buffer 29 request" "Not requested,Requested"
|
|
bitfld.long 0x00 28. " [28] ,Add Tx buffer 28 request" "Not requested,Requested"
|
|
bitfld.long 0x00 27. " [27] ,Add Tx buffer 27 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Add Tx buffer 26 request" "Not requested,Requested"
|
|
bitfld.long 0x00 25. " [25] ,Add Tx buffer 25 request" "Not requested,Requested"
|
|
bitfld.long 0x00 24. " [24] ,Add Tx buffer 24 request" "Not requested,Requested"
|
|
bitfld.long 0x00 23. " [23] ,Add Tx buffer 23 request" "Not requested,Requested"
|
|
bitfld.long 0x00 22. " [22] ,Add Tx buffer 22 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Add Tx buffer 21 request" "Not requested,Requested"
|
|
bitfld.long 0x00 20. " [20] ,Add Tx buffer 20 request" "Not requested,Requested"
|
|
bitfld.long 0x00 19. " [19] ,Add Tx buffer 19 request" "Not requested,Requested"
|
|
bitfld.long 0x00 18. " [18] ,Add Tx buffer 18 request" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " [17] ,Add Tx buffer 17 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Add Tx buffer 16 request" "Not requested,Requested"
|
|
bitfld.long 0x00 15. " [15] ,Add Tx buffer 15 request" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [14] ,Add Tx buffer 14 request" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " [13] ,Add Tx buffer 13 request" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [12] ,Add Tx buffer 12 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Add Tx buffer 11 request" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,Add Tx buffer 10 request" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " [9] ,Add Tx buffer 9 request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [8] ,Add Tx buffer 8 request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " [7] ,Add Tx buffer 7 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Add Tx buffer 6 request" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,Add Tx buffer 5 request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Add Tx buffer 4 request" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Add Tx buffer 3 request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Add Tx buffer 2 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Add Tx buffer 1 request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Add Tx buffer 0 request" "Not requested,Requested"
|
|
line.long 0x04 "TXBCR,Tx Buffer Cancellation Request Register"
|
|
bitfld.long 0x04 31. " CR[31] ,Cancel Tx buffer 31 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 30. " [30] ,Cancel Tx buffer 30 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 29. " [29] ,Cancel Tx buffer 29 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 28. " [28] ,Cancel Tx buffer 28 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 27. " [27] ,Cancel Tx buffer 27 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 26. " [26] ,Cancel Tx buffer 26 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 25. " [25] ,Cancel Tx buffer 25 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 24. " [24] ,Cancel Tx buffer 24 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 23. " [23] ,Cancel Tx buffer 23 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 22. " [22] ,Cancel Tx buffer 22 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 21. " [21] ,Cancel Tx buffer 21 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 20. " [20] ,Cancel Tx buffer 20 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 19. " [19] ,Cancel Tx buffer 19 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 18. " [18] ,Cancel Tx buffer 18 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 17. " [17] ,Cancel Tx buffer 17 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,Cancel Tx buffer 16 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 15. " [15] ,Cancel Tx buffer 15 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 14. " [14] ,Cancel Tx buffer 14 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 13. " [13] ,Cancel Tx buffer 13 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 12. " [12] ,Cancel Tx buffer 12 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Cancel Tx buffer 11 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 10. " [10] ,Cancel Tx buffer 10 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 9. " [9] ,Cancel Tx buffer 9 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 8. " [8] ,Cancel Tx buffer 8 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 7. " [7] ,Cancel Tx buffer 7 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Cancel Tx buffer 6 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 5. " [5] ,Cancel Tx buffer 5 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 4. " [4] ,Cancel Tx buffer 4 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 3. " [3] ,Cancel Tx buffer 3 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 2. " [2] ,Cancel Tx buffer 2 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Cancel Tx buffer 1 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 0. " [0] ,Cancel Tx buffer 0 request" "Not cancelled,Cancelled"
|
|
else
|
|
rgroup.long 0x2D0++0x07
|
|
line.long 0x00 "TXBAR,Tx Buffer Add Request Register"
|
|
bitfld.long 0x00 31. " AR[31] ,Add Tx buffer 31 request" "Not requested,Requested"
|
|
bitfld.long 0x00 30. " [30] ,Add Tx buffer 30 request" "Not requested,Requested"
|
|
bitfld.long 0x00 29. " [29] ,Add Tx buffer 29 request" "Not requested,Requested"
|
|
bitfld.long 0x00 28. " [28] ,Add Tx buffer 28 request" "Not requested,Requested"
|
|
bitfld.long 0x00 27. " [27] ,Add Tx buffer 27 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Add Tx buffer 26 request" "Not requested,Requested"
|
|
bitfld.long 0x00 25. " [25] ,Add Tx buffer 25 request" "Not requested,Requested"
|
|
bitfld.long 0x00 24. " [24] ,Add Tx buffer 24 request" "Not requested,Requested"
|
|
bitfld.long 0x00 23. " [23] ,Add Tx buffer 23 request" "Not requested,Requested"
|
|
bitfld.long 0x00 22. " [22] ,Add Tx buffer 22 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Add Tx buffer 21 request" "Not requested,Requested"
|
|
bitfld.long 0x00 20. " [20] ,Add Tx buffer 20 request" "Not requested,Requested"
|
|
bitfld.long 0x00 19. " [19] ,Add Tx buffer 19 request" "Not requested,Requested"
|
|
bitfld.long 0x00 18. " [18] ,Add Tx buffer 18 request" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " [17] ,Add Tx buffer 17 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Add Tx buffer 16 request" "Not requested,Requested"
|
|
bitfld.long 0x00 15. " [15] ,Add Tx buffer 15 request" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [14] ,Add Tx buffer 14 request" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " [13] ,Add Tx buffer 13 request" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [12] ,Add Tx buffer 12 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Add Tx buffer 11 request" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,Add Tx buffer 10 request" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " [9] ,Add Tx buffer 9 request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [8] ,Add Tx buffer 8 request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " [7] ,Add Tx buffer 7 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Add Tx buffer 6 request" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,Add Tx buffer 5 request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Add Tx buffer 4 request" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Add Tx buffer 3 request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Add Tx buffer 2 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Add Tx buffer 1 request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Add Tx buffer 0 request" "Not requested,Requested"
|
|
line.long 0x04 "TXBCR,Tx Buffer Cancellation Request Register"
|
|
bitfld.long 0x04 31. " CR[31] ,Cancel Tx buffer 31 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 30. " [30] ,Cancel Tx buffer 30 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 29. " [29] ,Cancel Tx buffer 29 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 28. " [28] ,Cancel Tx buffer 28 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 27. " [27] ,Cancel Tx buffer 27 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 26. " [26] ,Cancel Tx buffer 26 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 25. " [25] ,Cancel Tx buffer 25 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 24. " [24] ,Cancel Tx buffer 24 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 23. " [23] ,Cancel Tx buffer 23 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 22. " [22] ,Cancel Tx buffer 22 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 21. " [21] ,Cancel Tx buffer 21 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 20. " [20] ,Cancel Tx buffer 20 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 19. " [19] ,Cancel Tx buffer 19 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 18. " [18] ,Cancel Tx buffer 18 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 17. " [17] ,Cancel Tx buffer 17 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,Cancel Tx buffer 16 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 15. " [15] ,Cancel Tx buffer 15 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 14. " [14] ,Cancel Tx buffer 14 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 13. " [13] ,Cancel Tx buffer 13 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 12. " [12] ,Cancel Tx buffer 12 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Cancel Tx buffer 11 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 10. " [10] ,Cancel Tx buffer 10 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 9. " [9] ,Cancel Tx buffer 9 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 8. " [8] ,Cancel Tx buffer 8 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 7. " [7] ,Cancel Tx buffer 7 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Cancel Tx buffer 6 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 5. " [5] ,Cancel Tx buffer 5 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 4. " [4] ,Cancel Tx buffer 4 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 3. " [3] ,Cancel Tx buffer 3 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 2. " [2] ,Cancel Tx buffer 2 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Cancel Tx buffer 1 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 0. " [0] ,Cancel Tx buffer 0 request" "Not cancelled,Cancelled"
|
|
endif
|
|
rgroup.long 0x2D8++0x07
|
|
line.long 0x00 "TXBTO,Tx Buffer Transmission Occurred Register"
|
|
bitfld.long 0x00 31. " TO[31] ,Tx buffer 31 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " [30] ,Tx buffer 30 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " [29] ,Tx buffer 29 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " [28] ,Tx buffer 28 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " [27] ,Tx buffer 27 transmission occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Tx buffer 26 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " [25] ,Tx buffer 25 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " [24] ,Tx buffer 24 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 23. " [23] ,Tx buffer 23 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " [22] ,Tx buffer 22 transmission occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Tx buffer 21 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " [20] ,Tx buffer 20 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 19. " [19] ,Tx buffer 19 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " [18] ,Tx buffer 18 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " [17] ,Tx buffer 17 transmission occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Tx buffer 16 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " [15] ,Tx buffer 15 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " [14] ,Tx buffer 14 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " [13] ,Tx buffer 13 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " [12] ,Tx buffer 12 transmission occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Tx buffer 11 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " [10] ,Tx buffer 10 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " [9] ,Tx buffer 9 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " [8] ,Tx buffer 8 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " [7] ,Tx buffer 7 transmission occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Tx buffer 6 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " [5] ,Tx buffer 5 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " [4] ,Tx buffer 4 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " [3] ,Tx buffer 3 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " [2] ,Tx buffer 2 transmission occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Tx buffer 1 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " [0] ,Tx buffer 0 transmission occurred" "Not occurred,Occurred"
|
|
line.long 0x04 "TXBCF,Tx Buffer Cancellation Finished Register"
|
|
bitfld.long 0x04 31. " CF[31] ,Tx buffer 31 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 30. " [30] ,Tx buffer 30 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 29. " [29] ,Tx buffer 29 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 28. " [28] ,Tx buffer 28 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 27. " [27] ,Tx buffer 27 cancellation finished" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x04 26. " [26] ,Tx buffer 26 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 25. " [25] ,Tx buffer 25 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 24. " [24] ,Tx buffer 24 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 23. " [23] ,Tx buffer 23 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 22. " [22] ,Tx buffer 22 cancellation finished" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x04 21. " [21] ,Tx buffer 21 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 20. " [20] ,Tx buffer 20 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 19. " [19] ,Tx buffer 19 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 18. " [18] ,Tx buffer 18 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 17. " [17] ,Tx buffer 17 cancellation finished" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,Tx buffer 16 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 15. " [15] ,Tx buffer 15 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 14. " [14] ,Tx buffer 14 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 13. " [13] ,Tx buffer 13 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 12. " [12] ,Tx buffer 12 cancellation finished" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Tx buffer 11 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 10. " [10] ,Tx buffer 10 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 9. " [9] ,Tx buffer 9 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 8. " [8] ,Tx buffer 8 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 7. " [7] ,Tx buffer 7 cancellation finished" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Tx buffer 6 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 5. " [5] ,Tx buffer 5 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 4. " [4] ,Tx buffer 4 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 3. " [3] ,Tx buffer 3 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 2. " [2] ,Tx buffer 2 cancellation finished" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Tx buffer 1 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 0. " [0] ,Tx buffer 0 cancellation finished" "Not finished,Finished"
|
|
group.long 0x2E0++0x07
|
|
line.long 0x00 "TXBTIE,Tx Transmission Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " TIE[31] ,Tx buffer 31 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Tx buffer 30 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Tx buffer 29 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Tx buffer 28 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Tx buffer 27 transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Tx buffer 26 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Tx buffer 25 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Tx buffer 24 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Tx buffer 23 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Tx buffer 22 transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Tx buffer 21 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Tx buffer 20 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Tx buffer 19 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Tx buffer 18 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Tx buffer 17 transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Tx buffer 16 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Tx buffer 15 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Tx buffer 14 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Tx buffer 13 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Tx buffer 12 transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Tx buffer 11 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Tx buffer 10 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Tx buffer 9 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Tx buffer 8 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Tx buffer 7 transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Tx buffer 6 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Tx buffer 5 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Tx buffer 4 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Tx buffer 3 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Tx buffer 2 transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Tx buffer 1 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Tx buffer 0 transmission interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "TXBCIE,Tx Cancellation Finished Interrupt Enable Register"
|
|
bitfld.long 0x04 31. " CFIE[31] ,Tx buffer 31 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [30] ,Tx buffer 30 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [29] ,Tx buffer 29 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [28] ,Tx buffer 28 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " [27] ,Tx buffer 27 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 26. " [26] ,Tx buffer 26 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [25] ,Tx buffer 25 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [24] ,Tx buffer 24 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " [23] ,Tx buffer 23 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [22] ,Tx buffer 22 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 21. " [21] ,Tx buffer 21 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [20] ,Tx buffer 20 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " [19] ,Tx buffer 19 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [18] ,Tx buffer 18 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [17] ,Tx buffer 17 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,Tx buffer 16 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " [15] ,Tx buffer 15 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [14] ,Tx buffer 14 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [13] ,Tx buffer 13 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [12] ,Tx buffer 12 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Tx buffer 11 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [10] ,Tx buffer 10 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [9] ,Tx buffer 9 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [8] ,Tx buffer 8 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " [7] ,Tx buffer 7 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Tx buffer 6 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [5] ,Tx buffer 5 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [4] ,Tx buffer 4 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " [3] ,Tx buffer 3 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,Tx buffer 2 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Tx buffer 1 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [0] ,Tx buffer 0 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "TXEFC,Tx Event FIFO Control Register"
|
|
bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address"
|
|
rgroup.long 0x2F4++0x07
|
|
line.long 0x00 "TXEFS,Tx Event FIFO Status Register"
|
|
bitfld.long 0x00 25. " TEFL ,Tx Event FIFO element lost" "Not lost,Lost"
|
|
bitfld.long 0x00 24. " EFF ,Event FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 16.--20. " EFPI ,Event FIFO put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " EFGI ,Event FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--5. " EFFL ,Event FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "TXEFA,Tx Event FIFO Acknowledge Index Register"
|
|
bitfld.long 0x04 0.--4. " EFAI ,Event FIFO acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MCAN ECC Module"
|
|
base ad:0xFFF7A000
|
|
width 21.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "REV,Aggregator Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Scheme number" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " BU ,Bu" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID ,Module ID"
|
|
bitfld.long 0x00 11.--15. " REVRTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " REVMAJ ,Major version" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom version" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " REVMIN ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "VECTOR,ECC Vector Register"
|
|
bitfld.long 0x00 24. " RD_SVBUS_DONE ,Status to indicate if read on serial VBUS is complete" "Not completed,Completed"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " RD_SVBUS_ADDR ,Read address"
|
|
bitfld.long 0x00 15. " RD_SVBUS ,Trigger a read on the serial VBUS" "Not triggered,Triggered"
|
|
hexmask.long.word 0x00 0.--10. 1. " ECC_VEC ,Value written to select the corresponding ECC RAM for control or status"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "STAT,Misc Status Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS ,Number of RAMS serviced by the ECC aggregator"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "CTRL,ECC Control Register"
|
|
bitfld.long 0x00 8. " CHECK_TIMEOUT ,Check timeout" "Not check,Check"
|
|
bitfld.long 0x00 7. " CHECK_PARITY ,Check parity" "Not check,Check"
|
|
bitfld.long 0x00 6. " ERROR_ONCE ,Force error only once" "Not force,Force"
|
|
bitfld.long 0x00 5. " FORCE_N_ROW ,Force error on any RAM read" "Not force,Force"
|
|
newline
|
|
bitfld.long 0x00 4. " FORCE_DED ,Force double bit error" "Not force,Force"
|
|
bitfld.long 0x00 3. " FORCE_SEC ,Force single bit error" "Not force,Force"
|
|
bitfld.long 0x00 2. " EN_RMW ,Enable RMW" "Disable,Enable"
|
|
bitfld.long 0x00 1. " ECC_CHK ,Enable ECC check" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 0. " ECC_EN ,Enable ECC" "Disable,Enable"
|
|
if (((per.l(ad:0xFFF7A000+0x14))&0x20)==0x20)
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "ERR_CTRL1,ECC Error Control Register 1"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ERR_CTRL1,ECC Error Control Register 1"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ERR_CTRL2,ECC Error Control Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " ECC_BIT[2] ,Data bit that needs to be flipped if double bit error needs to be forced"
|
|
hexmask.long.word 0x00 0.--15. 1. " [1] ,Data bit that needs to be flipped when force_sec is set"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ERR_STAT1,ECC Error Status Register 1"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " ECC_BIT1_STS ,Data bit that corresponds to the single-bit error"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ERR_STAT1,ECC Error Status Register 1"
|
|
bitfld.long 0x00 15. " CLR_ECC_CTRL_REG ,Clear ctrl reg error status" "Not clear,Clear"
|
|
bitfld.long 0x00 14. " CLR_ECC_PAR[1] ,Clear parity error status" "Not clear,Clear"
|
|
bitfld.long 0x00 13. " [0] ,Clear parity error status" "Not clear,Clear"
|
|
bitfld.long 0x00 12. " CLR_ECC_OTHER ,Clear other error status" "Not clear,Clear"
|
|
newline
|
|
bitfld.long 0x00 11. " CLR_ECC_DED[1] ,Clear double bit error status" "Not clear,Clear"
|
|
bitfld.long 0x00 10. " [0] ,Clear double bit error status" "Not clear,Clear"
|
|
bitfld.long 0x00 9. " CLR_ECC_SEC[1] ,Clear single bit error status" "Not clear,Clear"
|
|
bitfld.long 0x00 8. " [0] ,Clear single bit error status" "Not clear,Clear"
|
|
newline
|
|
bitfld.long 0x00 7. " ECC_CTRL_REG ,Force ctrl reg pending interrupt" "Not force,Force"
|
|
bitfld.long 0x00 6. " ECC_PAR[1] ,Force ECC parity pending interrupt" "Not force,Force"
|
|
bitfld.long 0x00 5. " [0] ,Force ECC parity pending interrupt" "Not force,Force"
|
|
bitfld.long 0x00 4. " ECC_OTHER ,Force ECC other pending interrupt" "Not force,Force"
|
|
newline
|
|
bitfld.long 0x00 3. " ECC_DED[1] ,Force ECC DED pending interrupt" "Not force,Force"
|
|
bitfld.long 0x00 2. " [0] ,Force ECC DED pending interrupt" "Not force,Force"
|
|
bitfld.long 0x00 1. " ECC_SEC[1] ,Force ECC SEC pending interrupt" "Not force,Force"
|
|
bitfld.long 0x00 0. " [0] ,Force ECC SEC pending interrupt" "Not force,Force"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "ERR_STAT2,ECC Error Status Register 2"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "ERR_STAT3,ECC Error Status Register 3"
|
|
bitfld.long 0x00 9. " CLR_TIMEOUT_PEND ,Clear timeout pending" "Not clear,Clear"
|
|
bitfld.long 0x00 1. " TIMEOUT_PEND ,Timeout pending" "Not pending,Pending"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SEC_EOI_REG,Single Error Correction End Of Interrupt Register"
|
|
bitfld.long 0x00 0. " SEC_EOI_WR ,EOI register" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "SEC_STATUS_REG0,Single Error Correction Interrupt Status Register"
|
|
bitfld.long 0x00 1. " CTRL_EDC_VBUSS_PEND ,Interrupt pending status for CTRL_EDC_VBUSS_PEND" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SEC_PEND ,Interrupt pending status for MSGMEM_PEND" "Not pending,Pending"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SEC_ENABLE_SET/CLR,Single Error Correction Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x40 1. " CTRL_EDC_VBUSS_EN ,CTRL_EDC_VBUSS_PEND interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x40 0. " SEC_EN ,MSGMEM_PEND interrupt enable" "Disabled,Enabled"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "DED_EOI_REG,Dual Error Detection End Of Interrupt Register"
|
|
bitfld.long 0x00 0. " DE_EOI_WR ,EOI register" "0,1"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "DED_STATUS_REG0,Dual Error Detection Interrupt Status Register"
|
|
bitfld.long 0x00 1. " CTRL_EDC_VBUSS_PEND ,Interrupt pending status fro CTRL_EDC_VBUSS_PEND" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " DED_PEND ,Interrupt pending status for MSGMEM_PEND" "Not pending,Pending"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "DED_ENABLE_SET/CLR,Dual Error Detection Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x40 1. " CTRL_EDC_VBUSS_EN ,CTRL_EDC_VBUSS_PEND interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x40 0. " DED_EN ,MSGMEM_PEND interrupt enable" "Disabled,Enabled"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "AGGR_ENABLE_SET/CLR,AGGR Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " TIMEOUT ,Interrupt enable for sv_bus_timeout errors" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PARITY ,Interrupt enable for parity errors" "Disabled,Enabled"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "AGGR_STATUS_SET/CLR,AGGR Interrupt Status Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " TIMEOUT ,Interrupt status for sv_bus_timeout errors" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PARITY ,Interrupt status for parity errors" "Not occurred,Occurred"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CAN-FD Module B Configuration"
|
|
base ad:0xFFF7C800
|
|
width 16.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SS_PID,Product ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID register scheme" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " BU ,Business Unit" ",,Processors,?..."
|
|
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID ,Module ID"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major revision" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " MINOR ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SS_CTRL,Control Register"
|
|
bitfld.long 0x00 6. " EXT_TS_CNTR_EN ,External timestamp counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " AUTOWAKEUP ,Automatic wakeup enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " WAKEUPREGEN ,Wakeup request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " DBGSUSP_FREE ,Debug suspend free" "Not freed,Freed"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SS_STAT,Status Register"
|
|
bitfld.long 0x00 2. " EN_FDOE ,Enable FDOE configuration" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MMI_DONE ,Memory initialization status" "In progress,Done"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SS_ICS,Interrupt Clear Shadow Register"
|
|
eventfld.long 0x00 0. " ICS ,External timestamp counter overflow interrupt status" "No interrupt,Interrupt"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SS_IRS,Interrupt Raw Status Register"
|
|
bitfld.long 0x00 0. " IRS ,External timestamp counter overflow interrupt status" "No interrupt,Interrupt"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SS_IECS,Interrupt Enable Clear Shadow Register"
|
|
eventfld.long 0x00 0. " IECS ,External timestamp counter overflow interrupt status" "No interrupt,Interrupt"
|
|
rgroup.long 0x18++0x07
|
|
line.long 0x00 "SS_IE,Interrupt Enable Register"
|
|
bitfld.long 0x00 0. " IE ,External timestamp counter overflow interrupt" "Disabled,Enabled"
|
|
line.long 0x04 "SS_IES,Interrupt Enable Status Register"
|
|
bitfld.long 0x04 0. " IES ,External timestamp counter overflow interrupt" "Low,High"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "SS_EOI,End Of Interrupt Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " EOI ,Pulse output corresponding to interrupt from EOI register"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SS_EXT_TS_PS,External Timestamp Prescaler Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PRESCALE ,Pulse output corresponding to interrupt from EOI register"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SS_EXT_TS_USIC,External Timestamp Unserviced Interrupts Counter Register"
|
|
bitfld.long 0x00 0.--4. " EXT_TS_INTR_CNTR ,Number of unserviced rollover interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x200++0x0B
|
|
line.long 0x00 "CREL,Core Release Register"
|
|
bitfld.long 0x00 28.--31. " REL ,Core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " STEP ,Step of core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SUBSTEP ,Sub-step of core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " YEAR ,Time stamp year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MON ,Time stamp month"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " DAY ,Time stamp day"
|
|
line.long 0x04 "ENDN,Endianess Test Value Register"
|
|
line.long 0x08 "CUST,Custom Register"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "DBTP,Data Bit Timing And Prescaler Register"
|
|
bitfld.long 0x00 23. " TDC ,Transmitter delay compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--20. " DBRP ,Data baud rate prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " DTSEG1 ,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4.--7. " DTSEG2 ,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " DSJW ,Data resynchronization jump width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0xFFF7C800+0x218))&0x80)==0x80)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "TEST,Test Register"
|
|
rbitfld.long 0x00 7. " RX ,Receive pin" "Low,High"
|
|
bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "0,1,2,3"
|
|
bitfld.long 0x00 4. " LBCK ,Loop back mode enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x210++0x03
|
|
line.long 0x00 "TEST,Test Register"
|
|
bitfld.long 0x00 7. " RX ,Receive pin" "Low,High"
|
|
bitfld.long 0x00 5.--6. " TX ,Control of transmit pin" "0,1,2,3"
|
|
bitfld.long 0x00 4. " LBCK ,Loop back mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x214++0x1B
|
|
line.long 0x00 "RWD,Watchdog Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " WDV ,Watchdog value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WDC ,Watchdog counter value"
|
|
line.long 0x04 "CCCR,Command Completion Coalescing Register"
|
|
bitfld.long 0x04 14. " TXP ,Transmit pause" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " EFBI ,Edge filtering during bus integration" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " PXHD ,Protocol exception handling disable" "No,Yes"
|
|
bitfld.long 0x04 9. " BRSE ,Bit rate switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " FDOE ,FD operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " TEST ,Test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " DAR ,Disable automatic retransmission" "No,Yes"
|
|
bitfld.long 0x04 5. " MON ,Bus monitoring mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CSR ,Clock stop request" "Not requested,Requested"
|
|
rbitfld.long 0x04 3. " CSA ,Clock stop acknowledge" "Not acknowledged,Acknowledged"
|
|
newline
|
|
bitfld.long 0x04 2. " ASM ,Restricted operation mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " CCE ,Configuration change enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " INIT ,Start software initialization" "Not started,Started"
|
|
line.long 0x08 "NBTP,Nominal Bit Timing And Prescaler Register"
|
|
hexmask.long.byte 0x08 25.--31. 1. " NSJW ,Nominal resynchronization jump width"
|
|
hexmask.long.word 0x08 16.--24. 1. " NBRP ,Nominal baud rate prescaler"
|
|
hexmask.long.byte 0x08 8.--15. 1. " NTSEG1 ,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x08 0.--6. 1. " NTSEG2 ,Nominal time segment after sample point"
|
|
line.long 0x0C "TSCC,Timestamp Counter Control Register"
|
|
bitfld.long 0x0C 16.--19. " TCP ,Timestamp counter prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--1. " TSS ,Timestamp select" "0,1,2,3"
|
|
line.long 0x10 "TSCV,Timestamp Counter Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " TSC ,Timestamp counter"
|
|
line.long 0x14 "TOCC,Timeout Counter Control Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " TOP ,Timeout period"
|
|
bitfld.long 0x14 1.--2. " TOS ,Timeout select" "0,1,2,3"
|
|
bitfld.long 0x14 0. " ETOC ,Enable timeout counter" "Disabled,Enabled"
|
|
line.long 0x18 "TOCV,Timeout Counter Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " TOC ,Timeout counter"
|
|
rgroup.long 0x240++0x07
|
|
line.long 0x00 "ECR,Error Counter Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CEL ,CAN error logging"
|
|
bitfld.long 0x00 15. " RP ,Receive error passive" "No,Yes"
|
|
hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive error counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit error counter"
|
|
line.long 0x04 "PSR,Packet Start Register"
|
|
hexmask.long.byte 0x04 16.--22. 1. " TDCV ,Transmitter delay compensation value"
|
|
bitfld.long 0x04 14. " PXE ,Protocol exception event" "Not occurred,Occurred"
|
|
bitfld.long 0x04 13. " RFDF ,Received a CAN FD message" "Not received,Received"
|
|
bitfld.long 0x04 12. " RBRS ,BRS flag of last received CAN FD message" "Low,High"
|
|
bitfld.long 0x04 11. " RESI ,ESI flag of last received CAN FD Message" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 8.--10. " DLEC ,Data phase last error code" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 7. " BO ,BUS_OFF status" "Low,High"
|
|
bitfld.long 0x04 6. " EW ,Warning status" "Low,High"
|
|
bitfld.long 0x04 5. " EP ,Error passive" "Low,High"
|
|
bitfld.long 0x04 3.--4. " ACT ,Activity" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 0.--2. " LEC ,Last error code" "0,1,2,3,4,5,6,7"
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "TDCR,Transmitter Delay Compensation Register"
|
|
hexmask.long.byte 0x00 8.--14. 0x01 " TDCO ,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x00 0.--6. 1. " TDCF ,Transmitter delay compensation filter window length"
|
|
group.long 0x250++0x0F
|
|
line.long 0x00 "IR,Interrupt Register"
|
|
bitfld.long 0x00 29. " ARA ,Access to reserved address" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " PED ,Protocol error in data phase" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " PEA ,Protocol error in arbitration phase" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " WDI ,Watchdog interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " BO ,BUS_OFF status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 24. " EW ,Warning status" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " EP ,Error passive" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " ELO ,Error logging overflow" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " BEU ,Bit error uncorrected" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " BEC ,Bit error corrected" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 19. " DRX ,Message stored to dedicated Rx buffer" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " TOO ,Timeout occurred" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " MRAF ,Message RAM access failure" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " TSW ,Timestamp wraparound" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " TEFL ,Tx event FIFO element lost" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 14. " TEFF ,Tx event FIFO full" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " TEFW ,Tx event FIFO watermark reached" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " TEFN ,Tx event FIFO new entry" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " TFE ,Tx FIFO empty" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " TCF ,Transmission cancellation finished" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " TC ,Transmission complete" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " HPM ,High priority message" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " RF1L ,Rx FIFO 1 message lost" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " RF1F ,Rx FIFO 1 full" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " RF1W ,Rx FIFO 1 watermark reached" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 4. " RF1N ,Rx FIFO 1 new message" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " RF0L ,Rx FIFO 0 message lost" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " RF0F ,Rx FIFO 0 Full" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RF0W ,Rx FIFO 0 watermark reached" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " RF0N ,Rx FIFO 0 new message" "No interrupt,Interrupt"
|
|
line.long 0x04 "IE,Interrupt Enable Register"
|
|
bitfld.long 0x04 29. " ARAE ,Access to reserved address enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " PEDE ,Protocol error in data phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " PEAE ,Protocol error in arbitration phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " WDIE ,Watchdog interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " BOE ,BUS_OFF status enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 24. " EWE ,Warning status enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " EPE ,Error passive enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ELOE ,Error logging overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " BEUE ,Bit error uncorrected enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " BECE ,Bit error corrected enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " DRXE ,Message stored to dedicated Rx buffer Enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " TOOE ,Timeout occurred enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " MRAFE ,Message RAM access failure enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " TSWE ,Timestamp wraparound enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " TEFLE ,Tx event FIFO element lost enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 14. " TEFFE ,Tx event FIFO full enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " TEFWE ,Tx event FIFO watermark reached enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " TEFNE ,Tx event FIFO new entry enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " TFEE ,Tx FIFO empty enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " TCFE ,Transmission cancellation finished enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 9. " TCE ,Transmission complete enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " HPME ,High priority message enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " RF1LE ,Rx FIFO 1 message lost enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RF1FE ,Rx FIFO 1 full enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " RF1WE ,Rx FIFO 1 watermark reached enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " RF1NE ,Rx FIFO 1 new message enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " RF0LE ,Rx FIFO 0 message lost enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RF0FE ,Rx FIFO 0 full enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RF0WE ,Rx FIFO 0 watermark reached enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RF0NE ,Rx FIFO 0 new message enable" "Disabled,Enabled"
|
|
line.long 0x08 "ILS,Interrupt Line Select Register"
|
|
bitfld.long 0x08 29. " ARAL ,Access to reserved address interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 28. " PEDL ,Protocol error in data phase interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 27. " PEAL ,Protocol error in arbitration phase interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 26. " WDIL ,Watchdog interrupt interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 25. " BOL ,BUS_OFF status interrupt line" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 24. " EWL ,Warning status interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 23. " EPL ,Error passive interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 22. " ELOL ,Error logging overflow interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 21. " BEUL ,Bit error uncorrected interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 20. " BECL ,Bit error corrected interrupt line" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 19. " DRXL ,Message stored to dedicated Rx buffer interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 18. " TOOL ,Timeout occurred interrupt Line" "INT0,INT1"
|
|
bitfld.long 0x08 17. " MRAFL ,Message RAM access failure interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 16. " TSWL ,Timestamp wraparound interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 15. " TEFLL ,Tx event FIFO element lost interrupt line" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 14. " TEFFL ,Tx event FIFO full interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 13. " TEFWL ,Tx event FIFO watermark reached interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 12. " TEFNL ,Tx event FIFO new entry interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 11. " TFEL ,Tx FIFO empty interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 10. " TCFL ,Transmission cancellation finished interrupt line" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 9. " TCL ,Transmission complete interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 8. " HPML ,High priority message interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 7. " RF1LL ,Rx FIFO 1 message lost interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 6. " RF1FL ,Rx FIFO 1 full interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 5. " RF1WL ,Rx FIFO 1 watermark reached interrupt line" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 4. " RF1NL ,Rx FIFO 1 new message interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 3. " RF0LL ,Rx FIFO 0 message lost interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 2. " RF0FL ,Rx FIFO 0 full interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 1. " RF0WL ,Rx FIFO 0 watermark reached interrupt line" "INT0,INT1"
|
|
bitfld.long 0x08 0. " RF0NL ,Rx FIFO 0 new message interrupt line" "INT0,INT1"
|
|
line.long 0x0C "ILE,Interrupt Line Enable Register"
|
|
bitfld.long 0x0C 1. " EINT[1] ,Enable interrupt line 1" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [0] ,Enable interrupt line 0" "Disabled,Enabled"
|
|
group.long 0x280++0x0B
|
|
line.long 0x00 "GFC,Global Filter Configuration Register"
|
|
bitfld.long 0x00 4.--5. " ANFS ,Accept non-matching frames standard" "0,1,2,3"
|
|
bitfld.long 0x00 2.--3. " ANFE ,Accept non-matching frames extended" "0,1,2,3"
|
|
bitfld.long 0x00 1. " RRFS ,Reject remote frames standard" "Not rejected,Rejected"
|
|
bitfld.long 0x00 0. " RRFE ,Reject remote frames extended" "Not rejected,Rejected"
|
|
line.long 0x04 "SIDFC,Standard ID Filter Configuration Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " LSS_S ,List size standard"
|
|
hexmask.long.word 0x04 2.--15. 0x04 " FLSSA_S ,Filter list standard start address"
|
|
line.long 0x08 "XIDFC,Extended ID Filter Configuration Register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " LSS_X ,List size standard"
|
|
hexmask.long.word 0x08 2.--15. 0x04 " FLSSA_X ,Filter list standard start address"
|
|
group.long 0x290++0x13
|
|
line.long 0x00 "XIDAM,Extended Mask ID Register"
|
|
bitfld.long 0x00 28. " EIDM ,Extended ID mask 28" "0,1"
|
|
bitfld.long 0x00 27. ",Extended ID mask 27" "0,1"
|
|
bitfld.long 0x00 26. ",Extended ID mask 26" "0,1"
|
|
bitfld.long 0x00 25. ",Extended ID mask 25" "0,1"
|
|
bitfld.long 0x00 24. ",Extended ID mask 24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. ",Extended ID mask 23" "0,1"
|
|
bitfld.long 0x00 22. ",Extended ID mask 22" "0,1"
|
|
bitfld.long 0x00 21. ",Extended ID mask 21" "0,1"
|
|
bitfld.long 0x00 20. ",Extended ID mask 20" "0,1"
|
|
bitfld.long 0x00 19. ",Extended ID mask 19" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. ",Extended ID mask 18" "0,1"
|
|
bitfld.long 0x00 17. ",Extended ID mask 17" "0,1"
|
|
bitfld.long 0x00 16. ",Extended ID mask 16" "0,1"
|
|
bitfld.long 0x00 15. ",Extended ID mask 15" "0,1"
|
|
bitfld.long 0x00 14. ",Extended ID mask 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. ",Extended ID mask 13" "0,1"
|
|
bitfld.long 0x00 12. ",Extended ID mask 12" "0,1"
|
|
bitfld.long 0x00 11. ",Extended ID mask 11" "0,1"
|
|
bitfld.long 0x00 10. ",Extended ID mask 10" "0,1"
|
|
bitfld.long 0x00 9. ",Extended ID mask 9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. ",Extended ID mask 8" "0,1"
|
|
bitfld.long 0x00 7. ",Extended ID mask 7" "0,1"
|
|
bitfld.long 0x00 6. ",Extended ID mask 6" "0,1"
|
|
bitfld.long 0x00 5. ",Extended ID mask 5" "0,1"
|
|
bitfld.long 0x00 4. ",Extended ID mask 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. ",Extended ID mask 3" "0,1"
|
|
bitfld.long 0x00 2. ",Extended ID mask 2" "0,1"
|
|
bitfld.long 0x00 1. ",Extended ID mask 1" "0,1"
|
|
bitfld.long 0x00 0. ",Extended ID mask 0" "0,1"
|
|
line.long 0x04 "HPMS,High Priority Message Status Register"
|
|
bitfld.long 0x04 15. " FLST ,Filter list" "0,1"
|
|
hexmask.long.byte 0x04 8.--14. 1. " FIDX ,Filter index"
|
|
bitfld.long 0x04 6.--7. " MSI ,Message storage indicator" "0,1,2,3"
|
|
bitfld.long 0x04 0.--5. " BIDX ,Buffer index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "NDAT1,New Data 1 Register"
|
|
line.long 0x0C "NDAT2,New Data 2 Register"
|
|
line.long 0x10 "RXF0C,Rx FIFO 0 Control Register"
|
|
bitfld.long 0x10 31. " F0OM ,Rx FIFO 0 operation mode" "Blocking,Overwrite"
|
|
hexmask.long.byte 0x10 24.--30. 1. " F0WM ,Rx FIFO 0 watermark"
|
|
hexmask.long.word 0x10 15.--22. 1. " F0S ,Rx FIFO 0 size"
|
|
hexmask.long.word 0x10 2.--14. 0x04 " F0SA ,Rx FIFO 0 start address"
|
|
rgroup.long 0x2A4++0x03
|
|
line.long 0x00 "RXF0S,Rx FIFO 0 Status Register"
|
|
bitfld.long 0x00 25. " RF0L ,Rx FIFO 0 message lost" "Not lost,Lost"
|
|
bitfld.long 0x00 24. " F0F ,Rx FIFO 0 full" "Not full,Full"
|
|
hexmask.long.byte 0x00 16.--21. 1. " F0PI ,Rx FIFO 0 put index"
|
|
bitfld.long 0x00 8.--13. " F0GI ,Rx FIFO 0 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " F0FL ,Rx FIFO 0 fill level"
|
|
group.long 0x2A8++0x0B
|
|
line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge Register"
|
|
bitfld.long 0x00 0.--5. " F0AI ,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "RXBC,Rx FIFO 0 Buffer Control Register"
|
|
hexmask.long.word 0x04 2.--15. 0x04 " RBSA ,Rx buffer start address"
|
|
line.long 0x08 "RXF1C,Rx FIFO 1 Control Register"
|
|
bitfld.long 0x08 31. " F1OM ,Rx FIFO 1 operation mode" "Blocking,Overwrite"
|
|
hexmask.long.byte 0x08 24.--30. 1. " F1WM ,Rx FIFO 1 watermark"
|
|
hexmask.long.word 0x08 15.--22. 1. " F1S ,Rx FIFO 1 size"
|
|
hexmask.long.word 0x08 2.--14. 0x04 " F1SA ,Rx FIFO 1 start address"
|
|
rgroup.long 0x2B4++0x03
|
|
line.long 0x00 "RXF1S,Rx FIFO 1 Status Register"
|
|
bitfld.long 0x00 25. " RF1L ,Rx FIFO 1 message lost" "Not lost,Lost"
|
|
bitfld.long 0x00 24. " F1F ,Rx FIFO 1 full" "Not full,Full"
|
|
hexmask.long.byte 0x00 16.--21. 1. " F1PI ,Rx FIFO 1 put index"
|
|
bitfld.long 0x00 8.--13. " F1GI ,Rx FIFO 1 get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 0.--6. 1. " F1FL ,Rx FIFO 1 fill level"
|
|
group.long 0x2B8++0x07
|
|
line.long 0x00 "RXF1A,Rx FIFO 0 Acknowledge Register"
|
|
bitfld.long 0x00 0.--5. " F1AI ,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "RXESC,Rx Size Control Register"
|
|
bitfld.long 0x04 8.--10. " RBDS ,Rx Buffer data field size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 4.--6. " F1DS ,Rx FIFO 1 data field size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " F0DS ,Rx FIFO 0 data field Size" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2C0++0x07
|
|
line.long 0x00 "TXBC,Tx Buffer Control Register"
|
|
bitfld.long 0x00 30. " TFQM ,Tx FIFO/queue mode" "FIFO,Queue"
|
|
bitfld.long 0x00 24.--29. " TFQS ,Transmit FIFO/queue size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " NDTB ,Number of dedicated transmit buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " TBSA ,Tx buffers start address"
|
|
line.long 0x04 "TXFQS,Tx FIFO/Queue Status Register"
|
|
bitfld.long 0x04 21. " TFQF ,Tx FIFO/queue full" "Not full,Full"
|
|
bitfld.long 0x04 16.--20. " TFQPI ,Tx FIFO/queue put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 8.--12. " TFGI ,Tx queue get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 0.--5. " TFFL ,Tx FIFO free level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "TXESC,Tx Buffer Size Control Register"
|
|
bitfld.long 0x00 0.--2. " TBDS ,Tx buffer data field size" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x2CC++0x03
|
|
line.long 0x00 "TXBRP,Tx Buffer Request Pending Register"
|
|
bitfld.long 0x00 31. " TRP[31] ,Tx buffer 31 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " [30] ,Tx buffer 30 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " [29] ,Tx buffer 29 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " [28] ,Tx buffer 28 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " [27] ,Tx buffer 27 transmission request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Tx buffer 26 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " [25] ,Tx buffer 25 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " [24] ,Tx buffer 24 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " [23] ,Tx buffer 23 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " [22] ,Tx buffer 22 transmission request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Tx buffer 21 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " [20] ,Tx buffer 20 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " [19] ,Tx buffer 19 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " [18] ,Tx buffer 18 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " [17] ,Tx buffer 17 transmission request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Tx buffer 16 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " [15] ,Tx buffer 15 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " [14] ,Tx buffer 14 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " [13] ,Tx buffer 13 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " [12] ,Tx buffer 12 transmission request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Tx buffer 11 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " [10] ,Tx buffer 10 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " [9] ,Tx buffer 9 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " [8] ,Tx buffer 8 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " [7] ,Tx buffer 7 transmission request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Tx buffer 6 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " [5] ,Tx buffer 5 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " [4] ,Tx buffer 4 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " [3] ,Tx buffer 3 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " [2] ,Tx buffer 2 transmission request pending" "Not pending,Pending"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Tx buffer 1 transmission request pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " [0] ,Tx buffer 0 transmission request pending" "Not pending,Pending"
|
|
if (((per.l(ad:0xFFF7C800+0x218))&0x02)==0x00)
|
|
group.long 0x2D0++0x07
|
|
line.long 0x00 "TXBAR,Tx Buffer Add Request Register"
|
|
bitfld.long 0x00 31. " AR[31] ,Add Tx buffer 31 request" "Not requested,Requested"
|
|
bitfld.long 0x00 30. " [30] ,Add Tx buffer 30 request" "Not requested,Requested"
|
|
bitfld.long 0x00 29. " [29] ,Add Tx buffer 29 request" "Not requested,Requested"
|
|
bitfld.long 0x00 28. " [28] ,Add Tx buffer 28 request" "Not requested,Requested"
|
|
bitfld.long 0x00 27. " [27] ,Add Tx buffer 27 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Add Tx buffer 26 request" "Not requested,Requested"
|
|
bitfld.long 0x00 25. " [25] ,Add Tx buffer 25 request" "Not requested,Requested"
|
|
bitfld.long 0x00 24. " [24] ,Add Tx buffer 24 request" "Not requested,Requested"
|
|
bitfld.long 0x00 23. " [23] ,Add Tx buffer 23 request" "Not requested,Requested"
|
|
bitfld.long 0x00 22. " [22] ,Add Tx buffer 22 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Add Tx buffer 21 request" "Not requested,Requested"
|
|
bitfld.long 0x00 20. " [20] ,Add Tx buffer 20 request" "Not requested,Requested"
|
|
bitfld.long 0x00 19. " [19] ,Add Tx buffer 19 request" "Not requested,Requested"
|
|
bitfld.long 0x00 18. " [18] ,Add Tx buffer 18 request" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " [17] ,Add Tx buffer 17 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Add Tx buffer 16 request" "Not requested,Requested"
|
|
bitfld.long 0x00 15. " [15] ,Add Tx buffer 15 request" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [14] ,Add Tx buffer 14 request" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " [13] ,Add Tx buffer 13 request" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [12] ,Add Tx buffer 12 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Add Tx buffer 11 request" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,Add Tx buffer 10 request" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " [9] ,Add Tx buffer 9 request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [8] ,Add Tx buffer 8 request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " [7] ,Add Tx buffer 7 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Add Tx buffer 6 request" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,Add Tx buffer 5 request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Add Tx buffer 4 request" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Add Tx buffer 3 request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Add Tx buffer 2 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Add Tx buffer 1 request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Add Tx buffer 0 request" "Not requested,Requested"
|
|
line.long 0x04 "TXBCR,Tx Buffer Cancellation Request Register"
|
|
bitfld.long 0x04 31. " CR[31] ,Cancel Tx buffer 31 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 30. " [30] ,Cancel Tx buffer 30 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 29. " [29] ,Cancel Tx buffer 29 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 28. " [28] ,Cancel Tx buffer 28 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 27. " [27] ,Cancel Tx buffer 27 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 26. " [26] ,Cancel Tx buffer 26 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 25. " [25] ,Cancel Tx buffer 25 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 24. " [24] ,Cancel Tx buffer 24 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 23. " [23] ,Cancel Tx buffer 23 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 22. " [22] ,Cancel Tx buffer 22 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 21. " [21] ,Cancel Tx buffer 21 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 20. " [20] ,Cancel Tx buffer 20 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 19. " [19] ,Cancel Tx buffer 19 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 18. " [18] ,Cancel Tx buffer 18 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 17. " [17] ,Cancel Tx buffer 17 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,Cancel Tx buffer 16 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 15. " [15] ,Cancel Tx buffer 15 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 14. " [14] ,Cancel Tx buffer 14 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 13. " [13] ,Cancel Tx buffer 13 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 12. " [12] ,Cancel Tx buffer 12 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Cancel Tx buffer 11 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 10. " [10] ,Cancel Tx buffer 10 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 9. " [9] ,Cancel Tx buffer 9 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 8. " [8] ,Cancel Tx buffer 8 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 7. " [7] ,Cancel Tx buffer 7 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Cancel Tx buffer 6 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 5. " [5] ,Cancel Tx buffer 5 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 4. " [4] ,Cancel Tx buffer 4 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 3. " [3] ,Cancel Tx buffer 3 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 2. " [2] ,Cancel Tx buffer 2 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Cancel Tx buffer 1 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 0. " [0] ,Cancel Tx buffer 0 request" "Not cancelled,Cancelled"
|
|
else
|
|
rgroup.long 0x2D0++0x07
|
|
line.long 0x00 "TXBAR,Tx Buffer Add Request Register"
|
|
bitfld.long 0x00 31. " AR[31] ,Add Tx buffer 31 request" "Not requested,Requested"
|
|
bitfld.long 0x00 30. " [30] ,Add Tx buffer 30 request" "Not requested,Requested"
|
|
bitfld.long 0x00 29. " [29] ,Add Tx buffer 29 request" "Not requested,Requested"
|
|
bitfld.long 0x00 28. " [28] ,Add Tx buffer 28 request" "Not requested,Requested"
|
|
bitfld.long 0x00 27. " [27] ,Add Tx buffer 27 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Add Tx buffer 26 request" "Not requested,Requested"
|
|
bitfld.long 0x00 25. " [25] ,Add Tx buffer 25 request" "Not requested,Requested"
|
|
bitfld.long 0x00 24. " [24] ,Add Tx buffer 24 request" "Not requested,Requested"
|
|
bitfld.long 0x00 23. " [23] ,Add Tx buffer 23 request" "Not requested,Requested"
|
|
bitfld.long 0x00 22. " [22] ,Add Tx buffer 22 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Add Tx buffer 21 request" "Not requested,Requested"
|
|
bitfld.long 0x00 20. " [20] ,Add Tx buffer 20 request" "Not requested,Requested"
|
|
bitfld.long 0x00 19. " [19] ,Add Tx buffer 19 request" "Not requested,Requested"
|
|
bitfld.long 0x00 18. " [18] ,Add Tx buffer 18 request" "Not requested,Requested"
|
|
bitfld.long 0x00 17. " [17] ,Add Tx buffer 17 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Add Tx buffer 16 request" "Not requested,Requested"
|
|
bitfld.long 0x00 15. " [15] ,Add Tx buffer 15 request" "Not requested,Requested"
|
|
bitfld.long 0x00 14. " [14] ,Add Tx buffer 14 request" "Not requested,Requested"
|
|
bitfld.long 0x00 13. " [13] ,Add Tx buffer 13 request" "Not requested,Requested"
|
|
bitfld.long 0x00 12. " [12] ,Add Tx buffer 12 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Add Tx buffer 11 request" "Not requested,Requested"
|
|
bitfld.long 0x00 10. " [10] ,Add Tx buffer 10 request" "Not requested,Requested"
|
|
bitfld.long 0x00 9. " [9] ,Add Tx buffer 9 request" "Not requested,Requested"
|
|
bitfld.long 0x00 8. " [8] ,Add Tx buffer 8 request" "Not requested,Requested"
|
|
bitfld.long 0x00 7. " [7] ,Add Tx buffer 7 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Add Tx buffer 6 request" "Not requested,Requested"
|
|
bitfld.long 0x00 5. " [5] ,Add Tx buffer 5 request" "Not requested,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Add Tx buffer 4 request" "Not requested,Requested"
|
|
bitfld.long 0x00 3. " [3] ,Add Tx buffer 3 request" "Not requested,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Add Tx buffer 2 request" "Not requested,Requested"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Add Tx buffer 1 request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " [0] ,Add Tx buffer 0 request" "Not requested,Requested"
|
|
line.long 0x04 "TXBCR,Tx Buffer Cancellation Request Register"
|
|
bitfld.long 0x04 31. " CR[31] ,Cancel Tx buffer 31 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 30. " [30] ,Cancel Tx buffer 30 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 29. " [29] ,Cancel Tx buffer 29 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 28. " [28] ,Cancel Tx buffer 28 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 27. " [27] ,Cancel Tx buffer 27 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 26. " [26] ,Cancel Tx buffer 26 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 25. " [25] ,Cancel Tx buffer 25 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 24. " [24] ,Cancel Tx buffer 24 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 23. " [23] ,Cancel Tx buffer 23 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 22. " [22] ,Cancel Tx buffer 22 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 21. " [21] ,Cancel Tx buffer 21 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 20. " [20] ,Cancel Tx buffer 20 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 19. " [19] ,Cancel Tx buffer 19 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 18. " [18] ,Cancel Tx buffer 18 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 17. " [17] ,Cancel Tx buffer 17 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,Cancel Tx buffer 16 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 15. " [15] ,Cancel Tx buffer 15 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 14. " [14] ,Cancel Tx buffer 14 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 13. " [13] ,Cancel Tx buffer 13 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 12. " [12] ,Cancel Tx buffer 12 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Cancel Tx buffer 11 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 10. " [10] ,Cancel Tx buffer 10 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 9. " [9] ,Cancel Tx buffer 9 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 8. " [8] ,Cancel Tx buffer 8 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 7. " [7] ,Cancel Tx buffer 7 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Cancel Tx buffer 6 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 5. " [5] ,Cancel Tx buffer 5 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 4. " [4] ,Cancel Tx buffer 4 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 3. " [3] ,Cancel Tx buffer 3 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 2. " [2] ,Cancel Tx buffer 2 request" "Not cancelled,Cancelled"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Cancel Tx buffer 1 request" "Not cancelled,Cancelled"
|
|
bitfld.long 0x04 0. " [0] ,Cancel Tx buffer 0 request" "Not cancelled,Cancelled"
|
|
endif
|
|
rgroup.long 0x2D8++0x07
|
|
line.long 0x00 "TXBTO,Tx Buffer Transmission Occurred Register"
|
|
bitfld.long 0x00 31. " TO[31] ,Tx buffer 31 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " [30] ,Tx buffer 30 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " [29] ,Tx buffer 29 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " [28] ,Tx buffer 28 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " [27] ,Tx buffer 27 transmission occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Tx buffer 26 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " [25] ,Tx buffer 25 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " [24] ,Tx buffer 24 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 23. " [23] ,Tx buffer 23 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " [22] ,Tx buffer 22 transmission occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Tx buffer 21 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " [20] ,Tx buffer 20 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 19. " [19] ,Tx buffer 19 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " [18] ,Tx buffer 18 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " [17] ,Tx buffer 17 transmission occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Tx buffer 16 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " [15] ,Tx buffer 15 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " [14] ,Tx buffer 14 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " [13] ,Tx buffer 13 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " [12] ,Tx buffer 12 transmission occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Tx buffer 11 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " [10] ,Tx buffer 10 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " [9] ,Tx buffer 9 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " [8] ,Tx buffer 8 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " [7] ,Tx buffer 7 transmission occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Tx buffer 6 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " [5] ,Tx buffer 5 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " [4] ,Tx buffer 4 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " [3] ,Tx buffer 3 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " [2] ,Tx buffer 2 transmission occurred" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Tx buffer 1 transmission occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " [0] ,Tx buffer 0 transmission occurred" "Not occurred,Occurred"
|
|
line.long 0x04 "TXBCF,Tx Buffer Cancellation Finished Register"
|
|
bitfld.long 0x04 31. " CF[31] ,Tx buffer 31 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 30. " [30] ,Tx buffer 30 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 29. " [29] ,Tx buffer 29 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 28. " [28] ,Tx buffer 28 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 27. " [27] ,Tx buffer 27 cancellation finished" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x04 26. " [26] ,Tx buffer 26 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 25. " [25] ,Tx buffer 25 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 24. " [24] ,Tx buffer 24 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 23. " [23] ,Tx buffer 23 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 22. " [22] ,Tx buffer 22 cancellation finished" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x04 21. " [21] ,Tx buffer 21 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 20. " [20] ,Tx buffer 20 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 19. " [19] ,Tx buffer 19 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 18. " [18] ,Tx buffer 18 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 17. " [17] ,Tx buffer 17 cancellation finished" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,Tx buffer 16 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 15. " [15] ,Tx buffer 15 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 14. " [14] ,Tx buffer 14 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 13. " [13] ,Tx buffer 13 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 12. " [12] ,Tx buffer 12 cancellation finished" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Tx buffer 11 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 10. " [10] ,Tx buffer 10 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 9. " [9] ,Tx buffer 9 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 8. " [8] ,Tx buffer 8 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 7. " [7] ,Tx buffer 7 cancellation finished" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Tx buffer 6 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 5. " [5] ,Tx buffer 5 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 4. " [4] ,Tx buffer 4 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 3. " [3] ,Tx buffer 3 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 2. " [2] ,Tx buffer 2 cancellation finished" "Not finished,Finished"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Tx buffer 1 cancellation finished" "Not finished,Finished"
|
|
bitfld.long 0x04 0. " [0] ,Tx buffer 0 cancellation finished" "Not finished,Finished"
|
|
group.long 0x2E0++0x07
|
|
line.long 0x00 "TXBTIE,Tx Transmission Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " TIE[31] ,Tx buffer 31 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Tx buffer 30 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Tx buffer 29 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Tx buffer 28 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Tx buffer 27 transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Tx buffer 26 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Tx buffer 25 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Tx buffer 24 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Tx buffer 23 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Tx buffer 22 transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " [21] ,Tx buffer 21 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Tx buffer 20 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Tx buffer 19 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Tx buffer 18 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Tx buffer 17 transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Tx buffer 16 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Tx buffer 15 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Tx buffer 14 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Tx buffer 13 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Tx buffer 12 transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Tx buffer 11 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Tx buffer 10 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Tx buffer 9 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Tx buffer 8 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Tx buffer 7 transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Tx buffer 6 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Tx buffer 5 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Tx buffer 4 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Tx buffer 3 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Tx buffer 2 transmission interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Tx buffer 1 transmission interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Tx buffer 0 transmission interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "TXBCIE,Tx Cancellation Finished Interrupt Enable Register"
|
|
bitfld.long 0x04 31. " CFIE[31] ,Tx buffer 31 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [30] ,Tx buffer 30 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [29] ,Tx buffer 29 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [28] ,Tx buffer 28 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " [27] ,Tx buffer 27 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 26. " [26] ,Tx buffer 26 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [25] ,Tx buffer 25 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [24] ,Tx buffer 24 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " [23] ,Tx buffer 23 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [22] ,Tx buffer 22 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 21. " [21] ,Tx buffer 21 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [20] ,Tx buffer 20 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " [19] ,Tx buffer 19 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [18] ,Tx buffer 18 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [17] ,Tx buffer 17 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,Tx buffer 16 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " [15] ,Tx buffer 15 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [14] ,Tx buffer 14 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [13] ,Tx buffer 13 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [12] ,Tx buffer 12 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Tx buffer 11 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [10] ,Tx buffer 10 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [9] ,Tx buffer 9 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [8] ,Tx buffer 8 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " [7] ,Tx buffer 7 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Tx buffer 6 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [5] ,Tx buffer 5 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [4] ,Tx buffer 4 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " [3] ,Tx buffer 3 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,Tx buffer 2 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Tx buffer 1 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [0] ,Tx buffer 0 cancellation finished interrupt enable" "Disabled,Enabled"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "TXEFC,Tx Event FIFO Control Register"
|
|
bitfld.long 0x00 24.--29. " EFWM ,Event FIFO watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. " EFS ,Event FIFO size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x00 2.--15. 0x04 " EFSA ,Event FIFO start address"
|
|
rgroup.long 0x2F4++0x07
|
|
line.long 0x00 "TXEFS,Tx Event FIFO Status Register"
|
|
bitfld.long 0x00 25. " TEFL ,Tx Event FIFO element lost" "Not lost,Lost"
|
|
bitfld.long 0x00 24. " EFF ,Event FIFO full" "Not full,Full"
|
|
bitfld.long 0x00 16.--20. " EFPI ,Event FIFO put index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. " EFGI ,Event FIFO get index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--5. " EFFL ,Event FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "TXEFA,Tx Event FIFO Acknowledge Index Register"
|
|
bitfld.long 0x04 0.--4. " EFAI ,Event FIFO acknowledge index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MCAN ECC Module B"
|
|
base ad:0xFFF7A000
|
|
width 21.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "REV,Aggregator Revision Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Scheme number" "0,1,2,3"
|
|
bitfld.long 0x00 28.--29. " BU ,Bu" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " MODULE_ID ,Module ID"
|
|
bitfld.long 0x00 11.--15. " REVRTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " REVMAJ ,Major version" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom version" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " REVMIN ,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "VECTOR,ECC Vector Register"
|
|
bitfld.long 0x00 24. " RD_SVBUS_DONE ,Status to indicate if read on serial VBUS is complete" "Not completed,Completed"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " RD_SVBUS_ADDR ,Read address"
|
|
bitfld.long 0x00 15. " RD_SVBUS ,Trigger a read on the serial VBUS" "Not triggered,Triggered"
|
|
hexmask.long.word 0x00 0.--10. 1. " ECC_VEC ,Value written to select the corresponding ECC RAM for control or status"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "STAT,Misc Status Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " NUM_RAMS ,Number of RAMS serviced by the ECC aggregator"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "CTRL,ECC Control Register"
|
|
bitfld.long 0x00 8. " CHECK_TIMEOUT ,Check timeout" "Not check,Check"
|
|
bitfld.long 0x00 7. " CHECK_PARITY ,Check parity" "Not check,Check"
|
|
bitfld.long 0x00 6. " ERROR_ONCE ,Force error only once" "Not force,Force"
|
|
bitfld.long 0x00 5. " FORCE_N_ROW ,Force error on any RAM read" "Not force,Force"
|
|
newline
|
|
bitfld.long 0x00 4. " FORCE_DED ,Force double bit error" "Not force,Force"
|
|
bitfld.long 0x00 3. " FORCE_SEC ,Force single bit error" "Not force,Force"
|
|
bitfld.long 0x00 2. " EN_RMW ,Enable RMW" "Disable,Enable"
|
|
bitfld.long 0x00 1. " ECC_CHK ,Enable ECC check" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 0. " ECC_EN ,Enable ECC" "Disable,Enable"
|
|
if (((per.l(ad:0xFFF7A000+0x14))&0x20)==0x20)
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "ERR_CTRL1,ECC Error Control Register 1"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ERR_CTRL1,ECC Error Control Register 1"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ERR_CTRL2,ECC Error Control Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " ECC_BIT[2] ,Data bit that needs to be flipped if double bit error needs to be forced"
|
|
hexmask.long.word 0x00 0.--15. 1. " [1] ,Data bit that needs to be flipped when force_sec is set"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "ERR_STAT1,ECC Error Status Register 1"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " ECC_BIT1_STS ,Data bit that corresponds to the single-bit error"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "ERR_STAT1,ECC Error Status Register 1"
|
|
bitfld.long 0x00 15. " CLR_ECC_CTRL_REG ,Clear ctrl reg error status" "Not clear,Clear"
|
|
bitfld.long 0x00 14. " CLR_ECC_PAR[1] ,Clear parity error status" "Not clear,Clear"
|
|
bitfld.long 0x00 13. " [0] ,Clear parity error status" "Not clear,Clear"
|
|
bitfld.long 0x00 12. " CLR_ECC_OTHER ,Clear other error status" "Not clear,Clear"
|
|
newline
|
|
bitfld.long 0x00 11. " CLR_ECC_DED[1] ,Clear double bit error status" "Not clear,Clear"
|
|
bitfld.long 0x00 10. " [0] ,Clear double bit error status" "Not clear,Clear"
|
|
bitfld.long 0x00 9. " CLR_ECC_SEC[1] ,Clear single bit error status" "Not clear,Clear"
|
|
bitfld.long 0x00 8. " [0] ,Clear single bit error status" "Not clear,Clear"
|
|
newline
|
|
bitfld.long 0x00 7. " ECC_CTRL_REG ,Force ctrl reg pending interrupt" "Not force,Force"
|
|
bitfld.long 0x00 6. " ECC_PAR[1] ,Force ECC parity pending interrupt" "Not force,Force"
|
|
bitfld.long 0x00 5. " [0] ,Force ECC parity pending interrupt" "Not force,Force"
|
|
bitfld.long 0x00 4. " ECC_OTHER ,Force ECC other pending interrupt" "Not force,Force"
|
|
newline
|
|
bitfld.long 0x00 3. " ECC_DED[1] ,Force ECC DED pending interrupt" "Not force,Force"
|
|
bitfld.long 0x00 2. " [0] ,Force ECC DED pending interrupt" "Not force,Force"
|
|
bitfld.long 0x00 1. " ECC_SEC[1] ,Force ECC SEC pending interrupt" "Not force,Force"
|
|
bitfld.long 0x00 0. " [0] ,Force ECC SEC pending interrupt" "Not force,Force"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "ERR_STAT2,ECC Error Status Register 2"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "ERR_STAT3,ECC Error Status Register 3"
|
|
bitfld.long 0x00 9. " CLR_TIMEOUT_PEND ,Clear timeout pending" "Not clear,Clear"
|
|
bitfld.long 0x00 1. " TIMEOUT_PEND ,Timeout pending" "Not pending,Pending"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SEC_EOI_REG,Single Error Correction End Of Interrupt Register"
|
|
bitfld.long 0x00 0. " SEC_EOI_WR ,EOI register" "0,1"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "SEC_STATUS_REG0,Single Error Correction Interrupt Status Register"
|
|
bitfld.long 0x00 1. " CTRL_EDC_VBUSS_PEND ,Interrupt pending status for CTRL_EDC_VBUSS_PEND" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " SEC_PEND ,Interrupt pending status for MSGMEM_PEND" "Not pending,Pending"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SEC_ENABLE_SET/CLR,Single Error Correction Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x40 1. " CTRL_EDC_VBUSS_EN ,CTRL_EDC_VBUSS_PEND interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x40 0. " SEC_EN ,MSGMEM_PEND interrupt enable" "Disabled,Enabled"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "DED_EOI_REG,Dual Error Detection End Of Interrupt Register"
|
|
bitfld.long 0x00 0. " DE_EOI_WR ,EOI register" "0,1"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "DED_STATUS_REG0,Dual Error Detection Interrupt Status Register"
|
|
bitfld.long 0x00 1. " CTRL_EDC_VBUSS_PEND ,Interrupt pending status fro CTRL_EDC_VBUSS_PEND" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " DED_PEND ,Interrupt pending status for MSGMEM_PEND" "Not pending,Pending"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "DED_ENABLE_SET/CLR,Dual Error Detection Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x40 1. " CTRL_EDC_VBUSS_EN ,CTRL_EDC_VBUSS_PEND interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x40 0. " DED_EN ,MSGMEM_PEND interrupt enable" "Disabled,Enabled"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "AGGR_ENABLE_SET/CLR,AGGR Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " TIMEOUT ,Interrupt enable for sv_bus_timeout errors" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PARITY ,Interrupt enable for parity errors" "Disabled,Enabled"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "AGGR_STATUS_SET/CLR,AGGR Interrupt Status Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " TIMEOUT ,Interrupt status for sv_bus_timeout errors" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " PARITY ,Interrupt status for parity errors" "Not occurred,Occurred"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.open "MIBSPI (Multi-Buffered Serial Peripheral Interface Module)"
|
|
tree "Control Registers A"
|
|
base ad:0xFFF7F400
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SPIGCR0,SPI Global Control Register 0"
|
|
bitfld.long 0x00 0. " NRESET ,Reset bit for the module" "Reset,No reset"
|
|
if (((per.l(ad:0xFFF7F400+0x04))&0x03)==0x03)
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Internal loop-back test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine mode" "Active,Powerdown"
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input"
|
|
line.long 0x04 "SPIINT0,SPI Interrupt Enable Register"
|
|
bitfld.long 0x04 24. " ENABLEHIGHZ ,SPIENA pin high-impedance enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " DMAREQEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TXINTENA ,TX interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RXINTENA ,RX interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " OVRNINTENA ,Overrun interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " BITERRENA ,Interrupt on bit error enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " DESYNCENA ,Interrupt on desynchronized slave enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PARERRENA ,Interrupt on parity error enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TIMEOUTENA ,Interrupt on ENA signal time-out enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " DLENERRENA ,Data length error interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPILVL,SPI Interrupt Level Register"
|
|
bitfld.long 0x08 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 6. " OVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 3. " DESYNCLVL ,Desynchronized slave interrupt level" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 1. " TIMEOUTLVL ,SPIENA pin time-out interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 0. " DLENERRLVL ,Data length error interrupt level (line) select" "INT0,INT1"
|
|
else
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine mode" "Active,Powerdown"
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input"
|
|
line.long 0x04 "SPIINT0,SPI Interrupt Enable Register"
|
|
bitfld.long 0x04 24. " ENABLEHIGHZ ,SPIENA pin high-impedance enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " DMAREQEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TXINTENA ,TX interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RXINTENA ,RX interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " OVRNINTENA ,Overrun interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " BITERRENA ,Interrupt on bit error enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PARERRENA ,Interrupt on parity error enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TIMEOUTENA ,Interrupt on ENA signal time-out enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " DLENERRENA ,Data length error interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPILVL,SPI Interrupt Level Register"
|
|
bitfld.long 0x08 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 6. " OVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " TIMEOUTLVL ,SPIENA pin time-out interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 0. " DLENERRLVL ,Data length error interrupt level (line) select" "INT0,INT1"
|
|
endif
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "SPIFLG,SPI Flag Register"
|
|
rbitfld.long 0x00 24. " BUFINITACTIVE ,Status of multi-buffer initialization process" "Completed,Not completed"
|
|
rbitfld.long 0x00 9. " TXINTFLG ,Transmitter empty interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " RXINTFLG ,Receiver full interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " OVRNINTFLG ,Receiver overrun flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " BITERRFLG ,Mismatch of internal transmit data and transmitted data flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 3. " DESYNCFLG ,De-synchronization of slave device" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " PARERRFLG ,Calculated parity differs from received parity bit" "No error,Error"
|
|
eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out due to non-activation of ENA signal" "No time-out,Time-out"
|
|
eventfld.long 0x00 0. " DLENERRFLG ,Data length error flag" "No error,Error"
|
|
line.long 0x04 "SPIPC0,SPI Pin Control Register 0"
|
|
bitfld.long 0x04 31. " SOMIFUN[7] ,Slave out master in pin 7 function" "GPIO,SPI"
|
|
bitfld.long 0x04 30. " [6] ,Slave out master in pin 6 function" "GPIO,SPI"
|
|
bitfld.long 0x04 29. " [5] ,Slave out master in pin 5 function" "GPIO,SPI"
|
|
bitfld.long 0x04 28. " [4] ,Slave out master in pin 4 function" "GPIO,SPI"
|
|
bitfld.long 0x04 27. " [3] ,Slave out master in pin 3 function" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 26. " [2] ,Slave out master in pin 2 function" "GPIO,SPI"
|
|
bitfld.long 0x04 25. " [1] ,Slave out master in pin 1 function" "GPIO,SPI"
|
|
bitfld.long 0x04 24. " [0] ,Slave out master in pin 0 function" "GPIO,SPI"
|
|
bitfld.long 0x04 23. " SIMOFUN[7] ,Slave in master out pin 7 function" "GPIO,SPI"
|
|
bitfld.long 0x04 22. " [6] ,Slave in master out pin 6 function" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 21. " [5] ,Slave in master out pin 5 function" "GPIO,SPI"
|
|
bitfld.long 0x04 20. " [4] ,Slave in master out pin 4 function" "GPIO,SPI"
|
|
bitfld.long 0x04 19. " [3] ,Slave in master out pin 3 function" "GPIO,SPI"
|
|
bitfld.long 0x04 18. " [2] ,Slave in master out pin 2 function" "GPIO,SPI"
|
|
bitfld.long 0x04 17. " [1] ,Slave in master out pin 1 function" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 16. " [0] ,Slave in master out pin 0 function" "GPIO,SPI"
|
|
bitfld.long 0x04 11. " SOMIFUN0 ,Slave out master in pin 0 function" "GPIO,SPI"
|
|
bitfld.long 0x04 10. " SIMOFUN0 ,Slave in master out pin 0 function" "GPIO,SPI"
|
|
bitfld.long 0x04 9. " CLKFUN ,SPI clock function" "GPIO,SPI"
|
|
bitfld.long 0x04 8. " ENAFUN ,SPIENA function" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 7. " SCSFUN[7] ,SPISCS pin 7 function" "GPIO,SPI"
|
|
bitfld.long 0x04 6. " [6] ,SPISCS pin 6 function" "GPIO,SPI"
|
|
bitfld.long 0x04 5. " [5] ,SPISCS pin 5 function" "GPIO,SPI"
|
|
bitfld.long 0x04 4. " [4] ,SPISCS pin 4 function" "GPIO,SPI"
|
|
bitfld.long 0x04 3. " [3] ,SPISCS pin 3 function" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,SPISCS pin 2 function" "GPIO,SPI"
|
|
bitfld.long 0x04 1. " [1] ,SPISCS pin 1 function" "GPIO,SPI"
|
|
bitfld.long 0x04 0. " [0] ,SPISCS pin 0 function" "GPIO,SPI"
|
|
line.long 0x08 "SPIPC1,SPI Pin Control Register 1"
|
|
bitfld.long 0x08 31. " SOMIDIR[7] ,SPISOMI pin 7 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 30. " [6] ,SPISOMI pin 6 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 29. " [5] ,SPISOMI pin 5 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 28. " [4] ,SPISOMI pin 4 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 27. " [3] ,SPISOMI pin 3 direction" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x08 26. " [2] ,SPISOMI pin 2 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 25. " [1] ,SPISOMI pin 1 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 24. " [0] ,SPISOMI pin 0 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 23. " SIMODIR[7] ,SPISIMO pin 7 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 22. " [6] ,SPISIMO pin 6 direction" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x08 21. " [5] ,SPISIMO pin 5 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 20. " [4] ,SPISIMO pin 4 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 19. " [3] ,SPISIMO pin 3 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 18. " [2] ,SPISIMO pin 2 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 17. " [1] ,SPISIMO pin 1 direction" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x08 16. " [0] ,SPISIMO pin 0 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 11. " SOMIDIR0 ,SPISOMI pin 0 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 10. " SIMODIR0 ,SPISIMO pin 0 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 9. " CLKDIR ,SPI clock direction" "GPIO,SPI"
|
|
bitfld.long 0x08 8. " ENADIR ,SPIENA direction" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x08 7. " SCSDIR[7] ,SPISCS pin 7 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 6. " [6] ,SPISCS pin 6 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 5. " [5] ,SPISCS pin 5 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 4. " [4] ,SPISCS pin 4 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 3. " [3] ,SPISCS pin 3 direction" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x08 2. " [2] ,SPISCS pin 2 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 1. " [1] ,SPISCS pin 1 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 0. " [0] ,SPISCS pin 0 direction" "GPIO,SPI"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SPIPC2,SPI Pin Control Register 2"
|
|
bitfld.long 0x00 31. " SOMIDIN[7] ,SPISOMI pin 7 data in" "0,1"
|
|
bitfld.long 0x00 30. " [6] ,SPISOMI pin 6 data in" "0,1"
|
|
bitfld.long 0x00 29. " [5] ,SPISOMI pin 5 data in" "0,1"
|
|
bitfld.long 0x00 28. " [4] ,SPISOMI pin 4 data in" "0,1"
|
|
bitfld.long 0x00 27. " [3] ,SPISOMI pin 3 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. " [2] ,SPISOMI pin 2 data in" "0,1"
|
|
bitfld.long 0x00 25. " [1] ,SPISOMI pin 1 data in" "0,1"
|
|
bitfld.long 0x00 24. " [0] ,SPISOMI pin 0 data in" "0,1"
|
|
bitfld.long 0x00 23. " SIMODIN[7] ,SPISIMO pin 7 data in" "0,1"
|
|
bitfld.long 0x00 22. " [6] ,SPISIMO pin 6 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. " [5] ,SPISIMO pin 5 data in" "0,1"
|
|
bitfld.long 0x00 20. " [4] ,SPISIMO pin 4 data in" "0,1"
|
|
bitfld.long 0x00 19. " [3] ,SPISIMO pin 3 data in" "0,1"
|
|
bitfld.long 0x00 18. " [2] ,SPISIMO pin 2 data in" "0,1"
|
|
bitfld.long 0x00 17. " [1] ,SPISIMO pin 1 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " [0] ,SPISIMO pin 0 data in" "0,1"
|
|
bitfld.long 0x00 11. " SOMIDIN0 ,SPISOMI pin 0 data in" "0,1"
|
|
bitfld.long 0x00 10. " SIMODIN0 ,SPISIMO pin 0 data in" "0,1"
|
|
bitfld.long 0x00 9. " CLKDIN ,Clock data in" "0,1"
|
|
bitfld.long 0x00 8. " ENADIN ,SPIENA data in" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " SCSDIN[7] ,SPISCS pin 7 data in" "0,1"
|
|
bitfld.long 0x00 6. " [6] ,SPISCS pin 6 data in" "0,1"
|
|
bitfld.long 0x00 5. " [5] ,SPISCS pin 5 data in" "0,1"
|
|
bitfld.long 0x00 4. " [4] ,SPISCS pin 4 data in" "0,1"
|
|
bitfld.long 0x00 3. " [3] ,SPISCS pin 3 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,SPISCS pin 2 data in" "0,1"
|
|
bitfld.long 0x00 1. " [1] ,SPISCS pin 1 data in" "0,1"
|
|
bitfld.long 0x00 0. " [0] ,SPISCS pin 0 data in" "0,1"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SPIPC3,SPI Pin Control Register 3"
|
|
bitfld.long 0x00 31. " SOMIDOUT[7] ,SPISOMI pin 7 data out write" "0,1"
|
|
bitfld.long 0x00 30. " [6] ,SPISOMI pin 6 data out write" "0,1"
|
|
bitfld.long 0x00 29. " [5] ,SPISOMI pin 5 data out write" "0,1"
|
|
bitfld.long 0x00 28. " [4] ,SPISOMI pin 4 data out write" "0,1"
|
|
bitfld.long 0x00 27. " [3] ,SPISOMI pin 3 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. " [2] ,SPISOMI pin 2 data out write" "0,1"
|
|
bitfld.long 0x00 25. " [1] ,SPISOMI pin 1 data out write" "0,1"
|
|
bitfld.long 0x00 24. " [0] ,SPISOMI pin 0 data out write" "0,1"
|
|
bitfld.long 0x00 23. " SIMODOUT[7] ,SPISIMO pin 7 data out write" "0,1"
|
|
bitfld.long 0x00 22. " [6] ,SPISIMO pin 6 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. " [5] ,SPISIMO pin 5 data out write" "0,1"
|
|
bitfld.long 0x00 20. " [4] ,SPISIMO pin 4 data out write" "0,1"
|
|
bitfld.long 0x00 19. " [3] ,SPISIMO pin 3 data out write" "0,1"
|
|
bitfld.long 0x00 18. " [2] ,SPISIMO pin 2 data out write" "0,1"
|
|
bitfld.long 0x00 17. " [1] ,SPISIMO pin 1 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " [0] ,SPISIMO pin 0 data out write" "0,1"
|
|
bitfld.long 0x00 11. " SOMIDOUT0 ,SPISOMI pin 0 data out write" "0,1"
|
|
bitfld.long 0x00 10. " SIMODOUT0 ,SPISIMO pin 0 data out write" "0,1"
|
|
bitfld.long 0x00 9. " CLKDOUT ,SPI clock data out write" "0,1"
|
|
bitfld.long 0x00 8. " ENADOUT ,SPIENA data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " SCSDOUT[7] ,SPISCS pin 7 data out write" "0,1"
|
|
bitfld.long 0x00 6. " [6] ,SPISCS pin 6 data out write" "0,1"
|
|
bitfld.long 0x00 5. " [5] ,SPISCS pin 5 data out write" "0,1"
|
|
bitfld.long 0x00 4. " [4] ,SPISCS pin 4 data out write" "0,1"
|
|
bitfld.long 0x00 3. " [3] ,SPISCS pin 3 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,SPISCS pin 2 data out write" "0,1"
|
|
bitfld.long 0x00 1. " [1] ,SPISCS pin 1 data out write" "0,1"
|
|
bitfld.long 0x00 0. " [0] ,SPISCS pin 0 data out write" "0,1"
|
|
line.long 0x04 "SPIPC4,SPI Pin Control Register 4"
|
|
bitfld.long 0x04 31. " SOMISET[7] ,SPISOMI pin 7 data out set" "No effect,Set"
|
|
bitfld.long 0x04 30. " [6] ,SPISOMI pin 6 data out set" "No effect,Set"
|
|
bitfld.long 0x04 29. " [5] ,SPISOMI pin 5 data out set" "No effect,Set"
|
|
bitfld.long 0x04 28. " [4] ,SPISOMI pin 4 data out set" "No effect,Set"
|
|
bitfld.long 0x04 27. " [3] ,SPISOMI pin 3 data out set" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x04 26. " [2] ,SPISOMI pin 2 data out set" "No effect,Set"
|
|
bitfld.long 0x04 25. " [1] ,SPISOMI pin 1 data out set" "No effect,Set"
|
|
bitfld.long 0x04 24. " [0] ,SPISOMI pin 0 data out set" "No effect,Set"
|
|
bitfld.long 0x04 23. " SIMOSET[7] ,SPISIMO pin 7 data out set" "No effect,Set"
|
|
bitfld.long 0x04 22. " [6] ,SPISIMO pin 6 data out set" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x04 21. " [5] ,SPISIMO pin 5 data out set" "No effect,Set"
|
|
bitfld.long 0x04 20. " [4] ,SPISIMO pin 4 data out set" "No effect,Set"
|
|
bitfld.long 0x04 19. " [3] ,SPISIMO pin 3 data out set" "No effect,Set"
|
|
bitfld.long 0x04 18. " [2] ,SPISIMO pin 2 data out set" "No effect,Set"
|
|
bitfld.long 0x04 17. " [1] ,SPISIMO pin 1 data out set" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x04 16. " [0] ,SPISIMO pin 0 data out set" "No effect,Set"
|
|
bitfld.long 0x04 11. " SOMISET0 ,SPISOMI pin 0 data out set" "No effect,Set"
|
|
bitfld.long 0x04 10. " SIMOSET0 ,SPISIMO pin 0 data out set" "No effect,Set"
|
|
bitfld.long 0x04 9. " CLKSET ,SPICLK data out set" "No effect,Set"
|
|
bitfld.long 0x04 8. " ENASET ,SPIENA data out set" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x04 7. " SCSSET[7] ,SPISCS pin 7 data out set" "No effect,Set"
|
|
bitfld.long 0x04 6. " [6] ,SPISCS pin 6 data out set" "No effect,Set"
|
|
bitfld.long 0x04 5. " [5] ,SPISCS pin 5 data out set" "No effect,Set"
|
|
bitfld.long 0x04 4. " [4] ,SPISCS pin 4 data out set" "No effect,Set"
|
|
bitfld.long 0x04 3. " [3] ,SPISCS pin 3 data out set" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,SPISCS pin 2 data out set" "No effect,Set"
|
|
bitfld.long 0x04 1. " [1] ,SPISCS pin 1 data out set" "No effect,Set"
|
|
bitfld.long 0x04 0. " [0] ,SPISCS pin 0 data out set" "No effect,Set"
|
|
line.long 0x08 "SPIPC5,SPI Pin Control Register 5"
|
|
bitfld.long 0x08 31. " SOMICLR[7] ,SPISOMI pin 7 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 30. " [6] ,SPISOMI pin 6 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 29. " [5] ,SPISOMI pin 5 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 28. " [4] ,SPISOMI pin 4 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 27. " [3] ,SPISOMI pin 3 data out clear" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x08 26. " [2] ,SPISOMI pin 2 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 25. " [1] ,SPISOMI pin 1 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 24. " [0] ,SPISOMI pin 0 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 23. " SIMOCLR[7] ,SPISIMO pin 7 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 22. " [6] ,SPISIMO pin 6 data out clear" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x08 21. " [5] ,SPISIMO pin 5 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 20. " [4] ,SPISIMO pin 4 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 19. " [3] ,SPISIMO pin 3 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 18. " [2] ,SPISIMO pin 2 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 17. " [1] ,SPISIMO pin 1 data out clear" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x08 16. " [0] ,SPISIMO pin 0 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 11. " SOMICLR0 ,SPISOMI pin 0 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 10. " SIMOCLR0 ,SPISIMO pin 0 data out clear" "No effect,Clear"
|
|
bitfld.long 0x08 9. " CLKCLR ,SPICLK data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 8. " ENACLR ,SPIENA data out clear" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x08 7. " SCSCLR[7] ,SPISCS pin 7 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 6. " [6] ,SPISCS pin 6 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 5. " [5] ,SPISCS pin 5 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 4. " [4] ,SPISCS pin 4 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 3. " [3] ,SPISCS pin 3 data out clear" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x08 2. " [2] ,SPISCS pin 2 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 1. " [1] ,SPISCS pin 1 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 0. " [0] ,SPISCS pin 0 data out clear" "No effect,Cleared"
|
|
line.long 0x0C "SPIPC6,SPI Pin Control Register 6"
|
|
bitfld.long 0x0C 31. " SOMIPDR[7] ,SPISOMI pin 7 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [6] ,SPISOMI pin 6 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [5] ,SPISOMI pin 5 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [4] ,SPISOMI pin 4 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " [3] ,SPISOMI pin 3 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 26. " [2] ,SPISOMI pin 2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [1] ,SPISOMI pin 1 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [0] ,SPISOMI pin 0 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " SIMOPDR[7] ,SPISIMO pin 7 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [6] ,SPISIMO pin 6 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 21. " [5] ,SPISIMO pin 5 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [4] ,SPISIMO pin 4 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 19. " [3] ,SPISIMO pin 3 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [2] ,SPISIMO pin 2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [1] ,SPISIMO pin 1 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 16. " [0] ,SPISIMO pin 0 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " SOMIPDR0 ,SPISOMI pin 0 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " SIMOPDR0 ,SPISIMO pin 0 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " CLKPDR ,SPI clock open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " ENAPDR ,SPIENA open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 7. " SCSPDR[7] ,SPISCS pin 7 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [6] ,SPISCS pin 6 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [5] ,SPISCS pin 5 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [4] ,SPISCS pin 4 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " [3] ,SPISCS pin 3 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " [2] ,SPISCS pin 2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [1] ,SPISCS pin 1 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [0] ,SPISCS pin 0 open drain enable" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SPIDAT0,SPI Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI transmit data"
|
|
if (((per.l(ad:0xFFF7F400+0x04))&0x03)==0x03)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SPIDAT1,Transmit Data Register 1"
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
newline
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SPIDAT1,Transmit Data Register 1"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
newline
|
|
endif
|
|
width 18.
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SPIBUF,SPI Receive Buffer Register"
|
|
in
|
|
newline
|
|
if (((per.l(ad:0xFFF7F400+0x04))&0x03)==0x03)
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SPIEMU,SPI Emulation Register"
|
|
bitfld.long 0x00 31. " RXEMPTY ,Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR ,Receive data buffer overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 29. " TXFULL ,Transmit data buffer full" "Empty,Full"
|
|
bitfld.long 0x00 28. " BITERR ,Mismatch of internal transmit data and transmitted data" "No error,Error"
|
|
bitfld.long 0x00 27. " DESYNC ,De-synchronization of slave device" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " PARITYERR ,Calculated parity differs from received parity bit" "No error,Error"
|
|
bitfld.long 0x00 25. " TIMEOUT ,Time-out due to non-activation of ENA pin" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " DLENERR ,Data length error flag" "No error,Error"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " EMU_RXDATA ,SPI receive data"
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip select active to transmit start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit end to chip select inactive delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit data finished to ENA pin inactive time out"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip select active to ENA signal active time out"
|
|
line.long 0x04 "SPIDEF,SPI Default Chip Select Register"
|
|
bitfld.long 0x04 7. " CSDEF[7] ,Chip select default pattern bit 7" "0,1"
|
|
bitfld.long 0x04 6. " [6] ,Chip select default pattern bit 6" "0,1"
|
|
bitfld.long 0x04 5. " [5] ,Chip select default pattern bit 5" "0,1"
|
|
bitfld.long 0x04 4. " [4] ,Chip select default pattern bit 4" "0,1"
|
|
bitfld.long 0x04 3. " [3] ,Chip select default pattern bit 3" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Chip select default pattern bit 2" "0,1"
|
|
bitfld.long 0x04 1. " [1] ,Chip select default pattern bit 1" "0,1"
|
|
bitfld.long 0x04 0. " [0] ,Chip select default pattern bit 0" "0,1"
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SPIEMU,SPI Emulation Register"
|
|
bitfld.long 0x00 31. " RXEMPTY ,Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR ,Receive data buffer overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 29. " TXFULL ,Transmit data buffer full" "Empty,Full"
|
|
bitfld.long 0x00 28. " BITERR ,Mismatch of internal transmit data and transmitted data" "No error,Error"
|
|
bitfld.long 0x00 26. " PARITYERR ,Calculated parity differs from received parity bit" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 24. " DLENERR ,Data Length Error flag" "No error,Error"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " EMU_RXDATA ,SPI receive data"
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "SPIDEF,SPI Default Chip Select Register"
|
|
endif
|
|
if (((per.l(ad:0xFFF7F400+0x04))&0x03)==0x03)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SPIFMT0,SPI Data Format Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
|
|
bitfld.long 0x00 23. " PARPOL ,Parity polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WAITENA ,The master waits for the ENA signal from slave for data format 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SHIFTDIR ,Shift direction for data format 0" "MSB,LSB"
|
|
newline
|
|
bitfld.long 0x00 19. " HDUPLEX_ENA ,Half Duplex transfer mode enable for data format 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
bitfld.long 0x00 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
|
|
bitfld.long 0x00 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
|
|
newline
|
|
bitfld.long 0x00 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SPIFMT1,SPI Data Format Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
|
|
bitfld.long 0x00 23. " PARPOL ,Parity polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WAITENA ,The master waits for the ENA signal from slave for data format 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SHIFTDIR ,Shift direction for data format 1" "MSB,LSB"
|
|
newline
|
|
bitfld.long 0x00 19. " HDUPLEX_ENA ,Half Duplex transfer mode enable for data format 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
bitfld.long 0x00 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
|
|
bitfld.long 0x00 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
|
|
newline
|
|
bitfld.long 0x00 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SPIFMT2,SPI Data Format Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
|
|
bitfld.long 0x00 23. " PARPOL ,Parity polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WAITENA ,The master waits for the ENA signal from slave for data format 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SHIFTDIR ,Shift direction for data format 2" "MSB,LSB"
|
|
newline
|
|
bitfld.long 0x00 19. " HDUPLEX_ENA ,Half Duplex transfer mode enable for data format 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
bitfld.long 0x00 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
|
|
bitfld.long 0x00 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
|
|
newline
|
|
bitfld.long 0x00 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SPIFMT3,SPI Data Format Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
|
|
bitfld.long 0x00 23. " PARPOL ,Parity polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WAITENA ,The master waits for the ENA signal from slave for data format 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SHIFTDIR ,Shift direction for data format 3" "MSB,LSB"
|
|
newline
|
|
bitfld.long 0x00 19. " HDUPLEX_ENA ,Half Duplex transfer mode enable for data format 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
bitfld.long 0x00 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
|
|
bitfld.long 0x00 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
|
|
newline
|
|
bitfld.long 0x00 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SPIFMT0,SPI Data Format Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
|
|
bitfld.long 0x00 23. " PARPOL ,Parity polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SHIFTDIR ,Shift direction for data format 0" "MSB,LSB"
|
|
bitfld.long 0x00 19. " HDUPLEX_ENA ,Half Duplex transfer mode enable for data format 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
bitfld.long 0x00 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
|
|
bitfld.long 0x00 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
|
|
bitfld.long 0x00 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SPIFMT1,SPI Data Format Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
|
|
bitfld.long 0x00 23. " PARPOL ,Parity polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SHIFTDIR ,Shift direction for data format 1" "MSB,LSB"
|
|
bitfld.long 0x00 19. " HDUPLEX_ENA ,Half Duplex transfer mode enable for data format 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
bitfld.long 0x00 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
|
|
bitfld.long 0x00 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
|
|
bitfld.long 0x00 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SPIFMT2,SPI Data Format Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
|
|
bitfld.long 0x00 23. " PARPOL ,Parity polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SHIFTDIR ,Shift direction for data format 2" "MSB,LSB"
|
|
bitfld.long 0x00 19. " HDUPLEX_ENA ,Half Duplex transfer mode enable for data format 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
bitfld.long 0x00 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
|
|
bitfld.long 0x00 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
|
|
bitfld.long 0x00 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SPIFMT3,SPI Data Format Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
|
|
bitfld.long 0x00 23. " PARPOL ,Parity polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SHIFTDIR ,Shift direction for data format 3" "MSB,LSB"
|
|
bitfld.long 0x00 19. " HDUPLEX_ENA ,Half Duplex transfer mode enable for data format 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
bitfld.long 0x00 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
|
|
bitfld.long 0x00 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
|
|
bitfld.long 0x00 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
endif
|
|
newline
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0/MibSPI Transfer Group Interrupt Vector Register 0"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "TGINTVECT1,SPI Interrupt Vector Register 1/MibSPI Transfer Group Interrupt Vector Register 1"
|
|
in
|
|
newline
|
|
group.long 0x68++0x0B
|
|
line.long 0x00 "SPIPC9,SPI Pin Control Register 9"
|
|
bitfld.long 0x00 31. " SOMISRS7[7] ,SPISOMI pin 7 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 30. " [6] ,SPISOMI pin 6 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 29. " [5] ,SPISOMI pin 5 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 28. " [4] ,SPISOMI pin 4 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 27. " [3] ,SPISOMI pin 3 slew rate" "Normal,Slow"
|
|
newline
|
|
bitfld.long 0x00 26. " [2] ,SPISOMI pin 2 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 25. " [1] ,SPISOMI pin 1 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 24. " [0] ,SPISOMI pin 0 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 23. " SIMOSRS7[7] ,SPISIMO pin 7 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 22. " [6] ,SPISIMO pin 6 slew rate" "Normal,Slow"
|
|
newline
|
|
bitfld.long 0x00 21. " [5] ,SPISIMO pin 5 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 20. " [4] ,SPISIMO pin 4 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 19. " [3] ,SPISIMO pin 3 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 18. " [2] ,SPISIMO pin 2 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 17. " [1] ,SPISIMO pin 1 slew rate" "Normal,Slow"
|
|
newline
|
|
bitfld.long 0x00 16. " [0] ,SPISIMO pin 0 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 11. " SOMISRS0 ,SPISOMI pin 0 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 10. " SIMOSRS0 ,SPISIMO pin 0 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 9. " CLKSRS ,SPICLK control slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 8. " ENASRS ,SPIENA control slew rate" "Fast,Slow"
|
|
newline
|
|
bitfld.long 0x00 7. " SCSSRS[7] ,SPISCS pin 7 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 6. " [6] ,SPISCS pin 6 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 5. " [5] ,SPISCS pin 5 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 4. " [4] ,SPISCS pin 4 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 3. " [3] ,SPISCS pin 3 slew rate" "Normal,Slow"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,SPISCS pin 2 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 1. " [1] ,SPISCS pin 1 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 0. " [0] ,SPISCS pin 0 slew rate" "Normal,Slow"
|
|
line.long 0x04 "SPIPMCTRL,SPI Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x04 30. " HSM_MODE3 ,Data format 3 High Speed Modulo Mode control" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " MODCLKPOL3 ,Data format 3 modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x04 26.--28. " MMODE3 ,Data format 3 SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x04 24.--25. " PMODE3 ,Data format 3 parallel mode data lines" "1,2,4,8"
|
|
bitfld.long 0x04 22. " HSM_MODE2 ,Data format 2 High Speed Modulo Mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 21. " MODCLKPOL2 ,Data format 2 modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x04 18.--20. " MMODE2 ,Data format 2 SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x04 16.--17. " PMODE2 ,Data format 2 parallel mode data lines" "1,2,4,8"
|
|
bitfld.long 0x04 14. " HSM_MODE1 ,Data format 1 High Speed Modulo Mode control" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " MODCLKPOL1 ,Data format 1 modulo mode SPICLK polarity" "Normal,Inverted"
|
|
newline
|
|
bitfld.long 0x04 10.--12. " MMODE1 ,Data format 1 SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x04 8.--9. " PMODE1 ,Data format 1 parallel mode data lines" "1,2,4,8"
|
|
bitfld.long 0x04 6. " HSM_MODE0 ,Data format 0 High Speed Modulo Mode control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " MODCLKPOL0 ,Data format 0 modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x04 2.--4. " MMODE0 ,Data format 0 SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
|
|
newline
|
|
bitfld.long 0x04 0.--1. " PMODE0 ,Data format 0 parallel mode data lines" "1,2,4,8"
|
|
line.long 0x08 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x08 16. " RXRAMACCESS ,Receive RAM access control" "Not writeable,Writeable"
|
|
bitfld.long 0x08 8.--11. " EXTENDED_BUF_ENA ,Enables the support for 256 buffers" ",,,,,128,,,,,256,?..."
|
|
bitfld.long 0x08 0. " MSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TGITENST_SET/CLR,MibSPI Transfer Group Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTENRDY[15] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [14] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [13] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [12] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [11] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [10] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [9] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [8] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [7] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [6] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [5] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [4] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [3] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [2] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [1] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [0] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTENSUS[15] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TGITLVST_SET/CLR,MibSPI Transfer Group Interrupt Level Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SETINTLVLRDY[15] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [14] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [13] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [12] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [11] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [10] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [9] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [8] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [7] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [6] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [5] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [4] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [3] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [2] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [1] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [0] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " SETINTLVLSUS[15] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TGINTFLG,Transfer Group Interrupt Flag Register"
|
|
eventfld.long 0x00 31. " INTFLGRDY[15] ,Transfer group 15 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 30. " [14] ,Transfer group 14 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 29. " [13] ,Transfer group 13 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 28. " [12] ,Transfer group 12 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 27. " [11] ,Transfer group 11 interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 26. " [10] ,Transfer group 10 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 25. " [9] ,Transfer group 9 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 24. " [8] ,Transfer group 8 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 23. " [7] ,Transfer group 7 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 22. " [6] ,Transfer group 6 interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 21. " [5] ,Transfer group 5 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 20. " [4] ,Transfer group 4 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 19. " [3] ,Transfer group 3 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 18. " [2] ,Transfer group 2 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 17. " [1] ,Transfer group 1 interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 16. " [0] ,Transfer group 0 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 15. " INTFLGSUS[15] ,Transfer group 15 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 14. " [14] ,Transfer group 14 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 13. " [13] ,Transfer group 13 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 12. " [12] ,Transfer group 12 interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
rbitfld.long 0x00 11. " [11] ,Transfer group 11 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 10. " [10] ,Transfer group 10 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 9. " [9] ,Transfer group 9 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 8. " [8] ,Transfer group 8 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 7. " [7] ,Transfer group 7 interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
rbitfld.long 0x00 6. " [6] ,Transfer group 6 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 5. " [5] ,Transfer group 5 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 4. " [4] ,Transfer group 4 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 3. " [3] ,Transfer group 3 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 2. " [2] ,Transfer group 2 interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
rbitfld.long 0x00 1. " [1] ,Transfer group 1 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 0. " [0] ,Transfer group 0 interrupt flag" "Not occurred,Occurred"
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "TICKCNT,Tick Count Register"
|
|
bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD ,Re-load the tick counter" "No effect,Reload"
|
|
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for the tick counter"
|
|
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer Register"
|
|
rbitfld.long 0x04 24.--28. " TGINSERVICE ,The transfer group currently being serviced by the sequencer" "No TG,TG0,TG1,TG2,TG3,TG4,TG5,TG6,TG7,TG8,TG9,TG10,TG11,TG12,TG13,TG14,TG15,?..."
|
|
hexmask.long.byte 0x04 8.--15. 0x01 " LPEND ,Last TG end pointer"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register 0"
|
|
bitfld.long 0x00 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST ,TG pointer reset mode" "No reset,Reset"
|
|
rbitfld.long 0x00 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register 1"
|
|
bitfld.long 0x00 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST ,TG pointer reset mode" "No reset,Reset"
|
|
rbitfld.long 0x00 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register 2"
|
|
bitfld.long 0x00 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST ,TG pointer reset mode" "No reset,Reset"
|
|
rbitfld.long 0x00 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register 3"
|
|
bitfld.long 0x00 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST ,TG pointer reset mode" "No reset,Reset"
|
|
rbitfld.long 0x00 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register 4"
|
|
bitfld.long 0x00 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST ,TG pointer reset mode" "No reset,Reset"
|
|
rbitfld.long 0x00 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register 5"
|
|
bitfld.long 0x00 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST ,TG pointer reset mode" "No reset,Reset"
|
|
rbitfld.long 0x00 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register 6"
|
|
bitfld.long 0x00 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST ,TG pointer reset mode" "No reset,Reset"
|
|
rbitfld.long 0x00 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register 7"
|
|
bitfld.long 0x00 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST ,TG pointer reset mode" "No reset,Reset"
|
|
rbitfld.long 0x00 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
if (((per.l(ad:0xFFF7F400+0x04))&0x03)==0x03)
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x00 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP ,Number of the physical DMA request line that is connected to the receive path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP ,Number of the physical DMA Request line that is connected to the transmit path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " NOBRK ,Non-interleaved DMA block transfer" "Interleaved,Non-interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rbitfld.long 0x00 7. " BUFID7 ,Extended bit of BUFID1" "0,1"
|
|
rbitfld.long 0x00 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x00 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP ,Number of the physical DMA request line that is connected to the receive path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP ,Number of the physical DMA Request line that is connected to the transmit path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " NOBRK ,Non-interleaved DMA block transfer" "Interleaved,Non-interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rbitfld.long 0x00 7. " BUFID7 ,Extended bit of BUFID2" "0,1"
|
|
rbitfld.long 0x00 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x00 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP ,Number of the physical DMA request line that is connected to the receive path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP ,Number of the physical DMA Request line that is connected to the transmit path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " NOBRK ,Non-interleaved DMA block transfer" "Interleaved,Non-interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rbitfld.long 0x00 7. " BUFID7 ,Extended bit of BUFID3" "0,1"
|
|
rbitfld.long 0x00 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x00 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP ,Number of the physical DMA request line that is connected to the receive path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP ,Number of the physical DMA Request line that is connected to the transmit path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " NOBRK ,Non-interleaved DMA block transfer" "Interleaved,Non-interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rbitfld.long 0x00 7. " BUFID7 ,Extended bit of BUFID4" "0,1"
|
|
rbitfld.long 0x00 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x00 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP ,Number of the physical DMA request line that is connected to the receive path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP ,Number of the physical DMA Request line that is connected to the transmit path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rbitfld.long 0x00 7. " BUFID7 ,Extended bit of BUFID0" "0,1"
|
|
rbitfld.long 0x00 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
rbitfld.long 0x00 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x00 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP ,Number of the physical DMA request line that is connected to the receive path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP ,Number of the physical DMA Request line that is connected to the transmit path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rbitfld.long 0x00 7. " BUFID7 ,Extended bit of BUFID1" "0,1"
|
|
rbitfld.long 0x00 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
rbitfld.long 0x00 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x00 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP ,Number of the physical DMA request line that is connected to the receive path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP ,Number of the physical DMA Request line that is connected to the transmit path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rbitfld.long 0x00 7. " BUFID7 ,Extended bit of BUFID2" "0,1"
|
|
rbitfld.long 0x00 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
rbitfld.long 0x00 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x00 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP ,Number of the physical DMA request line that is connected to the receive path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP ,Number of the physical DMA Request line that is connected to the transmit path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rbitfld.long 0x00 7. " BUFID7 ,Extended bit of BUFID3" "0,1"
|
|
rbitfld.long 0x00 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
rbitfld.long 0x00 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x00 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP ,Number of the physical DMA request line that is connected to the receive path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP ,Number of the physical DMA Request line that is connected to the transmit path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rbitfld.long 0x00 7. " BUFID7 ,Extended bit of BUFID4" "0,1"
|
|
rbitfld.long 0x00 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
rbitfld.long 0x00 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "ICOUNT0,MibSPI DMA0COUNT Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT0 ,The actual number of remaining DMA transfers"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "ICOUNT1,MibSPI DMA1COUNT Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT1 ,The actual number of remaining DMA transfers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "ICOUNT2,MibSPI DMA2COUNT Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT2 ,The actual number of remaining DMA transfers"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "ICOUNT3,MibSPI DMA3COUNT Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT3 ,The actual number of remaining DMA transfers"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "ICOUNT4,MibSPI DMA4COUNT Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT4 ,The actual number of remaining DMA transfers"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DMACNTLEN,DMA Large Count Register"
|
|
bitfld.long 0x00 0. " LARGE_COUNT ,ICOUNT value modified by writes to the DMAxCTRL" "Disabled,Enabled"
|
|
group.long 0x120++0x07
|
|
line.long 0x00 "PAR_ECC_CTRL,Parity/ECC Control Register"
|
|
bitfld.long 0x00 24.--27. " SBE_EVT_EN ,Single bit error event enable" ",,,,,Disabled,,,,,Enabled,?..."
|
|
bitfld.long 0x00 16.--19. " EDAC_MODE ,Error detection and correction mode" ",,,,,Disabled,,,,,Enabled,?..."
|
|
bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x04 "PAR_ECC_STAT,Parity/ECC Status Register"
|
|
eventfld.long 0x04 9. " SBE_FLG1 ,Single bit error in RXRAM" "No error,Error"
|
|
eventfld.long 0x04 8. " SBE_FLG0 ,Single bit error in TXRAM" "No error,Error"
|
|
eventfld.long 0x04 1. " EDFLG1 ,Uncorrectable parity or double bit ECC error" "No error,Error"
|
|
eventfld.long 0x04 0. " EDFLG0 ,Uncorrectable parity or double bit ECC error" "No error,Error"
|
|
newline
|
|
width 17.
|
|
hgroup.long 0x128++0x03
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x12C++0x03
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
in
|
|
newline
|
|
width 13.
|
|
newline
|
|
if (((per.l(ad:0xFFF7F400+0x134))&0x02)==0x02)&&(((per.l(ad:0xFFF7F400+0x134))&0xF00)==0xA00)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
eventfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not failed,Failed"
|
|
bitfld.long 0x00 20. " CTRLBITERR ,Controls inducing of BITERR during IO loopback test mode" "No effect,Flipped"
|
|
bitfld.long 0x00 19. " CTRLDESYNC ,Controls inducing of the desync error during IO loopback test mode" "No effect,Forced 0"
|
|
bitfld.long 0x00 18. " CTRLPARERR ,Controls inducing of parity errors during IO loopback test mode" "No effect,Flipped"
|
|
bitfld.long 0x00 17. " CTRLTIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No effect,Forced 1"
|
|
bitfld.long 0x00 16. " CTRLDLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No effect,Forced 1"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module IO loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "SPISCS[0],SPISCS[1],SPISCS[2],SPISCS[3],SPISCS[4],SPISCS[5],SPISCS[6],SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Injection of an error on the SPISCS[3:0] pins enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPBKTYPE ,Module IO loopback type" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 0. " RXPENA ,Analog loopback through the receive pin enable" "Disabled,Enabled"
|
|
newline
|
|
elif (((per.l(ad:0xFFF7F400+0x134))&0x02)==0x00)&&(((per.l(ad:0xFFF7F400+0x134))&0xF00)==0xA00)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 20. " CTRLBITERR ,Controls inducing of BITERR during IO loopback test mode" "No effect,Flipped"
|
|
bitfld.long 0x00 19. " CTRLDESYNC ,Controls inducing of the desync error during IO loopback test mode" "No effect,Forced 0"
|
|
bitfld.long 0x00 18. " CTRLPARERR ,Controls inducing of parity errors during IO loopback test mode" "No effect,Flipped"
|
|
bitfld.long 0x00 17. " CTRLTIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No effect,Forced 1"
|
|
bitfld.long 0x00 16. " CTRLDLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No effect,Forced 1"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module IO loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "SPISCS[0],SPISCS[1],SPISCS[2],SPISCS[3],SPISCS[4],SPISCS[5],SPISCS[6],SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Injection of an error on the SPISCS[3:0] pins enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPBKTYPE ,Module IO loopback type" "Digital,Analog"
|
|
elif (((per.l(ad:0xFFF7F400+0x134))&0x02)==0x02)&&(((per.l(ad:0xFFF7F400+0x134))&0xF00)!=0xA00)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module IO loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "SPISCS[0],SPISCS[1],SPISCS[2],SPISCS[3],SPISCS[4],SPISCS[5],SPISCS[6],SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Injection of an error on the SPISCS[3:0] pins enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPBKTYPE ,Module IO loopback type" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXPENA ,Analog loopback through the receive pin enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module IO loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "SPISCS[0],SPISCS[1],SPISCS[2],SPISCS[3],SPISCS[4],SPISCS[5],SPISCS[6],SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Injection of an error on the SPISCS[3:0] pins enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPBKTYPE ,Module IO loopback type" "Digital,Analog"
|
|
endif
|
|
width 21.
|
|
group.long 0x138++0x0B
|
|
line.long 0x00 "EXTENDED_PRESCALE_1,SPI Extended Prescale Register 1"
|
|
hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 ,Extended Prescale value for SPIFMT1"
|
|
hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 ,Extended Prescale value for SPIFMT0"
|
|
line.long 0x04 "EXTENDED_PRESCALE_2,SPI Extended Prescale Register 2"
|
|
hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 ,Extended Prescale value for SPIFMT3"
|
|
hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 ,Extended Prescale value for SPIFMT2"
|
|
line.long 0x08 "ECCDIAG_CTRL,ECC Diagnostic Control Register"
|
|
bitfld.long 0x08 0.--3. " ECCDIAG_EN ,ECC Diagnostic mode Enable Key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
if (((per.l(ad:0xFFF7F400+0x140))&0x0F)==0x05)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "ECCDIAG_STAT,ECC Diagnostic Status Register"
|
|
eventfld.long 0x00 17. " DEFLG1 ,RXRAM double bit error" "No error,Error"
|
|
eventfld.long 0x00 16. " DEFLG0 ,TXRAM double bit error" "No error,Error"
|
|
eventfld.long 0x00 1. " SEFLG1 ,RXRAM single bit error" "No error,Error"
|
|
eventfld.long 0x00 0. " SEFLG0 ,TXRAM single bit error" "No error,Error"
|
|
newline
|
|
else
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "ECCDIAG_STAT,ECC Diagnostic Status Register"
|
|
newline
|
|
endif
|
|
hgroup.long 0x148++0x03
|
|
hide.long 0x00 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
|
|
in
|
|
hgroup.long 0x14C++0x03
|
|
hide.long 0x00 "SBERRADDR0,Single Bit Error Address Register - TXRAM"
|
|
in
|
|
newline
|
|
rgroup.long 0x1FC++0x03
|
|
line.long 0x00 "SPIREV,SPI / MibSPI Revision ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Identification Scheme used to distinguish different ID schemes" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Indicates functionally equivalent module family"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major Revision number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Device specific implementation" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " MINOR ,Minor Revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Multi-Buffer RAM A"
|
|
base ad:0xFF0E0000
|
|
width 10.
|
|
tree "Multi-buffer RAM Transmit Data Registers"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TXRAM0,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "TXRAM1,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "TXRAM2,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TXRAM3,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TXRAM4,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TXRAM5,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TXRAM6,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TXRAM7,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TXRAM8,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TXRAM9,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TXRAM10,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TXRAM11,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TXRAM12,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TXRAM13,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TXRAM14,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TXRAM15,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TXRAM16,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TXRAM17,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TXRAM18,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TXRAM19,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TXRAM20,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TXRAM21,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TXRAM22,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TXRAM23,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TXRAM24,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TXRAM25,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TXRAM26,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TXRAM27,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TXRAM28,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TXRAM29,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TXRAM30,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TXRAM31,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TXRAM32,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TXRAM33,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "TXRAM34,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "TXRAM35,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "TXRAM36,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "TXRAM37,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TXRAM38,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TXRAM39,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TXRAM40,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "TXRAM41,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "TXRAM42,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "TXRAM43,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TXRAM44,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "TXRAM45,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "TXRAM46,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "TXRAM47,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TXRAM48,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TXRAM49,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TXRAM50,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TXRAM51,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TXRAM52,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "TXRAM53,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TXRAM54,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TXRAM55,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TXRAM56,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TXRAM57,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TXRAM58,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TXRAM59,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TXRAM60,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TXRAM61,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TXRAM62,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TXRAM63,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TXRAM64,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TXRAM65,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TXRAM66,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TXRAM67,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TXRAM68,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TXRAM69,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TXRAM70,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TXRAM71,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TXRAM72,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "TXRAM73,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "TXRAM74,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "TXRAM75,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TXRAM76,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TXRAM77,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TXRAM78,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TXRAM79,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "TXRAM80,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "TXRAM81,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "TXRAM82,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "TXRAM83,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "TXRAM84,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "TXRAM85,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "TXRAM86,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "TXRAM87,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "TXRAM88,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "TXRAM89,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "TXRAM90,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "TXRAM91,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "TXRAM92,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "TXRAM93,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "TXRAM94,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "TXRAM95,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "TXRAM96,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "TXRAM97,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "TXRAM98,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "TXRAM99,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "TXRAM100,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "TXRAM101,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "TXRAM102,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "TXRAM103,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TXRAM104,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "TXRAM105,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "TXRAM106,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "TXRAM107,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "TXRAM108,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "TXRAM109,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "TXRAM110,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "TXRAM111,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "TXRAM112,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "TXRAM113,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "TXRAM114,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "TXRAM115,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "TXRAM116,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "TXRAM117,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "TXRAM118,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "TXRAM119,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "TXRAM120,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "TXRAM121,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "TXRAM122,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "TXRAM123,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "TXRAM124,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "TXRAM125,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "TXRAM126,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "TXRAM127,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
tree.end
|
|
tree "Multi-buffer RAM Receive Buffer Registers"
|
|
hgroup.long 0x200++0x03
|
|
hide.long 0x00 "RXRAM0,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x204++0x03
|
|
hide.long 0x00 "RXRAM1,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x208++0x03
|
|
hide.long 0x00 "RXRAM2,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x20C++0x03
|
|
hide.long 0x00 "RXRAM3,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "RXRAM4,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x214++0x03
|
|
hide.long 0x00 "RXRAM5,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x218++0x03
|
|
hide.long 0x00 "RXRAM6,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "RXRAM7,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x220++0x03
|
|
hide.long 0x00 "RXRAM8,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x224++0x03
|
|
hide.long 0x00 "RXRAM9,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x228++0x03
|
|
hide.long 0x00 "RXRAM10,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x22C++0x03
|
|
hide.long 0x00 "RXRAM11,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x230++0x03
|
|
hide.long 0x00 "RXRAM12,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x234++0x03
|
|
hide.long 0x00 "RXRAM13,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x238++0x03
|
|
hide.long 0x00 "RXRAM14,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x23C++0x03
|
|
hide.long 0x00 "RXRAM15,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x240++0x03
|
|
hide.long 0x00 "RXRAM16,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x244++0x03
|
|
hide.long 0x00 "RXRAM17,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x248++0x03
|
|
hide.long 0x00 "RXRAM18,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x24C++0x03
|
|
hide.long 0x00 "RXRAM19,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x250++0x03
|
|
hide.long 0x00 "RXRAM20,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x254++0x03
|
|
hide.long 0x00 "RXRAM21,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x258++0x03
|
|
hide.long 0x00 "RXRAM22,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x25C++0x03
|
|
hide.long 0x00 "RXRAM23,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x260++0x03
|
|
hide.long 0x00 "RXRAM24,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x264++0x03
|
|
hide.long 0x00 "RXRAM25,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x268++0x03
|
|
hide.long 0x00 "RXRAM26,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x26C++0x03
|
|
hide.long 0x00 "RXRAM27,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x270++0x03
|
|
hide.long 0x00 "RXRAM28,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x274++0x03
|
|
hide.long 0x00 "RXRAM29,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x278++0x03
|
|
hide.long 0x00 "RXRAM30,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x27C++0x03
|
|
hide.long 0x00 "RXRAM31,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x280++0x03
|
|
hide.long 0x00 "RXRAM32,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x284++0x03
|
|
hide.long 0x00 "RXRAM33,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x288++0x03
|
|
hide.long 0x00 "RXRAM34,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x28C++0x03
|
|
hide.long 0x00 "RXRAM35,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x290++0x03
|
|
hide.long 0x00 "RXRAM36,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x294++0x03
|
|
hide.long 0x00 "RXRAM37,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x298++0x03
|
|
hide.long 0x00 "RXRAM38,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x29C++0x03
|
|
hide.long 0x00 "RXRAM39,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2A0++0x03
|
|
hide.long 0x00 "RXRAM40,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2A4++0x03
|
|
hide.long 0x00 "RXRAM41,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2A8++0x03
|
|
hide.long 0x00 "RXRAM42,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2AC++0x03
|
|
hide.long 0x00 "RXRAM43,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2B0++0x03
|
|
hide.long 0x00 "RXRAM44,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2B4++0x03
|
|
hide.long 0x00 "RXRAM45,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2B8++0x03
|
|
hide.long 0x00 "RXRAM46,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2BC++0x03
|
|
hide.long 0x00 "RXRAM47,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2C0++0x03
|
|
hide.long 0x00 "RXRAM48,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2C4++0x03
|
|
hide.long 0x00 "RXRAM49,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2C8++0x03
|
|
hide.long 0x00 "RXRAM50,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2CC++0x03
|
|
hide.long 0x00 "RXRAM51,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2D0++0x03
|
|
hide.long 0x00 "RXRAM52,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2D4++0x03
|
|
hide.long 0x00 "RXRAM53,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2D8++0x03
|
|
hide.long 0x00 "RXRAM54,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2DC++0x03
|
|
hide.long 0x00 "RXRAM55,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2E0++0x03
|
|
hide.long 0x00 "RXRAM56,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2E4++0x03
|
|
hide.long 0x00 "RXRAM57,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2E8++0x03
|
|
hide.long 0x00 "RXRAM58,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2EC++0x03
|
|
hide.long 0x00 "RXRAM59,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2F0++0x03
|
|
hide.long 0x00 "RXRAM60,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2F4++0x03
|
|
hide.long 0x00 "RXRAM61,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2F8++0x03
|
|
hide.long 0x00 "RXRAM62,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2FC++0x03
|
|
hide.long 0x00 "RXRAM63,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x300++0x03
|
|
hide.long 0x00 "RXRAM64,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "RXRAM65,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x308++0x03
|
|
hide.long 0x00 "RXRAM66,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x30C++0x03
|
|
hide.long 0x00 "RXRAM67,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "RXRAM68,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x314++0x03
|
|
hide.long 0x00 "RXRAM69,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x318++0x03
|
|
hide.long 0x00 "RXRAM70,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x31C++0x03
|
|
hide.long 0x00 "RXRAM71,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x320++0x03
|
|
hide.long 0x00 "RXRAM72,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x324++0x03
|
|
hide.long 0x00 "RXRAM73,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x328++0x03
|
|
hide.long 0x00 "RXRAM74,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x32C++0x03
|
|
hide.long 0x00 "RXRAM75,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x330++0x03
|
|
hide.long 0x00 "RXRAM76,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x334++0x03
|
|
hide.long 0x00 "RXRAM77,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x338++0x03
|
|
hide.long 0x00 "RXRAM78,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x33C++0x03
|
|
hide.long 0x00 "RXRAM79,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x340++0x03
|
|
hide.long 0x00 "RXRAM80,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x344++0x03
|
|
hide.long 0x00 "RXRAM81,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x348++0x03
|
|
hide.long 0x00 "RXRAM82,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x34C++0x03
|
|
hide.long 0x00 "RXRAM83,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x350++0x03
|
|
hide.long 0x00 "RXRAM84,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x354++0x03
|
|
hide.long 0x00 "RXRAM85,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x358++0x03
|
|
hide.long 0x00 "RXRAM86,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x35C++0x03
|
|
hide.long 0x00 "RXRAM87,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x360++0x03
|
|
hide.long 0x00 "RXRAM88,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x364++0x03
|
|
hide.long 0x00 "RXRAM89,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x368++0x03
|
|
hide.long 0x00 "RXRAM90,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x36C++0x03
|
|
hide.long 0x00 "RXRAM91,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x370++0x03
|
|
hide.long 0x00 "RXRAM92,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x374++0x03
|
|
hide.long 0x00 "RXRAM93,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x378++0x03
|
|
hide.long 0x00 "RXRAM94,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x37C++0x03
|
|
hide.long 0x00 "RXRAM95,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x380++0x03
|
|
hide.long 0x00 "RXRAM96,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x384++0x03
|
|
hide.long 0x00 "RXRAM97,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x388++0x03
|
|
hide.long 0x00 "RXRAM98,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x38C++0x03
|
|
hide.long 0x00 "RXRAM99,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "RXRAM100,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x394++0x03
|
|
hide.long 0x00 "RXRAM101,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x398++0x03
|
|
hide.long 0x00 "RXRAM102,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x39C++0x03
|
|
hide.long 0x00 "RXRAM103,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3A0++0x03
|
|
hide.long 0x00 "RXRAM104,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3A4++0x03
|
|
hide.long 0x00 "RXRAM105,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3A8++0x03
|
|
hide.long 0x00 "RXRAM106,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3AC++0x03
|
|
hide.long 0x00 "RXRAM107,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3B0++0x03
|
|
hide.long 0x00 "RXRAM108,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3B4++0x03
|
|
hide.long 0x00 "RXRAM109,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3B8++0x03
|
|
hide.long 0x00 "RXRAM110,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3BC++0x03
|
|
hide.long 0x00 "RXRAM111,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3C0++0x03
|
|
hide.long 0x00 "RXRAM112,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3C4++0x03
|
|
hide.long 0x00 "RXRAM113,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3C8++0x03
|
|
hide.long 0x00 "RXRAM114,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3CC++0x03
|
|
hide.long 0x00 "RXRAM115,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3D0++0x03
|
|
hide.long 0x00 "RXRAM116,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3D4++0x03
|
|
hide.long 0x00 "RXRAM117,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3D8++0x03
|
|
hide.long 0x00 "RXRAM118,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3DC++0x03
|
|
hide.long 0x00 "RXRAM119,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3E0++0x03
|
|
hide.long 0x00 "RXRAM120,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3E4++0x03
|
|
hide.long 0x00 "RXRAM121,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3E8++0x03
|
|
hide.long 0x00 "RXRAM122,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3EC++0x03
|
|
hide.long 0x00 "RXRAM123,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3F0++0x03
|
|
hide.long 0x00 "RXRAM124,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3F4++0x03
|
|
hide.long 0x00 "RXRAM125,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3F8++0x03
|
|
hide.long 0x00 "RXRAM126,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3FC++0x03
|
|
hide.long 0x00 "RXRAM127,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpuis("AWR1642*")||cpuis("AWR1843*")||cpuis("AWR6843*"))
|
|
tree "Control Registers B"
|
|
base ad:0xFFF7F600
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SPIGCR0,SPI Global Control Register 0"
|
|
bitfld.long 0x00 0. " NRESET ,Reset bit for the module" "Reset,No reset"
|
|
if (((per.l(ad:0xFFF7F600+0x04))&0x03)==0x03)
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Internal loop-back test mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine mode" "Active,Powerdown"
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input"
|
|
line.long 0x04 "SPIINT0,SPI Interrupt Enable Register"
|
|
bitfld.long 0x04 24. " ENABLEHIGHZ ,SPIENA pin high-impedance enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " DMAREQEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TXINTENA ,TX interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RXINTENA ,RX interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " OVRNINTENA ,Overrun interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " BITERRENA ,Interrupt on bit error enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " DESYNCENA ,Interrupt on desynchronized slave enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PARERRENA ,Interrupt on parity error enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TIMEOUTENA ,Interrupt on ENA signal time-out enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " DLENERRENA ,Data length error interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPILVL,SPI Interrupt Level Register"
|
|
bitfld.long 0x08 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 6. " OVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 3. " DESYNCLVL ,Desynchronized slave interrupt level" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 1. " TIMEOUTLVL ,SPIENA pin time-out interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 0. " DLENERRLVL ,Data length error interrupt level (line) select" "INT0,INT1"
|
|
else
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SPIGCR1,SPI Global Control Register 1"
|
|
bitfld.long 0x00 24. " SPIEN ,SPI enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " POWERDOWN ,SPI state machine mode" "Active,Powerdown"
|
|
bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal"
|
|
bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input"
|
|
line.long 0x04 "SPIINT0,SPI Interrupt Enable Register"
|
|
bitfld.long 0x04 24. " ENABLEHIGHZ ,SPIENA pin high-impedance enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " DMAREQEN ,DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TXINTENA ,TX interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RXINTENA ,RX interrupt flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " OVRNINTENA ,Overrun interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 4. " BITERRENA ,Interrupt on bit error enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " PARERRENA ,Interrupt on parity error enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TIMEOUTENA ,Interrupt on ENA signal time-out enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " DLENERRENA ,Data length error interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "SPILVL,SPI Interrupt Level Register"
|
|
bitfld.long 0x08 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 6. " OVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1"
|
|
newline
|
|
bitfld.long 0x08 1. " TIMEOUTLVL ,SPIENA pin time-out interrupt level" "INT0,INT1"
|
|
bitfld.long 0x08 0. " DLENERRLVL ,Data length error interrupt level (line) select" "INT0,INT1"
|
|
endif
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "SPIFLG,SPI Flag Register"
|
|
rbitfld.long 0x00 24. " BUFINITACTIVE ,Status of multi-buffer initialization process" "Completed,Not completed"
|
|
rbitfld.long 0x00 9. " TXINTFLG ,Transmitter empty interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " RXINTFLG ,Receiver full interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " OVRNINTFLG ,Receiver overrun flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 4. " BITERRFLG ,Mismatch of internal transmit data and transmitted data flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 3. " DESYNCFLG ,De-synchronization of slave device" "Not occurred,Occurred"
|
|
eventfld.long 0x00 2. " PARERRFLG ,Calculated parity differs from received parity bit" "No error,Error"
|
|
eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out due to non-activation of ENA signal" "No time-out,Time-out"
|
|
eventfld.long 0x00 0. " DLENERRFLG ,Data length error flag" "No error,Error"
|
|
line.long 0x04 "SPIPC0,SPI Pin Control Register 0"
|
|
bitfld.long 0x04 31. " SOMIFUN[7] ,Slave out master in pin 7 function" "GPIO,SPI"
|
|
bitfld.long 0x04 30. " [6] ,Slave out master in pin 6 function" "GPIO,SPI"
|
|
bitfld.long 0x04 29. " [5] ,Slave out master in pin 5 function" "GPIO,SPI"
|
|
bitfld.long 0x04 28. " [4] ,Slave out master in pin 4 function" "GPIO,SPI"
|
|
bitfld.long 0x04 27. " [3] ,Slave out master in pin 3 function" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 26. " [2] ,Slave out master in pin 2 function" "GPIO,SPI"
|
|
bitfld.long 0x04 25. " [1] ,Slave out master in pin 1 function" "GPIO,SPI"
|
|
bitfld.long 0x04 24. " [0] ,Slave out master in pin 0 function" "GPIO,SPI"
|
|
bitfld.long 0x04 23. " SIMOFUN[7] ,Slave in master out pin 7 function" "GPIO,SPI"
|
|
bitfld.long 0x04 22. " [6] ,Slave in master out pin 6 function" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 21. " [5] ,Slave in master out pin 5 function" "GPIO,SPI"
|
|
bitfld.long 0x04 20. " [4] ,Slave in master out pin 4 function" "GPIO,SPI"
|
|
bitfld.long 0x04 19. " [3] ,Slave in master out pin 3 function" "GPIO,SPI"
|
|
bitfld.long 0x04 18. " [2] ,Slave in master out pin 2 function" "GPIO,SPI"
|
|
bitfld.long 0x04 17. " [1] ,Slave in master out pin 1 function" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 16. " [0] ,Slave in master out pin 0 function" "GPIO,SPI"
|
|
bitfld.long 0x04 11. " SOMIFUN0 ,Slave out master in pin 0 function" "GPIO,SPI"
|
|
bitfld.long 0x04 10. " SIMOFUN0 ,Slave in master out pin 0 function" "GPIO,SPI"
|
|
bitfld.long 0x04 9. " CLKFUN ,SPI clock function" "GPIO,SPI"
|
|
bitfld.long 0x04 8. " ENAFUN ,SPIENA function" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 7. " SCSFUN[7] ,SPISCS pin 7 function" "GPIO,SPI"
|
|
bitfld.long 0x04 6. " [6] ,SPISCS pin 6 function" "GPIO,SPI"
|
|
bitfld.long 0x04 5. " [5] ,SPISCS pin 5 function" "GPIO,SPI"
|
|
bitfld.long 0x04 4. " [4] ,SPISCS pin 4 function" "GPIO,SPI"
|
|
bitfld.long 0x04 3. " [3] ,SPISCS pin 3 function" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,SPISCS pin 2 function" "GPIO,SPI"
|
|
bitfld.long 0x04 1. " [1] ,SPISCS pin 1 function" "GPIO,SPI"
|
|
bitfld.long 0x04 0. " [0] ,SPISCS pin 0 function" "GPIO,SPI"
|
|
line.long 0x08 "SPIPC1,SPI Pin Control Register 1"
|
|
bitfld.long 0x08 31. " SOMIDIR[7] ,SPISOMI pin 7 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 30. " [6] ,SPISOMI pin 6 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 29. " [5] ,SPISOMI pin 5 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 28. " [4] ,SPISOMI pin 4 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 27. " [3] ,SPISOMI pin 3 direction" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x08 26. " [2] ,SPISOMI pin 2 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 25. " [1] ,SPISOMI pin 1 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 24. " [0] ,SPISOMI pin 0 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 23. " SIMODIR[7] ,SPISIMO pin 7 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 22. " [6] ,SPISIMO pin 6 direction" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x08 21. " [5] ,SPISIMO pin 5 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 20. " [4] ,SPISIMO pin 4 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 19. " [3] ,SPISIMO pin 3 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 18. " [2] ,SPISIMO pin 2 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 17. " [1] ,SPISIMO pin 1 direction" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x08 16. " [0] ,SPISIMO pin 0 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 11. " SOMIDIR0 ,SPISOMI pin 0 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 10. " SIMODIR0 ,SPISIMO pin 0 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 9. " CLKDIR ,SPI clock direction" "GPIO,SPI"
|
|
bitfld.long 0x08 8. " ENADIR ,SPIENA direction" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x08 7. " SCSDIR[7] ,SPISCS pin 7 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 6. " [6] ,SPISCS pin 6 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 5. " [5] ,SPISCS pin 5 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 4. " [4] ,SPISCS pin 4 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 3. " [3] ,SPISCS pin 3 direction" "GPIO,SPI"
|
|
newline
|
|
bitfld.long 0x08 2. " [2] ,SPISCS pin 2 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 1. " [1] ,SPISCS pin 1 direction" "GPIO,SPI"
|
|
bitfld.long 0x08 0. " [0] ,SPISCS pin 0 direction" "GPIO,SPI"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SPIPC2,SPI Pin Control Register 2"
|
|
bitfld.long 0x00 31. " SOMIDIN[7] ,SPISOMI pin 7 data in" "0,1"
|
|
bitfld.long 0x00 30. " [6] ,SPISOMI pin 6 data in" "0,1"
|
|
bitfld.long 0x00 29. " [5] ,SPISOMI pin 5 data in" "0,1"
|
|
bitfld.long 0x00 28. " [4] ,SPISOMI pin 4 data in" "0,1"
|
|
bitfld.long 0x00 27. " [3] ,SPISOMI pin 3 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. " [2] ,SPISOMI pin 2 data in" "0,1"
|
|
bitfld.long 0x00 25. " [1] ,SPISOMI pin 1 data in" "0,1"
|
|
bitfld.long 0x00 24. " [0] ,SPISOMI pin 0 data in" "0,1"
|
|
bitfld.long 0x00 23. " SIMODIN[7] ,SPISIMO pin 7 data in" "0,1"
|
|
bitfld.long 0x00 22. " [6] ,SPISIMO pin 6 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. " [5] ,SPISIMO pin 5 data in" "0,1"
|
|
bitfld.long 0x00 20. " [4] ,SPISIMO pin 4 data in" "0,1"
|
|
bitfld.long 0x00 19. " [3] ,SPISIMO pin 3 data in" "0,1"
|
|
bitfld.long 0x00 18. " [2] ,SPISIMO pin 2 data in" "0,1"
|
|
bitfld.long 0x00 17. " [1] ,SPISIMO pin 1 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " [0] ,SPISIMO pin 0 data in" "0,1"
|
|
bitfld.long 0x00 11. " SOMIDIN0 ,SPISOMI pin 0 data in" "0,1"
|
|
bitfld.long 0x00 10. " SIMODIN0 ,SPISIMO pin 0 data in" "0,1"
|
|
bitfld.long 0x00 9. " CLKDIN ,Clock data in" "0,1"
|
|
bitfld.long 0x00 8. " ENADIN ,SPIENA data in" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " SCSDIN[7] ,SPISCS pin 7 data in" "0,1"
|
|
bitfld.long 0x00 6. " [6] ,SPISCS pin 6 data in" "0,1"
|
|
bitfld.long 0x00 5. " [5] ,SPISCS pin 5 data in" "0,1"
|
|
bitfld.long 0x00 4. " [4] ,SPISCS pin 4 data in" "0,1"
|
|
bitfld.long 0x00 3. " [3] ,SPISCS pin 3 data in" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,SPISCS pin 2 data in" "0,1"
|
|
bitfld.long 0x00 1. " [1] ,SPISCS pin 1 data in" "0,1"
|
|
bitfld.long 0x00 0. " [0] ,SPISCS pin 0 data in" "0,1"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "SPIPC3,SPI Pin Control Register 3"
|
|
bitfld.long 0x00 31. " SOMIDOUT[7] ,SPISOMI pin 7 data out write" "0,1"
|
|
bitfld.long 0x00 30. " [6] ,SPISOMI pin 6 data out write" "0,1"
|
|
bitfld.long 0x00 29. " [5] ,SPISOMI pin 5 data out write" "0,1"
|
|
bitfld.long 0x00 28. " [4] ,SPISOMI pin 4 data out write" "0,1"
|
|
bitfld.long 0x00 27. " [3] ,SPISOMI pin 3 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. " [2] ,SPISOMI pin 2 data out write" "0,1"
|
|
bitfld.long 0x00 25. " [1] ,SPISOMI pin 1 data out write" "0,1"
|
|
bitfld.long 0x00 24. " [0] ,SPISOMI pin 0 data out write" "0,1"
|
|
bitfld.long 0x00 23. " SIMODOUT[7] ,SPISIMO pin 7 data out write" "0,1"
|
|
bitfld.long 0x00 22. " [6] ,SPISIMO pin 6 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. " [5] ,SPISIMO pin 5 data out write" "0,1"
|
|
bitfld.long 0x00 20. " [4] ,SPISIMO pin 4 data out write" "0,1"
|
|
bitfld.long 0x00 19. " [3] ,SPISIMO pin 3 data out write" "0,1"
|
|
bitfld.long 0x00 18. " [2] ,SPISIMO pin 2 data out write" "0,1"
|
|
bitfld.long 0x00 17. " [1] ,SPISIMO pin 1 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " [0] ,SPISIMO pin 0 data out write" "0,1"
|
|
bitfld.long 0x00 11. " SOMIDOUT0 ,SPISOMI pin 0 data out write" "0,1"
|
|
bitfld.long 0x00 10. " SIMODOUT0 ,SPISIMO pin 0 data out write" "0,1"
|
|
bitfld.long 0x00 9. " CLKDOUT ,SPI clock data out write" "0,1"
|
|
bitfld.long 0x00 8. " ENADOUT ,SPIENA data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " SCSDOUT[7] ,SPISCS pin 7 data out write" "0,1"
|
|
bitfld.long 0x00 6. " [6] ,SPISCS pin 6 data out write" "0,1"
|
|
bitfld.long 0x00 5. " [5] ,SPISCS pin 5 data out write" "0,1"
|
|
bitfld.long 0x00 4. " [4] ,SPISCS pin 4 data out write" "0,1"
|
|
bitfld.long 0x00 3. " [3] ,SPISCS pin 3 data out write" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,SPISCS pin 2 data out write" "0,1"
|
|
bitfld.long 0x00 1. " [1] ,SPISCS pin 1 data out write" "0,1"
|
|
bitfld.long 0x00 0. " [0] ,SPISCS pin 0 data out write" "0,1"
|
|
line.long 0x04 "SPIPC4,SPI Pin Control Register 4"
|
|
bitfld.long 0x04 31. " SOMISET[7] ,SPISOMI pin 7 data out set" "No effect,Set"
|
|
bitfld.long 0x04 30. " [6] ,SPISOMI pin 6 data out set" "No effect,Set"
|
|
bitfld.long 0x04 29. " [5] ,SPISOMI pin 5 data out set" "No effect,Set"
|
|
bitfld.long 0x04 28. " [4] ,SPISOMI pin 4 data out set" "No effect,Set"
|
|
bitfld.long 0x04 27. " [3] ,SPISOMI pin 3 data out set" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x04 26. " [2] ,SPISOMI pin 2 data out set" "No effect,Set"
|
|
bitfld.long 0x04 25. " [1] ,SPISOMI pin 1 data out set" "No effect,Set"
|
|
bitfld.long 0x04 24. " [0] ,SPISOMI pin 0 data out set" "No effect,Set"
|
|
bitfld.long 0x04 23. " SIMOSET[7] ,SPISIMO pin 7 data out set" "No effect,Set"
|
|
bitfld.long 0x04 22. " [6] ,SPISIMO pin 6 data out set" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x04 21. " [5] ,SPISIMO pin 5 data out set" "No effect,Set"
|
|
bitfld.long 0x04 20. " [4] ,SPISIMO pin 4 data out set" "No effect,Set"
|
|
bitfld.long 0x04 19. " [3] ,SPISIMO pin 3 data out set" "No effect,Set"
|
|
bitfld.long 0x04 18. " [2] ,SPISIMO pin 2 data out set" "No effect,Set"
|
|
bitfld.long 0x04 17. " [1] ,SPISIMO pin 1 data out set" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x04 16. " [0] ,SPISIMO pin 0 data out set" "No effect,Set"
|
|
bitfld.long 0x04 11. " SOMISET0 ,SPISOMI pin 0 data out set" "No effect,Set"
|
|
bitfld.long 0x04 10. " SIMOSET0 ,SPISIMO pin 0 data out set" "No effect,Set"
|
|
bitfld.long 0x04 9. " CLKSET ,SPICLK data out set" "No effect,Set"
|
|
bitfld.long 0x04 8. " ENASET ,SPIENA data out set" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x04 7. " SCSSET[7] ,SPISCS pin 7 data out set" "No effect,Set"
|
|
bitfld.long 0x04 6. " [6] ,SPISCS pin 6 data out set" "No effect,Set"
|
|
bitfld.long 0x04 5. " [5] ,SPISCS pin 5 data out set" "No effect,Set"
|
|
bitfld.long 0x04 4. " [4] ,SPISCS pin 4 data out set" "No effect,Set"
|
|
bitfld.long 0x04 3. " [3] ,SPISCS pin 3 data out set" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,SPISCS pin 2 data out set" "No effect,Set"
|
|
bitfld.long 0x04 1. " [1] ,SPISCS pin 1 data out set" "No effect,Set"
|
|
bitfld.long 0x04 0. " [0] ,SPISCS pin 0 data out set" "No effect,Set"
|
|
line.long 0x08 "SPIPC5,SPI Pin Control Register 5"
|
|
bitfld.long 0x08 31. " SOMICLR[7] ,SPISOMI pin 7 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 30. " [6] ,SPISOMI pin 6 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 29. " [5] ,SPISOMI pin 5 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 28. " [4] ,SPISOMI pin 4 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 27. " [3] ,SPISOMI pin 3 data out clear" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x08 26. " [2] ,SPISOMI pin 2 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 25. " [1] ,SPISOMI pin 1 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 24. " [0] ,SPISOMI pin 0 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 23. " SIMOCLR[7] ,SPISIMO pin 7 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 22. " [6] ,SPISIMO pin 6 data out clear" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x08 21. " [5] ,SPISIMO pin 5 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 20. " [4] ,SPISIMO pin 4 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 19. " [3] ,SPISIMO pin 3 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 18. " [2] ,SPISIMO pin 2 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 17. " [1] ,SPISIMO pin 1 data out clear" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x08 16. " [0] ,SPISIMO pin 0 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 11. " SOMICLR0 ,SPISOMI pin 0 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 10. " SIMOCLR0 ,SPISIMO pin 0 data out clear" "No effect,Clear"
|
|
bitfld.long 0x08 9. " CLKCLR ,SPICLK data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 8. " ENACLR ,SPIENA data out clear" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x08 7. " SCSCLR[7] ,SPISCS pin 7 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 6. " [6] ,SPISCS pin 6 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 5. " [5] ,SPISCS pin 5 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 4. " [4] ,SPISCS pin 4 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 3. " [3] ,SPISCS pin 3 data out clear" "No effect,Cleared"
|
|
newline
|
|
bitfld.long 0x08 2. " [2] ,SPISCS pin 2 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 1. " [1] ,SPISCS pin 1 data out clear" "No effect,Cleared"
|
|
bitfld.long 0x08 0. " [0] ,SPISCS pin 0 data out clear" "No effect,Cleared"
|
|
line.long 0x0C "SPIPC6,SPI Pin Control Register 6"
|
|
bitfld.long 0x0C 31. " SOMIPDR[7] ,SPISOMI pin 7 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " [6] ,SPISOMI pin 6 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " [5] ,SPISOMI pin 5 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " [4] ,SPISOMI pin 4 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 27. " [3] ,SPISOMI pin 3 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 26. " [2] ,SPISOMI pin 2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " [1] ,SPISOMI pin 1 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " [0] ,SPISOMI pin 0 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 23. " SIMOPDR[7] ,SPISIMO pin 7 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " [6] ,SPISIMO pin 6 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 21. " [5] ,SPISIMO pin 5 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " [4] ,SPISIMO pin 4 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 19. " [3] ,SPISIMO pin 3 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " [2] ,SPISIMO pin 2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " [1] ,SPISIMO pin 1 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 16. " [0] ,SPISIMO pin 0 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " SOMIPDR0 ,SPISOMI pin 0 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " SIMOPDR0 ,SPISIMO pin 0 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " CLKPDR ,SPI clock open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " ENAPDR ,SPIENA open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 7. " SCSPDR[7] ,SPISCS pin 7 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " [6] ,SPISCS pin 6 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " [5] ,SPISCS pin 5 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " [4] ,SPISCS pin 4 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " [3] ,SPISCS pin 3 open drain enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 2. " [2] ,SPISCS pin 2 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " [1] ,SPISCS pin 1 open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " [0] ,SPISCS pin 0 open drain enable" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SPIDAT0,SPI Transmit Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI transmit data"
|
|
if (((per.l(ad:0xFFF7F600+0x04))&0x03)==0x03)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SPIDAT1,Transmit Data Register 1"
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
newline
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SPIDAT1,Transmit Data Register 1"
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
newline
|
|
endif
|
|
width 18.
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SPIBUF,SPI Receive Buffer Register"
|
|
in
|
|
newline
|
|
if (((per.l(ad:0xFFF7F600+0x04))&0x03)==0x03)
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SPIEMU,SPI Emulation Register"
|
|
bitfld.long 0x00 31. " RXEMPTY ,Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR ,Receive data buffer overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 29. " TXFULL ,Transmit data buffer full" "Empty,Full"
|
|
bitfld.long 0x00 28. " BITERR ,Mismatch of internal transmit data and transmitted data" "No error,Error"
|
|
bitfld.long 0x00 27. " DESYNC ,De-synchronization of slave device" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " PARITYERR ,Calculated parity differs from received parity bit" "No error,Error"
|
|
bitfld.long 0x00 25. " TIMEOUT ,Time-out due to non-activation of ENA pin" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " DLENERR ,Data length error flag" "No error,Error"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " EMU_RXDATA ,SPI receive data"
|
|
group.long 0x48++0x07
|
|
line.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip select active to transmit start delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit end to chip select inactive delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit data finished to ENA pin inactive time out"
|
|
hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip select active to ENA signal active time out"
|
|
line.long 0x04 "SPIDEF,SPI Default Chip Select Register"
|
|
bitfld.long 0x04 7. " CSDEF[7] ,Chip select default pattern bit 7" "0,1"
|
|
bitfld.long 0x04 6. " [6] ,Chip select default pattern bit 6" "0,1"
|
|
bitfld.long 0x04 5. " [5] ,Chip select default pattern bit 5" "0,1"
|
|
bitfld.long 0x04 4. " [4] ,Chip select default pattern bit 4" "0,1"
|
|
bitfld.long 0x04 3. " [3] ,Chip select default pattern bit 3" "0,1"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Chip select default pattern bit 2" "0,1"
|
|
bitfld.long 0x04 1. " [1] ,Chip select default pattern bit 1" "0,1"
|
|
bitfld.long 0x04 0. " [0] ,Chip select default pattern bit 0" "0,1"
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SPIEMU,SPI Emulation Register"
|
|
bitfld.long 0x00 31. " RXEMPTY ,Receive data buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 30. " RXOVR ,Receive data buffer overrun" "No overrun,Overrun"
|
|
bitfld.long 0x00 29. " TXFULL ,Transmit data buffer full" "Empty,Full"
|
|
bitfld.long 0x00 28. " BITERR ,Mismatch of internal transmit data and transmitted data" "No error,Error"
|
|
bitfld.long 0x00 26. " PARITYERR ,Calculated parity differs from received parity bit" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 24. " DLENERR ,Data Length Error flag" "No error,Error"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " EMU_RXDATA ,SPI receive data"
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "SPIDELAY,SPI Delay Register"
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "SPIDEF,SPI Default Chip Select Register"
|
|
endif
|
|
if (((per.l(ad:0xFFF7F600+0x04))&0x03)==0x03)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SPIFMT0,SPI Data Format Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
|
|
bitfld.long 0x00 23. " PARPOL ,Parity polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WAITENA ,The master waits for the ENA signal from slave for data format 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SHIFTDIR ,Shift direction for data format 0" "MSB,LSB"
|
|
newline
|
|
bitfld.long 0x00 19. " HDUPLEX_ENA ,Half Duplex transfer mode enable for data format 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
bitfld.long 0x00 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
|
|
bitfld.long 0x00 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
|
|
newline
|
|
bitfld.long 0x00 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SPIFMT1,SPI Data Format Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
|
|
bitfld.long 0x00 23. " PARPOL ,Parity polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WAITENA ,The master waits for the ENA signal from slave for data format 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SHIFTDIR ,Shift direction for data format 1" "MSB,LSB"
|
|
newline
|
|
bitfld.long 0x00 19. " HDUPLEX_ENA ,Half Duplex transfer mode enable for data format 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
bitfld.long 0x00 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
|
|
bitfld.long 0x00 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
|
|
newline
|
|
bitfld.long 0x00 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SPIFMT2,SPI Data Format Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
|
|
bitfld.long 0x00 23. " PARPOL ,Parity polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WAITENA ,The master waits for the ENA signal from slave for data format 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SHIFTDIR ,Shift direction for data format 2" "MSB,LSB"
|
|
newline
|
|
bitfld.long 0x00 19. " HDUPLEX_ENA ,Half Duplex transfer mode enable for data format 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
bitfld.long 0x00 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
|
|
bitfld.long 0x00 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
|
|
newline
|
|
bitfld.long 0x00 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SPIFMT3,SPI Data Format Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
|
|
bitfld.long 0x00 23. " PARPOL ,Parity polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " WAITENA ,The master waits for the ENA signal from slave for data format 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SHIFTDIR ,Shift direction for data format 3" "MSB,LSB"
|
|
newline
|
|
bitfld.long 0x00 19. " HDUPLEX_ENA ,Half Duplex transfer mode enable for data format 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
bitfld.long 0x00 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
|
|
bitfld.long 0x00 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
|
|
newline
|
|
bitfld.long 0x00 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SPIFMT0,SPI Data Format Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 0"
|
|
bitfld.long 0x00 23. " PARPOL ,Parity polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITYENA ,Parity enable for data format 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SHIFTDIR ,Shift direction for data format 0" "MSB,LSB"
|
|
bitfld.long 0x00 19. " HDUPLEX_ENA ,Half Duplex transfer mode enable for data format 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
bitfld.long 0x00 17. " POLARITY ,SPI data format 0 clock polarity" "Low,High"
|
|
bitfld.long 0x00 16. " PHASE ,SPI data format 0 clock delay" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE ,SPI data format 0 prescaler"
|
|
bitfld.long 0x00 0.--4. " CHARLEN ,SPI data format 0 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SPIFMT1,SPI Data Format Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 1"
|
|
bitfld.long 0x00 23. " PARPOL ,Parity polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITYENA ,Parity enable for data format 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SHIFTDIR ,Shift direction for data format 1" "MSB,LSB"
|
|
bitfld.long 0x00 19. " HDUPLEX_ENA ,Half Duplex transfer mode enable for data format 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
bitfld.long 0x00 17. " POLARITY ,SPI data format 1 clock polarity" "Low,High"
|
|
bitfld.long 0x00 16. " PHASE ,SPI data format 1 clock delay" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE ,SPI data format 1 prescaler"
|
|
bitfld.long 0x00 0.--4. " CHARLEN ,SPI data format 1 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SPIFMT2,SPI Data Format Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 2"
|
|
bitfld.long 0x00 23. " PARPOL ,Parity polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITYENA ,Parity enable for data format 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SHIFTDIR ,Shift direction for data format 2" "MSB,LSB"
|
|
bitfld.long 0x00 19. " HDUPLEX_ENA ,Half Duplex transfer mode enable for data format 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
bitfld.long 0x00 17. " POLARITY ,SPI data format 2 clock polarity" "Low,High"
|
|
bitfld.long 0x00 16. " PHASE ,SPI data format 2 clock delay" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE ,SPI data format 2 prescaler"
|
|
bitfld.long 0x00 0.--4. " CHARLEN ,SPI data format 2 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SPIFMT3,SPI Data Format Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " WDELAY ,Delay in between transmissions for data format 3"
|
|
bitfld.long 0x00 23. " PARPOL ,Parity polarity" "Even,Odd"
|
|
bitfld.long 0x00 22. " PARITYENA ,Parity enable for data format 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SHIFTDIR ,Shift direction for data format 3" "MSB,LSB"
|
|
bitfld.long 0x00 19. " HDUPLEX_ENA ,Half Duplex transfer mode enable for data format 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " DISCSTIMERS ,Disable chip-select timers for this format" "No,Yes"
|
|
bitfld.long 0x00 17. " POLARITY ,SPI data format 3 clock polarity" "Low,High"
|
|
bitfld.long 0x00 16. " PHASE ,SPI data format 3 clock delay" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCALE ,SPI data format 3 prescaler"
|
|
bitfld.long 0x00 0.--4. " CHARLEN ,SPI data format 3 data-word length" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
endif
|
|
newline
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0/MibSPI Transfer Group Interrupt Vector Register 0"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "TGINTVECT1,SPI Interrupt Vector Register 1/MibSPI Transfer Group Interrupt Vector Register 1"
|
|
in
|
|
newline
|
|
group.long 0x68++0x0B
|
|
line.long 0x00 "SPIPC9,SPI Pin Control Register 9"
|
|
bitfld.long 0x00 31. " SOMISRS7[7] ,SPISOMI pin 7 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 30. " [6] ,SPISOMI pin 6 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 29. " [5] ,SPISOMI pin 5 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 28. " [4] ,SPISOMI pin 4 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 27. " [3] ,SPISOMI pin 3 slew rate" "Normal,Slow"
|
|
newline
|
|
bitfld.long 0x00 26. " [2] ,SPISOMI pin 2 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 25. " [1] ,SPISOMI pin 1 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 24. " [0] ,SPISOMI pin 0 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 23. " SIMOSRS7[7] ,SPISIMO pin 7 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 22. " [6] ,SPISIMO pin 6 slew rate" "Normal,Slow"
|
|
newline
|
|
bitfld.long 0x00 21. " [5] ,SPISIMO pin 5 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 20. " [4] ,SPISIMO pin 4 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 19. " [3] ,SPISIMO pin 3 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 18. " [2] ,SPISIMO pin 2 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 17. " [1] ,SPISIMO pin 1 slew rate" "Normal,Slow"
|
|
newline
|
|
bitfld.long 0x00 16. " [0] ,SPISIMO pin 0 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 11. " SOMISRS0 ,SPISOMI pin 0 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 10. " SIMOSRS0 ,SPISIMO pin 0 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 9. " CLKSRS ,SPICLK control slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 8. " ENASRS ,SPIENA control slew rate" "Fast,Slow"
|
|
newline
|
|
bitfld.long 0x00 7. " SCSSRS[7] ,SPISCS pin 7 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 6. " [6] ,SPISCS pin 6 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 5. " [5] ,SPISCS pin 5 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 4. " [4] ,SPISCS pin 4 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 3. " [3] ,SPISCS pin 3 slew rate" "Normal,Slow"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,SPISCS pin 2 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 1. " [1] ,SPISCS pin 1 slew rate" "Normal,Slow"
|
|
bitfld.long 0x00 0. " [0] ,SPISCS pin 0 slew rate" "Normal,Slow"
|
|
line.long 0x04 "SPIPMCTRL,SPI Parallel/Modulo Mode Control Register"
|
|
bitfld.long 0x04 30. " HSM_MODE3 ,Data format 3 High Speed Modulo Mode control" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " MODCLKPOL3 ,Data format 3 modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x04 26.--28. " MMODE3 ,Data format 3 SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x04 24.--25. " PMODE3 ,Data format 3 parallel mode data lines" "1,2,4,8"
|
|
bitfld.long 0x04 22. " HSM_MODE2 ,Data format 2 High Speed Modulo Mode control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 21. " MODCLKPOL2 ,Data format 2 modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x04 18.--20. " MMODE2 ,Data format 2 SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x04 16.--17. " PMODE2 ,Data format 2 parallel mode data lines" "1,2,4,8"
|
|
bitfld.long 0x04 14. " HSM_MODE1 ,Data format 1 High Speed Modulo Mode control" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " MODCLKPOL1 ,Data format 1 modulo mode SPICLK polarity" "Normal,Inverted"
|
|
newline
|
|
bitfld.long 0x04 10.--12. " MMODE1 ,Data format 1 SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
|
|
bitfld.long 0x04 8.--9. " PMODE1 ,Data format 1 parallel mode data lines" "1,2,4,8"
|
|
bitfld.long 0x04 6. " HSM_MODE0 ,Data format 0 High Speed Modulo Mode control" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " MODCLKPOL0 ,Data format 0 modulo mode SPICLK polarity" "Normal,Inverted"
|
|
bitfld.long 0x04 2.--4. " MMODE0 ,Data format 0 SPI/MibSPI data lines" "1,2,3,4,5,6,?..."
|
|
newline
|
|
bitfld.long 0x04 0.--1. " PMODE0 ,Data format 0 parallel mode data lines" "1,2,4,8"
|
|
line.long 0x08 "MIBSPIE,MibSPI Enable Register"
|
|
bitfld.long 0x08 16. " RXRAMACCESS ,Receive RAM access control" "Not writeable,Writeable"
|
|
bitfld.long 0x08 8.--11. " EXTENDED_BUF_ENA ,Enables the support for 256 buffers" ",,,,,128,,,,,256,?..."
|
|
bitfld.long 0x08 0. " MSPIENA ,Multi-buffer mode enable" "Disabled,Enabled"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TGITENST_SET/CLR,MibSPI Transfer Group Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTENRDY[15] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [14] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [13] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [12] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [11] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [10] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [9] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [8] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [7] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [6] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [5] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [4] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [3] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [2] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [1] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [0] ,TG interrupt set (enable) when transfer finished" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTENSUS[15] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,TG interrupt set (enabled) when transfer suspended" "Disabled,Enabled"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TGITLVST_SET/CLR,MibSPI Transfer Group Interrupt Level Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " SETINTLVLRDY[15] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [14] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [13] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [12] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [11] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [10] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [9] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [8] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [7] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [6] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [5] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [4] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [3] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [2] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [1] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [0] ,Transfer group completed interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " SETINTLVLSUS[15] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Transfer group suspended interrupt level set" "INT0,INT1"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TGINTFLG,Transfer Group Interrupt Flag Register"
|
|
eventfld.long 0x00 31. " INTFLGRDY[15] ,Transfer group 15 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 30. " [14] ,Transfer group 14 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 29. " [13] ,Transfer group 13 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 28. " [12] ,Transfer group 12 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 27. " [11] ,Transfer group 11 interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 26. " [10] ,Transfer group 10 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 25. " [9] ,Transfer group 9 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 24. " [8] ,Transfer group 8 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 23. " [7] ,Transfer group 7 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 22. " [6] ,Transfer group 6 interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 21. " [5] ,Transfer group 5 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 20. " [4] ,Transfer group 4 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 19. " [3] ,Transfer group 3 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 18. " [2] ,Transfer group 2 interrupt flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 17. " [1] ,Transfer group 1 interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x00 16. " [0] ,Transfer group 0 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 15. " INTFLGSUS[15] ,Transfer group 15 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 14. " [14] ,Transfer group 14 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 13. " [13] ,Transfer group 13 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 12. " [12] ,Transfer group 12 interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
rbitfld.long 0x00 11. " [11] ,Transfer group 11 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 10. " [10] ,Transfer group 10 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 9. " [9] ,Transfer group 9 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 8. " [8] ,Transfer group 8 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 7. " [7] ,Transfer group 7 interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
rbitfld.long 0x00 6. " [6] ,Transfer group 6 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 5. " [5] ,Transfer group 5 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 4. " [4] ,Transfer group 4 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 3. " [3] ,Transfer group 3 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 2. " [2] ,Transfer group 2 interrupt flag" "Not occurred,Occurred"
|
|
newline
|
|
rbitfld.long 0x00 1. " [1] ,Transfer group 1 interrupt flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 0. " [0] ,Transfer group 0 interrupt flag" "Not occurred,Occurred"
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "TICKCNT,Tick Count Register"
|
|
bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RELOAD ,Re-load the tick counter" "No effect,Reload"
|
|
bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "Format 0,Format 1,Format 2,Format 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for the tick counter"
|
|
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer Register"
|
|
rbitfld.long 0x04 24.--28. " TGINSERVICE ,The transfer group currently being serviced by the sequencer" "No TG,TG0,TG1,TG2,TG3,TG4,TG5,TG6,TG7,TG8,TG9,TG10,TG11,TG12,TG13,TG14,TG15,?..."
|
|
hexmask.long.byte 0x04 8.--15. 0x01 " LPEND ,Last TG end pointer"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TG0CTRL,MibSPI Transfer Group Control Register 0"
|
|
bitfld.long 0x00 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST ,TG pointer reset mode" "No reset,Reset"
|
|
rbitfld.long 0x00 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TG1CTRL,MibSPI Transfer Group Control Register 1"
|
|
bitfld.long 0x00 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST ,TG pointer reset mode" "No reset,Reset"
|
|
rbitfld.long 0x00 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TG2CTRL,MibSPI Transfer Group Control Register 2"
|
|
bitfld.long 0x00 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST ,TG pointer reset mode" "No reset,Reset"
|
|
rbitfld.long 0x00 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "TG3CTRL,MibSPI Transfer Group Control Register 3"
|
|
bitfld.long 0x00 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST ,TG pointer reset mode" "No reset,Reset"
|
|
rbitfld.long 0x00 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "TG4CTRL,MibSPI Transfer Group Control Register 4"
|
|
bitfld.long 0x00 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST ,TG pointer reset mode" "No reset,Reset"
|
|
rbitfld.long 0x00 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "TG5CTRL,MibSPI Transfer Group Control Register 5"
|
|
bitfld.long 0x00 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST ,TG pointer reset mode" "No reset,Reset"
|
|
rbitfld.long 0x00 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TG6CTRL,MibSPI Transfer Group Control Register 6"
|
|
bitfld.long 0x00 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST ,TG pointer reset mode" "No reset,Reset"
|
|
rbitfld.long 0x00 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "TG7CTRL,MibSPI Transfer Group Control Register 7"
|
|
bitfld.long 0x00 31. " TGENA ,TG enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " ONESHOT ,Single transfer for TG" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PRST ,TG pointer reset mode" "No reset,Reset"
|
|
rbitfld.long 0x00 28. " TGTD ,TG triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 20.--23. " TRGEVT ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High active,Low-active,Always,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " TRIGSRC ,Trigger source" "Disabled,EXT[0],EXT[1],EXT[2],EXT[3],EXT[4],EXT[5],EXT[6],EXT[7],EXT[8],EXT[9,EXT[10,EXT[11,EXT[12,EXT[13],TICK"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " PSTART ,TG start address"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " PCURRENT ,Pointer to current buffer"
|
|
if (((per.l(ad:0xFFF7F600+0x04))&0x03)==0x03)
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x00 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP ,Number of the physical DMA request line that is connected to the receive path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP ,Number of the physical DMA Request line that is connected to the transmit path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " NOBRK ,Non-interleaved DMA block transfer" "Interleaved,Non-interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rbitfld.long 0x00 7. " BUFID7 ,Extended bit of BUFID1" "0,1"
|
|
rbitfld.long 0x00 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x00 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP ,Number of the physical DMA request line that is connected to the receive path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP ,Number of the physical DMA Request line that is connected to the transmit path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " NOBRK ,Non-interleaved DMA block transfer" "Interleaved,Non-interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rbitfld.long 0x00 7. " BUFID7 ,Extended bit of BUFID2" "0,1"
|
|
rbitfld.long 0x00 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x00 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP ,Number of the physical DMA request line that is connected to the receive path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP ,Number of the physical DMA Request line that is connected to the transmit path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " NOBRK ,Non-interleaved DMA block transfer" "Interleaved,Non-interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rbitfld.long 0x00 7. " BUFID7 ,Extended bit of BUFID3" "0,1"
|
|
rbitfld.long 0x00 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x00 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP ,Number of the physical DMA request line that is connected to the receive path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP ,Number of the physical DMA Request line that is connected to the transmit path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " NOBRK ,Non-interleaved DMA block transfer" "Interleaved,Non-interleaved"
|
|
bitfld.long 0x00 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rbitfld.long 0x00 7. " BUFID7 ,Extended bit of BUFID4" "0,1"
|
|
rbitfld.long 0x00 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x00 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP ,Number of the physical DMA request line that is connected to the receive path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP ,Number of the physical DMA Request line that is connected to the transmit path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rbitfld.long 0x00 7. " BUFID7 ,Extended bit of BUFID0" "0,1"
|
|
rbitfld.long 0x00 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
rbitfld.long 0x00 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "DMA1CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x00 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP ,Number of the physical DMA request line that is connected to the receive path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP ,Number of the physical DMA Request line that is connected to the transmit path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rbitfld.long 0x00 7. " BUFID7 ,Extended bit of BUFID1" "0,1"
|
|
rbitfld.long 0x00 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
rbitfld.long 0x00 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DMA2CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x00 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP ,Number of the physical DMA request line that is connected to the receive path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP ,Number of the physical DMA Request line that is connected to the transmit path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rbitfld.long 0x00 7. " BUFID7 ,Extended bit of BUFID2" "0,1"
|
|
rbitfld.long 0x00 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
rbitfld.long 0x00 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "DMA3CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x00 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP ,Number of the physical DMA request line that is connected to the receive path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP ,Number of the physical DMA Request line that is connected to the transmit path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rbitfld.long 0x00 7. " BUFID7 ,Extended bit of BUFID3" "0,1"
|
|
rbitfld.long 0x00 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
rbitfld.long 0x00 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "DMA4CTRL,MibSPI DMA Channel Control Register 1"
|
|
bitfld.long 0x00 31. " ONESHOT ,Auto-disable of DMA channel after ICOUNT+1 transfers" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 24.--30. 1. " BUFID ,Buffer utilized for DMA transfer"
|
|
bitfld.long 0x00 20.--23. " RXDMA_MAP ,Number of the physical DMA request line that is connected to the receive path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " TXDMA_MAP ,Number of the physical DMA Request line that is connected to the transmit path of the MibSPI DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " RXDMAENA ,Receive data DMA channel enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " TXDMAENA ,Transmit data DMA channel enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--12. " ICOUNT ,Initial count of DMA transfers" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
rbitfld.long 0x00 7. " BUFID7 ,Extended bit of BUFID4" "0,1"
|
|
rbitfld.long 0x00 6. " COUNTBIT17 ,17th bit of the COUNT field of DMAxCOUNT register" "0,1"
|
|
rbitfld.long 0x00 0.--5. " COUNT ,Actual number of remaining DMA transfers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "ICOUNT0,MibSPI DMA0COUNT Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT0 ,The actual number of remaining DMA transfers"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "ICOUNT1,MibSPI DMA1COUNT Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT1 ,The actual number of remaining DMA transfers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "ICOUNT2,MibSPI DMA2COUNT Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT2 ,The actual number of remaining DMA transfers"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "ICOUNT3,MibSPI DMA3COUNT Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT3 ,The actual number of remaining DMA transfers"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "ICOUNT4,MibSPI DMA4COUNT Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNT4 ,The actual number of remaining DMA transfers"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DMACNTLEN,DMA Large Count Register"
|
|
bitfld.long 0x00 0. " LARGE_COUNT ,ICOUNT value modified by writes to the DMAxCTRL" "Disabled,Enabled"
|
|
group.long 0x120++0x07
|
|
line.long 0x00 "PAR_ECC_CTRL,Parity/ECC Control Register"
|
|
bitfld.long 0x00 24.--27. " SBE_EVT_EN ,Single bit error event enable" ",,,,,Disabled,,,,,Enabled,?..."
|
|
bitfld.long 0x00 16.--19. " EDAC_MODE ,Error detection and correction mode" ",,,,,Disabled,,,,,Enabled,?..."
|
|
bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x04 "PAR_ECC_STAT,Parity/ECC Status Register"
|
|
eventfld.long 0x04 9. " SBE_FLG1 ,Single bit error in RXRAM" "No error,Error"
|
|
eventfld.long 0x04 8. " SBE_FLG0 ,Single bit error in TXRAM" "No error,Error"
|
|
eventfld.long 0x04 1. " EDFLG1 ,Uncorrectable parity or double bit ECC error" "No error,Error"
|
|
eventfld.long 0x04 0. " EDFLG0 ,Uncorrectable parity or double bit ECC error" "No error,Error"
|
|
newline
|
|
width 17.
|
|
hgroup.long 0x128++0x03
|
|
hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x12C++0x03
|
|
hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register"
|
|
in
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
|
|
in
|
|
newline
|
|
width 13.
|
|
newline
|
|
if (((per.l(ad:0xFFF7F600+0x134))&0x02)==0x02)&&(((per.l(ad:0xFFF7F600+0x134))&0xF00)==0xA00)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
eventfld.long 0x00 24. " SCSFAILFLG ,Failure on SPISCS pin compare during analog loopback" "Not failed,Failed"
|
|
bitfld.long 0x00 20. " CTRLBITERR ,Controls inducing of BITERR during IO loopback test mode" "No effect,Flipped"
|
|
bitfld.long 0x00 19. " CTRLDESYNC ,Controls inducing of the desync error during IO loopback test mode" "No effect,Forced 0"
|
|
bitfld.long 0x00 18. " CTRLPARERR ,Controls inducing of parity errors during IO loopback test mode" "No effect,Flipped"
|
|
bitfld.long 0x00 17. " CTRLTIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No effect,Forced 1"
|
|
bitfld.long 0x00 16. " CTRLDLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No effect,Forced 1"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module IO loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "SPISCS[0],SPISCS[1],SPISCS[2],SPISCS[3],SPISCS[4],SPISCS[5],SPISCS[6],SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Injection of an error on the SPISCS[3:0] pins enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPBKTYPE ,Module IO loopback type" "Digital,Analog"
|
|
newline
|
|
bitfld.long 0x00 0. " RXPENA ,Analog loopback through the receive pin enable" "Disabled,Enabled"
|
|
newline
|
|
elif (((per.l(ad:0xFFF7F600+0x134))&0x02)==0x00)&&(((per.l(ad:0xFFF7F600+0x134))&0xF00)==0xA00)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
bitfld.long 0x00 20. " CTRLBITERR ,Controls inducing of BITERR during IO loopback test mode" "No effect,Flipped"
|
|
bitfld.long 0x00 19. " CTRLDESYNC ,Controls inducing of the desync error during IO loopback test mode" "No effect,Forced 0"
|
|
bitfld.long 0x00 18. " CTRLPARERR ,Controls inducing of parity errors during IO loopback test mode" "No effect,Flipped"
|
|
bitfld.long 0x00 17. " CTRLTIMEOUT ,Controls inducing of the timeout error during I/O loopbacK test mode" "No effect,Forced 1"
|
|
bitfld.long 0x00 16. " CTRLDLENERR ,Controls inducing of the data length error during I/O loopback test mode" "No effect,Forced 1"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module IO loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "SPISCS[0],SPISCS[1],SPISCS[2],SPISCS[3],SPISCS[4],SPISCS[5],SPISCS[6],SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Injection of an error on the SPISCS[3:0] pins enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPBKTYPE ,Module IO loopback type" "Digital,Analog"
|
|
elif (((per.l(ad:0xFFF7F600+0x134))&0x02)==0x02)&&(((per.l(ad:0xFFF7F600+0x134))&0xF00)!=0xA00)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module IO loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "SPISCS[0],SPISCS[1],SPISCS[2],SPISCS[3],SPISCS[4],SPISCS[5],SPISCS[6],SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Injection of an error on the SPISCS[3:0] pins enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPBKTYPE ,Module IO loopback type" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXPENA ,Analog loopback through the receive pin enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IOLPBKTSTCR,SPI IO Loopback Test Control Register"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module IO loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 3.--5. " ERRSCSPIN ,Inject error on chip-select pin number" "SPISCS[0],SPISCS[1],SPISCS[2],SPISCS[3],SPISCS[4],SPISCS[5],SPISCS[6],SPISCS[7]"
|
|
bitfld.long 0x00 2. " CTRLSCSPINERR ,Injection of an error on the SPISCS[3:0] pins enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPBKTYPE ,Module IO loopback type" "Digital,Analog"
|
|
endif
|
|
width 21.
|
|
group.long 0x138++0x0B
|
|
line.long 0x00 "EXTENDED_PRESCALE_1,SPI Extended Prescale Register 1"
|
|
hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 ,Extended Prescale value for SPIFMT1"
|
|
hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 ,Extended Prescale value for SPIFMT0"
|
|
line.long 0x04 "EXTENDED_PRESCALE_2,SPI Extended Prescale Register 2"
|
|
hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 ,Extended Prescale value for SPIFMT3"
|
|
hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 ,Extended Prescale value for SPIFMT2"
|
|
line.long 0x08 "ECCDIAG_CTRL,ECC Diagnostic Control Register"
|
|
bitfld.long 0x08 0.--3. " ECCDIAG_EN ,ECC Diagnostic mode Enable Key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
if (((per.l(ad:0xFFF7F600+0x140))&0x0F)==0x05)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "ECCDIAG_STAT,ECC Diagnostic Status Register"
|
|
eventfld.long 0x00 17. " DEFLG1 ,RXRAM double bit error" "No error,Error"
|
|
eventfld.long 0x00 16. " DEFLG0 ,TXRAM double bit error" "No error,Error"
|
|
eventfld.long 0x00 1. " SEFLG1 ,RXRAM single bit error" "No error,Error"
|
|
eventfld.long 0x00 0. " SEFLG0 ,TXRAM single bit error" "No error,Error"
|
|
newline
|
|
else
|
|
hgroup.long 0x144++0x03
|
|
hide.long 0x00 "ECCDIAG_STAT,ECC Diagnostic Status Register"
|
|
newline
|
|
endif
|
|
hgroup.long 0x148++0x03
|
|
hide.long 0x00 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
|
|
in
|
|
hgroup.long 0x14C++0x03
|
|
hide.long 0x00 "SBERRADDR0,Single Bit Error Address Register - TXRAM"
|
|
in
|
|
newline
|
|
rgroup.long 0x1FC++0x03
|
|
line.long 0x00 "SPIREV,SPI / MibSPI Revision ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Identification Scheme used to distinguish different ID schemes" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Indicates functionally equivalent module family"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major Revision number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Device specific implementation" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " MINOR ,Minor Revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Multi-Buffer RAM B"
|
|
base ad:0xFF0C0000
|
|
width 10.
|
|
tree "Multi-buffer RAM Transmit Data Registers"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TXRAM0,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "TXRAM1,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "TXRAM2,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TXRAM3,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TXRAM4,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TXRAM5,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TXRAM6,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TXRAM7,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TXRAM8,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TXRAM9,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TXRAM10,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TXRAM11,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TXRAM12,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TXRAM13,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TXRAM14,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TXRAM15,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TXRAM16,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TXRAM17,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TXRAM18,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TXRAM19,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TXRAM20,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TXRAM21,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TXRAM22,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TXRAM23,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TXRAM24,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TXRAM25,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TXRAM26,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TXRAM27,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TXRAM28,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TXRAM29,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TXRAM30,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TXRAM31,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TXRAM32,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "TXRAM33,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "TXRAM34,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "TXRAM35,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "TXRAM36,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "TXRAM37,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "TXRAM38,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "TXRAM39,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "TXRAM40,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "TXRAM41,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "TXRAM42,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "TXRAM43,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "TXRAM44,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "TXRAM45,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "TXRAM46,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "TXRAM47,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "TXRAM48,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TXRAM49,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "TXRAM50,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "TXRAM51,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "TXRAM52,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "TXRAM53,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "TXRAM54,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "TXRAM55,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "TXRAM56,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "TXRAM57,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "TXRAM58,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "TXRAM59,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "TXRAM60,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "TXRAM61,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "TXRAM62,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "TXRAM63,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "TXRAM64,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "TXRAM65,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "TXRAM66,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "TXRAM67,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "TXRAM68,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "TXRAM69,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "TXRAM70,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "TXRAM71,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "TXRAM72,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "TXRAM73,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "TXRAM74,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "TXRAM75,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "TXRAM76,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "TXRAM77,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "TXRAM78,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "TXRAM79,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "TXRAM80,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "TXRAM81,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "TXRAM82,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "TXRAM83,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "TXRAM84,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "TXRAM85,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "TXRAM86,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "TXRAM87,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "TXRAM88,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "TXRAM89,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "TXRAM90,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "TXRAM91,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "TXRAM92,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "TXRAM93,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "TXRAM94,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "TXRAM95,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "TXRAM96,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "TXRAM97,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "TXRAM98,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "TXRAM99,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "TXRAM100,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "TXRAM101,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "TXRAM102,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "TXRAM103,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TXRAM104,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "TXRAM105,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "TXRAM106,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "TXRAM107,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "TXRAM108,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "TXRAM109,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "TXRAM110,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "TXRAM111,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "TXRAM112,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "TXRAM113,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "TXRAM114,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "TXRAM115,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "TXRAM116,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "TXRAM117,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "TXRAM118,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "TXRAM119,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "TXRAM120,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "TXRAM121,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "TXRAM122,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "TXRAM123,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "TXRAM124,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "TXRAM125,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "TXRAM126,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "TXRAM127,Multi-buffer RAM Transmit Data Register"
|
|
bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect"
|
|
newline
|
|
bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active"
|
|
newline
|
|
bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number"
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data"
|
|
tree.end
|
|
tree "Multi-buffer RAM Receive Buffer Registers"
|
|
hgroup.long 0x200++0x03
|
|
hide.long 0x00 "RXRAM0,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x204++0x03
|
|
hide.long 0x00 "RXRAM1,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x208++0x03
|
|
hide.long 0x00 "RXRAM2,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x20C++0x03
|
|
hide.long 0x00 "RXRAM3,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "RXRAM4,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x214++0x03
|
|
hide.long 0x00 "RXRAM5,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x218++0x03
|
|
hide.long 0x00 "RXRAM6,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "RXRAM7,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x220++0x03
|
|
hide.long 0x00 "RXRAM8,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x224++0x03
|
|
hide.long 0x00 "RXRAM9,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x228++0x03
|
|
hide.long 0x00 "RXRAM10,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x22C++0x03
|
|
hide.long 0x00 "RXRAM11,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x230++0x03
|
|
hide.long 0x00 "RXRAM12,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x234++0x03
|
|
hide.long 0x00 "RXRAM13,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x238++0x03
|
|
hide.long 0x00 "RXRAM14,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x23C++0x03
|
|
hide.long 0x00 "RXRAM15,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x240++0x03
|
|
hide.long 0x00 "RXRAM16,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x244++0x03
|
|
hide.long 0x00 "RXRAM17,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x248++0x03
|
|
hide.long 0x00 "RXRAM18,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x24C++0x03
|
|
hide.long 0x00 "RXRAM19,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x250++0x03
|
|
hide.long 0x00 "RXRAM20,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x254++0x03
|
|
hide.long 0x00 "RXRAM21,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x258++0x03
|
|
hide.long 0x00 "RXRAM22,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x25C++0x03
|
|
hide.long 0x00 "RXRAM23,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x260++0x03
|
|
hide.long 0x00 "RXRAM24,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x264++0x03
|
|
hide.long 0x00 "RXRAM25,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x268++0x03
|
|
hide.long 0x00 "RXRAM26,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x26C++0x03
|
|
hide.long 0x00 "RXRAM27,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x270++0x03
|
|
hide.long 0x00 "RXRAM28,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x274++0x03
|
|
hide.long 0x00 "RXRAM29,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x278++0x03
|
|
hide.long 0x00 "RXRAM30,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x27C++0x03
|
|
hide.long 0x00 "RXRAM31,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x280++0x03
|
|
hide.long 0x00 "RXRAM32,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x284++0x03
|
|
hide.long 0x00 "RXRAM33,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x288++0x03
|
|
hide.long 0x00 "RXRAM34,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x28C++0x03
|
|
hide.long 0x00 "RXRAM35,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x290++0x03
|
|
hide.long 0x00 "RXRAM36,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x294++0x03
|
|
hide.long 0x00 "RXRAM37,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x298++0x03
|
|
hide.long 0x00 "RXRAM38,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x29C++0x03
|
|
hide.long 0x00 "RXRAM39,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2A0++0x03
|
|
hide.long 0x00 "RXRAM40,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2A4++0x03
|
|
hide.long 0x00 "RXRAM41,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2A8++0x03
|
|
hide.long 0x00 "RXRAM42,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2AC++0x03
|
|
hide.long 0x00 "RXRAM43,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2B0++0x03
|
|
hide.long 0x00 "RXRAM44,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2B4++0x03
|
|
hide.long 0x00 "RXRAM45,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2B8++0x03
|
|
hide.long 0x00 "RXRAM46,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2BC++0x03
|
|
hide.long 0x00 "RXRAM47,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2C0++0x03
|
|
hide.long 0x00 "RXRAM48,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2C4++0x03
|
|
hide.long 0x00 "RXRAM49,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2C8++0x03
|
|
hide.long 0x00 "RXRAM50,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2CC++0x03
|
|
hide.long 0x00 "RXRAM51,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2D0++0x03
|
|
hide.long 0x00 "RXRAM52,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2D4++0x03
|
|
hide.long 0x00 "RXRAM53,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2D8++0x03
|
|
hide.long 0x00 "RXRAM54,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2DC++0x03
|
|
hide.long 0x00 "RXRAM55,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2E0++0x03
|
|
hide.long 0x00 "RXRAM56,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2E4++0x03
|
|
hide.long 0x00 "RXRAM57,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2E8++0x03
|
|
hide.long 0x00 "RXRAM58,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2EC++0x03
|
|
hide.long 0x00 "RXRAM59,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2F0++0x03
|
|
hide.long 0x00 "RXRAM60,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2F4++0x03
|
|
hide.long 0x00 "RXRAM61,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2F8++0x03
|
|
hide.long 0x00 "RXRAM62,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x2FC++0x03
|
|
hide.long 0x00 "RXRAM63,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x300++0x03
|
|
hide.long 0x00 "RXRAM64,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "RXRAM65,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x308++0x03
|
|
hide.long 0x00 "RXRAM66,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x30C++0x03
|
|
hide.long 0x00 "RXRAM67,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "RXRAM68,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x314++0x03
|
|
hide.long 0x00 "RXRAM69,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x318++0x03
|
|
hide.long 0x00 "RXRAM70,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x31C++0x03
|
|
hide.long 0x00 "RXRAM71,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x320++0x03
|
|
hide.long 0x00 "RXRAM72,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x324++0x03
|
|
hide.long 0x00 "RXRAM73,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x328++0x03
|
|
hide.long 0x00 "RXRAM74,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x32C++0x03
|
|
hide.long 0x00 "RXRAM75,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x330++0x03
|
|
hide.long 0x00 "RXRAM76,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x334++0x03
|
|
hide.long 0x00 "RXRAM77,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x338++0x03
|
|
hide.long 0x00 "RXRAM78,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x33C++0x03
|
|
hide.long 0x00 "RXRAM79,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x340++0x03
|
|
hide.long 0x00 "RXRAM80,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x344++0x03
|
|
hide.long 0x00 "RXRAM81,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x348++0x03
|
|
hide.long 0x00 "RXRAM82,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x34C++0x03
|
|
hide.long 0x00 "RXRAM83,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x350++0x03
|
|
hide.long 0x00 "RXRAM84,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x354++0x03
|
|
hide.long 0x00 "RXRAM85,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x358++0x03
|
|
hide.long 0x00 "RXRAM86,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x35C++0x03
|
|
hide.long 0x00 "RXRAM87,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x360++0x03
|
|
hide.long 0x00 "RXRAM88,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x364++0x03
|
|
hide.long 0x00 "RXRAM89,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x368++0x03
|
|
hide.long 0x00 "RXRAM90,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x36C++0x03
|
|
hide.long 0x00 "RXRAM91,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x370++0x03
|
|
hide.long 0x00 "RXRAM92,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x374++0x03
|
|
hide.long 0x00 "RXRAM93,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x378++0x03
|
|
hide.long 0x00 "RXRAM94,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x37C++0x03
|
|
hide.long 0x00 "RXRAM95,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x380++0x03
|
|
hide.long 0x00 "RXRAM96,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x384++0x03
|
|
hide.long 0x00 "RXRAM97,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x388++0x03
|
|
hide.long 0x00 "RXRAM98,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x38C++0x03
|
|
hide.long 0x00 "RXRAM99,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "RXRAM100,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x394++0x03
|
|
hide.long 0x00 "RXRAM101,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x398++0x03
|
|
hide.long 0x00 "RXRAM102,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x39C++0x03
|
|
hide.long 0x00 "RXRAM103,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3A0++0x03
|
|
hide.long 0x00 "RXRAM104,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3A4++0x03
|
|
hide.long 0x00 "RXRAM105,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3A8++0x03
|
|
hide.long 0x00 "RXRAM106,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3AC++0x03
|
|
hide.long 0x00 "RXRAM107,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3B0++0x03
|
|
hide.long 0x00 "RXRAM108,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3B4++0x03
|
|
hide.long 0x00 "RXRAM109,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3B8++0x03
|
|
hide.long 0x00 "RXRAM110,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3BC++0x03
|
|
hide.long 0x00 "RXRAM111,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3C0++0x03
|
|
hide.long 0x00 "RXRAM112,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3C4++0x03
|
|
hide.long 0x00 "RXRAM113,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3C8++0x03
|
|
hide.long 0x00 "RXRAM114,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3CC++0x03
|
|
hide.long 0x00 "RXRAM115,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3D0++0x03
|
|
hide.long 0x00 "RXRAM116,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3D4++0x03
|
|
hide.long 0x00 "RXRAM117,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3D8++0x03
|
|
hide.long 0x00 "RXRAM118,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3DC++0x03
|
|
hide.long 0x00 "RXRAM119,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3E0++0x03
|
|
hide.long 0x00 "RXRAM120,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3E4++0x03
|
|
hide.long 0x00 "RXRAM121,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3E8++0x03
|
|
hide.long 0x00 "RXRAM122,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3EC++0x03
|
|
hide.long 0x00 "RXRAM123,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3F0++0x03
|
|
hide.long 0x00 "RXRAM124,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3F4++0x03
|
|
hide.long 0x00 "RXRAM125,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3F8++0x03
|
|
hide.long 0x00 "RXRAM126,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
hgroup.long 0x3FC++0x03
|
|
hide.long 0x00 "RXRAM127,Multi-buffer RAM Receive Buffer Register"
|
|
in
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "QSPI (Quad Serial Peripheral Interface)"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
tree "EXT FLASH"
|
|
base ad:0xC0000000
|
|
width 5.
|
|
rgroup.long 0x04++0x03 "Product ID"
|
|
line.long 0x00 "PID,Product ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Register scheme number" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Module function"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL release version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major release number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom IP" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " MINOR ,Minor release number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
width 27.
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Forced,No-idle,Smart,Smart wakeup"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "INTR_STATUS_RAW_SET,INTR Interrupt Status Raw/Set Register"
|
|
bitfld.long 0x00 1. " WIRQ_RAW ,Word interrupt raw status" "Inactive,Active"
|
|
bitfld.long 0x00 0. " FIRQ_RAW ,Frame interrupt raw status" "Inactive,Active"
|
|
line.long 0x04 "INTR_STATUS_ENABLED_CLEAR,INTR Enabled Status Enabled/Clear Register"
|
|
eventfld.long 0x04 1. " WIRQ_ENA ,Word interrupt enabled status" "Inactive,Active"
|
|
eventfld.long 0x04 0. " FIRQ_ENA ,Frame interrupt enabled status" "Inactive,Active"
|
|
line.long 0x08 "INTR_ENABLE_SET/CLR,Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x08 1. 0x08 1. 0x0C 1. " WIRQ_ENA ,Word interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x0C 0. " FIRQ_ENA ,Frame interrupt enable" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "INTC_EOI,EOI Register"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SPI_CLOCK_CNTRL,SPI Clock Control Register"
|
|
bitfld.long 0x00 31. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " DCLK_DIV ,Serial data clock divide by ratio"
|
|
sif cpuis("AWR1843*")
|
|
if (((per.l(ad:0xC0000000+0x44))&0x01)==0x00)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xC0000000+0x44))&0x01010101)==0x00000000)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0000000+0x44))&0x01010101)==0x00000001)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0000000+0x44))&0x01010101)==0x00000100)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0000000+0x44))&0x01010101)==0x00000101)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0000000+0x44))&0x01010101)==0x00010000)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0000000+0x44))&0x01010101)==0x00010001)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0000000+0x44))&0x01010101)==0x00010100)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0000000+0x44))&0x01010101)==0x00010101)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0000000+0x44))&0x01010101)==0x01000000)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0000000+0x44))&0x01010101)==0x01000001)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0000000+0x44))&0x01010101)==0x01000100)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0000000+0x44))&0x01010101)==0x01000101)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0000000+0x44))&0x01010101)==0x01010000)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0000000+0x44))&0x01010101)==0x01010001)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0000000+0x44))&0x01010101)==0x01010100)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
endif
|
|
endif
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMD,SPI Command Register"
|
|
bitfld.long 0x00 28.--29. " CSNUM ,Device select" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--25. 1. " WLEN ,Word length"
|
|
bitfld.long 0x00 16.--18. " CMD ,Transfer command" ",4 R single,4 W single,4 R dual,,3 R single,3 W single,6 R quad"
|
|
newline
|
|
bitfld.long 0x00 15. " FIRQ ,Frame count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WIRQ ,Word count interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--11. 1. " FLEN ,Frame length"
|
|
newline
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "SPI_STATUS,SPI Status Register"
|
|
in
|
|
newline
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SPI_DATA,SPI Data Register"
|
|
if (((per.l(ad:0xC0000000+0x54))&0xC00)==0x000)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SPI_SETUP0,Memory Mapped SPI Setup 0 Register"
|
|
bitfld.long 0x00 24.--28. " NUM_D_BITS ,Number of dummy bits to use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WCMD ,Write command"
|
|
bitfld.long 0x00 12.--13. " READ_TYPE ,Read command mode" "Normal,Dual,Normal,Quad"
|
|
bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "Default,8,16,24"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1,2,3,4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RCMD ,Read command"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SPI_SETUP0,Memory Mapped SPI Setup 0 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WCMD ,Write command"
|
|
bitfld.long 0x00 12.--13. " READ_TYPE ,Read command mode" "Normal,Dual,Normal,Quad"
|
|
bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "Default,8,16,24"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1,2,3,4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RCMD ,Read command"
|
|
endif
|
|
if (((per.l(ad:0xC0000000+0x58))&0xC00)==0x000)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SPI_SETUP1,Memory Mapped SPI Setup 1 Register"
|
|
bitfld.long 0x00 24.--28. " NUM_D_BITS ,Number of dummy bits to use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WCMD ,Write command"
|
|
bitfld.long 0x00 12.--13. " READ_TYPE ,Read command mode" "Normal,Dual,Normal,Quad"
|
|
bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "Default,8,16,24"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1,2,3,4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RCMD ,Read command"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SPI_SETUP1,Memory Mapped SPI Setup 1 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WCMD ,Write command"
|
|
bitfld.long 0x00 12.--13. " READ_TYPE ,Read command mode" "Normal,Dual,Normal,Quad"
|
|
bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "Default,8,16,24"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1,2,3,4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RCMD ,Read command"
|
|
endif
|
|
if (((per.l(ad:0xC0000000+0x5C))&0xC00)==0x000)
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SPI_SETUP2,Memory Mapped SPI Setup 2 Register"
|
|
bitfld.long 0x00 24.--28. " NUM_D_BITS ,Number of dummy bits to use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WCMD ,Write command"
|
|
bitfld.long 0x00 12.--13. " READ_TYPE ,Read command mode" "Normal,Dual,Normal,Quad"
|
|
bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "Default,8,16,24"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1,2,3,4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RCMD ,Read command"
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SPI_SETUP2,Memory Mapped SPI Setup 2 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WCMD ,Write command"
|
|
bitfld.long 0x00 12.--13. " READ_TYPE ,Read command mode" "Normal,Dual,Normal,Quad"
|
|
bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "Default,8,16,24"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1,2,3,4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RCMD ,Read command"
|
|
endif
|
|
if (((per.l(ad:0xC0000000+0x60))&0xC00)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SPI_SETUP3,Memory Mapped SPI Setup 3 Register"
|
|
bitfld.long 0x00 24.--28. " NUM_D_BITS ,Number of dummy bits to use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WCMD ,Write command"
|
|
bitfld.long 0x00 12.--13. " READ_TYPE ,Read command mode" "Normal,Dual,Normal,Quad"
|
|
bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "Default,8,16,24"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1,2,3,4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RCMD ,Read command"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SPI_SETUP3,Memory Mapped SPI Setup 3 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WCMD ,Write command"
|
|
bitfld.long 0x00 12.--13. " READ_TYPE ,Read command mode" "Normal,Dual,Normal,Quad"
|
|
bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "Default,8,16,24"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1,2,3,4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RCMD ,Read command"
|
|
endif
|
|
newline
|
|
group.long 0x64++0x0F
|
|
line.long 0x00 "SPI_SWITCH,Memory Mapped SPI Switch Register"
|
|
bitfld.long 0x00 1. " MM_INT_EN ,Memory mapped mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MMPT_S ,Memory mapped protocol translator enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPI_DATA1,SPI Data Register"
|
|
line.long 0x08 "SPI_DATA2,SPI Data Register"
|
|
line.long 0x0C "SPI_DATA3,SPI Data Register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "MSS QSPI"
|
|
base ad:0xC0800000
|
|
width 5.
|
|
rgroup.long 0x04++0x03 "Product ID"
|
|
line.long 0x00 "PID,Product ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Register scheme number" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Module function"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL release version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major release number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom IP" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " MINOR ,Minor release number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
width 27.
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Forced,No-idle,Smart,Smart wakeup"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "INTR_STATUS_RAW_SET,INTR Interrupt Status Raw/Set Register"
|
|
bitfld.long 0x00 1. " WIRQ_RAW ,Word interrupt raw status" "Inactive,Active"
|
|
bitfld.long 0x00 0. " FIRQ_RAW ,Frame interrupt raw status" "Inactive,Active"
|
|
line.long 0x04 "INTR_STATUS_ENABLED_CLEAR,INTR Enabled Status Enabled/Clear Register"
|
|
eventfld.long 0x04 1. " WIRQ_ENA ,Word interrupt enabled status" "Inactive,Active"
|
|
eventfld.long 0x04 0. " FIRQ_ENA ,Frame interrupt enabled status" "Inactive,Active"
|
|
line.long 0x08 "INTR_ENABLE_SET/CLR,Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x08 1. 0x08 1. 0x0C 1. " WIRQ_ENA ,Word interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x0C 0. " FIRQ_ENA ,Frame interrupt enable" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "INTC_EOI,EOI Register"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SPI_CLOCK_CNTRL,SPI Clock Control Register"
|
|
bitfld.long 0x00 31. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " DCLK_DIV ,Serial data clock divide by ratio"
|
|
sif cpuis("AWR1843*")
|
|
if (((per.l(ad:0xC0800000+0x44))&0x01)==0x00)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0xC0800000+0x44))&0x01010101)==0x00000000)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0800000+0x44))&0x01010101)==0x00000001)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0800000+0x44))&0x01010101)==0x00000100)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0800000+0x44))&0x01010101)==0x00000101)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0800000+0x44))&0x01010101)==0x00010000)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0800000+0x44))&0x01010101)==0x00010001)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0800000+0x44))&0x01010101)==0x00010100)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0800000+0x44))&0x01010101)==0x00010101)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0800000+0x44))&0x01010101)==0x01000000)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0800000+0x44))&0x01010101)==0x01000001)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0800000+0x44))&0x01010101)==0x01000100)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0800000+0x44))&0x01010101)==0x01000101)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0800000+0x44))&0x01010101)==0x01010000)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0800000+0x44))&0x01010101)==0x01010001)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
elif (((per.l(ad:0xC0800000+0x44))&0x01010101)==0x01010100)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SPI_DC,SPI Data Control Register"
|
|
bitfld.long 0x00 27.--28. " DD3 ,Data delay for chip select 3" "No delay,1,2,3"
|
|
bitfld.long 0x00 26. " CKPH3 ,Clock phase for chip select 3 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 25. " CSP3 ,Chip select polarity for chip select 3" "Low,High"
|
|
bitfld.long 0x00 24. " CKP3 ,Clock polarity for chip select 3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19.--20. " DD2 ,Data delay for chip select 2" "No delay,1,2,3"
|
|
bitfld.long 0x00 18. " CKPH2 ,Clock phase for chip select 2 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 17. " CSP2 ,Chip select polarity for chip select 2" "Low,High"
|
|
bitfld.long 0x00 16. " CKP2 ,Clock polarity for chip select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11.--12. " DD1 ,Data delay for chip select 1" "No delay,1,2,3"
|
|
bitfld.long 0x00 10. " CKPH1 ,Clock phase for chip select 1 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 9. " CSP1 ,Chip select polarity for chip select 1" "Low,High"
|
|
bitfld.long 0x00 8. " CKP1 ,Clock polarity for chip select 1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3.--4. " DD0 ,Data delay for chip select 0" "No delay,1,2,3"
|
|
bitfld.long 0x00 2. " CKPH0 ,Clock phase for chip select 0 (data shift out/input)" "Rising/falling,Falling/rising"
|
|
bitfld.long 0x00 1. " CSP0 ,Chip select polarity for chip select 0" "Low,High"
|
|
bitfld.long 0x00 0. " CKP0 ,Clock polarity for chip select 0" "0,1"
|
|
endif
|
|
endif
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SPI_CMD,SPI Command Register"
|
|
bitfld.long 0x00 28.--29. " CSNUM ,Device select" "0,1,2,3"
|
|
hexmask.long.word 0x00 19.--25. 1. " WLEN ,Word length"
|
|
bitfld.long 0x00 16.--18. " CMD ,Transfer command" ",4 R single,4 W single,4 R dual,,3 R single,3 W single,6 R quad"
|
|
newline
|
|
bitfld.long 0x00 15. " FIRQ ,Frame count interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " WIRQ ,Word count interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--11. 1. " FLEN ,Frame length"
|
|
newline
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "SPI_STATUS,SPI Status Register"
|
|
in
|
|
newline
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SPI_DATA,SPI Data Register"
|
|
if (((per.l(ad:0xC0800000+0x54))&0xC00)==0x000)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SPI_SETUP0,Memory Mapped SPI Setup 0 Register"
|
|
bitfld.long 0x00 24.--28. " NUM_D_BITS ,Number of dummy bits to use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WCMD ,Write command"
|
|
bitfld.long 0x00 12.--13. " READ_TYPE ,Read command mode" "Normal,Dual,Normal,Quad"
|
|
bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "Default,8,16,24"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1,2,3,4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RCMD ,Read command"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SPI_SETUP0,Memory Mapped SPI Setup 0 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WCMD ,Write command"
|
|
bitfld.long 0x00 12.--13. " READ_TYPE ,Read command mode" "Normal,Dual,Normal,Quad"
|
|
bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "Default,8,16,24"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1,2,3,4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RCMD ,Read command"
|
|
endif
|
|
if (((per.l(ad:0xC0800000+0x58))&0xC00)==0x000)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SPI_SETUP1,Memory Mapped SPI Setup 1 Register"
|
|
bitfld.long 0x00 24.--28. " NUM_D_BITS ,Number of dummy bits to use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WCMD ,Write command"
|
|
bitfld.long 0x00 12.--13. " READ_TYPE ,Read command mode" "Normal,Dual,Normal,Quad"
|
|
bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "Default,8,16,24"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1,2,3,4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RCMD ,Read command"
|
|
else
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SPI_SETUP1,Memory Mapped SPI Setup 1 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WCMD ,Write command"
|
|
bitfld.long 0x00 12.--13. " READ_TYPE ,Read command mode" "Normal,Dual,Normal,Quad"
|
|
bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "Default,8,16,24"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1,2,3,4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RCMD ,Read command"
|
|
endif
|
|
if (((per.l(ad:0xC0800000+0x5C))&0xC00)==0x000)
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SPI_SETUP2,Memory Mapped SPI Setup 2 Register"
|
|
bitfld.long 0x00 24.--28. " NUM_D_BITS ,Number of dummy bits to use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WCMD ,Write command"
|
|
bitfld.long 0x00 12.--13. " READ_TYPE ,Read command mode" "Normal,Dual,Normal,Quad"
|
|
bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "Default,8,16,24"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1,2,3,4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RCMD ,Read command"
|
|
else
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SPI_SETUP2,Memory Mapped SPI Setup 2 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WCMD ,Write command"
|
|
bitfld.long 0x00 12.--13. " READ_TYPE ,Read command mode" "Normal,Dual,Normal,Quad"
|
|
bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "Default,8,16,24"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1,2,3,4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RCMD ,Read command"
|
|
endif
|
|
if (((per.l(ad:0xC0800000+0x60))&0xC00)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SPI_SETUP3,Memory Mapped SPI Setup 3 Register"
|
|
bitfld.long 0x00 24.--28. " NUM_D_BITS ,Number of dummy bits to use" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WCMD ,Write command"
|
|
bitfld.long 0x00 12.--13. " READ_TYPE ,Read command mode" "Normal,Dual,Normal,Quad"
|
|
bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "Default,8,16,24"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1,2,3,4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RCMD ,Read command"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SPI_SETUP3,Memory Mapped SPI Setup 3 Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " WCMD ,Write command"
|
|
bitfld.long 0x00 12.--13. " READ_TYPE ,Read command mode" "Normal,Dual,Normal,Quad"
|
|
bitfld.long 0x00 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read" "Default,8,16,24"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent" "1,2,3,4"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RCMD ,Read command"
|
|
endif
|
|
newline
|
|
group.long 0x64++0x0F
|
|
line.long 0x00 "SPI_SWITCH,Memory Mapped SPI Switch Register"
|
|
bitfld.long 0x00 1. " MM_INT_EN ,Memory mapped mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MMPT_S ,Memory mapped protocol translator enable" "Disabled,Enabled"
|
|
line.long 0x04 "SPI_DATA1,SPI Data Register"
|
|
line.long 0x08 "SPI_DATA2,SPI Data Register"
|
|
line.long 0x0C "SPI_DATA3,SPI Data Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
base ad:0xFFF7D400
|
|
width 17.
|
|
if (((per.l(ad:0xFFF7D400+0x24))&0x100)==0x100)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ICOAR,I2C Own Address Register"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " A ,Own address"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ICOAR,I2C Own Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " A ,Own address"
|
|
endif
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "ICIMR,I2C Interrupt Mask Register"
|
|
bitfld.long 0x00 6. " AAS ,Address as slave interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " SCD ,Stop condition detection mask" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " ICXRDY ,Transmit data ready interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 3. " ICRRDY ,Receive data ready interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " ARDY ,Register access ready interrupt mask" "Masked,Not masked"
|
|
newline
|
|
bitfld.long 0x00 1. " NACK ,No acknowledgement interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " AL ,Arbitration lost interrupt mask" "Masked,Not masked"
|
|
line.long 0x04 "ICSTR,I2C Status Register"
|
|
eventfld.long 0x04 14. " SDIR ,Slave direction" "Receiver,Transmitter"
|
|
eventfld.long 0x04 13. " NACKSNT ,No acknowledge sent" "Not sent,Sent"
|
|
bitfld.long 0x04 12. " BB ,Bus busy" "Not busy,Busy"
|
|
bitfld.long 0x04 11. " RSFULL ,Receive shift full" "Not full,Full"
|
|
bitfld.long 0x04 10. " XSMT ,Transmit shift empty not" "Empty,Not empty"
|
|
newline
|
|
bitfld.long 0x04 9. " AAS ,Address as slave" "No,Yes"
|
|
bitfld.long 0x04 8. " AD0 ,Address zero status" "Not all 0's,All 0's"
|
|
eventfld.long 0x04 5. " SCD ,Stop condition detection" "Not detected,Detected"
|
|
bitfld.long 0x04 4. " ICXRDY ,Transmit data ready interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 3. " ICRRDY ,Receive data ready interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 2. " ARDY ,Register-access-ready interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 1. " NACK ,No-acknowledgement interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 0. " AL ,Arbitration lost interrupt flag" "No interrupt,Interrupt"
|
|
if (((per.l(ad:0xFFF7D400+0x24))&0x20)==0x00)
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "ICCLKL,I2C Clock Divider Low Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ICCL ,Low time I2C SCL clock division factor"
|
|
line.long 0x04 "ICCKH,I2C Clock Control High Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " ICCH ,High time I2C SCL clock division factor"
|
|
else
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "ICCLKL,I2C Clock Divider Low Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ICCL ,Low time I2C SCL clock division factor"
|
|
line.long 0x04 "ICCKH,I2C Clock Control High Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " ICCH ,High time I2C SCL clock division factor"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ICCNT,I2C Data Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ICDC ,Data count"
|
|
newline
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "ICDRR,I2C Data Receive Register"
|
|
in
|
|
newline
|
|
if (((per.l(ad:0xFFF7D400+0x24))&0x100)==0x100)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ICSAR,I2C Slave Address Register"
|
|
hexmask.long.word 0x00 0.--9. 0x01 " A ,Slave address"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ICSAR,I2C Slave Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " A ,Slave address"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ICDXR,I2C Data Transmit Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " D ,Transmit data"
|
|
if (((per.l(ad:0xFFF7D400+0x24))&0x608)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ICMDR,I2C Mode Register"
|
|
bitfld.long 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "ACK,NACK"
|
|
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
newline
|
|
bitfld.long 0x00 9. " TRX ,Transmitter/receiver" "Receiver,Transmitter"
|
|
bitfld.long 0x00 8. " XA ,Expanded address enable" "7-bit addressing,10-bit addressing"
|
|
newline
|
|
bitfld.long 0x00 5. " IRS ,I2C reset" "Reset,No reset"
|
|
bitfld.long 0x00 3. " FDF ,Free data format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " BC ,Bit count" "9,,3,4,5,6,7,8"
|
|
newline
|
|
elif (((per.l(ad:0xFFF7D400+0x24))&0x608)==0x08)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ICMDR,I2C Mode Register"
|
|
bitfld.long 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "ACK,NACK"
|
|
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
newline
|
|
bitfld.long 0x00 9. " TRX ,Transmitter/receiver" "Receiver,Transmitter"
|
|
bitfld.long 0x00 8. " XA ,Expanded address enable" "7-bit addressing,10-bit addressing"
|
|
newline
|
|
bitfld.long 0x00 5. " IRS ,I2C reset" "Reset,No reset"
|
|
bitfld.long 0x00 3. " FDF ,Free data format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " BC ,Bit count" "8,,2,3,4,5,6,7"
|
|
newline
|
|
elif (((per.l(ad:0xFFF7D400+0x24))&0x608)==0x408)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ICMDR,I2C Mode Register"
|
|
bitfld.long 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "ACK,NACK"
|
|
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " STT ,Start condition" "Not generated,Generated"
|
|
bitfld.long 0x00 11. " STP ,Stop condition" "Not generated,Generated"
|
|
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
newline
|
|
bitfld.long 0x00 9. " TRX ,Transmitter/receiver" "Receiver,Transmitter"
|
|
bitfld.long 0x00 8. " XA ,Expand address enable" "7-bit addressing,10-bit addressing"
|
|
bitfld.long 0x00 7. " RM ,Repeat mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IRS ,I2C reset" "Reset,No reset"
|
|
bitfld.long 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 3. " FDF ,Free data format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " BC ,Bit count" "8,,2,3,4,5,6,7"
|
|
newline
|
|
elif (((per.l(ad:0xFFF7D400+0x24))&0x608)==0x400)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ICMDR,I2C Mode Register"
|
|
bitfld.long 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "ACK,NACK"
|
|
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " STT ,Start condition" "Not generated,Generated"
|
|
bitfld.long 0x00 11. " STP ,Stop condition" "Not generated,Generated"
|
|
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
newline
|
|
bitfld.long 0x00 9. " TRX ,Transmitter/receiver" "Receiver,Transmitter"
|
|
bitfld.long 0x00 8. " XA ,Expand address enable" "7-bit addressing,10-bit addressing"
|
|
bitfld.long 0x00 7. " RM ,Repeat mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IRS ,I2C reset" "Reset,No reset"
|
|
bitfld.long 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 3. " FDF ,Free data format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " BC ,Bit count" "9,,3,4,5,6,7,8"
|
|
newline
|
|
elif (((per.l(ad:0xFFF7D400+0x24))&0x608)==0x600)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ICMDR,I2C Mode Register"
|
|
textfld " "
|
|
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " STT ,Start condition" "Not generated,Generated"
|
|
bitfld.long 0x00 11. " STP ,Stop condition" "Not generated,Generated"
|
|
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
newline
|
|
bitfld.long 0x00 9. " TRX ,Transmitter/receiver" "Receiver,Transmitter"
|
|
bitfld.long 0x00 8. " XA ,Expand address enable" "7-bit addressing,10-bit addressing"
|
|
bitfld.long 0x00 7. " RM ,Repeat mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DLB ,Digital loop back enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IRS ,I2C reset not" "Reset,No reset"
|
|
bitfld.long 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 3. " FDF ,Free data format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " BC ,Bit count" "9,,3,4,5,6,7,8"
|
|
newline
|
|
elif (((per.l(ad:0xFFF7D400+0x24))&0x608)==0x608)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ICMDR,I2C Mode Register"
|
|
textfld " "
|
|
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " STT ,Start condition" "Not generated,Generated"
|
|
bitfld.long 0x00 11. " STP ,Stop condition" "Not generated,Generated"
|
|
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
newline
|
|
bitfld.long 0x00 9. " TRX ,Transmitter/receiver" "Receiver,Transmitter"
|
|
bitfld.long 0x00 8. " XA ,Expand address enable" "7-bit addressing,10-bit addressing"
|
|
bitfld.long 0x00 7. " RM ,Repeat mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DLB ,Digital loop back enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IRS ,I2C reset" "Reset,No reset"
|
|
bitfld.long 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 3. " FDF ,Free data format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " BC ,Bit count" "8,,2,3,4,5,6,7"
|
|
newline
|
|
elif (((per.l(ad:0xFFF7D400+0x24))&0x608)==0x208)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ICMDR,I2C Mode Register"
|
|
textfld " "
|
|
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
newline
|
|
bitfld.long 0x00 9. " TRX ,Transmitter/receiver" "Receiver,Transmitter"
|
|
bitfld.long 0x00 8. " XA ,Expand address enable" "7-bit addressing,10-bit addressing"
|
|
textfld " "
|
|
bitfld.long 0x00 5. " IRS ,I2C reset" "Reset,No reset"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 3. " FDF ,Free data format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " BC ,Bit count" "8,,2,3,4,5,6,7"
|
|
newline
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ICMDR,I2C Mode Register"
|
|
textfld " "
|
|
bitfld.long 0x00 14. " FREE ,Free running bit" "Disabled,Enabled"
|
|
textfld " "
|
|
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
newline
|
|
bitfld.long 0x00 9. " TRX ,Transmitter/receiver" "Receiver,Transmitter"
|
|
bitfld.long 0x00 8. " XA ,Expand address enable" "7-bit addressing,10-bit addressing"
|
|
textfld " "
|
|
bitfld.long 0x00 5. " IRS ,I2C reset" "Reset,No reset"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 3. " FDF ,Free data format enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " BC ,Bit count" "9,,3,4,5,6,7,8"
|
|
newline
|
|
endif
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "ICIVR,I2C Interrupt Vector Register"
|
|
in
|
|
newline
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ICEMDR,I2C Extended Mode Register"
|
|
bitfld.long 0x00 1. " IGNACK ,Ignore NACK" "Not ignored,Ignored"
|
|
bitfld.long 0x00 0. " BCM ,Backwards compatibility mode" "Disabled,Enabled"
|
|
if (((per.l(ad:0xFFF7D400+0x24))&0x20)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ICPSC,I2C Prescaler Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IPSC ,Prescaler"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "ICPSC,I2C Prescaler Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IPSC ,Prescaler"
|
|
endif
|
|
group.long 0x34++0x0B
|
|
line.long 0x00 "ICPID1,I2C Peripheral ID Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CLASS ,Peripheral class"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REVISION ,Revision level of the I2C"
|
|
line.long 0x04 "ICPID2,I2C Peripheral ID Register 2"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TYPE ,Peripheral type"
|
|
line.long 0x08 "ICDMAC,I2C DMA Control Register"
|
|
bitfld.long 0x08 1. " TXDMAEN ,DMA transmit event enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " RXDMAEN ,DMA receive event enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0xFFF7D400+0x24))&0x20)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "ICPFUNC,I2C Pin Function Register"
|
|
bitfld.long 0x00 0. " PFUNC0 ,SCL and SDA pin function" "SCL/SDA,GPIO"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "ICPFUNC,I2C Pin Function Register"
|
|
bitfld.long 0x00 0. " PFUNC0 ,SCL and SDA pin function" "SCL/SDA,GPIO"
|
|
endif
|
|
if (((per.l(ad:0xFFF7D400+0x48))&0x01)==0x01)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ICPDIR,I2C Pin Direction Register"
|
|
bitfld.long 0x00 1. " PDIR1 ,SDA pin direction" "Input,Output"
|
|
bitfld.long 0x00 0. " PDIR0 ,SCL pin direction" "Input,Output"
|
|
else
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ICPDIR,I2C Pin Direction Register"
|
|
endif
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "ICPDIN,I2C Pin Data In Register"
|
|
bitfld.long 0x00 1. " PDIN1 ,SDA pin logic level" "Low,High"
|
|
bitfld.long 0x00 0. " PDIN0 ,SCL pin logic level" "Low,High"
|
|
if ((((per.l(ad:0xFFF7D400+0x48))&0x01)==0x01)&&(((per.l(ad:0xFFF7D400+0x4C))&0x03)==0x03))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "ICPDOUT_SET/CLR,I2C Pin Data Out Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDOUT1 ,Level driven on SDA pin" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDOUT0 ,Level driven on SCL pin" "Low,High"
|
|
elif ((((per.l(ad:0xFFF7D400+0x48))&0x01)==0x01)&&(((per.l(ad:0xFFF7D400+0x4C))&0x03)==0x02))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "ICPDOUT_SET/CLR,I2C Pin Data Out Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDOUT1 ,Level driven on SDA pin" "Low,High"
|
|
elif ((((per.l(ad:0xFFF7D400+0x48))&0x01)==0x01)&&(((per.l(ad:0xFFF7D400+0x4C))&0x03)==0x01))
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "ICPDOUT_SET/CLR,I2C Pin Data Out Set/Clear Register"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDOUT0 ,Level driven on SCL pin" "Low,High"
|
|
else
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "ICPDOUT_SET/CLR,I2C Pin Data Out Set/Clear Register"
|
|
endif
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "ICPDRV,I2C Pin Driver Mode Register"
|
|
bitfld.long 0x00 1. " PDRV1 ,Driver mode of output buffer for SDA pin" "I2C,GPIO"
|
|
bitfld.long 0x00 0. " PDRV0 ,Driver mode of output buffer for SCL pin" "I2C,GPIO"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
tree.open "SCI (Serial Communication Interface)"
|
|
tree "SCI-A"
|
|
base ad:0xFFF7E500
|
|
width 22.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SCIGCR0,SCI Global Control Register 0"
|
|
bitfld.long 0x00 0. " RESET ,SCI module reset" "Reset,No reset"
|
|
line.long 0x04 "SCIGCR1,SCI Global Control Register 1"
|
|
bitfld.long 0x04 25. " TXENA ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " RXENA ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CONT ,Continue on suspend" "Frozen,Continued"
|
|
bitfld.long 0x04 16. " LOOPBACK ,Loopback enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " POWERDOWN ,Low-power mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 8. " SLEEP ,Sleep mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " SWNRST ,Software reset enable" "Low,High"
|
|
bitfld.long 0x04 5. " CLOCK ,SCI internal clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " STOP ,SCI number of stop bits per frame" "One,Two"
|
|
bitfld.long 0x04 3. " PARITY ,SCI parity odd/even selection" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x04 2. " PARITY_ENA ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TIMING_MODE ,SCI timing mode bit" "Synchronous,Asynchronous"
|
|
bitfld.long 0x04 0. " COMM_MODE ,SCI communication mode bit" "Idle-line,Address-bit"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SCISETINT_SET/CLR,SCI Set/Clear Interrupt Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FEINT ,Framing-error interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OEINT ,Overrun-error interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PEINT ,Parity interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RXDMAALL ,Receive DMA all" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RXDMA ,Receive DMA" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TXDMA ,Transmit DMA" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RXINT ,Receiver interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TXINT ,Transmitter interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUPINT ,Wakeup interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDTINT ,Break detect interrupt" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SCISETINTLVL_SET/CLR,SCI Set/Clear Interrupt Level Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FEINT ,Framing-error interrupt level" "0,1"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OEINT ,Overrun-error interrupt level" "0,1"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PEINT ,Parity interrupt level" "0,1"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RXDMAALL ,Receive DMA all level" "0,1"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RXDMA ,Receive DMA level" "0,1"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TXDMA ,Transmit DMA level" "0,1"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RXINT ,Receiver interrupt enable level" "0,1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TXINT ,Transmitter interrupt level" "0,1"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUPINT ,Wakeup interrupt level" "0,1"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDTINT ,Break detect interrupt level" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SCIFLR,SCI Flags Register"
|
|
eventfld.long 0x00 26. " FE ,Framing error flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 25. " OE ,Overrun error flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 24. " PE ,Parity error flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " RXWAKE ,Receiver wakeup detect flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " TXEMPTY ,Transmitter empty flag" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 10. " TXWAKE ,Transmitter wakeup method select" "Data,Address"
|
|
eventfld.long 0x00 9. " RXRDY ,Receiver ready flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " TXRDY ,Transmitter buffer register ready flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " BUSY ,Bus busy flag" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " IDLE ,SCI receiver in idle state" "Idle,Not idle"
|
|
newline
|
|
eventfld.long 0x00 1. " WAKEUP ,Wakeup flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " BRKDT ,SCI break-detect flag" "Not occurred,Occurred"
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "SCIINTVECT0,SCI Interrupt Vector Offset 0"
|
|
bitfld.long 0x00 0.--3. " INVECT0 ,Interrupt vector offset for INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "SCIINTVECT1,SCI Interrupt Vector Offset 1"
|
|
bitfld.long 0x04 0.--3. " INVECT1 ,Interrupt vector offset for INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "SCIFORMAT,SCI Format Control Register"
|
|
bitfld.long 0x00 0.--2. " CHAR ,Character length control bits" "1,2,3,4,5,6,7,8"
|
|
line.long 0x04 "BRS,Baud Rate Selection Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " BAUD ,SCI 24-bit baud rate"
|
|
width 7.
|
|
rgroup.long 0x30++0x07 "SCI Data Buffers"
|
|
line.long 0x00 "SCIED,Receiver Emulation Data Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulator data"
|
|
line.long 0x04 "SCIRD,Receiver Data Buffer"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RD ,Receiver data"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SCITD,Transmit Data Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit data"
|
|
width 9.
|
|
group.long 0x3C++0x07 "SCI Pin I/O Control Registers"
|
|
line.long 0x00 "SCIPIO0,SCI Pin I/O Control Register 0"
|
|
bitfld.long 0x00 2. " TXFUNC ,Transfer function" "Digital I/O,Transmit pin"
|
|
bitfld.long 0x00 1. " RXFUNC ,Receive function" "Digital I/O,Receive pin"
|
|
line.long 0x04 "SCIPIO1,SCI Pin I/O Control Register 1"
|
|
bitfld.long 0x04 2. " TXDIR ,Transfer pin direction" "Input,Output"
|
|
bitfld.long 0x04 1. " RXDIR ,Receive pin direction" "Input,Output"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SCIPIO2,SCI Pin I/O Control Register 2"
|
|
bitfld.long 0x00 2. " TXIN ,Transfer pin in" "Low,High"
|
|
bitfld.long 0x00 1. " RXIN ,Receive pin in" "Low,High"
|
|
group.long 0x48++0x17
|
|
line.long 0x00 "SCIPIO3,SCI Pin I/O Control Register 3"
|
|
bitfld.long 0x00 2. " TXOUT ,Transfer pin out" "Low,High"
|
|
bitfld.long 0x00 1. " RXOUT ,Receive pin out" "Low,High"
|
|
line.long 0x04 "SCIPIO4,SCI Pin I/O Control Register 4"
|
|
bitfld.long 0x04 2. " TXSET ,Transfer pin set" "Low,High"
|
|
bitfld.long 0x04 1. " RXSET ,Receive pin set" "Low,High"
|
|
line.long 0x08 "SCIPIO5,SCI Pin I/O Control Register 5"
|
|
bitfld.long 0x08 2. " TXCLR ,Transfer pin clear" "Low,High"
|
|
bitfld.long 0x08 1. " RXCLR ,Receive pin clear" "Low,High"
|
|
line.long 0x0C "SCIPIO6,SCI Pin I/O Control Register 6"
|
|
bitfld.long 0x0C 2. " TXPDR ,Transfer pin open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " RXPDR ,Receive pin open drain enable" "Disabled,Enabled"
|
|
line.long 0x10 "SCIPIO7,SCI Pin I/O Control Register 7"
|
|
bitfld.long 0x10 2. " TXPD ,Transfer pin pull control disable" "No,Yes"
|
|
bitfld.long 0x10 1. " RXPD ,Receive pin pull control disable" "No,Yes"
|
|
line.long 0x14 "SCIPIO8,SCI Pin I/O Control Register 8"
|
|
bitfld.long 0x14 2. " TXPSL ,Transfer pin pull select" "Down,Up"
|
|
bitfld.long 0x14 1. " RXPSL ,Receive pin pull select" "Down,Up"
|
|
newline
|
|
width 11.
|
|
if (((per.l(ad:0xFFF7E500+0x90))&0xF00)==0xA00)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "IODFTCTRL,Input/Output Error Enable Register"
|
|
bitfld.long 0x00 26. " FEN ,Frame error enable" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " PEN ,Parity error enable" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " BRKD_TENA ,Break detect error enable" "Not occurred,Occurred"
|
|
bitfld.long 0x00 19.--20. " PIN_SAMPLE_MASK ,Pin sample mask" "No mask,7th SCLK,8th SCLK,9th SCLK"
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Pin sample mask" "No delay,/1SCLK,/2SCLK,/3SCLK,/4SCLK,/5SCLK,/6SCLK,/7SCLK"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IODFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXPENA ,Module analog loopback through receive pin enable" "Transmit,Receive"
|
|
else
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "IODFTCTRL,Input/Output Error Enable Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCI-B"
|
|
base ad:0xFFF7E700
|
|
width 22.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SCIGCR0,SCI Global Control Register 0"
|
|
bitfld.long 0x00 0. " RESET ,SCI module reset" "Reset,No reset"
|
|
line.long 0x04 "SCIGCR1,SCI Global Control Register 1"
|
|
bitfld.long 0x04 25. " TXENA ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " RXENA ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CONT ,Continue on suspend" "Frozen,Continued"
|
|
bitfld.long 0x04 16. " LOOPBACK ,Loopback enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " POWERDOWN ,Low-power mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 8. " SLEEP ,Sleep mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " SWNRST ,Software reset enable" "Low,High"
|
|
bitfld.long 0x04 5. " CLOCK ,SCI internal clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " STOP ,SCI number of stop bits per frame" "One,Two"
|
|
bitfld.long 0x04 3. " PARITY ,SCI parity odd/even selection" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x04 2. " PARITY_ENA ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TIMING_MODE ,SCI timing mode bit" "Synchronous,Asynchronous"
|
|
bitfld.long 0x04 0. " COMM_MODE ,SCI communication mode bit" "Idle-line,Address-bit"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SCISETINT_SET/CLR,SCI Set/Clear Interrupt Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FEINT ,Framing-error interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OEINT ,Overrun-error interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PEINT ,Parity interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RXDMAALL ,Receive DMA all" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RXDMA ,Receive DMA" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TXDMA ,Transmit DMA" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RXINT ,Receiver interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TXINT ,Transmitter interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUPINT ,Wakeup interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDTINT ,Break detect interrupt" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SCISETINTLVL_SET/CLR,SCI Set/Clear Interrupt Level Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FEINT ,Framing-error interrupt level" "0,1"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OEINT ,Overrun-error interrupt level" "0,1"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PEINT ,Parity interrupt level" "0,1"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RXDMAALL ,Receive DMA all level" "0,1"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RXDMA ,Receive DMA level" "0,1"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TXDMA ,Transmit DMA level" "0,1"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RXINT ,Receiver interrupt enable level" "0,1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TXINT ,Transmitter interrupt level" "0,1"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUPINT ,Wakeup interrupt level" "0,1"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDTINT ,Break detect interrupt level" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SCIFLR,SCI Flags Register"
|
|
eventfld.long 0x00 26. " FE ,Framing error flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 25. " OE ,Overrun error flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 24. " PE ,Parity error flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " RXWAKE ,Receiver wakeup detect flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " TXEMPTY ,Transmitter empty flag" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 10. " TXWAKE ,Transmitter wakeup method select" "Data,Address"
|
|
eventfld.long 0x00 9. " RXRDY ,Receiver ready flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " TXRDY ,Transmitter buffer register ready flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " BUSY ,Bus busy flag" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " IDLE ,SCI receiver in idle state" "Idle,Not idle"
|
|
newline
|
|
eventfld.long 0x00 1. " WAKEUP ,Wakeup flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " BRKDT ,SCI break-detect flag" "Not occurred,Occurred"
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "SCIINTVECT0,SCI Interrupt Vector Offset 0"
|
|
bitfld.long 0x00 0.--3. " INVECT0 ,Interrupt vector offset for INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "SCIINTVECT1,SCI Interrupt Vector Offset 1"
|
|
bitfld.long 0x04 0.--3. " INVECT1 ,Interrupt vector offset for INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "SCIFORMAT,SCI Format Control Register"
|
|
bitfld.long 0x00 0.--2. " CHAR ,Character length control bits" "1,2,3,4,5,6,7,8"
|
|
line.long 0x04 "BRS,Baud Rate Selection Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " BAUD ,SCI 24-bit baud rate"
|
|
width 7.
|
|
rgroup.long 0x30++0x07 "SCI Data Buffers"
|
|
line.long 0x00 "SCIED,Receiver Emulation Data Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulator data"
|
|
line.long 0x04 "SCIRD,Receiver Data Buffer"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RD ,Receiver data"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SCITD,Transmit Data Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit data"
|
|
width 9.
|
|
group.long 0x3C++0x07 "SCI Pin I/O Control Registers"
|
|
line.long 0x00 "SCIPIO0,SCI Pin I/O Control Register 0"
|
|
bitfld.long 0x00 2. " TXFUNC ,Transfer function" "Digital I/O,Transmit pin"
|
|
bitfld.long 0x00 1. " RXFUNC ,Receive function" "Digital I/O,Receive pin"
|
|
line.long 0x04 "SCIPIO1,SCI Pin I/O Control Register 1"
|
|
bitfld.long 0x04 2. " TXDIR ,Transfer pin direction" "Input,Output"
|
|
bitfld.long 0x04 1. " RXDIR ,Receive pin direction" "Input,Output"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SCIPIO2,SCI Pin I/O Control Register 2"
|
|
bitfld.long 0x00 2. " TXIN ,Transfer pin in" "Low,High"
|
|
bitfld.long 0x00 1. " RXIN ,Receive pin in" "Low,High"
|
|
group.long 0x48++0x17
|
|
line.long 0x00 "SCIPIO3,SCI Pin I/O Control Register 3"
|
|
bitfld.long 0x00 2. " TXOUT ,Transfer pin out" "Low,High"
|
|
bitfld.long 0x00 1. " RXOUT ,Receive pin out" "Low,High"
|
|
line.long 0x04 "SCIPIO4,SCI Pin I/O Control Register 4"
|
|
bitfld.long 0x04 2. " TXSET ,Transfer pin set" "Low,High"
|
|
bitfld.long 0x04 1. " RXSET ,Receive pin set" "Low,High"
|
|
line.long 0x08 "SCIPIO5,SCI Pin I/O Control Register 5"
|
|
bitfld.long 0x08 2. " TXCLR ,Transfer pin clear" "Low,High"
|
|
bitfld.long 0x08 1. " RXCLR ,Receive pin clear" "Low,High"
|
|
line.long 0x0C "SCIPIO6,SCI Pin I/O Control Register 6"
|
|
bitfld.long 0x0C 2. " TXPDR ,Transfer pin open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " RXPDR ,Receive pin open drain enable" "Disabled,Enabled"
|
|
line.long 0x10 "SCIPIO7,SCI Pin I/O Control Register 7"
|
|
bitfld.long 0x10 2. " TXPD ,Transfer pin pull control disable" "No,Yes"
|
|
bitfld.long 0x10 1. " RXPD ,Receive pin pull control disable" "No,Yes"
|
|
line.long 0x14 "SCIPIO8,SCI Pin I/O Control Register 8"
|
|
bitfld.long 0x14 2. " TXPSL ,Transfer pin pull select" "Down,Up"
|
|
bitfld.long 0x14 1. " RXPSL ,Receive pin pull select" "Down,Up"
|
|
newline
|
|
width 11.
|
|
if (((per.l(ad:0xFFF7E700+0x90))&0xF00)==0xA00)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "IODFTCTRL,Input/Output Error Enable Register"
|
|
bitfld.long 0x00 26. " FEN ,Frame error enable" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " PEN ,Parity error enable" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " BRKD_TENA ,Break detect error enable" "Not occurred,Occurred"
|
|
bitfld.long 0x00 19.--20. " PIN_SAMPLE_MASK ,Pin sample mask" "No mask,7th SCLK,8th SCLK,9th SCLK"
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Pin sample mask" "No delay,/1SCLK,/2SCLK,/3SCLK,/4SCLK,/5SCLK,/6SCLK,/7SCLK"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IODFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXPENA ,Module analog loopback through receive pin enable" "Transmit,Receive"
|
|
else
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "IODFTCTRL,Input/Output Error Enable Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree.open "SCI (Serial Communication Interface)"
|
|
tree "SCI-A"
|
|
base ad:0xFFF7E500
|
|
width 11.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR0,SCI Global Control Register 0"
|
|
bitfld.long 0x00 0. " RESET ,SCI module reset" "Reset,No reset"
|
|
if (((per.l(ad:0xFFF7E500+0x04))&0x04)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GCR1,SCI Global Control Register 1"
|
|
bitfld.long 0x00 25. " TXENA ,SCI transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CONT ,Continue on suspend" "Frozen,Continued"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,Loop back mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POWERDOWN ,Power down" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI sleep enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SW_NRESET ,Software reset" "Reset,Ready"
|
|
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 4. " STOP ,SCI number of stop bits per frame" "1 bit,2 bits"
|
|
bitfld.long 0x00 3. " PARITY ,SCI parity odd/even selection" "Odd,Even"
|
|
bitfld.long 0x00 2. " PARITY_ENA ,Parity enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI timing mode" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI communication mode" "Idle-line,Address-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GCR1,SCI Global Control Register 1"
|
|
bitfld.long 0x00 25. " TXENA ,SCI transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CONT ,Continue on suspend" "Frozen,Continued"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,Loop back mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POWERDOWN ,Power down" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI sleep enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SW_NRESET ,Software reset" "Reset,Ready"
|
|
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 4. " STOP ,SCI number of stop bits per frame" "1 bit,2 bits"
|
|
bitfld.long 0x00 2. " PARITY_ENA ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI timing mode" "Synchronous,Asynchronous"
|
|
textline " "
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI communication mode" "Idle-line,Address-bit"
|
|
endif
|
|
textline " "
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SETINT,SCI Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_SET/CLR ,Framing-error interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_SET/CLR ,Overrun-error interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_SET/CLR ,Parity interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_SET/CLR ,Receive DMA all" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_SET/CLR ,Receive DMA" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_SET/CLR ,Transmit DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_SET/CLR ,Receiver interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_SET/CLR ,Transmitter interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_SET/CLR ,Wake-up interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_SET/CLR ,Break-detect interrupt" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SETINTLVL,SCI Interrupt Level Set/Clear Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_SET/CLR ,Framing-error interrupt level" "INT0,INT1"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_SET/CLR ,Overrun-error interrupt level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_SET/CLR ,Parity error interrupt level" "INT0,INT1"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_INT_LVL_SET/CLR ,Receive DMA all interrupt level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_SET/CLR ,Receiver interrupt level" "INT0,INT1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_SET/CLR ,Transmitter interrupt level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_SET/CLR ,Wake-up interrupt level" "INT0,INT1"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_SET/CLR ,Break-detect interrupt level" "INT0,INT1"
|
|
textline " "
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FLR,SCI Flags Register"
|
|
eventfld.long 0x00 26. " FE ,Framing error flag" "No error,Error"
|
|
eventfld.long 0x00 25. " OE ,Overrun error flag" "No error,Error"
|
|
eventfld.long 0x00 24. " PE ,Parity error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RXWAKE ,Receiver wakeup detect flag" "Not address,Address"
|
|
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter empty flag" "Not empty,Empty"
|
|
bitfld.long 0x00 10. " TXWAKE ,SCI transmitter wakeup method select" "Data,Address"
|
|
textline " "
|
|
eventfld.long 0x00 9. " RXRDY ,Receiver ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " TXRDY ,Transmitter buffer register ready flag" "Full,Ready"
|
|
bitfld.long 0x00 3. " BUSY ,BUSY flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLE ,SCI receiver in idle state" "Detected,Not detected"
|
|
eventfld.long 0x00 1. " WAKEUP ,Wake-up flag" "No wake up,Wake up"
|
|
eventfld.long 0x00 0. " BRKDT ,SCI break-detect flag" "Not detected,Detected"
|
|
textline " "
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "INVECT0,SCI Interrupt Vector Offset 0"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "INVECT1,SCI Interrupt Vector Offset 1"
|
|
in
|
|
textline " "
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "FORMAT,SCI Format Control Register"
|
|
bitfld.long 0x00 0.--2. " CHAR ,SCI character length" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
|
|
line.long 0x04 "BRS,Baud Rate Selection Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " BAUD ,SCI 24-bit baud selection"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "ED,Receiver Emulation Data Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulator data"
|
|
textline " "
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "RD,Receiver Data Buffer"
|
|
in
|
|
textline " "
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "TD,Transmit Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit data"
|
|
line.long 0x04 "PIO0,SCI Pin I/O Control Register 0"
|
|
bitfld.long 0x04 2. " TX_FUNC ,Defines the function of pin SCITX" "GPIO,SCI"
|
|
bitfld.long 0x04 1. " RX_FUNC ,Defines the function of pin SCIRX" "GPIO,SCI"
|
|
if (((per.l(ad:0xFFF7E500+0x3C))&0x06)==0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PIO1,SCI Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive direction" "Input,Output"
|
|
elif (((per.l(ad:0xFFF7E500+0x3C))&0x06)==0x02)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PIO1,SCI Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit direction" "Input,Output"
|
|
elif (((per.l(ad:0xFFF7E500+0x3C))&0x06)==0x04)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PIO1,SCI Pin I/O Control Register 1"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive direction" "Input,Output"
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "PIO1,SCI Pin I/O Control Register 1"
|
|
endif
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "PIO2,SCI Pin I/O Control Register 2"
|
|
bitfld.long 0x00 2. " TX_IN ,Current value on the SCITX pin" "Low,High"
|
|
bitfld.long 0x00 1. " RX_IN ,Current value on the SCIRX pin" "Low,High"
|
|
if (((per.l(ad:0xFFF7E500+0x3C))&0x06)==0x00)&&(((per.l(ad:0xFFF7E500+0x40))&0x06)==0x06)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO3,SCI Pin I/O Control Register 3"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX_OUT_SET/CLR ,SCITX pin data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX_OUT_SET/CLR ,SCIRX pin data output" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PIO6,SCI Pin I/O Control Register 6"
|
|
bitfld.long 0x00 2. " TX_PDR ,TX pin open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RX_PDR ,RX pin open drain enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFF7E500+0x3C))&0x04)==0x00)&&(((per.l(ad:0xFFF7E500+0x40))&0x04)==0x04)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO3,SCI Pin I/O Control Register 3"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX_OUT_SET/CLR ,SCITX pin data output" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PIO6,SCI Pin I/O Control Register 6"
|
|
bitfld.long 0x00 2. " TX_PDR ,TX pin open drain enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFF7E500+0x3C))&0x02)==0x00)&&(((per.l(ad:0xFFF7E500+0x40))&0x02)==0x02)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO3,SCI Pin I/O Control Register 3"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX_OUT_SET/CLR ,SCIRX pin data output" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PIO6,SCI Pin I/O Control Register 6"
|
|
bitfld.long 0x00 1. " RX_PDR ,RX pin open drain enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "PIO3,SCI Pin I/O Control Register 3"
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "PIO6,SCI Pin I/O Control Register 6"
|
|
endif
|
|
group.long 0x58++0x07
|
|
line.long 0x00 "PIO7,SCI Pin I/O Control Register 7"
|
|
bitfld.long 0x00 2. " TX_PD ,TX pin pull control disable" "No,Yes"
|
|
bitfld.long 0x00 1. " RX_PD ,RX pin pull control disable" "No,Yes"
|
|
line.long 0x04 "PIO8,SCI Pin I/O Control Register 8"
|
|
bitfld.long 0x04 2. " TX_PSL ,TX pin pull select" "Pull down,Pull up"
|
|
bitfld.long 0x04 1. " RX_PSL ,RX pin pull select" "Pull down,Pull up"
|
|
textline " "
|
|
if (((per.l(ad:0xFFF7E500+0x90))&0xF00)==0xA00)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "IODFTCTRL,Input/Output Error Enable Register"
|
|
bitfld.long 0x00 26. " FEN ,Frame error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PEN ,Parity error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " BRKD_TENA ,Break detect error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--20. " PSM ,Pin sample mask" "Not used,Inverted at 7th SCLK,Inverted at 8th SCLK,Inverted at 9th SCLK"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit shift" "No delay,1 SCLK,2 SCLK,3 SCLK,4 SCLK,5 SCLK,6 SCLK,No delay"
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IODFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXPENA ,Module analog loopback through receive/transmit pin enable" "Transmit,Receive"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "IODFTCTRL,Input/Output Error Enable Register"
|
|
bitfld.long 0x00 26. " FEN ,Frame error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PEN ,Parity error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " BRKD_TENA ,Break detect error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "Not used,Inverted at 7th SCLK,Inverted at 8th SCLK,Inverted at 9th SCLK"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit shift" "No delay,1 SCLK,2 SCLK,3 SCLK,4 SCLK,5 SCLK,6 SCLK,No delay"
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCI-B"
|
|
base ad:0xFFF7E700
|
|
width 11.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR0,SCI Global Control Register 0"
|
|
bitfld.long 0x00 0. " RESET ,SCI module reset" "Reset,No reset"
|
|
if (((per.l(ad:0xFFF7E700+0x04))&0x04)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GCR1,SCI Global Control Register 1"
|
|
bitfld.long 0x00 25. " TXENA ,SCI transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CONT ,Continue on suspend" "Frozen,Continued"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,Loop back mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POWERDOWN ,Power down" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI sleep enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SW_NRESET ,Software reset" "Reset,Ready"
|
|
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 4. " STOP ,SCI number of stop bits per frame" "1 bit,2 bits"
|
|
bitfld.long 0x00 3. " PARITY ,SCI parity odd/even selection" "Odd,Even"
|
|
bitfld.long 0x00 2. " PARITY_ENA ,Parity enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI timing mode" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI communication mode" "Idle-line,Address-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GCR1,SCI Global Control Register 1"
|
|
bitfld.long 0x00 25. " TXENA ,SCI transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CONT ,Continue on suspend" "Frozen,Continued"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,Loop back mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POWERDOWN ,Power down" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI sleep enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SW_NRESET ,Software reset" "Reset,Ready"
|
|
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 4. " STOP ,SCI number of stop bits per frame" "1 bit,2 bits"
|
|
bitfld.long 0x00 2. " PARITY_ENA ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI timing mode" "Synchronous,Asynchronous"
|
|
textline " "
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI communication mode" "Idle-line,Address-bit"
|
|
endif
|
|
textline " "
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SETINT,SCI Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_SET/CLR ,Framing-error interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_SET/CLR ,Overrun-error interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_SET/CLR ,Parity interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_SET/CLR ,Receive DMA all" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_SET/CLR ,Receive DMA" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_SET/CLR ,Transmit DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_SET/CLR ,Receiver interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_SET/CLR ,Transmitter interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_SET/CLR ,Wake-up interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_SET/CLR ,Break-detect interrupt" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SETINTLVL,SCI Interrupt Level Set/Clear Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_SET/CLR ,Framing-error interrupt level" "INT0,INT1"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_SET/CLR ,Overrun-error interrupt level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_SET/CLR ,Parity error interrupt level" "INT0,INT1"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_INT_LVL_SET/CLR ,Receive DMA all interrupt level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_SET/CLR ,Receiver interrupt level" "INT0,INT1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_SET/CLR ,Transmitter interrupt level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_SET/CLR ,Wake-up interrupt level" "INT0,INT1"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_SET/CLR ,Break-detect interrupt level" "INT0,INT1"
|
|
textline " "
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FLR,SCI Flags Register"
|
|
eventfld.long 0x00 26. " FE ,Framing error flag" "No error,Error"
|
|
eventfld.long 0x00 25. " OE ,Overrun error flag" "No error,Error"
|
|
eventfld.long 0x00 24. " PE ,Parity error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RXWAKE ,Receiver wakeup detect flag" "Not address,Address"
|
|
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter empty flag" "Not empty,Empty"
|
|
bitfld.long 0x00 10. " TXWAKE ,SCI transmitter wakeup method select" "Data,Address"
|
|
textline " "
|
|
eventfld.long 0x00 9. " RXRDY ,Receiver ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " TXRDY ,Transmitter buffer register ready flag" "Full,Ready"
|
|
bitfld.long 0x00 3. " BUSY ,BUSY flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLE ,SCI receiver in idle state" "Detected,Not detected"
|
|
eventfld.long 0x00 1. " WAKEUP ,Wake-up flag" "No wake up,Wake up"
|
|
eventfld.long 0x00 0. " BRKDT ,SCI break-detect flag" "Not detected,Detected"
|
|
textline " "
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "INVECT0,SCI Interrupt Vector Offset 0"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "INVECT1,SCI Interrupt Vector Offset 1"
|
|
in
|
|
textline " "
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "FORMAT,SCI Format Control Register"
|
|
bitfld.long 0x00 0.--2. " CHAR ,SCI character length" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
|
|
line.long 0x04 "BRS,Baud Rate Selection Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " BAUD ,SCI 24-bit baud selection"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "ED,Receiver Emulation Data Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulator data"
|
|
textline " "
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "RD,Receiver Data Buffer"
|
|
in
|
|
textline " "
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "TD,Transmit Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit data"
|
|
line.long 0x04 "PIO0,SCI Pin I/O Control Register 0"
|
|
bitfld.long 0x04 2. " TX_FUNC ,Defines the function of pin SCITX" "GPIO,SCI"
|
|
bitfld.long 0x04 1. " RX_FUNC ,Defines the function of pin SCIRX" "GPIO,SCI"
|
|
if (((per.l(ad:0xFFF7E700+0x3C))&0x06)==0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PIO1,SCI Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive direction" "Input,Output"
|
|
elif (((per.l(ad:0xFFF7E700+0x3C))&0x06)==0x02)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PIO1,SCI Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit direction" "Input,Output"
|
|
elif (((per.l(ad:0xFFF7E700+0x3C))&0x06)==0x04)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PIO1,SCI Pin I/O Control Register 1"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive direction" "Input,Output"
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "PIO1,SCI Pin I/O Control Register 1"
|
|
endif
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "PIO2,SCI Pin I/O Control Register 2"
|
|
bitfld.long 0x00 2. " TX_IN ,Current value on the SCITX pin" "Low,High"
|
|
bitfld.long 0x00 1. " RX_IN ,Current value on the SCIRX pin" "Low,High"
|
|
if (((per.l(ad:0xFFF7E700+0x3C))&0x06)==0x00)&&(((per.l(ad:0xFFF7E700+0x40))&0x06)==0x06)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO3,SCI Pin I/O Control Register 3"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX_OUT_SET/CLR ,SCITX pin data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX_OUT_SET/CLR ,SCIRX pin data output" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PIO6,SCI Pin I/O Control Register 6"
|
|
bitfld.long 0x00 2. " TX_PDR ,TX pin open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RX_PDR ,RX pin open drain enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFF7E700+0x3C))&0x04)==0x00)&&(((per.l(ad:0xFFF7E700+0x40))&0x04)==0x04)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO3,SCI Pin I/O Control Register 3"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX_OUT_SET/CLR ,SCITX pin data output" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PIO6,SCI Pin I/O Control Register 6"
|
|
bitfld.long 0x00 2. " TX_PDR ,TX pin open drain enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0xFFF7E700+0x3C))&0x02)==0x00)&&(((per.l(ad:0xFFF7E700+0x40))&0x02)==0x02)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO3,SCI Pin I/O Control Register 3"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX_OUT_SET/CLR ,SCIRX pin data output" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PIO6,SCI Pin I/O Control Register 6"
|
|
bitfld.long 0x00 1. " RX_PDR ,RX pin open drain enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "PIO3,SCI Pin I/O Control Register 3"
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "PIO6,SCI Pin I/O Control Register 6"
|
|
endif
|
|
group.long 0x58++0x07
|
|
line.long 0x00 "PIO7,SCI Pin I/O Control Register 7"
|
|
bitfld.long 0x00 2. " TX_PD ,TX pin pull control disable" "No,Yes"
|
|
bitfld.long 0x00 1. " RX_PD ,RX pin pull control disable" "No,Yes"
|
|
line.long 0x04 "PIO8,SCI Pin I/O Control Register 8"
|
|
bitfld.long 0x04 2. " TX_PSL ,TX pin pull select" "Pull down,Pull up"
|
|
bitfld.long 0x04 1. " RX_PSL ,RX pin pull select" "Pull down,Pull up"
|
|
textline " "
|
|
if (((per.l(ad:0xFFF7E700+0x90))&0xF00)==0xA00)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "IODFTCTRL,Input/Output Error Enable Register"
|
|
bitfld.long 0x00 26. " FEN ,Frame error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PEN ,Parity error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " BRKD_TENA ,Break detect error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--20. " PSM ,Pin sample mask" "Not used,Inverted at 7th SCLK,Inverted at 8th SCLK,Inverted at 9th SCLK"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit shift" "No delay,1 SCLK,2 SCLK,3 SCLK,4 SCLK,5 SCLK,6 SCLK,No delay"
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IODFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXPENA ,Module analog loopback through receive/transmit pin enable" "Transmit,Receive"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "IODFTCTRL,Input/Output Error Enable Register"
|
|
bitfld.long 0x00 26. " FEN ,Frame error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PEN ,Parity error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " BRKD_TENA ,Break detect error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "Not used,Inverted at 7th SCLK,Inverted at 8th SCLK,Inverted at 9th SCLK"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit shift" "No delay,1 SCLK,2 SCLK,3 SCLK,4 SCLK,5 SCLK,6 SCLK,No delay"
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
tree.open "DCC (Dual Clock Comparator)"
|
|
base ad:0xFFFFEC00
|
|
width 15.
|
|
tree "DCC A"
|
|
sif cpuis("AWR6843*")
|
|
group.long (0x00+0x0)++0x03
|
|
line.long 0x00 "DCCGCTRL,DCC General Control Register"
|
|
bitfld.long 0x00 12.--15. " DONENA ,Done signal enable" ",,,,,Disabled,,,,,Enabled,?..."
|
|
bitfld.long 0x00 8.--11. " SINGLESHOT ,Single/Continuous checking mode" ",,,,,Continuous,,,,,Single,?..."
|
|
bitfld.long 0x00 4.--7. " ERRENA ,Error signal enable" ",,,,,Disabled,,,,,Enabled,?..."
|
|
bitfld.long 0x00 0.--3. " DCCENA ,DCC start enable" ",,,,,Disabled,,,,,Enabled,?..."
|
|
else
|
|
group.long (0x00+0x0)++0x03
|
|
line.long 0x00 "DCCGCTRL,DCC General Control Register"
|
|
bitfld.long 0x00 12.--15. " DONENA ,Done signal enable" ",,,,Disabled,,Enabled,?..."
|
|
bitfld.long 0x00 8.--11. " SINGLESHOT ,Single/Continuous checking mode" ",,,,Continuous,,Single,?..."
|
|
bitfld.long 0x00 4.--7. " ERRENA ,Error signal enable" ",,,,Disabled,,Enabled,?..."
|
|
bitfld.long 0x00 0.--3. " DCCENA ,DCC start enable" ",,,,Disabled,,Enabled,?..."
|
|
endif
|
|
rgroup.long (0x04+0x0)++0x03
|
|
line.long 0x00 "DCCREV,DCC Revision Register"
|
|
bitfld.long 0x00 28.--30. " SCHEME ,SCHEME" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 14.--25. 1. " FUNC ,Functional release number"
|
|
bitfld.long 0x00 9.--13. " RTL ,Design release number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--8. " MAJOR ,Major revision number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. " CUSTOM ,Module special version" "0,1"
|
|
bitfld.long 0x00 0.--4. " MINOR ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x08+0x0)++0x0F
|
|
line.long 0x00 "DCCCNTSEED0,DCC Counter Seed Value 0 Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED0 ,Seed value for counter 0"
|
|
line.long 0x04 "DCCVALIDSEED0,DCC Valid Duration Counter Seed Value 0 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALIDSEED0 ,Seed value for valid duration counter 0"
|
|
line.long 0x08 "DCCCNTSEED1,DCC Counter Seed Value 1 Register"
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " COUNTSEED1 ,Seed value for counter 1"
|
|
line.long 0x0C "DCCSTAT,DCC Status Register"
|
|
bitfld.long 0x0C 1. " DONE ,Done flag status" "Occurred,Not Occurred"
|
|
bitfld.long 0x0C 0. " ERR ,Error flag status" "Occurred,Not Occurred"
|
|
rgroup.long (0x18+0x0)++0x0B
|
|
line.long 0x00 "DCCCNT0,DCC Counter Value 0 Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0 ,Counter 0 value"
|
|
line.long 0x04 "DCCVALID0,DCC Valid Counter Value 0 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALID0 ,Valid counter 0 value"
|
|
line.long 0x08 "DCCCNT1,DCC Counter Value 1 Register"
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " COUNT1 ,Counter 1 value"
|
|
group.long (0x24+0x0)++0x07
|
|
line.long 0x00 "DCCCLKSSRC1,DCC Clock Source 1 Register"
|
|
bitfld.long 0x00 12.--15. " KEY_B4 ,Key programming" ",,,,,,,,,,KEY,?..."
|
|
bitfld.long 0x00 0.--3. " CLK_SRC1 ,Clock source selection for source 0" "REF_CLK,CPU_CLK,RC_CLK,RC_CLK,RC_CLK,RC_CLK,RC_CLK,RC_CLK,?..."
|
|
line.long 0x04 "DCCCLKSSRC0,DCC Clock Source 0 Register"
|
|
bitfld.long 0x04 0.--3. " CLK_SRC0 ,Clock source selection for source 0" "REF_CLK,,,,,PPL_240,,,,,PLL_600,?..."
|
|
tree.end
|
|
tree "DCC B"
|
|
sif cpuis("AWR6843*")
|
|
group.long (0x00+0x800)++0x03
|
|
line.long 0x00 "DCCGCTRL,DCC General Control Register"
|
|
bitfld.long 0x00 12.--15. " DONENA ,Done signal enable" ",,,,,Disabled,,,,,Enabled,?..."
|
|
bitfld.long 0x00 8.--11. " SINGLESHOT ,Single/Continuous checking mode" ",,,,,Continuous,,,,,Single,?..."
|
|
bitfld.long 0x00 4.--7. " ERRENA ,Error signal enable" ",,,,,Disabled,,,,,Enabled,?..."
|
|
bitfld.long 0x00 0.--3. " DCCENA ,DCC start enable" ",,,,,Disabled,,,,,Enabled,?..."
|
|
else
|
|
group.long (0x00+0x800)++0x03
|
|
line.long 0x00 "DCCGCTRL,DCC General Control Register"
|
|
bitfld.long 0x00 12.--15. " DONENA ,Done signal enable" ",,,,Disabled,,Enabled,?..."
|
|
bitfld.long 0x00 8.--11. " SINGLESHOT ,Single/Continuous checking mode" ",,,,Continuous,,Single,?..."
|
|
bitfld.long 0x00 4.--7. " ERRENA ,Error signal enable" ",,,,Disabled,,Enabled,?..."
|
|
bitfld.long 0x00 0.--3. " DCCENA ,DCC start enable" ",,,,Disabled,,Enabled,?..."
|
|
endif
|
|
rgroup.long (0x04+0x800)++0x03
|
|
line.long 0x00 "DCCREV,DCC Revision Register"
|
|
bitfld.long 0x00 28.--30. " SCHEME ,SCHEME" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 14.--25. 1. " FUNC ,Functional release number"
|
|
bitfld.long 0x00 9.--13. " RTL ,Design release number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 6.--8. " MAJOR ,Major revision number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. " CUSTOM ,Module special version" "0,1"
|
|
bitfld.long 0x00 0.--4. " MINOR ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x08+0x800)++0x0F
|
|
line.long 0x00 "DCCCNTSEED0,DCC Counter Seed Value 0 Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNTSEED0 ,Seed value for counter 0"
|
|
line.long 0x04 "DCCVALIDSEED0,DCC Valid Duration Counter Seed Value 0 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALIDSEED0 ,Seed value for valid duration counter 0"
|
|
line.long 0x08 "DCCCNTSEED1,DCC Counter Seed Value 1 Register"
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " COUNTSEED1 ,Seed value for counter 1"
|
|
line.long 0x0C "DCCSTAT,DCC Status Register"
|
|
bitfld.long 0x0C 1. " DONE ,Done flag status" "Occurred,Not Occurred"
|
|
bitfld.long 0x0C 0. " ERR ,Error flag status" "Occurred,Not Occurred"
|
|
rgroup.long (0x18+0x800)++0x0B
|
|
line.long 0x00 "DCCCNT0,DCC Counter Value 0 Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0 ,Counter 0 value"
|
|
line.long 0x04 "DCCVALID0,DCC Valid Counter Value 0 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALID0 ,Valid counter 0 value"
|
|
line.long 0x08 "DCCCNT1,DCC Counter Value 1 Register"
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " COUNT1 ,Counter 1 value"
|
|
group.long (0x24+0x800)++0x07
|
|
line.long 0x00 "DCCCLKSSRC1,DCC Clock Source 1 Register"
|
|
bitfld.long 0x00 12.--15. " KEY_B4 ,Key programming" ",,,,,,,,,,KEY,?..."
|
|
bitfld.long 0x00 0.--3. " CLK_SRC1 ,Clock source selection for source 0" "VCLK,DSS_CLK,BSS_CLK,QSPI_CLK,FDCAN_CLK,RED_CLK,CPU_CLK,RC_CLK,?..."
|
|
line.long 0x04 "DCCCLKSSRC0,DCC Clock Source 0 Register"
|
|
bitfld.long 0x04 0.--3. " CLK_SRC0 ,Clock source selection for source 0" "PLL_600,,,,,CPU_CLK,,,,,VCLK,?..."
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree.open "DCC (Dual Clock Comparator)"
|
|
tree "DCC-A"
|
|
base ad:0xFFFFEC00
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCTRL,Global Control Register"
|
|
bitfld.long 0x00 12.--15. " DONE_INT_ENA ,Done interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " SINGLE_SHOT ,Single-Shot mode enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Enabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 4.--7. " ERR_ENA ,Error interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DCC_ENA ,DCC enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "REV,Revision ID"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Functional release number"
|
|
bitfld.long 0x00 11.--15. " RTL ,Design release number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major revision number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom version number" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " MINOR ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CNTSEED0,DCC Counter0 Seed Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0_SEED ,Seed value for DCC counter0"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "VALIDSEED0,Valid0 Seed Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALID0_SEED ,Seed value for DCC valid0"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CNTSEED1,DCC Counter1 Seed Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1_SEED ,Seed value for DCC counter1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,Status Register"
|
|
eventfld.long 0x00 1. " DONE_FLG ,Single-Shot sequence done flag" "Not done,Done"
|
|
eventfld.long 0x00 0. " ERR_FLG ,Error flag" "No error,Error"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "CNT0,DCC Counter0 Value Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0 ,Value of DCC counter0"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "VALID0,Valid0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALID0 ,Current value for DCC valid0"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CNT1,DCC Counter1 Value Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1 ,Value of DCC counter1"
|
|
if (((per.l(ad:0xFFFFEC00+0x24))&0xF000)==0xA000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CNT0CLKSRC,DCC Counter0 Clock Source Selection Register"
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DCC-B"
|
|
base ad:0xFFFFF400
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCTRL,Global Control Register"
|
|
bitfld.long 0x00 12.--15. " DONE_INT_ENA ,Done interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " SINGLE_SHOT ,Single-Shot mode enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Enabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 4.--7. " ERR_ENA ,Error interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DCC_ENA ,DCC enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "REV,Revision ID"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Functional release number"
|
|
bitfld.long 0x00 11.--15. " RTL ,Design release number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. " MAJOR ,Major revision number" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 6.--7. " CUSTOM ,Custom version number" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. " MINOR ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CNTSEED0,DCC Counter0 Seed Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0_SEED ,Seed value for DCC counter0"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "VALIDSEED0,Valid0 Seed Value"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALID0_SEED ,Seed value for DCC valid0"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CNTSEED1,DCC Counter1 Seed Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1_SEED ,Seed value for DCC counter1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,Status Register"
|
|
eventfld.long 0x00 1. " DONE_FLG ,Single-Shot sequence done flag" "Not done,Done"
|
|
eventfld.long 0x00 0. " ERR_FLG ,Error flag" "No error,Error"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "CNT0,DCC Counter0 Value Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0 ,Value of DCC counter0"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "VALID0,Valid0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALID0 ,Current value for DCC valid0"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CNT1,DCC Counter1 Value Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1 ,Value of DCC counter1"
|
|
if (((per.l(ad:0xFFFFF400+0x24))&0xF000)==0xA000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CNT1CLKSRC,DCC Counter1 Clock Source Selection Register"
|
|
bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CNT0CLKSRC,DCC Counter0 Clock Source Selection Register"
|
|
bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "ESM (Error Signaling Module)"
|
|
base ad:0xFFFFF500
|
|
width 19.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ESMIEPSR1_SET/CLR,ESM Influence Error Pin Set/Status Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " IEPSET[31] ,Set/Clear influence on error pin 31" "No influence,Influence"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear influence on error pin 30" "No influence,Influence"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Set/Clear influence on error pin 29" "No influence,Influence"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear influence on error pin 28" "No influence,Influence"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear influence on error pin 27" "No influence,Influence"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear influence on error pin 26" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Set/Clear influence on error pin 25" "No influence,Influence"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear influence on error pin 24" "No influence,Influence"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear influence on error pin 23" "No influence,Influence"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear influence on error pin 22" "No influence,Influence"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear influence on error pin 21" "No influence,Influence"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/Clear influence on error pin 20" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear influence on error pin 19" "No influence,Influence"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear influence on error pin 18" "No influence,Influence"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear influence on error pin 17" "No influence,Influence"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear influence on error pin 16" "No influence,Influence"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear influence on error pin 15" "No influence,Influence"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear influence on error pin 14" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear influence on error pin 13" "No influence,Influence"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear influence on error pin 12" "No influence,Influence"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear influence on error pin 11" "No influence,Influence"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear influence on error pin 10" "No influence,Influence"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear influence on error pin 9" "No influence,Influence"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear influence on error pin 8" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear influence on error pin 7" "No influence,Influence"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear influence on error pin 6" "No influence,Influence"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear influence on error pin 5" "No influence,Influence"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/Clear influence on error pin 4" "No influence,Influence"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear influence on error pin 3" "No influence,Influence"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear influence on error pin 2" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear influence on error pin 1" "No influence,Influence"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set/Clear influence on error pin 0" "No influence,Influence"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ESMIESR1_SET/CLR,ESM Interrupt Enable Set/Status Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTENSET[31] ,Set/Clear interrupt enable 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear interrupt enable 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Set/Clear interrupt enable 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear interrupt enable 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear interrupt enable 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear interrupt enable 26" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Set/Clear interrupt enable 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear interrupt enable 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear interrupt enable 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear interrupt enable 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear interrupt enable 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/Clear interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear interrupt enable 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear interrupt enable 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear interrupt enable 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear interrupt enable 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear interrupt enable 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear interrupt enable 14" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear interrupt enable 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear interrupt enable 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear interrupt enable 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear interrupt enable 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt enable 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear interrupt enable 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear interrupt enable 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear interrupt enable 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/Clear interrupt enable 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear interrupt enable 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear interrupt enable 2" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear interrupt enable 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set/Clear interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ESMILSR1_SET/CLR,ESM Interrupt Level Set/Status Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVLSET[31] ,Set/Clear interrupt level 31" "Low,High"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear interrupt level 30" "Low,High"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Set/Clear interrupt level 29" "Low,High"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear interrupt level 28" "Low,High"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear interrupt level 27" "Low,High"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear interrupt level 26" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Set/Clear interrupt level 25" "Low,High"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear interrupt level 24" "Low,High"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear interrupt level 23" "Low,High"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear interrupt level 22" "Low,High"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear interrupt level 21" "Low,High"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/Clear interrupt level 20" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear interrupt level 19" "Low,High"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear interrupt level 18" "Low,High"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear interrupt level 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear interrupt level 16" "Low,High"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear interrupt level 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear interrupt level 14" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear interrupt level 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear interrupt level 12" "Low,High"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear interrupt level 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear interrupt level 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt level 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt level 8" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear interrupt level 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear interrupt level 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear interrupt level 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/Clear interrupt level 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear interrupt level 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear interrupt level 2" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear interrupt level 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set/Clear interrupt level 0" "Low,High"
|
|
group.long 0x18++0x0B
|
|
line.long 0x00 "ESMSR1,ESM Status Register 1"
|
|
eventfld.long 0x00 31. " ESF[31] ,Error status flag 31" "No error,Error"
|
|
eventfld.long 0x00 30. " [30] ,Error status flag 30" "No error,Error"
|
|
eventfld.long 0x00 29. " [29] ,Error status flag 29" "No error,Error"
|
|
eventfld.long 0x00 28. " [28] ,Error status flag 28" "No error,Error"
|
|
eventfld.long 0x00 27. " [27] ,Error status flag 27" "No error,Error"
|
|
eventfld.long 0x00 26. " [26] ,Error status flag 26" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 25. " [25] ,Error status flag 25" "No error,Error"
|
|
eventfld.long 0x00 24. " [24] ,Error status flag 24" "No error,Error"
|
|
eventfld.long 0x00 23. " [23] ,Error status flag 23" "No error,Error"
|
|
eventfld.long 0x00 22. " [22] ,Error status flag 22" "No error,Error"
|
|
eventfld.long 0x00 21. " [21] ,Error status flag 21" "No error,Error"
|
|
eventfld.long 0x00 20. " [20] ,Error status flag 20" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Error status flag 19" "No error,Error"
|
|
eventfld.long 0x00 18. " [18] ,Error status flag 18" "No error,Error"
|
|
eventfld.long 0x00 17. " [17] ,Error status flag 17" "No error,Error"
|
|
eventfld.long 0x00 16. " [16] ,Error status flag 16" "No error,Error"
|
|
eventfld.long 0x00 15. " [15] ,Error status flag 15" "No error,Error"
|
|
eventfld.long 0x00 14. " [14] ,Error status flag 14" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 13. " [13] ,Error status flag 13" "No error,Error"
|
|
eventfld.long 0x00 12. " [12] ,Error status flag 12" "No error,Error"
|
|
eventfld.long 0x00 11. " [11] ,Error status flag 11" "No error,Error"
|
|
eventfld.long 0x00 10. " [10] ,Error status flag 10" "No error,Error"
|
|
eventfld.long 0x00 9. " [9] ,Error status flag 9" "No error,Error"
|
|
eventfld.long 0x00 8. " [8] ,Error status flag 8" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Error status flag 7" "No error,Error"
|
|
eventfld.long 0x00 6. " [6] ,Error status flag 6" "No error,Error"
|
|
eventfld.long 0x00 5. " [5] ,Error status flag 5" "No error,Error"
|
|
eventfld.long 0x00 4. " [4] ,Error status flag 4" "No error,Error"
|
|
eventfld.long 0x00 3. " [3] ,Error status flag 3" "No error,Error"
|
|
eventfld.long 0x00 2. " [2] ,Error status flag 2" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 1. " [1] ,Error status flag 1" "No error,Error"
|
|
eventfld.long 0x00 0. " [0] ,Error status flag 0" "No error,Error"
|
|
line.long 0x04 "ESMSR2,ESM Status Register 2"
|
|
eventfld.long 0x04 31. " ESF[31] ,Error status flag 31" "No error,Error"
|
|
eventfld.long 0x04 30. " [30] ,Error status flag 30" "No error,Error"
|
|
eventfld.long 0x04 29. " [29] ,Error status flag 29" "No error,Error"
|
|
eventfld.long 0x04 28. " [28] ,Error status flag 28" "No error,Error"
|
|
eventfld.long 0x04 27. " [27] ,Error status flag 27" "No error,Error"
|
|
eventfld.long 0x04 26. " [26] ,Error status flag 26" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 25. " [25] ,Error status flag 25" "No error,Error"
|
|
eventfld.long 0x04 24. " [24] ,Error status flag 24" "No error,Error"
|
|
eventfld.long 0x04 23. " [23] ,Error status flag 23" "No error,Error"
|
|
eventfld.long 0x04 22. " [22] ,Error status flag 22" "No error,Error"
|
|
eventfld.long 0x04 21. " [21] ,Error status flag 21" "No error,Error"
|
|
eventfld.long 0x04 20. " [20] ,Error status flag 20" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 19. " [19] ,Error status flag 19" "No error,Error"
|
|
eventfld.long 0x04 18. " [18] ,Error status flag 18" "No error,Error"
|
|
eventfld.long 0x04 17. " [17] ,Error status flag 17" "No error,Error"
|
|
eventfld.long 0x04 16. " [16] ,Error status flag 16" "No error,Error"
|
|
eventfld.long 0x04 15. " [15] ,Error status flag 15" "No error,Error"
|
|
eventfld.long 0x04 14. " [14] ,Error status flag 14" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 13. " [13] ,Error status flag 13" "No error,Error"
|
|
eventfld.long 0x04 12. " [12] ,Error status flag 12" "No error,Error"
|
|
eventfld.long 0x04 11. " [11] ,Error status flag 11" "No error,Error"
|
|
eventfld.long 0x04 10. " [10] ,Error status flag 10" "No error,Error"
|
|
eventfld.long 0x04 9. " [9] ,Error status flag 9" "No error,Error"
|
|
eventfld.long 0x04 8. " [8] ,Error status flag 8" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 7. " [7] ,Error status flag 7" "No error,Error"
|
|
eventfld.long 0x04 6. " [6] ,Error status flag 6" "No error,Error"
|
|
eventfld.long 0x04 5. " [5] ,Error status flag 5" "No error,Error"
|
|
eventfld.long 0x04 4. " [4] ,Error status flag 4" "No error,Error"
|
|
eventfld.long 0x04 3. " [3] ,Error status flag 3" "No error,Error"
|
|
eventfld.long 0x04 2. " [2] ,Error status flag 2" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 1. " [1] ,Error status flag 1" "No error,Error"
|
|
eventfld.long 0x04 0. " [0] ,Error status flag 0" "No error,Error"
|
|
line.long 0x08 "ESMSR3,ESM Status Register 3"
|
|
eventfld.long 0x08 31. " ESF[31] ,Error status flag 31" "No error,Error"
|
|
eventfld.long 0x08 30. " [30] ,Error status flag 30" "No error,Error"
|
|
eventfld.long 0x08 29. " [29] ,Error status flag 29" "No error,Error"
|
|
eventfld.long 0x08 28. " [28] ,Error status flag 28" "No error,Error"
|
|
eventfld.long 0x08 27. " [27] ,Error status flag 27" "No error,Error"
|
|
eventfld.long 0x08 26. " [26] ,Error status flag 26" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 25. " [25] ,Error status flag 25" "No error,Error"
|
|
eventfld.long 0x08 24. " [24] ,Error status flag 24" "No error,Error"
|
|
eventfld.long 0x08 23. " [23] ,Error status flag 23" "No error,Error"
|
|
eventfld.long 0x08 22. " [22] ,Error status flag 22" "No error,Error"
|
|
eventfld.long 0x08 21. " [21] ,Error status flag 21" "No error,Error"
|
|
eventfld.long 0x08 20. " [20] ,Error status flag 20" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 19. " [19] ,Error status flag 19" "No error,Error"
|
|
eventfld.long 0x08 18. " [18] ,Error status flag 18" "No error,Error"
|
|
eventfld.long 0x08 17. " [17] ,Error status flag 17" "No error,Error"
|
|
eventfld.long 0x08 16. " [16] ,Error status flag 16" "No error,Error"
|
|
eventfld.long 0x08 15. " [15] ,Error status flag 15" "No error,Error"
|
|
eventfld.long 0x08 14. " [14] ,Error status flag 14" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 13. " [13] ,Error status flag 13" "No error,Error"
|
|
eventfld.long 0x08 12. " [12] ,Error status flag 12" "No error,Error"
|
|
eventfld.long 0x08 11. " [11] ,Error status flag 11" "No error,Error"
|
|
eventfld.long 0x08 10. " [10] ,Error status flag 10" "No error,Error"
|
|
eventfld.long 0x08 9. " [9] ,Error status flag 9" "No error,Error"
|
|
eventfld.long 0x08 8. " [8] ,Error status flag 8" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 7. " [7] ,Error status flag 7" "No error,Error"
|
|
eventfld.long 0x08 6. " [6] ,Error status flag 6" "No error,Error"
|
|
eventfld.long 0x08 5. " [5] ,Error status flag 5" "No error,Error"
|
|
eventfld.long 0x08 4. " [4] ,Error status flag 4" "No error,Error"
|
|
eventfld.long 0x08 3. " [3] ,Error status flag 3" "No error,Error"
|
|
eventfld.long 0x08 2. " [2] ,Error status flag 2" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 1. " [1] ,Error status flag 1" "No error,Error"
|
|
eventfld.long 0x08 0. " [0] ,Error status flag 0" "No error,Error"
|
|
rgroup.long 0x24++0x0B
|
|
line.long 0x00 "ESMEPSR,ESM Error Pin Status Register"
|
|
bitfld.long 0x00 0. " EPSF ,Error pin status flag" "Occurred,Not Occurred"
|
|
line.long 0x04 "ESMIOFFHR,ESM Interrupt Offset High Register"
|
|
hexmask.long.byte 0x04 0.--6. 1. " INTOFFH ,Offset high level interrupt"
|
|
line.long 0x08 "ESMIOFFLR,ESM Interrupt Offset Low Register"
|
|
hexmask.long.byte 0x08 0.--6. 1. " INTOFFL ,Offset low level interrupt"
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "ESMLTCR,ESM Low-Time Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LTCP ,Error Pin Low-Time Counter"
|
|
line.long 0x04 "ESMLTCPR,ESM Low-Time Counter Preload Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " LTCP ,Low-time counter pre-load value"
|
|
line.long 0x08 "ESMEKR,ESM Error Key Register"
|
|
bitfld.long 0x08 0.--3. " EKEY ,Error Key" "Normal,Normal,Normal,Normal,Normal,LTC,Normal,Normal,Normal,Normal,Forced,Normal,Normal,Normal,Normal,Normal"
|
|
line.long 0x0C "ESMSSR2,ESM Status Shadow Register 2"
|
|
eventfld.long 0x0C 31. " ESF[31] ,Error status flag 31" "No error,Error"
|
|
eventfld.long 0x0C 30. " [30] ,Error status flag 30" "No error,Error"
|
|
eventfld.long 0x0C 29. " [29] ,Error status flag 29" "No error,Error"
|
|
eventfld.long 0x0C 28. " [28] ,Error status flag 28" "No error,Error"
|
|
eventfld.long 0x0C 27. " [27] ,Error status flag 27" "No error,Error"
|
|
eventfld.long 0x0C 26. " [26] ,Error status flag 26" "No error,Error"
|
|
newline
|
|
eventfld.long 0x0C 25. " [25] ,Error status flag 25" "No error,Error"
|
|
eventfld.long 0x0C 24. " [24] ,Error status flag 24" "No error,Error"
|
|
eventfld.long 0x0C 23. " [23] ,Error status flag 23" "No error,Error"
|
|
eventfld.long 0x0C 22. " [22] ,Error status flag 22" "No error,Error"
|
|
eventfld.long 0x0C 21. " [21] ,Error status flag 21" "No error,Error"
|
|
eventfld.long 0x0C 20. " [20] ,Error status flag 20" "No error,Error"
|
|
newline
|
|
eventfld.long 0x0C 19. " [19] ,Error status flag 19" "No error,Error"
|
|
eventfld.long 0x0C 18. " [18] ,Error status flag 18" "No error,Error"
|
|
eventfld.long 0x0C 17. " [17] ,Error status flag 17" "No error,Error"
|
|
eventfld.long 0x0C 16. " [16] ,Error status flag 16" "No error,Error"
|
|
eventfld.long 0x0C 15. " [15] ,Error status flag 15" "No error,Error"
|
|
eventfld.long 0x0C 14. " [14] ,Error status flag 14" "No error,Error"
|
|
newline
|
|
eventfld.long 0x0C 13. " [13] ,Error status flag 13" "No error,Error"
|
|
eventfld.long 0x0C 12. " [12] ,Error status flag 12" "No error,Error"
|
|
eventfld.long 0x0C 11. " [11] ,Error status flag 11" "No error,Error"
|
|
eventfld.long 0x0C 10. " [10] ,Error status flag 10" "No error,Error"
|
|
eventfld.long 0x0C 9. " [9] ,Error status flag 9" "No error,Error"
|
|
eventfld.long 0x0C 8. " [8] ,Error status flag 8" "No error,Error"
|
|
newline
|
|
eventfld.long 0x0C 7. " [7] ,Error status flag 7" "No error,Error"
|
|
eventfld.long 0x0C 6. " [6] ,Error status flag 6" "No error,Error"
|
|
eventfld.long 0x0C 5. " [5] ,Error status flag 5" "No error,Error"
|
|
eventfld.long 0x0C 4. " [4] ,Error status flag 4" "No error,Error"
|
|
eventfld.long 0x0C 3. " [3] ,Error status flag 3" "No error,Error"
|
|
eventfld.long 0x0C 2. " [2] ,Error status flag 2" "No error,Error"
|
|
newline
|
|
eventfld.long 0x0C 1. " [1] ,Error status flag 1" "No error,Error"
|
|
eventfld.long 0x0C 0. " [0] ,Error status flag 0" "No error,Error"
|
|
line.long 0x10 "ESMIEPSR4_SET/CLR,ESM Influence Error Pin Set/Status Register 4"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x04 31. " IEPSET[31] ,Set/Clear influence on error pin 31" "No influence,Influence"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x04 30. " [30] ,Set/Clear influence on error pin 30" "No influence,Influence"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x04 29. " [29] ,Set/Clear influence on error pin 29" "No influence,Influence"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x04 28. " [28] ,Set/Clear influence on error pin 28" "No influence,Influence"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x04 27. " [27] ,Set/Clear influence on error pin 27" "No influence,Influence"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x04 26. " [26] ,Set/Clear influence on error pin 26" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x10 25. 0x10 25. 0x04 25. " [25] ,Set/Clear influence on error pin 25" "No influence,Influence"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x04 24. " [24] ,Set/Clear influence on error pin 24" "No influence,Influence"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x04 23. " [23] ,Set/Clear influence on error pin 23" "No influence,Influence"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x04 22. " [22] ,Set/Clear influence on error pin 22" "No influence,Influence"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x04 21. " [21] ,Set/Clear influence on error pin 21" "No influence,Influence"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x04 20. " [20] ,Set/Clear influence on error pin 20" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x10 19. 0x10 19. 0x04 19. " [19] ,Set/Clear influence on error pin 19" "No influence,Influence"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x04 18. " [18] ,Set/Clear influence on error pin 18" "No influence,Influence"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x04 17. " [17] ,Set/Clear influence on error pin 17" "No influence,Influence"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x04 16. " [16] ,Set/Clear influence on error pin 16" "No influence,Influence"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x04 15. " [15] ,Set/Clear influence on error pin 15" "No influence,Influence"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x04 14. " [14] ,Set/Clear influence on error pin 14" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x10 13. 0x10 13. 0x04 13. " [13] ,Set/Clear influence on error pin 13" "No influence,Influence"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x04 12. " [12] ,Set/Clear influence on error pin 12" "No influence,Influence"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x04 11. " [11] ,Set/Clear influence on error pin 11" "No influence,Influence"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x04 10. " [10] ,Set/Clear influence on error pin 10" "No influence,Influence"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x04 9. " [9] ,Set/Clear influence on error pin 9" "No influence,Influence"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x04 8. " [8] ,Set/Clear influence on error pin 8" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x10 7. 0x10 7. 0x04 7. " [7] ,Set/Clear influence on error pin 7" "No influence,Influence"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x04 6. " [6] ,Set/Clear influence on error pin 6" "No influence,Influence"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x04 5. " [5] ,Set/Clear influence on error pin 5" "No influence,Influence"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x04 4. " [4] ,Set/Clear influence on error pin 4" "No influence,Influence"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x04 3. " [3] ,Set/Clear influence on error pin 3" "No influence,Influence"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x04 2. " [2] ,Set/Clear influence on error pin 2" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x10 1. 0x10 1. 0x04 1. " [1] ,Set/Clear influence on error pin 1" "No influence,Influence"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x04 0. " [0] ,Set/Clear influence on error pin 0" "No influence,Influence"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "ESMIESR4_SET/CLR,ESM Interrupt Enable Set/Status Register 4"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTENSET[31] ,Set/Clear interrupt enable 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear interrupt enable 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Set/Clear interrupt enable 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear interrupt enable 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear interrupt enable 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear interrupt enable 26" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Set/Clear interrupt enable 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear interrupt enable 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear interrupt enable 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear interrupt enable 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear interrupt enable 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/Clear interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear interrupt enable 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear interrupt enable 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear interrupt enable 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear interrupt enable 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear interrupt enable 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear interrupt enable 14" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear interrupt enable 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear interrupt enable 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear interrupt enable 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear interrupt enable 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt enable 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear interrupt enable 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear interrupt enable 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear interrupt enable 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/Clear interrupt enable 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear interrupt enable 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear interrupt enable 2" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear interrupt enable 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set/Clear interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "ESMILSR4_SET/CLR,ESM Interrupt Level Set/Status Register 4"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVLSET[31] ,Set/Clear interrupt level 31" "Low,High"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear interrupt level 30" "Low,High"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Set/Clear interrupt level 29" "Low,High"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear interrupt level 28" "Low,High"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear interrupt level 27" "Low,High"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear interrupt level 26" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Set/Clear interrupt level 25" "Low,High"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear interrupt level 24" "Low,High"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear interrupt level 23" "Low,High"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear interrupt level 22" "Low,High"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear interrupt level 21" "Low,High"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/Clear interrupt level 20" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear interrupt level 19" "Low,High"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear interrupt level 18" "Low,High"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear interrupt level 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear interrupt level 16" "Low,High"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear interrupt level 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear interrupt level 14" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear interrupt level 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear interrupt level 12" "Low,High"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear interrupt level 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear interrupt level 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt level 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt level 8" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear interrupt level 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear interrupt level 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear interrupt level 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/Clear interrupt level 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear interrupt level 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear interrupt level 2" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear interrupt level 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set/Clear interrupt level 0" "Low,High"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ESMSR4,ESM Status Register 4"
|
|
eventfld.long 0x00 31. " ESF[31] ,Error status flag 31" "No error,Error"
|
|
eventfld.long 0x00 30. " [30] ,Error status flag 30" "No error,Error"
|
|
eventfld.long 0x00 29. " [29] ,Error status flag 29" "No error,Error"
|
|
eventfld.long 0x00 28. " [28] ,Error status flag 28" "No error,Error"
|
|
eventfld.long 0x00 27. " [27] ,Error status flag 27" "No error,Error"
|
|
eventfld.long 0x00 26. " [26] ,Error status flag 26" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 25. " [25] ,Error status flag 25" "No error,Error"
|
|
eventfld.long 0x00 24. " [24] ,Error status flag 24" "No error,Error"
|
|
eventfld.long 0x00 23. " [23] ,Error status flag 23" "No error,Error"
|
|
eventfld.long 0x00 22. " [22] ,Error status flag 22" "No error,Error"
|
|
eventfld.long 0x00 21. " [21] ,Error status flag 21" "No error,Error"
|
|
eventfld.long 0x00 20. " [20] ,Error status flag 20" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Error status flag 19" "No error,Error"
|
|
eventfld.long 0x00 18. " [18] ,Error status flag 18" "No error,Error"
|
|
eventfld.long 0x00 17. " [17] ,Error status flag 17" "No error,Error"
|
|
eventfld.long 0x00 16. " [16] ,Error status flag 16" "No error,Error"
|
|
eventfld.long 0x00 15. " [15] ,Error status flag 15" "No error,Error"
|
|
eventfld.long 0x00 14. " [14] ,Error status flag 14" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 13. " [13] ,Error status flag 13" "No error,Error"
|
|
eventfld.long 0x00 12. " [12] ,Error status flag 12" "No error,Error"
|
|
eventfld.long 0x00 11. " [11] ,Error status flag 11" "No error,Error"
|
|
eventfld.long 0x00 10. " [10] ,Error status flag 10" "No error,Error"
|
|
eventfld.long 0x00 9. " [9] ,Error status flag 9" "No error,Error"
|
|
eventfld.long 0x00 8. " [8] ,Error status flag 8" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Error status flag 7" "No error,Error"
|
|
eventfld.long 0x00 6. " [6] ,Error status flag 6" "No error,Error"
|
|
eventfld.long 0x00 5. " [5] ,Error status flag 5" "No error,Error"
|
|
eventfld.long 0x00 4. " [4] ,Error status flag 4" "No error,Error"
|
|
eventfld.long 0x00 3. " [3] ,Error status flag 3" "No error,Error"
|
|
eventfld.long 0x00 2. " [2] ,Error status flag 2" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 1. " [1] ,Error status flag 1" "No error,Error"
|
|
eventfld.long 0x00 0. " [0] ,Error status flag 0" "No error,Error"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ESMIEPSR7_SET/CLR,ESM Influence Error Pin Set/Status Register 7"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " IEPSET[31] ,Set/Clear influence on error pin 31" "No influence,Influence"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear influence on error pin 30" "No influence,Influence"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Set/Clear influence on error pin 29" "No influence,Influence"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear influence on error pin 28" "No influence,Influence"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear influence on error pin 27" "No influence,Influence"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear influence on error pin 26" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Set/Clear influence on error pin 25" "No influence,Influence"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear influence on error pin 24" "No influence,Influence"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear influence on error pin 23" "No influence,Influence"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear influence on error pin 22" "No influence,Influence"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear influence on error pin 21" "No influence,Influence"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/Clear influence on error pin 20" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear influence on error pin 19" "No influence,Influence"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear influence on error pin 18" "No influence,Influence"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear influence on error pin 17" "No influence,Influence"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear influence on error pin 16" "No influence,Influence"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear influence on error pin 15" "No influence,Influence"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear influence on error pin 14" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear influence on error pin 13" "No influence,Influence"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear influence on error pin 12" "No influence,Influence"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear influence on error pin 11" "No influence,Influence"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear influence on error pin 10" "No influence,Influence"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear influence on error pin 9" "No influence,Influence"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear influence on error pin 8" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear influence on error pin 7" "No influence,Influence"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear influence on error pin 6" "No influence,Influence"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear influence on error pin 5" "No influence,Influence"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/Clear influence on error pin 4" "No influence,Influence"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear influence on error pin 3" "No influence,Influence"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear influence on error pin 2" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear influence on error pin 1" "No influence,Influence"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set/Clear influence on error pin 0" "No influence,Influence"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "ESMIESR7_SET/CLR,ESM Interrupt Enable Set/Status Register 7"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTENSET[31] ,Set/Clear interrupt enable 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear interrupt enable 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Set/Clear interrupt enable 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear interrupt enable 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear interrupt enable 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear interrupt enable 26" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Set/Clear interrupt enable 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear interrupt enable 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear interrupt enable 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear interrupt enable 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear interrupt enable 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/Clear interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear interrupt enable 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear interrupt enable 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear interrupt enable 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear interrupt enable 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear interrupt enable 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear interrupt enable 14" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear interrupt enable 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear interrupt enable 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear interrupt enable 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear interrupt enable 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt enable 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear interrupt enable 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear interrupt enable 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear interrupt enable 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/Clear interrupt enable 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear interrupt enable 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear interrupt enable 2" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear interrupt enable 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set/Clear interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "ESMILSR7_SET/CLR,ESM Interrupt Level Set/Status Register 7"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVLSET[31] ,Set/Clear interrupt level 31" "Low,High"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear interrupt level 30" "Low,High"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Set/Clear interrupt level 29" "Low,High"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear interrupt level 28" "Low,High"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear interrupt level 27" "Low,High"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear interrupt level 26" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Set/Clear interrupt level 25" "Low,High"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear interrupt level 24" "Low,High"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear interrupt level 23" "Low,High"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear interrupt level 22" "Low,High"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear interrupt level 21" "Low,High"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/Clear interrupt level 20" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear interrupt level 19" "Low,High"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear interrupt level 18" "Low,High"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear interrupt level 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear interrupt level 16" "Low,High"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear interrupt level 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear interrupt level 14" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear interrupt level 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear interrupt level 12" "Low,High"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear interrupt level 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear interrupt level 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt level 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt level 8" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear interrupt level 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear interrupt level 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear interrupt level 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/Clear interrupt level 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear interrupt level 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear interrupt level 2" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear interrupt level 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set/Clear interrupt level 0" "Low,High"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "ESMSR7,ESM Status Register 7"
|
|
eventfld.long 0x00 31. " ESF[31] ,Error status flag 31" "No error,Error"
|
|
eventfld.long 0x00 30. " [30] ,Error status flag 30" "No error,Error"
|
|
eventfld.long 0x00 29. " [29] ,Error status flag 29" "No error,Error"
|
|
eventfld.long 0x00 28. " [28] ,Error status flag 28" "No error,Error"
|
|
eventfld.long 0x00 27. " [27] ,Error status flag 27" "No error,Error"
|
|
eventfld.long 0x00 26. " [26] ,Error status flag 26" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 25. " [25] ,Error status flag 25" "No error,Error"
|
|
eventfld.long 0x00 24. " [24] ,Error status flag 24" "No error,Error"
|
|
eventfld.long 0x00 23. " [23] ,Error status flag 23" "No error,Error"
|
|
eventfld.long 0x00 22. " [22] ,Error status flag 22" "No error,Error"
|
|
eventfld.long 0x00 21. " [21] ,Error status flag 21" "No error,Error"
|
|
eventfld.long 0x00 20. " [20] ,Error status flag 20" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Error status flag 19" "No error,Error"
|
|
eventfld.long 0x00 18. " [18] ,Error status flag 18" "No error,Error"
|
|
eventfld.long 0x00 17. " [17] ,Error status flag 17" "No error,Error"
|
|
eventfld.long 0x00 16. " [16] ,Error status flag 16" "No error,Error"
|
|
eventfld.long 0x00 15. " [15] ,Error status flag 15" "No error,Error"
|
|
eventfld.long 0x00 14. " [14] ,Error status flag 14" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 13. " [13] ,Error status flag 13" "No error,Error"
|
|
eventfld.long 0x00 12. " [12] ,Error status flag 12" "No error,Error"
|
|
eventfld.long 0x00 11. " [11] ,Error status flag 11" "No error,Error"
|
|
eventfld.long 0x00 10. " [10] ,Error status flag 10" "No error,Error"
|
|
eventfld.long 0x00 9. " [9] ,Error status flag 9" "No error,Error"
|
|
eventfld.long 0x00 8. " [8] ,Error status flag 8" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Error status flag 7" "No error,Error"
|
|
eventfld.long 0x00 6. " [6] ,Error status flag 6" "No error,Error"
|
|
eventfld.long 0x00 5. " [5] ,Error status flag 5" "No error,Error"
|
|
eventfld.long 0x00 4. " [4] ,Error status flag 4" "No error,Error"
|
|
eventfld.long 0x00 3. " [3] ,Error status flag 3" "No error,Error"
|
|
eventfld.long 0x00 2. " [2] ,Error status flag 2" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 1. " [1] ,Error status flag 1" "No error,Error"
|
|
eventfld.long 0x00 0. " [0] ,Error status flag 0" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
base ad:0xFE000000
|
|
width 17.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL0,Global Control Register 0"
|
|
bitfld.long 0x00 30. " CH4_BYTE_SWAP ,Byte swap enable across data size" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CH4_BIT_SWAP ,MSB/LSB swapping" "MSB,LSB"
|
|
bitfld.long 0x00 27.--28. 31. " CH4_CRC_SEL ,CRC type select" "CRC-64,CRC-16,CRC-32,E2E Profile 4,VDA CAN/SAE-J1850 CRC-8,H2F/Autosar 4.0,CASTAGNOLI/iSCSI,E2E Profile 4"
|
|
bitfld.long 0x00 25.--26. " CH4_DW_SEL ,CRC data size select" "64 bit,16 bit,32 Bit,?..."
|
|
bitfld.long 0x00 24. " CH4_PSA_SWREST ,Channel 4 PSA software reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 22. " CH3_BYTE_SWAP ,Byte swap enable across data size" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CH3_BIT_SWAP ,MSB/LSB swapping" "MSB,LSB"
|
|
bitfld.long 0x00 19.--20. 23. " CH3_CRC_SEL ,CRC type select" "CRC-64,CRC-16,CRC-32,E2E Profile 4,VDA CAN/SAE-J1850 CRC-8,H2F/Autosar 4.0,CASTAGNOLI/iSCSI,E2E Profile 4"
|
|
bitfld.long 0x00 17.--18. " CH3_DW_SEL ,CRC data size select" "64 bit,16 bit,32 Bit,?..."
|
|
bitfld.long 0x00 16. " CH3_PSA_SWREST ,Channel 3 PSA software reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 14. " CH2_BYTE_SWAP ,Byte swap enable across data size" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CH2_BIT_SWAP ,MSB/LSB swapping" "MSB,LSB"
|
|
bitfld.long 0x00 11.--12. 15. " CH2_CRC_SEL ,CRC type select" "CRC-64,CRC-16,CRC-32,E2E Profile 4,VDA CAN/SAE-J1850 CRC-8,H2F/Autosar 4.0,CASTAGNOLI/iSCSI,E2E Profile 4"
|
|
bitfld.long 0x00 9.--10. " CH2_DW_SEL ,CRC data size select" "64 bit,16 bit,32 Bit,?..."
|
|
bitfld.long 0x00 8. " CH2_PSA_SWREST ,Channel 2 PSA software reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 6. " CH1_BYTE_SWAP ,Byte swap enable across data size" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CH1_BIT_SWAP ,MSB/LSB swapping" "MSB,LSB"
|
|
bitfld.long 0x00 3.--4. 7. " CH1_CRC_SEL ,CRC type select" "CRC-64,CRC-16,CRC-32,E2E Profile 4,VDA CAN/SAE-J1850 CRC-8,H2F/Autosar 4.0,CASTAGNOLI/iSCSI,E2E Profile 4"
|
|
bitfld.long 0x00 1.--2. " CH1_DW_SEL ,CRC data size select" "64 bit,16 bit,32 Bit,?..."
|
|
bitfld.long 0x00 0. " CH1_PSA_SWREST ,Channel 1 PSA software reset" "No reset,Reset"
|
|
newline
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " PWDN ,Power down" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CTRL2,Global Control Register 2"
|
|
bitfld.long 0x00 24.--25. " CH4_MODE ,Channel 4 mode" "Data Capture mode,Auto mode,,Full-CPU mode"
|
|
bitfld.long 0x00 16.--17. " CH3_MODE ,Channel 3 mode" "Data Capture mode,Auto mode,,Full-CPU mode"
|
|
bitfld.long 0x00 8.--9. " CH2_MODE ,Channel 2 mode" "Data Capture mode,Auto mode,,Full-CPU mode"
|
|
bitfld.long 0x00 4. " CH1_TRACEEN ,Channel 1 data trace enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CH1_MODE ,Channel 1 mode" "Data Capture mode,Auto mode,,Full-CPU mode"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "INT_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 28. -0x10 28. -0x08 28. " CH4_TIMEOUT ,Channel 4 timeout status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x10 27. -0x08 27. " CH4_UNDER ,Channel 4 underrun status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x10 26. -0x08 26. " CH4_OVER ,Channel 4 overrun status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x10 25. -0x08 25. " CH4_CRCFAIL ,Channel 4 fail status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 20. -0x10 20. -0x08 20. " CH3_TIMEOUT ,Channel 3 timeout status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x10 19. -0x08 19. " CH3_UNDER ,Channel 3 underrun status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x10 18. -0x08 18. " CH3_OVER ,Channel 3 overrun status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x10 17. -0x08 17. " CH3_CRCFAIL ,Channel 3 fail status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x10 12. -0x08 12. " CH2_TIMEOUT ,Channel 2 timeout status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x10 11. -0x08 11. " CH2_UNDER ,Channel 2 underrun status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x10 10. -0x08 10. " CH2_OVER ,Channel 2 overrun status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x10 9. -0x08 9. " CH2_CRCFAIL ,Channel 2 fail status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x10 4. -0x08 4. " CH1_TIMEOUT ,Channel 1 timeout status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x10 3. -0x08 3. " CH1_UNDER ,Channel 1 underrun status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x10 2. -0x08 2. " CH1_OVER ,Channel 1 overrun status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x10 1. -0x08 1. " CH1_CRCFAIL ,Channel 1 compare fail status" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "INT_OFFSET_REG,Interrupt Offset Register"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " OFSTREG ,CRC interrupt offset"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "BUSY,Busy Register During Auto Mode"
|
|
bitfld.long 0x00 24. " CH4_BUSY ,Channel 4 busy flag" "Not busy,Busy"
|
|
bitfld.long 0x00 16. " CH3_BUSY ,Channel 3 busy flag" "Not busy,Busy"
|
|
bitfld.long 0x00 8. " CH2_BUSY ,Channel 2 busy flag" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " CH1_BUSY ,Channel 1 busy flag" "Not busy,Busy"
|
|
group.long 0x40++0x13
|
|
line.long 0x00 "PCOUNT_REG1,Pattern Counter Pre-load Register 1"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT1 ,Number of data patterns in one sector to be compressed before a CRC is performed"
|
|
line.long 0x04 "SCOUNT_REG1,Sector Counter Pre-load Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT1 ,The number of sectors in one block of memory"
|
|
line.long 0x08 "CURSEC_REG1,Current Sector Register 1"
|
|
hexmask.long.word 0x08 0.--15. 1. " CRC_CURSEC1 ,Current sector number of which the signature verification fails"
|
|
line.long 0x0C "WDTOPLD1,Channel 1 Watchdog Timeout Preload Register A"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " CRC_WDTOPLD1 ,Number of clock cycles within which the DMA must transfer the next block of data patterns"
|
|
line.long 0x10 "BCTOPLD1,Channel 1 Block Complete Timeout Preload Register B"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " CRC_BCTOPLD1 ,Number of clock cycles within which the CRC for an entire block needs to complete"
|
|
group.long (0x40+0x20)++0x0F
|
|
line.long 0x00 "PSA_SIGREGL1,Channel 1 PSA Signature Low Register"
|
|
line.long 0x04 "PSA_SIGREGH1,Channel 1 PSA Signature High Register"
|
|
line.long 0x08 "CRC_REGL1,Channel 1 CRC Value Low Register"
|
|
line.long 0x0C "CRC_REGH1,Channel 1 CRC Value High Register"
|
|
rgroup.long (0x40+0x30)++0x0F
|
|
line.long 0x00 "PSA_SECSIGREGL1,Channel 1 PSA Sector Signature Low Register"
|
|
line.long 0x04 "PSA_SECSIGREGH1,Channel 1 PSA Sector Signature High Register"
|
|
line.long 0x08 "RAW_DATAREGL1,Channel 1 Raw Data Low Register"
|
|
line.long 0x0C "RAW_DATAREGH1,Channel 1 Raw Data High Register"
|
|
group.long 0x80++0x13
|
|
line.long 0x00 "PCOUNT_REG2,Pattern Counter Pre-load Register 2"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT2 ,Number of data patterns in one sector to be compressed before a CRC is performed"
|
|
line.long 0x04 "SCOUNT_REG2,Sector Counter Pre-load Register 2"
|
|
hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT2 ,The number of sectors in one block of memory"
|
|
line.long 0x08 "CURSEC_REG2,Current Sector Register 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " CRC_CURSEC2 ,Current sector number of which the signature verification fails"
|
|
line.long 0x0C "WDTOPLD2,Channel 2 Watchdog Timeout Preload Register A"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " CRC_WDTOPLD2 ,Number of clock cycles within which the DMA must transfer the next block of data patterns"
|
|
line.long 0x10 "BCTOPLD2,Channel 2 Block Complete Timeout Preload Register B"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " CRC_BCTOPLD2 ,Number of clock cycles within which the CRC for an entire block needs to complete"
|
|
group.long (0x80+0x20)++0x0F
|
|
line.long 0x00 "PSA_SIGREGL2,Channel 2 PSA Signature Low Register"
|
|
line.long 0x04 "PSA_SIGREGH2,Channel 2 PSA Signature High Register"
|
|
line.long 0x08 "CRC_REGL2,Channel 2 CRC Value Low Register"
|
|
line.long 0x0C "CRC_REGH2,Channel 2 CRC Value High Register"
|
|
rgroup.long (0x80+0x30)++0x0F
|
|
line.long 0x00 "PSA_SECSIGREGL2,Channel 2 PSA Sector Signature Low Register"
|
|
line.long 0x04 "PSA_SECSIGREGH2,Channel 2 PSA Sector Signature High Register"
|
|
line.long 0x08 "RAW_DATAREGL2,Channel 2 Raw Data Low Register"
|
|
line.long 0x0C "RAW_DATAREGH2,Channel 2 Raw Data High Register"
|
|
group.long 0xC0++0x13
|
|
line.long 0x00 "PCOUNT_REG3,Pattern Counter Pre-load Register 3"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT3 ,Number of data patterns in one sector to be compressed before a CRC is performed"
|
|
line.long 0x04 "SCOUNT_REG3,Sector Counter Pre-load Register 3"
|
|
hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT3 ,The number of sectors in one block of memory"
|
|
line.long 0x08 "CURSEC_REG3,Current Sector Register 3"
|
|
hexmask.long.word 0x08 0.--15. 1. " CRC_CURSEC3 ,Current sector number of which the signature verification fails"
|
|
line.long 0x0C "WDTOPLD3,Channel 3 Watchdog Timeout Preload Register A"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " CRC_WDTOPLD3 ,Number of clock cycles within which the DMA must transfer the next block of data patterns"
|
|
line.long 0x10 "BCTOPLD3,Channel 3 Block Complete Timeout Preload Register B"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " CRC_BCTOPLD3 ,Number of clock cycles within which the CRC for an entire block needs to complete"
|
|
group.long (0xC0+0x20)++0x0F
|
|
line.long 0x00 "PSA_SIGREGL3,Channel 3 PSA Signature Low Register"
|
|
line.long 0x04 "PSA_SIGREGH3,Channel 3 PSA Signature High Register"
|
|
line.long 0x08 "CRC_REGL3,Channel 3 CRC Value Low Register"
|
|
line.long 0x0C "CRC_REGH3,Channel 3 CRC Value High Register"
|
|
rgroup.long (0xC0+0x30)++0x0F
|
|
line.long 0x00 "PSA_SECSIGREGL3,Channel 3 PSA Sector Signature Low Register"
|
|
line.long 0x04 "PSA_SECSIGREGH3,Channel 3 PSA Sector Signature High Register"
|
|
line.long 0x08 "RAW_DATAREGL3,Channel 3 Raw Data Low Register"
|
|
line.long 0x0C "RAW_DATAREGH3,Channel 3 Raw Data High Register"
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "PCOUNT_REG4,Pattern Counter Pre-load Register 4"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT4 ,Number of data patterns in one sector to be compressed before a CRC is performed"
|
|
line.long 0x04 "SCOUNT_REG4,Sector Counter Pre-load Register 4"
|
|
hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT4 ,The number of sectors in one block of memory"
|
|
line.long 0x08 "CURSEC_REG4,Current Sector Register 4"
|
|
hexmask.long.word 0x08 0.--15. 1. " CRC_CURSEC4 ,Current sector number of which the signature verification fails"
|
|
line.long 0x0C "WDTOPLD4,Channel 4 Watchdog Timeout Preload Register A"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " CRC_WDTOPLD4 ,Number of clock cycles within which the DMA must transfer the next block of data patterns"
|
|
line.long 0x10 "BCTOPLD4,Channel 4 Block Complete Timeout Preload Register B"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " CRC_BCTOPLD4 ,Number of clock cycles within which the CRC for an entire block needs to complete"
|
|
group.long (0x100+0x20)++0x0F
|
|
line.long 0x00 "PSA_SIGREGL4,Channel 4 PSA Signature Low Register"
|
|
line.long 0x04 "PSA_SIGREGH4,Channel 4 PSA Signature High Register"
|
|
line.long 0x08 "CRC_REGL4,Channel 4 CRC Value Low Register"
|
|
line.long 0x0C "CRC_REGH4,Channel 4 CRC Value High Register"
|
|
rgroup.long (0x100+0x30)++0x0F
|
|
line.long 0x00 "PSA_SECSIGREGL4,Channel 4 PSA Sector Signature Low Register"
|
|
line.long 0x04 "PSA_SECSIGREGH4,Channel 4 PSA Sector Signature High Register"
|
|
line.long 0x08 "RAW_DATAREGL4,Channel 4 Raw Data Low Register"
|
|
line.long 0x0C "RAW_DATAREGH4,Channel 4 Raw Data High Register"
|
|
newline
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "MCRC_BUS_SEL,Data Bus Tracing Selection Register"
|
|
bitfld.long 0x00 2. " ME ,Enable the tracing of VBUSM" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DTCME ,Enable the tracing of data TCM" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ITCME ,Enable the tracing of instruction" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("AWR6843*")
|
|
tree "PBIST (Programmable Built-In Self-Test)"
|
|
base ad:0xFFFFE400
|
|
width 11.
|
|
sif cpuis("AWR1843*")
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "DLR,Datalogger 0"
|
|
bitfld.long 0x00 9. " DLR9 ,Default testing mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DLR4 ,Config access mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " DLR3 ,Do not change this bit from" ",1"
|
|
bitfld.long 0x00 2. " DLR2 ,ROM-based testing mode" "Disabled,Enabled"
|
|
else
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "DLR,Datalogger 0 Register"
|
|
bitfld.long 0x00 9. " DLR9 ,Default testing mode" "No,Yes"
|
|
bitfld.long 0x00 4. " DLR4 ,Config access" "No,Yes"
|
|
bitfld.long 0x00 2. " DLR2 ,ROM-based testing" "No,Yes"
|
|
endif
|
|
group.long 0x180++0x0B
|
|
line.long 0x00 "PACT,PBIST Activate Register"
|
|
bitfld.long 0x00 0. " PBIST_PACT ,Pbist active / ROM clock enable register" "Disabled,Enabled"
|
|
line.long 0x04 "ID,PBIST ID Register"
|
|
hexmask.long.byte 0x04 0.--4. 1. " PBIST_ID ,Unique ID assigned to each PBIST controller in a device with multiple PBIST controllers"
|
|
line.long 0x08 "OVR,PBIST Override Register"
|
|
bitfld.long 0x08 0. " PBIST_OVR ,RINFO override bit" "No override,Override"
|
|
rgroup.long 0x190++0x0F
|
|
line.long 0x00 "FSFR0,Fail Status Fail Port 0 Register"
|
|
bitfld.long 0x00 0. " PBIST_FSFR0 ,Fail status fail register port 0" "No failure,Failure"
|
|
line.long 0x04 "FSFR1,Fail Status Fail Port 1 Register"
|
|
bitfld.long 0x04 0. " PBIST_FSFR1 ,Fail status fail register port 1" "No failure,Failure"
|
|
line.long 0x08 "FSRCR0,Fail Status Count Port 0 Register"
|
|
bitfld.long 0x08 0.--3. " PBIST_FSRCR0 ,Fail status count port 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "FSRCR1,Fail Status Count Port 1 Register"
|
|
bitfld.long 0x0C 0.--3. " PBIST_FSRCR1 ,Fail status count port 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C0++0x0B
|
|
line.long 0x00 "ROM,Rom Mask Register"
|
|
bitfld.long 0x00 0.--1. " PBIST_ROM ,Rom mask" "No information,RAM Group,Algorithm info,Algorithm/RAM info"
|
|
line.long 0x04 "ALGO,ROM Algorithm Mask Register"
|
|
bitfld.long 0x04 1. " ALGO0_[1] ,March13N for L2 UMAP / parity / tag RAMs" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [0] ,March13N for L1P and L1D RAMs" "Disabled,Enabled"
|
|
line.long 0x08 "RINFOL,RAM Info Mask Lower Register"
|
|
bitfld.long 0x08 3. " RINFOL0_[3] ,Memory group for L2 UMAP and PARITY single port RAMs" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Memory group for L2 TAG single port RAMs" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [1] ,Memory group for L1P single port RAMs" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [0] ,Memory group for L1D single port RAMs" "Disabled,Enabled"
|
|
sif cpuis("AWR1843*")
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "RINFOU,RAM Info Mask Upper 0"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "STC (Self-Test Controller)"
|
|
base ad:0xFFFFE600
|
|
width 17.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "STCGCR0,STC Global Control Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " INTCOUNT_B16 ,Number of intervals of self test run"
|
|
bitfld.long 0x00 8.--10. " CAP_IDLE_CYCLE ,Idle cycles in the capture phase insertion" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " SCANEN_HIGH_CAP_IDLE_CYCLE ,Idle cycles in the shift clock and misr_log_clk generation insertion" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. " RS_CNT_B1 ,Restart/Continue/Preload" "Continue,Restart,Preload,Preload"
|
|
line.long 0x04 "STCGCR1,STC Global Control Register 1"
|
|
bitfld.long 0x04 8.--11. " SEG0_CORE_SEL ,Segment 0 CORE for self test" "Not selected,Selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected,Not selected"
|
|
bitfld.long 0x04 6. " CODEC_SPREAD_MODE ,Codec spread mode control signal" "XOR,Spread"
|
|
bitfld.long 0x04 5. " LP_SCAN_MODE ,LP scan mode" "Normal,Low power"
|
|
bitfld.long 0x04 0.--3. " ST_ENA_B4 ,Self test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
line.long 0x08 "STCTPR,Self Test Run Timeout Counter Preload Register"
|
|
rgroup.long 0x0C++0x0F
|
|
line.long 0x00 "STC_CADDR,STC Current ROM Address Register"
|
|
line.long 0x04 "STCCICR,STC Current Interval Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " CORE2_ICOUNT ,Last interval number for core 2"
|
|
hexmask.long.word 0x04 0.--15. 1. " CORE1_ICOUNT ,Last interval number for core 1"
|
|
line.long 0x08 "STCGSTAT,Self Test Global Status Register"
|
|
bitfld.long 0x08 8.--11. " ST_ACTIVE ,Self test active" "Not active,Not active,Not active,Not active,Not active,Not active,Not active,Not active,Not active,Not active,Active,Not active,Not active,Not active,Not active,Not active"
|
|
bitfld.long 0x08 1. " TEST_FAIL ,Test fail flag" "Not failed,Failed"
|
|
bitfld.long 0x08 0. " TEST_DONE ,Test done flag" "Not done,Done"
|
|
line.long 0x0C "STCFSTAT,Self Test Fail Status Register"
|
|
bitfld.long 0x0C 3.--4. " FSEG_ID ,Failed segment ID" "0,1,2,3"
|
|
bitfld.long 0x0C 2. " TO_ER_B1 ,Timeout error" "No error,Error"
|
|
bitfld.long 0x0C 1. " CPU2_FAIL_B1 ,CPU2 failure info" "Not failed,Failed"
|
|
bitfld.long 0x0C 0. " CPU1_FAIL_B1 ,CPU1 failure info" "Not failed,Failed"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "STCSCSCR,Signature Compare Self Check Register"
|
|
bitfld.long 0x00 4. " FAULT_INS_B1 ,Fault insertion bit" "No fault,Fault"
|
|
bitfld.long 0x00 0.--3. " SELF_CHECK_KEY_B4 ,Signature compare logic self check key enable/disable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "STC_CADDR2,Current Address Register For CORE2"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "STC_SEGPLR,Segment 1st Interval Preload Register"
|
|
bitfld.long 0x00 0.--1. " SEGID_PLOAD ,Segment number for which preload is to be started" "0,1,2,3"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SEG0_START_ADDR,Core 1 Current MISR Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 0x01 " SEG_START_ADDR ,Segment 0 start address"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SEG1_START_ADDR,Core 1 Current MISR Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 0x01 " SEG_START_ADDR ,Segment 0 start address"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SEG2_START_ADDR,Core 1 Current MISR Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 0x01 " SEG_START_ADDR ,Segment 0 start address"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SEG3_START_ADDR,Core 1 Current MISR Register"
|
|
hexmask.long.tbyte 0x00 0.--19. 0x01 " SEG_START_ADDR ,Segment 0 start address"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "CORE1_CURMISR0,Core 1 Current MISR Register 0"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "CORE1_CURMISR1,Core 1 Current MISR Register 1"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CORE1_CURMISR2,Core 1 Current MISR Register 2"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "CORE1_CURMISR3,Core 1 Current MISR Register 3"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "CORE1_CURMISR4,Core 1 Current MISR Register 4"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "CORE1_CURMISR5,Core 1 Current MISR Register 5"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "CORE1_CURMISR6,Core 1 Current MISR Register 6"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "CORE1_CURMISR7,Core 1 Current MISR Register 7"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "CORE1_CURMISR8,Core 1 Current MISR Register 8"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "CORE1_CURMISR9,Core 1 Current MISR Register 9"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "CORE1_CURMISR10,Core 1 Current MISR Register 10"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "CORE1_CURMISR11,Core 1 Current MISR Register 11"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "CORE1_CURMISR12,Core 1 Current MISR Register 12"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "CORE1_CURMISR13,Core 1 Current MISR Register 13"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "CORE1_CURMISR14,Core 1 Current MISR Register 14"
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "CORE1_CURMISR15,Core 1 Current MISR Register 15"
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "CORE1_CURMISR16,Core 1 Current MISR Register 16"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "CORE1_CURMISR17,Core 1 Current MISR Register 17"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "CORE1_CURMISR18,Core 1 Current MISR Register 18"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "CORE1_CURMISR19,Core 1 Current MISR Register 19"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "CORE1_CURMISR20,Core 1 Current MISR Register 20"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "CORE1_CURMISR21,Core 1 Current MISR Register 21"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "CORE1_CURMISR22,Core 1 Current MISR Register 22"
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "CORE1_CURMISR23,Core 1 Current MISR Register 23"
|
|
rgroup.long 0x9C++0x03
|
|
line.long 0x00 "CORE1_CURMISR24,Core 1 Current MISR Register 24"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "CORE1_CURMISR25,Core 1 Current MISR Register 25"
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "CORE1_CURMISR26,Core 1 Current MISR Register 26"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "CORE1_CURMISR27,Core 1 Current MISR Register 27"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CORE2_CURMISR0,Core 2 Current MISR Register 0"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "CORE2_CURMISR1,Core 2 Current MISR Register 1"
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "CORE2_CURMISR2,Core 2 Current MISR Register 2"
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "CORE2_CURMISR3,Core 2 Current MISR Register 3"
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "CORE2_CURMISR4,Core 2 Current MISR Register 4"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "CORE2_CURMISR5,Core 2 Current MISR Register 5"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "CORE2_CURMISR6,Core 2 Current MISR Register 6"
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "CORE2_CURMISR7,Core 2 Current MISR Register 7"
|
|
rgroup.long 0xCC++0x03
|
|
line.long 0x00 "CORE2_CURMISR8,Core 2 Current MISR Register 8"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "CORE2_CURMISR9,Core 2 Current MISR Register 9"
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "CORE2_CURMISR10,Core 2 Current MISR Register 10"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "CORE2_CURMISR11,Core 2 Current MISR Register 11"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "CORE2_CURMISR12,Core 2 Current MISR Register 12"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "CORE2_CURMISR13,Core 2 Current MISR Register 13"
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "CORE2_CURMISR14,Core 2 Current MISR Register 14"
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "CORE2_CURMISR15,Core 2 Current MISR Register 15"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "CORE2_CURMISR16,Core 2 Current MISR Register 16"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "CORE2_CURMISR17,Core 2 Current MISR Register 17"
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "CORE2_CURMISR18,Core 2 Current MISR Register 18"
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "CORE2_CURMISR19,Core 2 Current MISR Register 19"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "CORE2_CURMISR20,Core 2 Current MISR Register 20"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "CORE2_CURMISR21,Core 2 Current MISR Register 21"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "CORE2_CURMISR22,Core 2 Current MISR Register 22"
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "CORE2_CURMISR23,Core 2 Current MISR Register 23"
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "CORE2_CURMISR24,Core 2 Current MISR Register 24"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "CORE2_CURMISR25,Core 2 Current MISR Register 25"
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "CORE2_CURMISR26,Core 2 Current MISR Register 26"
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "CORE2_CURMISR27,Core 2 Current MISR Register 27"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
else
|
|
tree.open "AWR (Power, Reset, Clock Management and Control Registers)"
|
|
tree "DSS_REG"
|
|
base ad:0x02000000
|
|
width 22.
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "RTIEVENTCAPTURESEL,RTI1 Event Capture Select Register"
|
|
bitfld.long 0x00 16.--19. " EVT[1] ,Source of interrupt for Counter value capture for RTI1 Event 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " [0] ,Source of interrupt for Counter value capture for RTI1 Event 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CQCFG1,CQ0 Configuration 1 Register"
|
|
hexmask.long.word 0x00 22.--30. 0x40 " CQ2BASEADDR ,Address to be added to be internal address pointer for CQ2"
|
|
hexmask.long.word 0x00 13.--21. 0x20 " CQ1BASEADDR ,Address to be added to be internal address pointer for CQ1"
|
|
hexmask.long.word 0x00 4.--12. 0x10 " CQ0BASEADDR ,Address to be added to be internal address pointer for CQ0"
|
|
newline
|
|
bitfld.long 0x00 3. " CQ96BITPACKEN ,This is used to pack the CQ data into only the LSB 96 bits of each row of the CQ memory" "0,1"
|
|
newline
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x00 0.--1. " CQDATAWIDTH ,This is used to appropriately pack the valid CQ data bits in appropriate bits in the CQ memory" "Raw 16,Raw 16,Raw 12,Raw 14"
|
|
else
|
|
bitfld.long 0x00 0.--1. " CQDATAWIDTH ,This is used to appropriately pack the valid CQ data bits in appropriate bits in the CQ memory" "0,Raw 16,Raw 12,Raw 14"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "TPCCPARSTATCFG,TPCCPARSTATCFG"
|
|
bitfld.long 0x00 10. " TPCCPARITYTSTEN ,Enable bit for the self test of the parity logic in TPCC" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TPCCPARITYEN ,Enable bit for the parity computation in TPCC" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " TPCCPARITYCLR ,Clear bit for the parity error from TPCC" "Not cleared,Cleared"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " TPCCPARITYSTAT ,Parity address from TPCC"
|
|
group.long 0x104++0x17
|
|
line.long 0x00 "TPTC0WRMPUSTADD0,TPTC0 Write MPU Start Address 0 Register"
|
|
line.long 0x04 "TPTC0WRMPUSTADD1,TPTC0 Write MPU Start Address 1 Register"
|
|
line.long 0x08 "TPTC0WRMPUSTADD2,TPTC0 Write MPU Start Address 2 Register"
|
|
line.long 0x0C "TPTC0WRMPUSTADD3,TPTC0 Write MPU Start Address 3 Register"
|
|
line.long 0x10 "TPTC0WRMPUSTADD4,TPTC0 Write MPU Start Address 4 Register"
|
|
line.long 0x14 "TPTC0WRMPUSTADD5,TPTC0 Write MPU Start Address 5 Register"
|
|
group.long 0x124++0x17
|
|
line.long 0x00 "TPTC0WRMPUENDADD0,TPTC0 Write MPU End Address 0 Register"
|
|
line.long 0x04 "TPTC0WRMPUENDADD1,TPTC0 Write MPU End Address 1 Register"
|
|
line.long 0x08 "TPTC0WRMPUENDADD2,TPTC0 Write MPU End Address 2 Register"
|
|
line.long 0x0C "TPTC0WRMPUENDADD3,TPTC0 Write MPU End Address 3 Register"
|
|
line.long 0x10 "TPTC0WRMPUENDADD4,TPTC0 Write MPU End Address 4 Register"
|
|
line.long 0x14 "TPTC0WRMPUENDADD5,TPTC0 Write MPU End Address 5 Register"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "TPTC0WRMPUERRADD,TPTC0 Write MPU Error Address Register"
|
|
group.long 0x148++0x17
|
|
line.long 0x00 "TPTC0RDMPUSTADD0,TPTC0 Read MPU Start Address 0 Register"
|
|
line.long 0x04 "TPTC0RDMPUSTADD1,TPTC0 Read MPU Start Address 1 Register"
|
|
line.long 0x08 "TPTC0RDMPUSTADD2,TPTC0 Read MPU Start Address 2 Register"
|
|
line.long 0x0C "TPTC0RDMPUSTADD3,TPTC0 Read MPU Start Address 3 Register"
|
|
line.long 0x10 "TPTC0RDMPUSTADD4,TPTC0 Read MPU Start Address 4 Register"
|
|
line.long 0x14 "TPTC0RDMPUSTADD5,TPTC0 Read MPU Start Address 5 Register"
|
|
group.long 0x168++0x17
|
|
line.long 0x00 "TPTC0RDMPUENDADD0,TPTC0 Read MPU End Address 0 Register"
|
|
line.long 0x04 "TPTC0RDMPUENDADD1,TPTC0 Read MPU End Address 1 Register"
|
|
line.long 0x08 "TPTC0RDMPUENDADD2,TPTC0 Read MPU End Address 2 Register"
|
|
line.long 0x0C "TPTC0RDMPUENDADD3,TPTC0 Read MPU End Address 3 Register"
|
|
line.long 0x10 "TPTC0RDMPUENDADD4,TPTC0 Read MPU End Address 4 Register"
|
|
line.long 0x14 "TPTC0RDMPUENDADD5,TPTC0 Read MPU End Address 5 Register"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "TPTC0RDMPUERRADD,TPTC0 Read MPU Error Address Register"
|
|
group.long 0x18C++0x17
|
|
line.long 0x00 "TPTC1WRMPUSTADD0,TPTC1 Write MPU Start Address 0 Register"
|
|
line.long 0x04 "TPTC1WRMPUSTADD1,TPTC1 Write MPU Start Address 1 Register"
|
|
line.long 0x08 "TPTC1WRMPUSTADD2,TPTC1 Write MPU Start Address 2 Register"
|
|
line.long 0x0C "TPTC1WRMPUSTADD3,TPTC1 Write MPU Start Address 3 Register"
|
|
line.long 0x10 "TPTC1WRMPUSTADD4,TPTC1 Write MPU Start Address 4 Register"
|
|
line.long 0x14 "TPTC1WRMPUSTADD5,TPTC1 Write MPU Start Address 5 Register"
|
|
group.long 0x1AC++0x17
|
|
line.long 0x00 "TPTC1WRMPUENDADD0,TPTC1 Write MPU End Address 0 Register"
|
|
line.long 0x04 "TPTC1WRMPUENDADD1,TPTC1 Write MPU End Address 1 Register"
|
|
line.long 0x08 "TPTC1WRMPUENDADD2,TPTC1 Write MPU End Address 2 Register"
|
|
line.long 0x0C "TPTC1WRMPUENDADD3,TPTC1 Write MPU End Address 3 Register"
|
|
line.long 0x10 "TPTC1WRMPUENDADD4,TPTC1 Write MPU End Address 4 Register"
|
|
line.long 0x14 "TPTC1WRMPUENDADD5,TPTC1 Write MPU End Address 5 Register"
|
|
rgroup.long 0x1CC++0x03
|
|
line.long 0x00 "TPTC1WRMPUERRADD,TPTC1 Write MPU Error Address Register"
|
|
group.long 0x1D0++0x17
|
|
line.long 0x00 "TPTC1RDMPUSTADD0,TPTC1 Read MPU Start Address 0 Register"
|
|
line.long 0x04 "TPTC1RDMPUSTADD1,TPTC1 Read MPU Start Address 1 Register"
|
|
line.long 0x08 "TPTC1RDMPUSTADD2,TPTC1 Read MPU Start Address 2 Register"
|
|
line.long 0x0C "TPTC1RDMPUSTADD3,TPTC1 Read MPU Start Address 3 Register"
|
|
line.long 0x10 "TPTC1RDMPUSTADD4,TPTC1 Read MPU Start Address 4 Register"
|
|
line.long 0x14 "TPTC1RDMPUSTADD5,TPTC1 Read MPU Start Address 5 Register"
|
|
group.long 0x1F0++0x17
|
|
line.long 0x00 "TPTC1RDMPUENDADD0,TPTC1 Read MPU End Address 0 Register"
|
|
line.long 0x04 "TPTC1RDMPUENDADD1,TPTC1 Read MPU End Address 1 Register"
|
|
line.long 0x08 "TPTC1RDMPUENDADD2,TPTC1 Read MPU End Address 2 Register"
|
|
line.long 0x0C "TPTC1RDMPUENDADD3,TPTC1 Read MPU End Address 3 Register"
|
|
line.long 0x10 "TPTC1RDMPUENDADD4,TPTC1 Read MPU End Address 4 Register"
|
|
line.long 0x14 "TPTC1RDMPUENDADD5,TPTC1 Read MPU End Address 5 Register"
|
|
rgroup.long 0x210++0x03
|
|
line.long 0x00 "TPTC1RDMPUERRADD,TPTC1 Read MPU Error Address Register"
|
|
group.long 0x214++0x07
|
|
line.long 0x00 "TPTCMPUVALIDCFG,TPTC MPU Valid Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TPTC1RDMPURNGVLD ,Valid bit for each address range for the MPU in the read port of TPTC1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TPTC1WRMPURNGVLD ,Valid bit for each address range for the MPU in the read port of TPTC1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TPTC0RDMPURNGVLD ,Valid bit for each address range for the MPU in the read port of TPTC1"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " TPTC0WRMPURNGVLD ,Valid bit for each address range for the MPU in the read port of TPTC1"
|
|
line.long 0x04 "TPTCMPUENCFG,TPTC MPU Enable Configuration Register"
|
|
bitfld.long 0x04 7. " TPTC1RDMPUERRCLR ,Clear flag for error from the MPU in the read port of TPTC1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " TPTC1WRMPUERRCLR ,Clear flag for error from the MPU in the write port of TPTC1" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " TPTC0RDMPUERRCLR ,Clear flag for error from the MPU in the read port of TPTC0" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 4. " TPTC0WRMPUERRCLR ,Clear flag for error from the MPU in the write port of TPTC0" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " TPTC1RDMPUEN ,Enable bit for the MPU in the read port of TPTC1" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " TPTC1WRMPUEN ,Enable bit for the MPU in the write port of TPTC1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " TPTC0RDMPUEN ,Enable bit for the MPU in the read port of TPTC0" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TPTC0WRMPUEN ,Enable bit for the MPU in the write port of TPTC0" "Disabled,Enabled"
|
|
group.long 0x21C++0x0F
|
|
line.long 0x00 "TESTPATTERNRX1ICFG,Test Pattern RX1 I Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TSTPATRX1IINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 0"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " TSTPATRX1IOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 0"
|
|
line.long 0x04 "TESTPATTERNRX2ICFG,TEST Pattern RX2 I Configuration Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " TSTPATRX2IINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 1"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " TSTPATRX2IOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 1"
|
|
line.long 0x08 "TESTPATTERNRX3ICFG,Test Pattern RX3 I Configuration Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " TSTPATRX3IINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 2"
|
|
hexmask.long.word 0x08 0.--15. 0x01 " TSTPATRX3IOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 2"
|
|
line.long 0x0C "TESTPATTERNRX4ICFG,Test Pattern RX4 I Configuration Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " TSTPATRX4IINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 3"
|
|
hexmask.long.word 0x0C 0.--15. 0x01 " TSTPATRX4IOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 3"
|
|
group.long 0x22C++0x0F
|
|
line.long 0x00 "TESTPATTERNRX1QCFG,Test Pattern RX1 Q Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TSTPATRX1QINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 0"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " TSTPATRX1QOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 0"
|
|
line.long 0x04 "TESTPATTERNRX2QCFG,Test Pattern RX2 Q Configuration Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " TSTPATRX2QINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 1"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " TSTPATRX2QOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 1"
|
|
line.long 0x08 "TESTPATTERNRX3QCFG,Test Pattern RX3 Q Configuration Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " TSTPATRX3QINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 2"
|
|
hexmask.long.word 0x08 0.--15. 0x01 " TSTPATRX3QOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 2"
|
|
line.long 0x0C "TESTPATTERNRX4QCFG,Test Pattern RX4 Q Configuration Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " TSTPATRX4QINCR ,Value to be added for each successive sample for the test pattern data in I channel RX channel 3"
|
|
hexmask.long.word 0x0C 0.--15. 0x01 " TSTPATRX4QOFFSET ,Offset value to be used for the first sample for the test pattern data in I channel RX channel 3"
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "TESTPATTERNVLDCFG,Test Pattern VLD Configuration"
|
|
bitfld.long 0x00 8.--10. " TSTPATGENEN ,Enable for test pattern generator" "Disabled,,,,,,,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TSTPATVLDCNT ,Number of DSS Interconnect clocks 200 MHz between successive samples for the test pattern gen"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "DSSMISC,DSS Miscellaneous Register"
|
|
bitfld.long 0x00 6.--8. " FFTACCSLVEN ,Enable HW accelerator" "Disabled,,,,,,,Enabled"
|
|
endif
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "TPCC1PARSTATCFG,TPCC1 Parity Stat Configuration Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " NU ,Number"
|
|
bitfld.long 0x00 11. " TPCC1PARITYTSTEN ,Enable bit for the self test of the parity logic in TPCC" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TPCC1PARITYEN ,Enable bit for the parity computation in TPCC" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " TPCC1PARITYCLR ,Clear bit for the parity error from TPCC write 0x1 to clear the status" "Not cleared,Cleared"
|
|
hexmask.long.word 0x00 0.--8. 0x01 " TPCC1PARITYSTAT ,Parity address from TPCC"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "DMMSWINT1,DMM Switch Interrupt 1 Register"
|
|
bitfld.long 0x00 22. " DMMCQWREN ,CQ write enable from DMM" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " DMMCQPINPONSEL ,CQ ping pong select for HIL mode" "0,1"
|
|
bitfld.long 0x00 20. " DMMCPBPMMEMSEL ,Select signal for muxing between HW registers/memory for CPBPM data" "HW registers,Memory"
|
|
newline
|
|
bitfld.long 0x00 19. " DMMCPBPMWREN ,CPBPM write enable from DMM" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DMMCPBPMPINPONSEL ,CP BPM ping pong select for HIL mode" "0,1"
|
|
bitfld.long 0x00 17. " DMMADCBUFWREN ,ADC buffer write enable from DMM" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. " DMMADCBUFPINPONSEL ,ADC Buffer ping pong select for HIL mode" "0,1"
|
|
group.long 0x270++0x13
|
|
line.long 0x00 "DSSINTRCFG,DSS Interrupt Configuration"
|
|
bitfld.long 0x00 7. " LGFRAMESTRTINTMUXSEL[1] ,Logical frame start select" "DFE,DMM global CFG bit"
|
|
bitfld.long 0x00 6. " [0] ,Interrupt select" "MUX,DMM SW interrupt 3"
|
|
bitfld.long 0x00 5. " PINPONINTMUXSEL[1] ,Ping pong switch select" "VIN/DFE,DMM global CFG bit"
|
|
newline
|
|
bitfld.long 0x00 4. " [0] ,Interrupt select" "MUX,DMM SW interrupt 2"
|
|
bitfld.long 0x00 3. " CHIRPAVLINTMUXSEL[1] ,Chirp available select" "VIN/DFE,DMM global CFG bit"
|
|
bitfld.long 0x00 2. " [0] ,Interrupt select" "MUX,DMM SW interrupt 1"
|
|
newline
|
|
bitfld.long 0x00 1. " FRAMESTRTINTMUXSEL[1] ,Frame start select" "VIN/DFE,DMM global CFG bit"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt select" "MUX,DMM SW interrupt 0"
|
|
line.long 0x04 "MPUMSTIDCFG1,MPU Master ID Configuration 1 Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " MPUMSTID[3] ,MPU master ID 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " [2] ,MPU master ID 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " [1] ,MPU master ID 1"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. " [0] ,MPU maser ID 0"
|
|
line.long 0x08 "MPUMSTIDCFG2,MPU Master ID Configuration 2 Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " MPUMSTID[7] ,MPU master ID 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " [6] ,MPU master ID 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " [5] ,MPU master ID 5"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. " [4] ,MPU master ID 4"
|
|
line.long 0x0C "MPUMSTIDCFG3,MPU Master ID Configuration 3 Register"
|
|
bitfld.long 0x0C 19. " MPUMSTIDEN ,Enable control for master ID based MPU" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " MPUERRCLR ,Error clear pulse for master ID based MPU" "Not cleared,Cleared"
|
|
hexmask.long.byte 0x0C 8.--15. 1. " MPUERRMSTID ,Error status field"
|
|
newline
|
|
bitfld.long 0x0C 7. " MPUMSTIDVLD[7] ,Master ID 7 valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 6. " [6] ,Master ID 6 valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 5. " [5] ,Master ID 5 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x0C 4. " [4] ,Master ID 4 valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 3. " [3] ,Master ID 3 valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 2. " [2] ,Master ID 2 valid" "Not valid,Valid"
|
|
newline
|
|
bitfld.long 0x0C 1. " [1] ,Master ID 1 valid" "Not valid,Valid"
|
|
bitfld.long 0x0C 0. " [0] ,Master ID 0 valid" "Not valid,Valid"
|
|
line.long 0x10 "HSRAM1ECCCFG,HSRAM1 ECC Configuration Register"
|
|
hexmask.long.word 0x10 15.--22. 1. " HSRAM1ECCREPAIREDBIT ,Bit position of the repaired bit in HSRAM1"
|
|
hexmask.long.word 0x10 4.--14. 0x10 " HSRAM1ECCFAULTADDRESS ,ECC fault address in HSRAM1"
|
|
bitfld.long 0x10 3. " HSRAM1ECCERRCLR ,Clear bit for ECC error indication in HSRAM1" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x10 2. " HSRAM1ECCEN ,Enable for ECC in HSRAM1" "Disabled,Enabled"
|
|
rbitfld.long 0x10 1. " HSRAM1ECCINITDONE ,Done status for ECC initialization for HSRAM1" "Not done,Done"
|
|
bitfld.long 0x10 0. " HSRAM1ECCINIT ,ECC initialization For HSRAM1" "Disabled,Enabled"
|
|
group.long 0x288++0x0B
|
|
line.long 0x00 "DATATRRAMECCCFG,DATATRRAM ECC Configuration Register"
|
|
hexmask.long.word 0x00 13.--20. 1. " DATATRRAMECCREPAIREDBIT ,Bit position of the repaired bit in DATATRRAM"
|
|
hexmask.long.word 0x00 4.--12. 0x10 " DATATRRAMECCFAULTADDRESS ,ECC fault address in DATATRRAM"
|
|
bitfld.long 0x00 3. " DATATRRAMECCERRCLR ,Clear bit for ECC error indication in DATATRRAM" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 2. " DATATRRAMECCEN ,Enable for ECC in DATATRRAM" "Disabled,Enabled"
|
|
rbitfld.long 0x00 1. " DATATRRAMECCINITDONE ,Done status for ECC initialization for data transfer RAM" "Not done,Done"
|
|
bitfld.long 0x00 0. " DATATRRAMECCINIT ,ECC initialization for data transfer RAM" "Disabled,Enabled"
|
|
line.long 0x04 "ADCBUFPINGECCCFG,ADC Buffer Ping ECC Configuration Register"
|
|
hexmask.long.word 0x04 15.--22. 1. " ADCBUFPINGECCREPAIREDBIT ,Bit position of the repaired bit in ADC buffer ping memory"
|
|
hexmask.long.word 0x04 4.--14. 0x10 " ADCBUFPINGECCFAULTADDRESS ,ECC fault address in ADC buffer ping memory"
|
|
bitfld.long 0x04 3. " ADCBUFPINGECCERRCLR ,Clear bit for ECC error indication in ADC buffer ping memory" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " ADCBUFPINGECCEN ,Enable for ECC in ADC buffer ping memory" "Disabled,Enabled"
|
|
rbitfld.long 0x04 1. " ADCBUFPINGECCINITDONE ,Done status for ECC initialization for ADC buffer ping memory" "Not done,Done"
|
|
bitfld.long 0x04 0. " ADCBUFPINGECCINIT ,ECC initialization For ADC buffer ping memory" "Disabled,Enabled"
|
|
line.long 0x08 "ADCBUFPONGECCCFG,ADC Buffer Pong ECC Configuration Register"
|
|
hexmask.long.word 0x08 15.--22. 1. " ADCBUFPONGECCREPAIREDBIT ,Bit position of the repaired bit in ADC buffer pong memory"
|
|
hexmask.long.word 0x08 4.--14. 0x10 " ADCBUFPONGECCFAULTADDRESS ,ECC fault address in ADC buffer pong memory"
|
|
bitfld.long 0x08 3. " ADCBUFPONGECCERRCLR ,Clear bit for ECC error indication in ADC buffer pong memory" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 2. " ADCBUFPONGECCEN ,Enable for ECC in ADC buffer pong memory" "Disabled,Enabled"
|
|
rbitfld.long 0x08 1. " ADCBUFPONGECCINITDONE ,Done status for ECC initialization for ADC buffer pong memory" "Not done,Done"
|
|
bitfld.long 0x08 0. " ADCBUFPONGECCINIT ,ECC initialization for ADC buffer pong memory" "Disabled,Enabled"
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "UMAP0PARITYCFG1,UMAP0 Parity Configuration 1 Register"
|
|
hexmask.long.word 0x00 15.--25. 0x80 " UMAP0BANK23ADDOUT ,Address corresponding to the parity error in bank 2 or bank 3 of UMAP0"
|
|
hexmask.long.word 0x00 4.--14. 0x10 " UMAP0BANK01ADDOUT ,Address corresponding to the parity error in bank 0 or bank 1 of UMAP0"
|
|
rbitfld.long 0x00 3. " UMAP0BANK23ERROUT ,Parity error indication from either bank 2 or bank 3 of UMAP0" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 2. " UMAP0BANK01ERROUT ,Parity error indication from either bank 0 or bank 1 of UMAP0" "No error,Error"
|
|
bitfld.long 0x00 1. " UMAP0PARERRCLR ,Clear pulse for all the error status from UMAP0 parity check logic" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " UMAP0PAREN ,Enable for UMAP0 parity check logic" "Disabled,Enabled"
|
|
rgroup.long 0x2A0++0x07
|
|
line.long 0x00 "UMAP0PARITYCFG2,UMAP1 Parity Configuration 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " UMAP0BANK1BITOUT ,Bit level indication corresponding to parity error from UMAP0 bank 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " UMAP0BANK0BITOUT ,Bit level indication corresponding to parity error from UMAP0 bank 0"
|
|
line.long 0x04 "UMAP0PARITYCFG3,UMAP0PARITYCFG3"
|
|
hexmask.long.word 0x04 16.--31. 1. " UMAP0BANK3BITOUT ,Bit level indication corresponding to parity error from UMAP0 bank 3"
|
|
hexmask.long.word 0x04 0.--15. 1. " UMAP0BANK2BITOUT ,Bit level indication corresponding to parity error from UMAP0 bank 2"
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "UMAP1PARITYCFG1,UMAP1 Parity Configuration 1 Register"
|
|
hexmask.long.word 0x00 15.--25. 0x80 " UMAP1BANK23ADDOUT ,Address corresponding to the parity error in bank 2 or bank 3 of UMAP1"
|
|
hexmask.long.word 0x00 4.--14. 0x10 " UMAP1BANK01ADDOUT ,Address corresponding to the parity error in bank 0 or bank 1 of UMAP1"
|
|
rbitfld.long 0x00 3. " UMAP1BANK23ERROUT ,Parity error indication from either bank 2 or bank 3 of UMAP1" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 2. " UMAP1BANK01ERROUT ,Parity error indication from either bank 0 or bank 1 of UMAP1" "No error,Error"
|
|
bitfld.long 0x00 1. " UMAP1PARERRCLR ,Clear pulse for all the error status from UMAP1 parity check logic" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " UMAP1PAREN ,Enable for UMAP1 parity check logic" "Disabled,Enabled"
|
|
rgroup.long 0x2AC++0x07
|
|
line.long 0x00 "UMAP1PARITYCFG2,UMAP1 Parity Configuration 2 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " UMAP1BANK1BITOUT ,Bit level indication corresponding to parity error from UMAP1 bank 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " UMAP1BANK0BITOUT ,Bit level indication corresponding to parity error from UMAP1 bank 0"
|
|
line.long 0x04 "UMAP1PARITYCFG3,UMAP1 Parity Configuration 3 Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " UMAP1BANK3BITOUT ,Bit level indication corresponding to parity error from UMAP1 bank 3"
|
|
hexmask.long.word 0x04 0.--15. 1. " UMAP1BANK2BITOUT ,Bit level indication corresponding to parity error from UMAP1 bank 2"
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "ESMGRP2MASKCFG,ESM Group2 Mask Configuration Register"
|
|
bitfld.long 0x00 31. " ESMGRP2MASK[31] ,Bit level mask for error signal 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " [30] ,Bit level mask for error signal 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " [29] ,Bit level mask for error signal 29" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Bit level mask for error signal 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " [27] ,Bit level mask for error signal 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " [26] ,Bit level mask for error signal 26" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Bit level mask for error signal 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " [24] ,Bit level mask for error signal 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " [23] ,Bit level mask for error signal 23" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Bit level mask for error signal 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " [21] ,Bit level mask for error signal 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " [20] ,Bit level mask for error signal 20" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Bit level mask for error signal 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " [18] ,Bit level mask for error signal 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " [17] ,Bit level mask for error signal 17" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Bit level mask for error signal 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " [15] ,Bit level mask for error signal 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " [14] ,Bit level mask for error signal 14" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Bit level mask for error signal 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " [12] ,Bit level mask for error signal 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " [11] ,Bit level mask for error signal 11" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Bit level mask for error signal 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " [9] ,Bit level mask for error signal 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Bit level mask for error signal 8" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Bit level mask for error signal 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " [6] ,Bit level mask for error signal 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Bit level mask for error signal 5" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Bit level mask for error signal 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " [3] ,Bit level mask for error signal 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,Bit level mask for error signal 2" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Bit level mask for error signal 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Bit level mask for error signal 0" "Not masked,Masked"
|
|
rgroup.long 0x2B8++0x0B
|
|
line.long 0x00 "L2MEMINITCFG1,L2 Memory Initialization Configuration 1 Register"
|
|
bitfld.long 0x00 31. " UMAP1BANK3PARINITDONE ,Initialization done status from UMAP1 bank 3 parity memory" "Not done,Done"
|
|
bitfld.long 0x00 30. " UMAP1BANK2PARINITDONE ,Initialization done status from UMAP1 bank 2 parity memory" "Not done,Done"
|
|
bitfld.long 0x00 29. " UMAP1BANK1PARINITDONE ,Initialization done status from UMAP1 bank 1 parity memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 28. " UMAP1BANK0PARINITDONE ,Initialization done status from UMAP1 bank 0 parity memory" "Not done,Done"
|
|
bitfld.long 0x00 27. " UMAP0BANK3PARINITDONE ,Initialization done status from UMAP0 bank 3 parity memory" "Not done,Done"
|
|
bitfld.long 0x00 26. " UMAP0BANK2PARINITDONE ,Initialization done status from UMAP0 bank 2 parity memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 25. " UMAP0BANK1PARINITDONE ,Initialization done status from UMAP0 bank 1 parity memory" "Not done,Done"
|
|
bitfld.long 0x00 24. " UMAP0BANK0PARINITDONE ,Initialization done status from UMAP0 bank 0 parity memory" "Not done,Done"
|
|
bitfld.long 0x00 23. " UMAP0BANK3DATAINITDONE ,Initialization done status from UMAP0 bank 3 data memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 22. " UMAP0BANK2DATAINITDONE ,Initialization done status from UMAP0 bank 2 data memory" "Not done,Done"
|
|
bitfld.long 0x00 21. " UMAP0BANK1DATAINITDONE ,Initialization done status from UMAP0 bank 1 data memory" "Not done,Done"
|
|
bitfld.long 0x00 20. " UMAP0BANK0DATAINITDONE ,Initialization done status from UMAP0 bank 0 data memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 19. " UMAP0BANK3DATAINITDONE ,Initialization done status from UMAP0 bank 3 data memory" "Not done,Done"
|
|
bitfld.long 0x00 18. " UMAP0BANK2DATAINITDONE ,Initialization done status from UMAP0 bank 2 data memory" "Not done,Done"
|
|
bitfld.long 0x00 17. " UMAP0BANK1DATAINITDONE ,Initialization done status from UMAP0 bank 1 data memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x00 16. " UMAP0BANK0DATAINITDONE ,Initialization done status from UMAP0 bank 0 data memory" "Not done,Done"
|
|
bitfld.long 0x00 15. " UMAP1BANK3PARINIT ,Initialization trigger for UMAP1 bank 3 parity memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 14. " UMAP1BANK2PARINIT ,Initialization trigger for UMAP1 bank 2 parity memory" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 13. " UMAP1BANK1PARINIT ,Initialization trigger for UMAP1 bank 1 parity memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 12. " UMAP1BANK0PARINIT ,Initialization trigger for UMAP1 bank 0 parity memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 11. " UMAP0BANK3PARINIT ,Initialization trigger for UMAP0 bank 3 parity memory" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 10. " UMAP0BANK2PARINIT ,Initialization trigger for UMAP0 bank 2 parity memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 9. " UMAP0BANK1PARINIT ,Initialization trigger for UMAP0 bank 1 parity memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 8. " UMAP0BANK0PARINIT ,Initialization trigger for UMAP0 bank 0 parity memory" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 7. " UMAP1BANK3DATAINIT ,Initialization trigger for UMAP1 bank 3 data memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 6. " UMAP1BANK2DATAINIT ,Initialization trigger for UMAP1 bank 2 data memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 5. " UMAP1BANK1DATAINIT ,Initialization trigger for UMAP1 bank 1 data memory" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 4. " UMAP1BANK0DATAINIT ,Initialization trigger for UMAP1 bank 0 data memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 3. " UMAP0BANK3DATAINIT ,Initialization trigger for UMAP0 bank 3 data memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 2. " UMAP0BANK2DATAINIT ,Initialization trigger for UMAP0 bank 2 data memory" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x00 1. " UMAP0BANK1DATAINIT ,Initialization trigger for UMAP0 bank 1 data memory" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " UMAP0BANK0DATAINIT ,Initialization trigger for UMAP0 bank 0 data memory" "Not triggered,Triggered"
|
|
line.long 0x04 "L2MEMINITCFG2,L2M Memory Initialization Configuration 2 Register"
|
|
bitfld.long 0x04 7. " UMAP1BANK1PARINITDONE ,Initialization done status for UMAP1 bank1 PRAM memory" "Not done,Done"
|
|
bitfld.long 0x04 6. " UMAP1BANK0PARINITDONE ,Initialization done status for UMAP1 bank 0 PRAM memory" "Not done,Done"
|
|
bitfld.long 0x04 5. " UMAP0BANK1PARINITDONE ,Initialization done status for UMAP0 bank 1 PRAM memory" "Not done,Done"
|
|
newline
|
|
bitfld.long 0x04 4. " UMAP0BANK0PARINITDONE ,Initialization done status for UMAP0 bank 0 PRAM memory" "Not done,Done"
|
|
bitfld.long 0x04 3. " UMAP1BANK1PRAMINIT ,Initialization trigger for UMAP1 bank 1 PRAM memory" "Not triggered,Triggered"
|
|
bitfld.long 0x04 2. " UMAP1BANK0PRAMINIT ,Initialization trigger for UMAP1 bank0 PRAM memory" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x04 1. " UMAP0BANK1PRAMINIT ,Initialization trigger for UMAP0 bank 1 PRAM memory" "Not triggered,Triggered"
|
|
bitfld.long 0x04 0. " UMAP0BANK0PRAMINIT ,Initialization trigger for UMAP0 bank 0 PRAM memory" "Not triggered,Triggered"
|
|
line.long 0x08 "GEMRSTCAUSE,GEM Reset Cause Register"
|
|
bitfld.long 0x08 24. " GEMRSTCAUSECLR ,GEM reset cause clear" "Not cleared,Cleared"
|
|
hexmask.long.byte 0x08 16.--23. 1. " GEMPORCAUSE ,DSP POR reset bitwise indication"
|
|
hexmask.long.byte 0x08 8.--15. 1. " GEMGRSTCAUSE ,DSP reset bitwise indication"
|
|
newline
|
|
hexmask.long.byte 0x08 0.--7. 1. " GEMLRSTCAUSE ,DSP reset bitwise indication"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "GEMPWRSMCFG4,GEM Power SM Configuration 4 Register"
|
|
bitfld.long 0x00 18. " GEMEVENTMASK ,Mask bit for events going to DSP" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " PWRSMLRSTHALT ,Signal to halt DSP power cycle state machine before de-asserting LRST of DSP" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " PWRSMSLEEPTRIG ,Sleep mode trigger for DSP power down state machine" "Disabled,Enabled"
|
|
group.long 0x2D4++0x17
|
|
line.long 0x00 "PWRSMWAKEMASK0,Power SM Wake Mask 0 Register"
|
|
bitfld.long 0x00 31. " PWRSMWAKEMASK0[31] ,Bit level mask for wakeup source bit 31" "Not masked,Masked"
|
|
bitfld.long 0x00 30. " [30] ,Bit level mask for wakeup source bit 30" "Not masked,Masked"
|
|
bitfld.long 0x00 29. " [29] ,Bit level mask for wakeup source bit 29" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Bit level mask for wakeup source bit 28" "Not masked,Masked"
|
|
bitfld.long 0x00 27. " [27] ,Bit level mask for wakeup source bit 27" "Not masked,Masked"
|
|
bitfld.long 0x00 26. " [26] ,Bit level mask for wakeup source bit 26" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Bit level mask for wakeup source bit 25" "Not masked,Masked"
|
|
bitfld.long 0x00 24. " [24] ,Bit level mask for wakeup source bit 24" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " [23] ,Bit level mask for wakeup source bit 23" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Bit level mask for wakeup source bit 22" "Not masked,Masked"
|
|
bitfld.long 0x00 21. " [21] ,Bit level mask for wakeup source bit 21" "Not masked,Masked"
|
|
bitfld.long 0x00 20. " [20] ,Bit level mask for wakeup source bit 20" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Bit level mask for wakeup source bit 19" "Not masked,Masked"
|
|
bitfld.long 0x00 18. " [18] ,Bit level mask for wakeup source bit 18" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " [17] ,Bit level mask for wakeup source bit 17" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Bit level mask for wakeup source bit 16" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " [15] ,Bit level mask for wakeup source bit 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " [14] ,Bit level mask for wakeup source bit 14" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Bit level mask for wakeup source bit 13" "Not masked,Masked"
|
|
bitfld.long 0x00 12. " [12] ,Bit level mask for wakeup source bit 12" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " [11] ,Bit level mask for wakeup source bit 11" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Bit level mask for wakeup source bit 10" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " [9] ,Bit level mask for wakeup source bit 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Bit level mask for wakeup source bit 8" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Bit level mask for wakeup source bit 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " [6] ,Bit level mask for wakeup source bit 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Bit level mask for wakeup source bit 5" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Bit level mask for wakeup source bit 4" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " [3] ,Bit level mask for wakeup source bit 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,Bit level mask for wakeup source bit 2" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Bit level mask for wakeup source bit 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Bit level mask for wakeup source bit 0" "Not masked,Masked"
|
|
line.long 0x04 "PWRSMWAKEMASK1,Power SM Wake Mask 1 Register"
|
|
bitfld.long 0x04 31. " PWRSMWAKEMASK1[63] ,Bit level mask for wakeup source bit 63" "Not masked,Masked"
|
|
bitfld.long 0x04 30. " [62] ,Bit level mask for wakeup source bit 62" "Not masked,Masked"
|
|
bitfld.long 0x04 29. " [61] ,Bit level mask for wakeup source bit 61" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 28. " [60] ,Bit level mask for wakeup source bit 60" "Not masked,Masked"
|
|
bitfld.long 0x04 27. " [59] ,Bit level mask for wakeup source bit 59" "Not masked,Masked"
|
|
bitfld.long 0x04 26. " [58] ,Bit level mask for wakeup source bit 58" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 25. " [57] ,Bit level mask for wakeup source bit 57" "Not masked,Masked"
|
|
bitfld.long 0x04 24. " [56] ,Bit level mask for wakeup source bit 56" "Not masked,Masked"
|
|
bitfld.long 0x04 23. " [55] ,Bit level mask for wakeup source bit 55" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 22. " [54] ,Bit level mask for wakeup source bit 54" "Not masked,Masked"
|
|
bitfld.long 0x04 21. " [53] ,Bit level mask for wakeup source bit 53" "Not masked,Masked"
|
|
bitfld.long 0x04 20. " [52] ,Bit level mask for wakeup source bit 52" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 19. " [51] ,Bit level mask for wakeup source bit 51" "Not masked,Masked"
|
|
bitfld.long 0x04 18. " [50] ,Bit level mask for wakeup source bit 50" "Not masked,Masked"
|
|
bitfld.long 0x04 17. " [49] ,Bit level mask for wakeup source bit 49" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 16. " [48] ,Bit level mask for wakeup source bit 48" "Not masked,Masked"
|
|
bitfld.long 0x04 15. " [47] ,Bit level mask for wakeup source bit 47" "Not masked,Masked"
|
|
bitfld.long 0x04 14. " [46] ,Bit level mask for wakeup source bit 46" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 13. " [45] ,Bit level mask for wakeup source bit 45" "Not masked,Masked"
|
|
bitfld.long 0x04 12. " [44] ,Bit level mask for wakeup source bit 44" "Not masked,Masked"
|
|
bitfld.long 0x04 11. " [43] ,Bit level mask for wakeup source bit 43" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 10. " [42] ,Bit level mask for wakeup source bit 42" "Not masked,Masked"
|
|
bitfld.long 0x04 9. " [41] ,Bit level mask for wakeup source bit 41" "Not masked,Masked"
|
|
bitfld.long 0x04 8. " [40] ,Bit level mask for wakeup source bit 40" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 7. " [39] ,Bit level mask for wakeup source bit 39" "Not masked,Masked"
|
|
bitfld.long 0x04 6. " [38] ,Bit level mask for wakeup source bit 38" "Not masked,Masked"
|
|
bitfld.long 0x04 5. " [37] ,Bit level mask for wakeup source bit 37" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 4. " [36] ,Bit level mask for wakeup source bit 36" "Not masked,Masked"
|
|
bitfld.long 0x04 3. " [35] ,Bit level mask for wakeup source bit 35" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " [34] ,Bit level mask for wakeup source bit 34" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,Bit level mask for wakeup source bit 33" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " [32] ,Bit level mask for wakeup source bit 32" "Not masked,Masked"
|
|
line.long 0x08 "PWRSMWAKEMASK2,Power SM Wake Mask 2 Register"
|
|
bitfld.long 0x08 31. " PWRSMWAKEMASK2[95] ,Bit level mask for wakeup source bit 95" "Not masked,Masked"
|
|
bitfld.long 0x08 30. " [94] ,Bit level mask for wakeup source bit 94" "Not masked,Masked"
|
|
bitfld.long 0x08 29. " [93] ,Bit level mask for wakeup source bit 93" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 28. " [92] ,Bit level mask for wakeup source bit 92" "Not masked,Masked"
|
|
bitfld.long 0x08 27. " [91] ,Bit level mask for wakeup source bit 91" "Not masked,Masked"
|
|
bitfld.long 0x08 26. " [90] ,Bit level mask for wakeup source bit 90" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 25. " [89] ,Bit level mask for wakeup source bit 89" "Not masked,Masked"
|
|
bitfld.long 0x08 24. " [88] ,Bit level mask for wakeup source bit 88" "Not masked,Masked"
|
|
bitfld.long 0x08 23. " [87] ,Bit level mask for wakeup source bit 87" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 22. " [86] ,Bit level mask for wakeup source bit 86" "Not masked,Masked"
|
|
bitfld.long 0x08 21. " [85] ,Bit level mask for wakeup source bit 85" "Not masked,Masked"
|
|
bitfld.long 0x08 20. " [84] ,Bit level mask for wakeup source bit 84" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 19. " [83] ,Bit level mask for wakeup source bit 83" "Not masked,Masked"
|
|
bitfld.long 0x08 18. " [82] ,Bit level mask for wakeup source bit 82" "Not masked,Masked"
|
|
bitfld.long 0x08 17. " [81] ,Bit level mask for wakeup source bit 81" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 16. " [80] ,Bit level mask for wakeup source bit 80" "Not masked,Masked"
|
|
bitfld.long 0x08 15. " [79] ,Bit level mask for wakeup source bit 79" "Not masked,Masked"
|
|
bitfld.long 0x08 14. " [78] ,Bit level mask for wakeup source bit 78" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 13. " [77] ,Bit level mask for wakeup source bit 77" "Not masked,Masked"
|
|
bitfld.long 0x08 12. " [76] ,Bit level mask for wakeup source bit 76" "Not masked,Masked"
|
|
bitfld.long 0x08 11. " [75] ,Bit level mask for wakeup source bit 75" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 10. " [74] ,Bit level mask for wakeup source bit 74" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " [73] ,Bit level mask for wakeup source bit 73" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " [72] ,Bit level mask for wakeup source bit 72" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 7. " [71] ,Bit level mask for wakeup source bit 71" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " [70] ,Bit level mask for wakeup source bit 70" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " [69] ,Bit level mask for wakeup source bit 69" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 4. " [68] ,Bit level mask for wakeup source bit 68" "Not masked,Masked"
|
|
bitfld.long 0x08 3. " [67] ,Bit level mask for wakeup source bit 67" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " [66] ,Bit level mask for wakeup source bit 66" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 1. " [65] ,Bit level mask for wakeup source bit 65" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " [64] ,Bit level mask for wakeup source bit 64" "Not masked,Masked"
|
|
line.long 0x0C "PWRSMMISEVTMASK0,Power SM Missed Event Mask 0 Register"
|
|
bitfld.long 0x0C 31. " PWRSMMISEVTMASK0[31] ,Bit level mask for missed event 31" "Not masked,Masked"
|
|
bitfld.long 0x0C 30. " [30] ,Bit level mask for missed event 30" "Not masked,Masked"
|
|
bitfld.long 0x0C 29. " [29] ,Bit level mask for missed event 29" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 28. " [28] ,Bit level mask for missed event 28" "Not masked,Masked"
|
|
bitfld.long 0x0C 27. " [27] ,Bit level mask for missed event 27" "Not masked,Masked"
|
|
bitfld.long 0x0C 26. " [26] ,Bit level mask for missed event 26" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 25. " [25] ,Bit level mask for missed event 25" "Not masked,Masked"
|
|
bitfld.long 0x0C 24. " [24] ,Bit level mask for missed event 24" "Not masked,Masked"
|
|
bitfld.long 0x0C 23. " [23] ,Bit level mask for missed event 23" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 22. " [22] ,Bit level mask for missed event 22" "Not masked,Masked"
|
|
bitfld.long 0x0C 21. " [21] ,Bit level mask for missed event 21" "Not masked,Masked"
|
|
bitfld.long 0x0C 20. " [20] ,Bit level mask for missed event 20" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 19. " [19] ,Bit level mask for missed event 19" "Not masked,Masked"
|
|
bitfld.long 0x0C 18. " [18] ,Bit level mask for missed event 18" "Not masked,Masked"
|
|
bitfld.long 0x0C 17. " [17] ,Bit level mask for missed event 17" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 16. " [16] ,Bit level mask for missed event 16" "Not masked,Masked"
|
|
bitfld.long 0x0C 15. " [15] ,Bit level mask for missed event 15" "Not masked,Masked"
|
|
bitfld.long 0x0C 14. " [14] ,Bit level mask for missed event 14" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 13. " [13] ,Bit level mask for missed event 13" "Not masked,Masked"
|
|
bitfld.long 0x0C 12. " [12] ,Bit level mask for missed event 12" "Not masked,Masked"
|
|
bitfld.long 0x0C 11. " [11] ,Bit level mask for missed event 11" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 10. " [10] ,Bit level mask for missed event 10" "Not masked,Masked"
|
|
bitfld.long 0x0C 9. " [9] ,Bit level mask for missed event 9" "Not masked,Masked"
|
|
bitfld.long 0x0C 8. " [8] ,Bit level mask for missed event 8" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 7. " [7] ,Bit level mask for missed event 7" "Not masked,Masked"
|
|
bitfld.long 0x0C 6. " [6] ,Bit level mask for missed event 6" "Not masked,Masked"
|
|
bitfld.long 0x0C 5. " [5] ,Bit level mask for missed event 5" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 4. " [4] ,Bit level mask for missed event 4" "Not masked,Masked"
|
|
bitfld.long 0x0C 3. " [3] ,Bit level mask for missed event 3" "Not masked,Masked"
|
|
bitfld.long 0x0C 2. " [2] ,Bit level mask for missed event 2" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x0C 1. " [1] ,Bit level mask for missed event 1" "Not masked,Masked"
|
|
bitfld.long 0x0C 0. " [0] ,Bit level mask for missed event 0" "Not masked,Masked"
|
|
line.long 0x10 "PWRSMMISEVTMASK1,Power SM Missed Event Mask 1 Register"
|
|
bitfld.long 0x10 31. " PWRSMMISEVTMASK1[63] ,Bit level mask for missed event 63" "Not masked,Masked"
|
|
bitfld.long 0x10 30. " [62] ,Bit level mask for missed event 62" "Not masked,Masked"
|
|
bitfld.long 0x10 29. " [61] ,Bit level mask for missed event 61" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 28. " [60] ,Bit level mask for missed event 60" "Not masked,Masked"
|
|
bitfld.long 0x10 27. " [59] ,Bit level mask for missed event 59" "Not masked,Masked"
|
|
bitfld.long 0x10 26. " [58] ,Bit level mask for missed event 58" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 25. " [57] ,Bit level mask for missed event 57" "Not masked,Masked"
|
|
bitfld.long 0x10 24. " [56] ,Bit level mask for missed event 56" "Not masked,Masked"
|
|
bitfld.long 0x10 23. " [55] ,Bit level mask for missed event 55" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 22. " [54] ,Bit level mask for missed event 54" "Not masked,Masked"
|
|
bitfld.long 0x10 21. " [53] ,Bit level mask for missed event 53" "Not masked,Masked"
|
|
bitfld.long 0x10 20. " [52] ,Bit level mask for missed event 52" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 19. " [51] ,Bit level mask for missed event 51" "Not masked,Masked"
|
|
bitfld.long 0x10 18. " [50] ,Bit level mask for missed event 50" "Not masked,Masked"
|
|
bitfld.long 0x10 17. " [49] ,Bit level mask for missed event 49" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 16. " [48] ,Bit level mask for missed event 48" "Not masked,Masked"
|
|
bitfld.long 0x10 15. " [47] ,Bit level mask for missed event 47" "Not masked,Masked"
|
|
bitfld.long 0x10 14. " [46] ,Bit level mask for missed event 46" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 13. " [45] ,Bit level mask for missed event 45" "Not masked,Masked"
|
|
bitfld.long 0x10 12. " [44] ,Bit level mask for missed event 44" "Not masked,Masked"
|
|
bitfld.long 0x10 11. " [43] ,Bit level mask for missed event 43" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 10. " [42] ,Bit level mask for missed event 42" "Not masked,Masked"
|
|
bitfld.long 0x10 9. " [41] ,Bit level mask for missed event 41" "Not masked,Masked"
|
|
bitfld.long 0x10 8. " [40] ,Bit level mask for missed event 40" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 7. " [39] ,Bit level mask for missed event 39" "Not masked,Masked"
|
|
bitfld.long 0x10 6. " [38] ,Bit level mask for missed event 38" "Not masked,Masked"
|
|
bitfld.long 0x10 5. " [37] ,Bit level mask for missed event 37" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 4. " [36] ,Bit level mask for missed event 36" "Not masked,Masked"
|
|
bitfld.long 0x10 3. " [35] ,Bit level mask for missed event 35" "Not masked,Masked"
|
|
bitfld.long 0x10 2. " [34] ,Bit level mask for missed event 34" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x10 1. " [33] ,Bit level mask for missed event 33" "Not masked,Masked"
|
|
bitfld.long 0x10 0. " [32] ,Bit level mask for missed event 32" "Not masked,Masked"
|
|
line.long 0x14 "PWRSMMISEVTMASK2,Power SM Missed Event Mask 2 Register"
|
|
bitfld.long 0x14 31. " PWRSMMISEVTMASK2[95] ,Bit level mask for missed event 95" "Not masked,Masked"
|
|
bitfld.long 0x14 30. " [94] ,Bit level mask for missed event 94" "Not masked,Masked"
|
|
bitfld.long 0x14 29. " [93] ,Bit level mask for missed event 93" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 28. " [92] ,Bit level mask for missed event 92" "Not masked,Masked"
|
|
bitfld.long 0x14 27. " [91] ,Bit level mask for missed event 91" "Not masked,Masked"
|
|
bitfld.long 0x14 26. " [90] ,Bit level mask for missed event 90" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 25. " [89] ,Bit level mask for missed event 89" "Not masked,Masked"
|
|
bitfld.long 0x14 24. " [88] ,Bit level mask for missed event 88" "Not masked,Masked"
|
|
bitfld.long 0x14 23. " [87] ,Bit level mask for missed event 87" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 22. " [86] ,Bit level mask for missed event 86" "Not masked,Masked"
|
|
bitfld.long 0x14 21. " [85] ,Bit level mask for missed event 85" "Not masked,Masked"
|
|
bitfld.long 0x14 20. " [84] ,Bit level mask for missed event 84" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 19. " [83] ,Bit level mask for missed event 83" "Not masked,Masked"
|
|
bitfld.long 0x14 18. " [82] ,Bit level mask for missed event 82" "Not masked,Masked"
|
|
bitfld.long 0x14 17. " [81] ,Bit level mask for missed event 81" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 16. " [80] ,Bit level mask for missed event 80" "Not masked,Masked"
|
|
bitfld.long 0x14 15. " [79] ,Bit level mask for missed event 79" "Not masked,Masked"
|
|
bitfld.long 0x14 14. " [78] ,Bit level mask for missed event 78" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 13. " [77] ,Bit level mask for missed event 77" "Not masked,Masked"
|
|
bitfld.long 0x14 12. " [76] ,Bit level mask for missed event 76" "Not masked,Masked"
|
|
bitfld.long 0x14 11. " [75] ,Bit level mask for missed event 75" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 10. " [74] ,Bit level mask for missed event 74" "Not masked,Masked"
|
|
bitfld.long 0x14 9. " [73] ,Bit level mask for missed event 73" "Not masked,Masked"
|
|
bitfld.long 0x14 8. " [72] ,Bit level mask for missed event 72" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 7. " [71] ,Bit level mask for missed event 71" "Not masked,Masked"
|
|
bitfld.long 0x14 6. " [70] ,Bit level mask for missed event 70" "Not masked,Masked"
|
|
bitfld.long 0x14 5. " [69] ,Bit level mask for missed event 69" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 4. " [68] ,Bit level mask for missed event 68" "Not masked,Masked"
|
|
bitfld.long 0x14 3. " [67] ,Bit level mask for missed event 67" "Not masked,Masked"
|
|
bitfld.long 0x14 2. " [66] ,Bit level mask for missed event 66" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x14 1. " [65] ,Bit level mask for missed event 65" "Not masked,Masked"
|
|
bitfld.long 0x14 0. " [64] ,Bit level mask for missed event 64" "Not masked,Masked"
|
|
rgroup.long 0x2EC++0x07
|
|
line.long 0x00 "PWRSMWAKESRCSTAT0,Power SM Wake Source Status 0 Register"
|
|
bitfld.long 0x00 31. " PWRSMWAKESRCSTAT0[31] ,Wakeup source status bit 31" "0,1"
|
|
bitfld.long 0x00 30. " [30] ,Wakeup source status bit 30" "0,1"
|
|
bitfld.long 0x00 29. " [29] ,Wakeup source status bit 29" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Wakeup source status bit 28" "0,1"
|
|
bitfld.long 0x00 27. " [27] ,Wakeup source status bit 27" "0,1"
|
|
bitfld.long 0x00 26. " [26] ,Wakeup source status bit 26" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Wakeup source status bit 25" "0,1"
|
|
bitfld.long 0x00 24. " [24] ,Wakeup source status bit 24" "0,1"
|
|
bitfld.long 0x00 23. " [23] ,Wakeup source status bit 23" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Wakeup source status bit 22" "0,1"
|
|
bitfld.long 0x00 21. " [21] ,Wakeup source status bit 21" "0,1"
|
|
bitfld.long 0x00 20. " [20] ,Wakeup source status bit 20" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Wakeup source status bit 19" "0,1"
|
|
bitfld.long 0x00 18. " [18] ,Wakeup source status bit 18" "0,1"
|
|
bitfld.long 0x00 17. " [17] ,Wakeup source status bit 17" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Wakeup source status bit 16" "0,1"
|
|
bitfld.long 0x00 15. " [15] ,Wakeup source status bit 15" "0,1"
|
|
bitfld.long 0x00 14. " [14] ,Wakeup source status bit 14" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Wakeup source status bit 13" "0,1"
|
|
bitfld.long 0x00 12. " [12] ,Wakeup source status bit 12" "0,1"
|
|
bitfld.long 0x00 11. " [11] ,Wakeup source status bit 11" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Wakeup source status bit 10" "0,1"
|
|
bitfld.long 0x00 9. " [9] ,Wakeup source status bit 9" "0,1"
|
|
bitfld.long 0x00 8. " [8] ,Wakeup source status bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Wakeup source status bit 7" "0,1"
|
|
bitfld.long 0x00 6. " [6] ,Wakeup source status bit 6" "0,1"
|
|
bitfld.long 0x00 5. " [5] ,Wakeup source status bit 5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Wakeup source status bit 4" "0,1"
|
|
bitfld.long 0x00 3. " [3] ,Wakeup source status bit 3" "0,1"
|
|
bitfld.long 0x00 2. " [2] ,Wakeup source status bit 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Wakeup source status bit 1" "0,1"
|
|
bitfld.long 0x00 0. " [0] ,Wakeup source status bit 0" "0,1"
|
|
line.long 0x04 "PWRSMWAKESRCSTAT1,Power SM Wake Source Status 1 Register"
|
|
bitfld.long 0x04 31. " PWRSMWAKESRCSTAT1[63] ,Wakeup source status bit 63" "0,1"
|
|
bitfld.long 0x04 30. " [62] ,Wakeup source status bit 62" "0,1"
|
|
bitfld.long 0x04 29. " [61] ,Wakeup source status bit 61" "0,1"
|
|
newline
|
|
bitfld.long 0x04 28. " [60] ,Wakeup source status bit 60" "0,1"
|
|
bitfld.long 0x04 27. " [59] ,Wakeup source status bit 59" "0,1"
|
|
bitfld.long 0x04 26. " [58] ,Wakeup source status bit 58" "0,1"
|
|
newline
|
|
bitfld.long 0x04 25. " [57] ,Wakeup source status bit 57" "0,1"
|
|
bitfld.long 0x04 24. " [56] ,Wakeup source status bit 56" "0,1"
|
|
bitfld.long 0x04 23. " [55] ,Wakeup source status bit 55" "0,1"
|
|
newline
|
|
bitfld.long 0x04 22. " [54] ,Wakeup source status bit 54" "0,1"
|
|
bitfld.long 0x04 21. " [53] ,Wakeup source status bit 53" "0,1"
|
|
bitfld.long 0x04 20. " [52] ,Wakeup source status bit 52" "0,1"
|
|
newline
|
|
bitfld.long 0x04 19. " [51] ,Wakeup source status bit 51" "0,1"
|
|
bitfld.long 0x04 18. " [50] ,Wakeup source status bit 50" "0,1"
|
|
bitfld.long 0x04 17. " [49] ,Wakeup source status bit 49" "0,1"
|
|
newline
|
|
bitfld.long 0x04 16. " [48] ,Wakeup source status bit 48" "0,1"
|
|
bitfld.long 0x04 15. " [47] ,Wakeup source status bit 47" "0,1"
|
|
bitfld.long 0x04 14. " [46] ,Wakeup source status bit 46" "0,1"
|
|
newline
|
|
bitfld.long 0x04 13. " [45] ,Wakeup source status bit 45" "0,1"
|
|
bitfld.long 0x04 12. " [44] ,Wakeup source status bit 44" "0,1"
|
|
bitfld.long 0x04 11. " [43] ,Wakeup source status bit 43" "0,1"
|
|
newline
|
|
bitfld.long 0x04 10. " [42] ,Wakeup source status bit 42" "0,1"
|
|
bitfld.long 0x04 9. " [41] ,Wakeup source status bit 41" "0,1"
|
|
bitfld.long 0x04 8. " [40] ,Wakeup source status bit 40" "0,1"
|
|
newline
|
|
bitfld.long 0x04 7. " [39] ,Wakeup source status bit 39" "0,1"
|
|
bitfld.long 0x04 6. " [38] ,Wakeup source status bit 38" "0,1"
|
|
bitfld.long 0x04 5. " [37] ,Wakeup source status bit 37" "0,1"
|
|
newline
|
|
bitfld.long 0x04 4. " [36] ,Wakeup source status bit 36" "0,1"
|
|
bitfld.long 0x04 3. " [35] ,Wakeup source status bit 35" "0,1"
|
|
bitfld.long 0x04 2. " [34] ,Wakeup source status bit 34" "0,1"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,Wakeup source status bit 33" "0,1"
|
|
bitfld.long 0x04 0. " [32] ,Wakeup source status bit 32" "0,1"
|
|
rgroup.long 0x320++0x0F
|
|
line.long 0x00 "PWRSMWAKESRCSTAT2,Power SM Wake Source Status 2 Register"
|
|
bitfld.long 0x00 31. " PWRSMWAKESRCSTAT2[95] ,Wakeup source status bit 95" "0,1"
|
|
bitfld.long 0x00 30. " [94] ,Wakeup source status bit 94" "0,1"
|
|
bitfld.long 0x00 29. " [93] ,Wakeup source status bit 93" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. " [92] ,Wakeup source status bit 92" "0,1"
|
|
bitfld.long 0x00 27. " [91] ,Wakeup source status bit 91" "0,1"
|
|
bitfld.long 0x00 26. " [90] ,Wakeup source status bit 90" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " [89] ,Wakeup source status bit 89" "0,1"
|
|
bitfld.long 0x00 24. " [88] ,Wakeup source status bit 88" "0,1"
|
|
bitfld.long 0x00 23. " [87] ,Wakeup source status bit 87" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. " [86] ,Wakeup source status bit 86" "0,1"
|
|
bitfld.long 0x00 21. " [85] ,Wakeup source status bit 85" "0,1"
|
|
bitfld.long 0x00 20. " [84] ,Wakeup source status bit 84" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " [83] ,Wakeup source status bit 83" "0,1"
|
|
bitfld.long 0x00 18. " [82] ,Wakeup source status bit 82" "0,1"
|
|
bitfld.long 0x00 17. " [81] ,Wakeup source status bit 81" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " [80] ,Wakeup source status bit 80" "0,1"
|
|
bitfld.long 0x00 15. " [79] ,Wakeup source status bit 79" "0,1"
|
|
bitfld.long 0x00 14. " [78] ,Wakeup source status bit 78" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. " [77] ,Wakeup source status bit 77" "0,1"
|
|
bitfld.long 0x00 12. " [76] ,Wakeup source status bit 76" "0,1"
|
|
bitfld.long 0x00 11. " [75] ,Wakeup source status bit 75" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. " [74] ,Wakeup source status bit 74" "0,1"
|
|
bitfld.long 0x00 9. " [73] ,Wakeup source status bit 73" "0,1"
|
|
bitfld.long 0x00 8. " [72] ,Wakeup source status bit 72" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " [71] ,Wakeup source status bit 71" "0,1"
|
|
bitfld.long 0x00 6. " [70] ,Wakeup source status bit 70" "0,1"
|
|
bitfld.long 0x00 5. " [69] ,Wakeup source status bit 69" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. " [68] ,Wakeup source status bit 68" "0,1"
|
|
bitfld.long 0x00 3. " [67] ,Wakeup source status bit 67" "0,1"
|
|
bitfld.long 0x00 2. " [66] ,Wakeup source status bit 66" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. " [65] ,Wakeup source status bit 65" "0,1"
|
|
bitfld.long 0x00 0. " [64] ,Wakeup source status bit 64" "0,1"
|
|
line.long 0x04 "PWRSMEVNTMONSTAT0,Power SM Event Monitor Status 0 Register"
|
|
bitfld.long 0x04 31. " PWRSMEVNTMONSTAT0[31] ,Missed event monitor status bit 31" "Not missed,Missed"
|
|
bitfld.long 0x04 30. " [30] ,Missed event monitor status bit 30" "Not missed,Missed"
|
|
bitfld.long 0x04 29. " [29] ,Missed event monitor status bit 29" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 28. " [28] ,Missed event monitor status bit 28" "Not missed,Missed"
|
|
bitfld.long 0x04 27. " [27] ,Missed event monitor status bit 27" "Not missed,Missed"
|
|
bitfld.long 0x04 26. " [26] ,Missed event monitor status bit 26" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,Missed event monitor status bit 25" "Not missed,Missed"
|
|
bitfld.long 0x04 24. " [24] ,Missed event monitor status bit 24" "Not missed,Missed"
|
|
bitfld.long 0x04 23. " [23] ,Missed event monitor status bit 23" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,Missed event monitor status bit 22" "Not missed,Missed"
|
|
bitfld.long 0x04 21. " [21] ,Missed event monitor status bit 21" "Not missed,Missed"
|
|
bitfld.long 0x04 20. " [20] ,Missed event monitor status bit 20" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Missed event monitor status bit 19" "Not missed,Missed"
|
|
bitfld.long 0x04 18. " [18] ,Missed event monitor status bit 18" "Not missed,Missed"
|
|
bitfld.long 0x04 17. " [17] ,Missed event monitor status bit 17" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 16. " [16] ,Missed event monitor status bit 16" "Not missed,Missed"
|
|
bitfld.long 0x04 15. " [15] ,Missed event monitor status bit 15" "Not missed,Missed"
|
|
bitfld.long 0x04 14. " [14] ,Missed event monitor status bit 14" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,Missed event monitor status bit 13" "Not missed,Missed"
|
|
bitfld.long 0x04 12. " [12] ,Missed event monitor status bit 12" "Not missed,Missed"
|
|
bitfld.long 0x04 11. " [11] ,Missed event monitor status bit 11" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 10. " [10] ,Missed event monitor status bit 10" "Not missed,Missed"
|
|
bitfld.long 0x04 9. " [9] ,Missed event monitor status bit 9" "Not missed,Missed"
|
|
bitfld.long 0x04 8. " [8] ,Missed event monitor status bit 8" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Missed event monitor status bit 7" "Not missed,Missed"
|
|
bitfld.long 0x04 6. " [6] ,Missed event monitor status bit 6" "Not missed,Missed"
|
|
bitfld.long 0x04 5. " [5] ,Missed event monitor status bit 5" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Missed event monitor status bit 4" "Not missed,Missed"
|
|
bitfld.long 0x04 3. " [3] ,Missed event monitor status bit 3" "Not missed,Missed"
|
|
bitfld.long 0x04 2. " [2] ,Missed event monitor status bit 2" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x04 1. " [1] ,Missed event monitor status bit 1" "Not missed,Missed"
|
|
bitfld.long 0x04 0. " [0] ,Missed event monitor status bit 0" "Not missed,Missed"
|
|
line.long 0x08 "PWRSMEVNTMONSTAT1,Power SM Event Monitor Status 1 Register"
|
|
bitfld.long 0x08 31. " PWRSMEVNTMONSTAT1[63] ,Missed event monitor status bit 63" "Not missed,Missed"
|
|
bitfld.long 0x08 30. " [62] ,Missed event monitor status bit 62" "Not missed,Missed"
|
|
bitfld.long 0x08 29. " [61] ,Missed event monitor status bit 61" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 28. " [60] ,Missed event monitor status bit 60" "Not missed,Missed"
|
|
bitfld.long 0x08 27. " [59] ,Missed event monitor status bit 59" "Not missed,Missed"
|
|
bitfld.long 0x08 26. " [58] ,Missed event monitor status bit 58" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 25. " [57] ,Missed event monitor status bit 57" "Not missed,Missed"
|
|
bitfld.long 0x08 24. " [56] ,Missed event monitor status bit 56" "Not missed,Missed"
|
|
bitfld.long 0x08 23. " [55] ,Missed event monitor status bit 55" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 22. " [54] ,Missed event monitor status bit 54" "Not missed,Missed"
|
|
bitfld.long 0x08 21. " [53] ,Missed event monitor status bit 53" "Not missed,Missed"
|
|
bitfld.long 0x08 20. " [52] ,Missed event monitor status bit 52" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 19. " [51] ,Missed event monitor status bit 51" "Not missed,Missed"
|
|
bitfld.long 0x08 18. " [50] ,Missed event monitor status bit 50" "Not missed,Missed"
|
|
bitfld.long 0x08 17. " [49] ,Missed event monitor status bit 49" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 16. " [48] ,Missed event monitor status bit 48" "Not missed,Missed"
|
|
bitfld.long 0x08 15. " [47] ,Missed event monitor status bit 47" "Not missed,Missed"
|
|
bitfld.long 0x08 14. " [46] ,Missed event monitor status bit 46" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 13. " [45] ,Missed event monitor status bit 45" "Not missed,Missed"
|
|
bitfld.long 0x08 12. " [44] ,Missed event monitor status bit 44" "Not missed,Missed"
|
|
bitfld.long 0x08 11. " [43] ,Missed event monitor status bit 43" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 10. " [42] ,Missed event monitor status bit 42" "Not missed,Missed"
|
|
bitfld.long 0x08 9. " [41] ,Missed event monitor status bit 41" "Not missed,Missed"
|
|
bitfld.long 0x08 8. " [40] ,Missed event monitor status bit 40" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 7. " [39] ,Missed event monitor status bit 39" "Not missed,Missed"
|
|
bitfld.long 0x08 6. " [38] ,Missed event monitor status bit 38" "Not missed,Missed"
|
|
bitfld.long 0x08 5. " [37] ,Missed event monitor status bit 37" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 4. " [36] ,Missed event monitor status bit 36" "Not missed,Missed"
|
|
bitfld.long 0x08 3. " [35] ,Missed event monitor status bit 35" "Not missed,Missed"
|
|
bitfld.long 0x08 2. " [34] ,Missed event monitor status bit 34" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x08 1. " [33] ,Missed event monitor status bit 33" "Not missed,Missed"
|
|
bitfld.long 0x08 0. " [32] ,Missed event monitor status bit 32" "Not missed,Missed"
|
|
line.long 0x0C "PWRSMEVNTMONSTAT2,Power SM Event Monitor Status 2 Register"
|
|
bitfld.long 0x0C 31. " PWRSMEVNTMONSTAT2[95] ,Missed event monitor status bit 95" "Not missed,Missed"
|
|
bitfld.long 0x0C 30. " [94] ,Missed event monitor status bit 94" "Not missed,Missed"
|
|
bitfld.long 0x0C 29. " [93] ,Missed event monitor status bit 93" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 28. " [92] ,Missed event monitor status bit 92" "Not missed,Missed"
|
|
bitfld.long 0x0C 27. " [91] ,Missed event monitor status bit 91" "Not missed,Missed"
|
|
bitfld.long 0x0C 26. " [90] ,Missed event monitor status bit 90" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 25. " [89] ,Missed event monitor status bit 89" "Not missed,Missed"
|
|
bitfld.long 0x0C 24. " [88] ,Missed event monitor status bit 88" "Not missed,Missed"
|
|
bitfld.long 0x0C 23. " [87] ,Missed event monitor status bit 87" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 22. " [86] ,Missed event monitor status bit 86" "Not missed,Missed"
|
|
bitfld.long 0x0C 21. " [85] ,Missed event monitor status bit 85" "Not missed,Missed"
|
|
bitfld.long 0x0C 20. " [84] ,Missed event monitor status bit 84" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 19. " [83] ,Missed event monitor status bit 83" "Not missed,Missed"
|
|
bitfld.long 0x0C 18. " [82] ,Missed event monitor status bit 82" "Not missed,Missed"
|
|
bitfld.long 0x0C 17. " [81] ,Missed event monitor status bit 81" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 16. " [80] ,Missed event monitor status bit 80" "Not missed,Missed"
|
|
bitfld.long 0x0C 15. " [79] ,Missed event monitor status bit 79" "Not missed,Missed"
|
|
bitfld.long 0x0C 14. " [78] ,Missed event monitor status bit 78" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 13. " [77] ,Missed event monitor status bit 77" "Not missed,Missed"
|
|
bitfld.long 0x0C 12. " [76] ,Missed event monitor status bit 76" "Not missed,Missed"
|
|
bitfld.long 0x0C 11. " [75] ,Missed event monitor status bit 75" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 10. " [74] ,Missed event monitor status bit 74" "Not missed,Missed"
|
|
bitfld.long 0x0C 9. " [73] ,Missed event monitor status bit 73" "Not missed,Missed"
|
|
bitfld.long 0x0C 8. " [72] ,Missed event monitor status bit 72" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 7. " [71] ,Missed event monitor status bit 71" "Not missed,Missed"
|
|
bitfld.long 0x0C 6. " [70] ,Missed event monitor status bit 70" "Not missed,Missed"
|
|
bitfld.long 0x0C 5. " [69] ,Missed event monitor status bit 69" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 4. " [68] ,Missed event monitor status bit 68" "Not missed,Missed"
|
|
bitfld.long 0x0C 3. " [67] ,Missed event monitor status bit 67" "Not missed,Missed"
|
|
bitfld.long 0x0C 2. " [66] ,Missed event monitor status bit 66" "Not missed,Missed"
|
|
newline
|
|
bitfld.long 0x0C 1. " [65] ,Missed event monitor status bit 65" "Not missed,Missed"
|
|
bitfld.long 0x0C 0. " [64] ,Missed event monitor status bit 64" "Not missed,Missed"
|
|
group.long 0x330++0x23
|
|
line.long 0x00 "PWRSMWAKESRCSTATCLR0,Power SM Wake Source Status Clear 0 Register"
|
|
bitfld.long 0x00 31. " PWRSMWAKESRCSTATCLR0[31] ,Clear wakeup source status bit 31" "Not cleared,Cleared"
|
|
bitfld.long 0x00 30. " [30] ,Clear wakeup source status bit 30" "Not cleared,Cleared"
|
|
bitfld.long 0x00 29. " [29] ,Clear wakeup source status bit 29" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 28. " [28] ,Clear wakeup source status bit 28" "Not cleared,Cleared"
|
|
bitfld.long 0x00 27. " [27] ,Clear wakeup source status bit 27" "Not cleared,Cleared"
|
|
bitfld.long 0x00 26. " [26] ,Clear wakeup source status bit 26" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Clear wakeup source status bit 25" "Not cleared,Cleared"
|
|
bitfld.long 0x00 24. " [24] ,Clear wakeup source status bit 24" "Not cleared,Cleared"
|
|
bitfld.long 0x00 23. " [23] ,Clear wakeup source status bit 23" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Clear wakeup source status bit 22" "Not cleared,Cleared"
|
|
bitfld.long 0x00 21. " [21] ,Clear wakeup source status bit 21" "Not cleared,Cleared"
|
|
bitfld.long 0x00 20. " [20] ,Clear wakeup source status bit 20" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Clear wakeup source status bit 19" "Not cleared,Cleared"
|
|
bitfld.long 0x00 18. " [18] ,Clear wakeup source status bit 18" "Not cleared,Cleared"
|
|
bitfld.long 0x00 17. " [17] ,Clear wakeup source status bit 17" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 16. " [16] ,Clear wakeup source status bit 16" "Not cleared,Cleared"
|
|
bitfld.long 0x00 15. " [15] ,Clear wakeup source status bit 15" "Not cleared,Cleared"
|
|
bitfld.long 0x00 14. " [14] ,Clear wakeup source status bit 14" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Clear wakeup source status bit 13" "Not cleared,Cleared"
|
|
bitfld.long 0x00 12. " [12] ,Clear wakeup source status bit 12" "Not cleared,Cleared"
|
|
bitfld.long 0x00 11. " [11] ,Clear wakeup source status bit 11" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Clear wakeup source status bit 10" "Not cleared,Cleared"
|
|
bitfld.long 0x00 9. " [9] ,Clear wakeup source status bit 9" "Not cleared,Cleared"
|
|
bitfld.long 0x00 8. " [8] ,Clear wakeup source status bit 8" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Clear wakeup source status bit 7" "Not cleared,Cleared"
|
|
bitfld.long 0x00 6. " [6] ,Clear wakeup source status bit 6" "Not cleared,Cleared"
|
|
bitfld.long 0x00 5. " [5] ,Clear wakeup source status bit 5" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Clear wakeup source status bit 4" "Not cleared,Cleared"
|
|
bitfld.long 0x00 3. " [3] ,Clear wakeup source status bit 3" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " [2] ,Clear wakeup source status bit 2" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Clear wakeup source status bit 1" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " [0] ,Clear wakeup source status bit 0" "Not cleared,Cleared"
|
|
line.long 0x04 "PWRSMWAKESRCSTATCLR1,Power SM Wake Source Status Clear 1 Register"
|
|
bitfld.long 0x04 31. " PWRSMWAKESRCSTATCLR1[63] ,Clear wakeup source status bit 63" "Not cleared,Cleared"
|
|
bitfld.long 0x04 30. " [62] ,Clear wakeup source status bit 62" "Not cleared,Cleared"
|
|
bitfld.long 0x04 29. " [61] ,Clear wakeup source status bit 61" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 28. " [60] ,Clear wakeup source status bit 60" "Not cleared,Cleared"
|
|
bitfld.long 0x04 27. " [59] ,Clear wakeup source status bit 59" "Not cleared,Cleared"
|
|
bitfld.long 0x04 26. " [58] ,Clear wakeup source status bit 58" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 25. " [57] ,Clear wakeup source status bit 57" "Not cleared,Cleared"
|
|
bitfld.long 0x04 24. " [56] ,Clear wakeup source status bit 56" "Not cleared,Cleared"
|
|
bitfld.long 0x04 23. " [55] ,Clear wakeup source status bit 55" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 22. " [54] ,Clear wakeup source status bit 54" "Not cleared,Cleared"
|
|
bitfld.long 0x04 21. " [53] ,Clear wakeup source status bit 53" "Not cleared,Cleared"
|
|
bitfld.long 0x04 20. " [52] ,Clear wakeup source status bit 52" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 19. " [51] ,Clear wakeup source status bit 51" "Not cleared,Cleared"
|
|
bitfld.long 0x04 18. " [50] ,Clear wakeup source status bit 50" "Not cleared,Cleared"
|
|
bitfld.long 0x04 17. " [49] ,Clear wakeup source status bit 49" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 16. " [48] ,Clear wakeup source status bit 48" "Not cleared,Cleared"
|
|
bitfld.long 0x04 15. " [47] ,Clear wakeup source status bit 47" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [46] ,Clear wakeup source status bit 46" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 13. " [45] ,Clear wakeup source status bit 45" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [44] ,Clear wakeup source status bit 44" "Not cleared,Cleared"
|
|
bitfld.long 0x04 11. " [43] ,Clear wakeup source status bit 43" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 10. " [42] ,Clear wakeup source status bit 42" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [41] ,Clear wakeup source status bit 41" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [40] ,Clear wakeup source status bit 40" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [39] ,Clear wakeup source status bit 39" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [38] ,Clear wakeup source status bit 38" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [37] ,Clear wakeup source status bit 37" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 4. " [36] ,Clear wakeup source status bit 36" "Not cleared,Cleared"
|
|
bitfld.long 0x04 3. " [35] ,Clear wakeup source status bit 35" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [34] ,Clear wakeup source status bit 34" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 1. " [33] ,Clear wakeup source status bit 33" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [32] ,Clear wakeup source status bit 32" "Not cleared,Cleared"
|
|
line.long 0x08 "PWRSMWAKESRCSTATCLR2,Power SM Wake Source Status Clear 2 Register"
|
|
bitfld.long 0x08 31. " PWRSMWAKESRCSTATCLR2[95] ,Clear wakeup source status bit 95" "Not cleared,Cleared"
|
|
bitfld.long 0x08 30. " [94] ,Clear wakeup source status bit 94" "Not cleared,Cleared"
|
|
bitfld.long 0x08 29. " [93] ,Clear wakeup source status bit 93" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 28. " [92] ,Clear wakeup source status bit 92" "Not cleared,Cleared"
|
|
bitfld.long 0x08 27. " [91] ,Clear wakeup source status bit 91" "Not cleared,Cleared"
|
|
bitfld.long 0x08 26. " [90] ,Clear wakeup source status bit 90" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 25. " [89] ,Clear wakeup source status bit 89" "Not cleared,Cleared"
|
|
bitfld.long 0x08 24. " [88] ,Clear wakeup source status bit 88" "Not cleared,Cleared"
|
|
bitfld.long 0x08 23. " [87] ,Clear wakeup source status bit 87" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 22. " [86] ,Clear wakeup source status bit 86" "Not cleared,Cleared"
|
|
bitfld.long 0x08 21. " [85] ,Clear wakeup source status bit 85" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " [84] ,Clear wakeup source status bit 84" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 19. " [83] ,Clear wakeup source status bit 83" "Not cleared,Cleared"
|
|
bitfld.long 0x08 18. " [82] ,Clear wakeup source status bit 82" "Not cleared,Cleared"
|
|
bitfld.long 0x08 17. " [81] ,Clear wakeup source status bit 81" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 16. " [80] ,Clear wakeup source status bit 80" "Not cleared,Cleared"
|
|
bitfld.long 0x08 15. " [79] ,Clear wakeup source status bit 79" "Not cleared,Cleared"
|
|
bitfld.long 0x08 14. " [78] ,Clear wakeup source status bit 78" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 13. " [77] ,Clear wakeup source status bit 77" "Not cleared,Cleared"
|
|
bitfld.long 0x08 12. " [76] ,Clear wakeup source status bit 76" "Not cleared,Cleared"
|
|
bitfld.long 0x08 11. " [75] ,Clear wakeup source status bit 75" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 10. " [74] ,Clear wakeup source status bit 74" "Not cleared,Cleared"
|
|
bitfld.long 0x08 9. " [73] ,Clear wakeup source status bit 73" "Not cleared,Cleared"
|
|
bitfld.long 0x08 8. " [72] ,Clear wakeup source status bit 72" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 7. " [71] ,Clear wakeup source status bit 71" "Not cleared,Cleared"
|
|
bitfld.long 0x08 6. " [70] ,Clear wakeup source status bit 70" "Not cleared,Cleared"
|
|
bitfld.long 0x08 5. " [69] ,Clear wakeup source status bit 69" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 4. " [68] ,Clear wakeup source status bit 68" "Not cleared,Cleared"
|
|
bitfld.long 0x08 3. " [67] ,Clear wakeup source status bit 67" "Not cleared,Cleared"
|
|
bitfld.long 0x08 2. " [66] ,Clear wakeup source status bit 66" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x08 1. " [65] ,Clear wakeup source status bit 65" "Not cleared,Cleared"
|
|
bitfld.long 0x08 0. " [64] ,Clear wakeup source status bit 64" "Not cleared,Cleared"
|
|
line.long 0x0C "ADCBUFCFG1,ADC Buffer Configuration 1 Register"
|
|
bitfld.long 0x0C 15. " ADCBUFCONTSTOPPL ,Enable stop pulse for continuous mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " ADCBUFCONTSTRTPL ,Enable start pulse for continuous mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " ADCBUFCONTMODEEN ,Continuous mode enable for ADC buffer" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 12. " ADCBUFWRITEMODE ,ADC buffer write mode" "Interleaved,Non-interleaved"
|
|
bitfld.long 0x0C 9. " RX3EN ,Enable for Rx3 write" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " RX2EN ,Enable for Rx2 write" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 7. " RX1EN ,Enable for Rx1 write" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " RX0EN ,Enable for Rx0 write" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " ADCBUFIQSWAP ,ADC buffer I/Q swap" "I LSB / Q MSB,I MSB / Q LSB"
|
|
newline
|
|
bitfld.long 0x0C 2. " ADCBUFREALONLYMODE ,ADC buffer mode select" "Complex,Real"
|
|
line.long 0x10 "ADCBUFCFG2,ADC Buffer Configuration 2 Register"
|
|
hexmask.long.word 0x10 16.--26. 0x01 " ADCBUFADDRX1 ,128 bit address offset 1"
|
|
hexmask.long.word 0x10 0.--10. 0x01 " ADCBUFADDRX0 ,128 bit address offset 0"
|
|
line.long 0x14 "ADCBUFCFG3,ADC Buffer Configuration 3 Register"
|
|
hexmask.long.word 0x14 16.--26. 0x01 " ADCBUFADDRX3 ,128 bit address offset 3"
|
|
hexmask.long.word 0x14 0.--10. 0x01 " ADCBUFADDRX2 ,128 bit address offset 2"
|
|
line.long 0x18 "ADCBUFCFG4,ADC Buffer Configuration 4 Register"
|
|
bitfld.long 0x18 21.--25. " ADCBUFNUMCHRPPONG ,Number of chirps to be stored in pong buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x18 16.--20. " ADCBUFNUMCHRPPING ,Number of chirps to be stored in ping buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x18 0.--15. 1. " ADCBUFSAMPCNT ,ADC buffer samples counter"
|
|
line.long 0x1C "STCPBISTSMCFG1,STC PBIST SM Configuration 1 Register"
|
|
rbitfld.long 0x1C 20. " PBISTTESTSTATCLR ,Clear bit for PBIST status" "Not cleared,Cleared"
|
|
rbitfld.long 0x1C 19. " PBISTTESTSTAT[1] ,PBIST fail indication from GEM" "Not failed,Failed"
|
|
rbitfld.long 0x1C 18. " PBISTTESTSTAT[0] ,PBIST done indication from GEM" "Not done,Done"
|
|
newline
|
|
rbitfld.long 0x1C 12.--17. " STCPBISTSMSTATE ,Current state of STC PBIST state machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x1C 4. " STCPBISTCKSTPACKMASK ,Mask bit for ignoring the clock stop ACK from GEM" "Not masked,Masked"
|
|
bitfld.long 0x1C 3. " STCPBISTLRSTDASRTHALT ,Configuration to halt the state machine before the final de-assertion of LRST" "Proceeded,Halt"
|
|
newline
|
|
bitfld.long 0x1C 2. " STCPBISTSMTRIG ,Trigger pulse for the STC PBIST state machine" "Not triggered,Triggered"
|
|
bitfld.long 0x1C 0.--1. " STCPBISTEN ,Enable for PBIST and STC" ",STC,PBIST,Both"
|
|
line.long 0x20 "STCPBISTSMCFG2,STC PBIST SM Configuration 2 Register"
|
|
bitfld.long 0x20 16. " BCK2BCKSTCEN ,Enables back to back STC" "Disabled,Enabled"
|
|
bitfld.long 0x20 12.--13. " GEMPBISTROMCLKSEL ,GEM PBIST ROM clock frequency" "600 Mhz,300 Mhz,200 Mhz,150 Mhz"
|
|
bitfld.long 0x20 6.--11. " GEMTMODEVLCTASRTCNT ,No of clocks after asserting GEM TMODE VLCT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
|
|
newline
|
|
bitfld.long 0x20 0.--5. " GEMTMODEVLCTDASRTCNT ,No of clocks after de-asserting GEM TMODE VLCT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
|
|
group.long 0x358++0x07
|
|
line.long 0x00 "RTI2EVENTCAPTURESEL,RTI2 Event Captured Select Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " RTI2EVT1 ,Used to select the event to be captured for RTI2 event 1"
|
|
hexmask.long.byte 0x00 0.--6. 1. " RTI2EVT0 ,Used to select the event to be captured for RTI2 event 0"
|
|
line.long 0x04 "DSSMISC5,DSS Miscellaneous 5 Register"
|
|
rbitfld.long 0x04 7. " TPCC1PARMEMINITDONE ,Memory initialization done status for the TPCC1 parity memory" "Disabled,Enabled"
|
|
rbitfld.long 0x04 6. " TPCC0PARMEMINITDONE ,Memory initialization done status for the TPCC0 parity memory" "Disabled,Enabled"
|
|
rbitfld.long 0x04 5. " TPCC1PARMEMINIT ,Memory initialization for the TPCC1 parity memory" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x04 4. " TPCC0PARMEMINIT ,Memory initialization for the TPCC0 parity memory" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CPBPMPIPOSELVAL ,Ping pong select override value for CPBPM (Read/Write)" "Pong/Ping,Ping/Pong"
|
|
bitfld.long 0x04 2. " CPBPMPIPOSELCNT ,Ping pong select override control for CPBPM memory" "SW register,HW FSM"
|
|
newline
|
|
bitfld.long 0x04 1. " CQPIPOSELVAL ,Ping pong select override value for CQ memory (Read/Write)" "Pong/Ping,Ping/Pong"
|
|
bitfld.long 0x04 0. " CQPIPOSELCNT ,Ping pong select override control for CQ memory" "SW register,HW FSM"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DSS_REG2"
|
|
base ad:0x02000C00
|
|
width 19.
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "TPTC2WRMPUSTADD0,TPTC2 Start Address Write For Region 0 Register"
|
|
line.long 0x04 "TPTC2WRMPUSTADD1,TPTC2 Start Address Write For Region 1 Register"
|
|
line.long 0x08 "TPTC2WRMPUSTADD2,TPTC2 Start Address Write For Region 2 Register"
|
|
line.long 0x0C "TPTC2WRMPUSTADD3,TPTC2 Start Address Write For Region 3 Register"
|
|
line.long 0x10 "TPTC2WRMPUSTADD4,TPTC2 Start Address Write For Region 4 Register"
|
|
line.long 0x14 "TPTC2WRMPUSTADD5,TPTC2 Start Address Write For Region 5 Register"
|
|
group.long 0x120++0x17
|
|
line.long 0x00 "TPTC2WRMPUENDADD0,TPTC2 End Address Write For Region 0 Register"
|
|
line.long 0x04 "TPTC2WRMPUENDADD1,TPTC2 End Address Write For Region 1 Register"
|
|
line.long 0x08 "TPTC2WRMPUENDADD2,TPTC2 End Address Write For Region 2 Register"
|
|
line.long 0x0C "TPTC2WRMPUENDADD3,TPTC2 End Address Write For Region 3 Register"
|
|
line.long 0x10 "TPTC2WRMPUENDADD4,TPTC2 End Address Write For Region 4 Register"
|
|
line.long 0x14 "TPTC2WRMPUENDADD5,TPTC2 End Address Write For Region 5 Register"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "TPTC2WRMPUERRADD,TPTC2 Write Address Status Register"
|
|
group.long 0x148++0x17
|
|
line.long 0x00 "TPTC2RDMPUSTADD0,TPTC2 Start Address Read For Region 0 Register"
|
|
line.long 0x04 "TPTC2RDMPUSTADD1,TPTC2 Start Address Read For Region 1 Register"
|
|
line.long 0x08 "TPTC2RDMPUSTADD2,TPTC2 Start Address Read For Region 2 Register"
|
|
line.long 0x0C "TPTC2RDMPUSTADD3,TPTC2 Start Address Read For Region 3 Register"
|
|
line.long 0x10 "TPTC2RDMPUSTADD4,TPTC2 Start Address Read For Region 4 Register"
|
|
line.long 0x14 "TPTC2RDMPUSTADD5,TPTC2 Start Address Read For Region 5 Register"
|
|
group.long 0x168++0x17
|
|
line.long 0x00 "TPTC2RDMPUENDADD0,TPTC2 End Address Read For Region 0 Register"
|
|
line.long 0x04 "TPTC2RDMPUENDADD1,TPTC2 End Address Read For Region 1 Register"
|
|
line.long 0x08 "TPTC2RDMPUENDADD2,TPTC2 End Address Read For Region 2 Register"
|
|
line.long 0x0C "TPTC2RDMPUENDADD3,TPTC2 End Address Read For Region 3 Register"
|
|
line.long 0x10 "TPTC2RDMPUENDADD4,TPTC2 End Address Read For Region 4 Register"
|
|
line.long 0x14 "TPTC2RDMPUENDADD5,TPTC2 End Address Read For Region 5 Register"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "TPTC2RDMPUERRADD,TPTC2 Read Address Status Register"
|
|
group.long 0x18C++0x17
|
|
line.long 0x00 "TPTC3WRMPUSTADD0,TPTC3 Start Address Write For Region 0 Register"
|
|
line.long 0x04 "TPTC3WRMPUSTADD1,TPTC3 Start Address Write For Region 1 Register"
|
|
line.long 0x08 "TPTC3WRMPUSTADD2,TPTC3 Start Address Write For Region 2 Register"
|
|
line.long 0x0C "TPTC3WRMPUSTADD3,TPTC3 Start Address Write For Region 3 Register"
|
|
line.long 0x10 "TPTC3WRMPUSTADD4,TPTC3 Start Address Write For Region 4 Register"
|
|
line.long 0x14 "TPTC3WRMPUSTADD5,TPTC3 Start Address Write For Region 5 Register"
|
|
group.long 0x1AC++0x17
|
|
line.long 0x00 "TPTC3WRMPUENDADD0,TPTC3 End Address Write For Region 0 Register"
|
|
line.long 0x04 "TPTC3WRMPUENDADD1,TPTC3 End Address Write For Region 1 Register"
|
|
line.long 0x08 "TPTC3WRMPUENDADD2,TPTC3 End Address Write For Region 2 Register"
|
|
line.long 0x0C "TPTC3WRMPUENDADD3,TPTC3 End Address Write For Region 3 Register"
|
|
line.long 0x10 "TPTC3WRMPUENDADD4,TPTC3 End Address Write For Region 4 Register"
|
|
line.long 0x14 "TPTC3WRMPUENDADD5,TPTC3 End Address Write For Region 5 Register"
|
|
rgroup.long 0x1CC++0x03
|
|
line.long 0x00 "TPTC3WRMPUERRADD,TPTC3 Write Address Status Register"
|
|
group.long 0x1D0++0x17
|
|
line.long 0x00 "TPTC3RDMPUSTADD0,TPTC3 Start Address Read For Region 0 Register"
|
|
line.long 0x04 "TPTC3RDMPUSTADD1,TPTC3 Start Address Read For Region 1 Register"
|
|
line.long 0x08 "TPTC3RDMPUSTADD2,TPTC3 Start Address Read For Region 2 Register"
|
|
line.long 0x0C "TPTC3RDMPUSTADD3,TPTC3 Start Address Read For Region 3 Register"
|
|
line.long 0x10 "TPTC3RDMPUSTADD4,TPTC3 Start Address Read For Region 4 Register"
|
|
line.long 0x14 "TPTC3RDMPUSTADD5,TPTC3 Start Address Read For Region 5 Register"
|
|
group.long 0x1F0++0x17
|
|
line.long 0x00 "TPTC3RDMPUENDADD0,TPTC3 End Address Read For Region 0 Register"
|
|
line.long 0x04 "TPTC3RDMPUENDADD1,TPTC3 End Address Read For Region 1 Register"
|
|
line.long 0x08 "TPTC3RDMPUENDADD2,TPTC3 End Address Read For Region 2 Register"
|
|
line.long 0x0C "TPTC3RDMPUENDADD3,TPTC3 End Address Read For Region 3 Register"
|
|
line.long 0x10 "TPTC3RDMPUENDADD4,TPTC3 End Address Read For Region 4 Register"
|
|
line.long 0x14 "TPTC3RDMPUENDADD5,TPTC3 End Address Read For Region 5 Register"
|
|
rgroup.long 0x210++0x03
|
|
line.long 0x00 "TPTC3RDMPUERRADD,TPTC3 Read Address Status Register"
|
|
group.long 0x214++0x07
|
|
line.long 0x00 "TPTCMPUVALIDCFG2,TPTCMPUVALIDCFG2 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " TPTC3RDMPURNGVLD ,TPTC3 read valid bit for each address range for the MPU"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TPTC3WRMPURNGVLD ,TPTC3 write valid bit for each address range for the MPU"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. " TPTC2RDMPURNGVLD ,TPTC2 read valid bit for each address range for the MPU"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TPTC2WRMPURNGVLD ,TPTC2 write valid bit for each address range for the MPU"
|
|
line.long 0x04 "TPTCMPUENCFG2,TPTCMPUENCFG2 Register"
|
|
eventfld.long 0x04 7. " TPTC3RDMPUERRCLR ,Clear flag for error from the MPU in the read port of TPTC3" "Not occurred,Occurred"
|
|
eventfld.long 0x04 6. " TPTC3WRMPUERRCLR ,Clear flag for error from the MPU in the write port of TPTC3" "Not occurred,Occurred"
|
|
eventfld.long 0x04 5. " TPTC2RDMPUERRCLR ,Clear flag for error from the MPU in the read port of TPTC2" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 4. " TPTC2WRMPUERRCLR ,Clear flag for error from the MPU in the write port of TPTC2" "Not occurred,Occurred"
|
|
bitfld.long 0x04 3. " TPTC3RDMPUEN ,MPU in the read port of TPTC3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " TPTC3WRMPUEN ,MPU in the write port of TPTC3 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " TPTC2RDMPUEN ,MPU in the read port of TPTC2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TPTC2WRMPUEN ,MPU in the write port of TPTC2 enable" "Disabled,Enabled"
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "L3ECCCFG1,L3ECCCFG1 Register"
|
|
hexmask.long.tbyte 0x00 3.--26. 1. " L3ECCREPAIREDBIT ,Bit position of repaired bit in L3 ECC memory"
|
|
rbitfld.long 0x00 2. " L3ECCERRSTAT ,L3 ECC error latched status" "No error,Error"
|
|
newline
|
|
rbitfld.long 0x00 1. " L3ECCERRCLR ,L3 ECC clear bit" "No clear,Clear"
|
|
bitfld.long 0x00 0. " L3ECCEN ,L3 ECC logic enable" "Disabled,Enabled"
|
|
rgroup.long 0x26C++0x03
|
|
line.long 0x00 "L3ECCCFG2,L3ECCCFG2 Register"
|
|
hexmask.long.tbyte 0x00 0.--16. 0x01 " L3ECCFAULTADDR ,Fault address of L3 ECC memory"
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "DSS2MSSSWIRQ,DSS2MSSSWIRQ Register"
|
|
bitfld.long 0x00 1. " MSSSWIRQ2 ,Generate a pulse from DSS to MSS VIM line 61" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MSSSWIRQ1 ,Generate a pulse from DSS to MSS VIM line 52" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "EDMA (Enhanced Direct Memory Access)"
|
|
tree.open "TPCC"
|
|
tree "TPCC0"
|
|
base ad:0x02010000
|
|
width 10.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "PID,Peripheral ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major revision"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision"
|
|
line.long 0x04 "CCCFG,CC Configuration Register"
|
|
bitfld.long 0x04 25. " MPEXIST ,Memory protection existence MPEXIST" "Not protected,Protected"
|
|
bitfld.long 0x04 24. " CHMAPEXIST ,Channel mapping existence" "Not mapped,Mapped"
|
|
bitfld.long 0x04 20.--21. " NUMREGN ,Number of MP and shadow regions" ",,,8 regions"
|
|
newline
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x04 16.--18. " NUM_EVQUE ,Number of queues/number of TCs" ",2 EDMA3TCs/Event,,4 EDMA3TCs/Event,?..."
|
|
elif cpuis("AWR6843*")
|
|
bitfld.long 0x04 16.--18. " NUM_EVQUE ,Number of queues/number of TCs" "1 TC/Event queue,2 TC/Event queue,3 TC/Event queue,4 TC/Event queue,5 TC/Event queue,6 TC/Event queue,7 TC/Event queue,8 TC/Event queue"
|
|
else
|
|
bitfld.long 0x04 16.--18. " NUMTC ,Number of queues/number of TCs" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("AWR6843*")
|
|
newline
|
|
bitfld.long 0x04 12.--14. " NUMPAENTRY ,Number of PARAM entries" ",,,128,256,?..."
|
|
bitfld.long 0x04 8.--10. " NUMINTCH ,Number of interrupt channels" ",,16,,64,?..."
|
|
bitfld.long 0x04 4.--6. " NUMQDMACH ,Number of QDMA channels" ",,,,8,?..."
|
|
bitfld.long 0x04 0.--2. " NUMDMACH ,Number of DMA channels" ",,,,,64,?..."
|
|
else
|
|
newline
|
|
bitfld.long 0x04 12.--14. " NUMPAENTRY ,Number of PARAM entries" ",,,128,,512,?..."
|
|
bitfld.long 0x04 8.--10. " NUMINTCH ,Number of interrupt channels" ",,16,,64,?..."
|
|
bitfld.long 0x04 4.--6. " NUMQDMACH ,Number of QDMA channels" ",,,,8,?..."
|
|
bitfld.long 0x04 0.--2. " NUMDMACH ,Number of DMA channels" ",,,16,,64,?..."
|
|
endif
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
|
|
hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,PARAM entry number for QDMA channel N"
|
|
bitfld.long 0x00 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PARAM entry defined by PAENTRY" "OPT,SRC,BCNT/ACNT,DST,DBIDX/SBIDX,BCNTRLD/LINK,DCIDX/SCIDX,CCNT"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "DMAQNUMN,DMA Queue Number Register"
|
|
bitfld.long 0x00 28.--30. " E7 ,DMA queue number for event #7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " E6 ,DMA queue number for event #6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " E5 ,DMA queue number for event #5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " E4 ,DMA queue number for event #4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " E3 ,DMA queue number for event #3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " E2 ,DMA queue number for event #2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " E1 ,DMA queue number for event #1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " E0 ,DMA queue number for event #0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register"
|
|
bitfld.long 0x00 28.--30. " E7 ,QDMA queue number for event #7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " E6 ,QDMA queue number for event #6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " E5 ,QDMA queue number for event #5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " E4 ,QDMA queue number for event #4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " E3 ,QDMA queue number for event #3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " E2 ,QDMA queue number for event #2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " E1 ,QDMA queue number for event #1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " E0 ,QDMA queue number for event #0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x280++0x07
|
|
line.long 0x00 "QUETCMAP,Queue To TC Mapping Register"
|
|
bitfld.long 0x00 4.--6. " TCNUMQ1 ,TC number for queue N" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " TCNUMQ0 ,TC number for queue N" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "QUEPRI,Queue Priority Register"
|
|
bitfld.long 0x04 4.--6. " PRIQ1 ,Priority level for queue 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " PRIQ0 ,Priority level for queue 0" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "EMR,Event Missed Register"
|
|
bitfld.long 0x00 31. " E31 ,Event missed #31" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " E30 ,Event missed #30" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " E29 ,Event missed #29" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " E28 ,Event missed #28" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " E27 ,Event missed #27" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " E26 ,Event missed #26" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 25. " E25 ,Event missed #25" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " E24 ,Event missed #24" "Not occurred,Occurred"
|
|
bitfld.long 0x00 23. " E23 ,Event missed #23" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " E22 ,Event missed #22" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " E21 ,Event missed #21" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " E20 ,Event missed #20" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 19. " E19 ,Event missed #19" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " E18 ,Event missed #18" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " E17 ,Event missed #17" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " E16 ,Event missed #16" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " E15 ,Event missed #15" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " E14 ,Event missed #14" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 13. " E13 ,Event missed #13" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " E12 ,Event missed #12" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " E11 ,Event missed #11" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " E10 ,Event missed #10" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " E9 ,Event missed #9" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " E8 ,Event missed #8" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 7. " E7 ,Event missed #7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " E6 ,Event missed #6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " E5 ,Event missed #5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " E4 ,Event missed #4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " E3 ,Event missed #3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " E2 ,Event missed #2" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,Event missed #1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " E0 ,Event missed #0" "Not occurred,Occurred"
|
|
line.long 0x04 "EMRH,Event Missed Register (High Part)"
|
|
bitfld.long 0x04 31. " E63 ,Event missed #63" "Not occurred,Occurred"
|
|
bitfld.long 0x04 30. " E62 ,Event missed #62" "Not occurred,Occurred"
|
|
bitfld.long 0x04 29. " E61 ,Event missed #61" "Not occurred,Occurred"
|
|
bitfld.long 0x04 28. " E60 ,Event missed #60" "Not occurred,Occurred"
|
|
bitfld.long 0x04 27. " E59 ,Event missed #59" "Not occurred,Occurred"
|
|
bitfld.long 0x04 26. " E58 ,Event missed #58" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 25. " E57 ,Event missed #57" "Not occurred,Occurred"
|
|
bitfld.long 0x04 24. " E56 ,Event missed #56" "Not occurred,Occurred"
|
|
bitfld.long 0x04 23. " E55 ,Event missed #55" "Not occurred,Occurred"
|
|
bitfld.long 0x04 22. " E54 ,Event missed #54" "Not occurred,Occurred"
|
|
bitfld.long 0x04 21. " E53 ,Event missed #53" "Not occurred,Occurred"
|
|
bitfld.long 0x04 20. " E52 ,Event missed #52" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 19. " E51 ,Event missed #51" "Not occurred,Occurred"
|
|
bitfld.long 0x04 18. " E50 ,Event missed #50" "Not occurred,Occurred"
|
|
bitfld.long 0x04 17. " E49 ,Event missed #49" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16. " E48 ,Event missed #48" "Not occurred,Occurred"
|
|
bitfld.long 0x04 15. " E47 ,Event missed #47" "Not occurred,Occurred"
|
|
bitfld.long 0x04 14. " E46 ,Event missed #46" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 13. " E45 ,Event missed #45" "Not occurred,Occurred"
|
|
bitfld.long 0x04 12. " E44 ,Event missed #44" "Not occurred,Occurred"
|
|
bitfld.long 0x04 11. " E43 ,Event missed #43" "Not occurred,Occurred"
|
|
bitfld.long 0x04 10. " E42 ,Event missed #42" "Not occurred,Occurred"
|
|
bitfld.long 0x04 9. " E41 ,Event missed #41" "Not occurred,Occurred"
|
|
bitfld.long 0x04 8. " E40 ,Event missed #40" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 7. " E39 ,Event missed #39" "Not occurred,Occurred"
|
|
bitfld.long 0x04 6. " E38 ,Event missed #38" "Not occurred,Occurred"
|
|
bitfld.long 0x04 5. " E37 ,Event missed #37" "Not occurred,Occurred"
|
|
bitfld.long 0x04 4. " E36 ,Event missed #36" "Not occurred,Occurred"
|
|
bitfld.long 0x04 3. " E35 ,Event missed #35" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " E34 ,Event missed #34" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 1. " E33 ,Event missed #33" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0. " E32 ,Event missed #32" "Not occurred,Occurred"
|
|
wgroup.long 0x308++0x07
|
|
line.long 0x00 "EMCR,Event Missed Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Event missed clear #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Event missed clear #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Event missed clear #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " E28 ,Event missed clear #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Event missed clear #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Event missed clear #26" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 25. " E25 ,Event missed clear #25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " E24 ,Event missed clear #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Event missed clear #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " E22 ,Event missed clear #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Event missed clear #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Event missed clear #20" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 19. " E19 ,Event missed clear #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Event missed clear #18" "No effect,Clear"
|
|
bitfld.long 0x00 17. " E17 ,Event missed clear #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " E16 ,Event missed clear #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Event missed clear #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Event missed clear #14" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 13. " E13 ,Event missed clear #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Event missed clear #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Event missed clear #11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " E10 ,Event missed clear #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Event missed clear #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Event missed clear #8" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 7. " E7 ,Event missed clear #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event missed clear #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event missed clear #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event missed clear #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event missed clear #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event missed clear #2" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,Event missed clear #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Event missed clear #0" "No effect,Clear"
|
|
line.long 0x04 "EMCRH,Event Missed Clear Register (High Part)"
|
|
bitfld.long 0x04 31. " E63 ,Event missed clear #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Event missed clear #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Event missed clear #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " E60 ,Event missed clear #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Event missed clear #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Event missed clear #58" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 25. " E57 ,Event missed clear #57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " E56 ,Event missed clear #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Event missed clear #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " E54 ,Event missed clear #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Event missed clear #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Event missed clear #52" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 19. " E51 ,Event missed clear #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Event missed clear #50" "No effect,Clear"
|
|
bitfld.long 0x04 17. " E49 ,Event missed clear #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " E48 ,Event missed clear #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Event missed clear #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Event missed clear #46" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 13. " E45 ,Event missed clear #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Event missed clear #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Event missed clear #43" "No effect,Clear"
|
|
bitfld.long 0x04 10. " E42 ,Event missed clear #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Event missed clear #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Event missed clear #40" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 7. " E39 ,Event missed clear #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Event missed clear #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Event missed clear #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " E36 ,Event missed clear #36" "No effect,Clear"
|
|
bitfld.long 0x04 3. " E35 ,Event missed clear #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Event missed clear #34" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 1. " E33 ,Event missed clear #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Event missed clear #32" "No effect,Clear"
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "QEMR,QDMA Event Missed Register"
|
|
bitfld.long 0x00 7. " E7 ,Event missed #7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " E6 ,Event missed #6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " E5 ,Event missed #5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " E4 ,Event missed #4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " E3 ,Event missed #3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " E2 ,Event missed #2" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,Event missed #1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " E0 ,Event missed #0" "Not occurred,Occurred"
|
|
wgroup.long 0x314++0x03
|
|
line.long 0x00 "QEMR,QDMA Event Missed Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,Event missed clear #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event missed clear #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event missed clear #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event missed clear #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event missed clear #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event missed clear #2" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,Event missed clear #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Event missed clear #0" "No effect,Clear"
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "CCERR,CC Error Register"
|
|
bitfld.long 0x00 16. " TCERR ,Transfer completion code error" "No error,Error"
|
|
bitfld.long 0x00 7. " QTHRXCD7 ,Queue threshold error for Q7" "No error,Error"
|
|
bitfld.long 0x00 6. " QTHRXCD6 ,Queue threshold error for Q6" "No error,Error"
|
|
bitfld.long 0x00 5. " QTHRXCD5 ,Queue threshold error for Q5" "No error,Error"
|
|
bitfld.long 0x00 4. " QTHRXCD4 ,Queue threshold error for Q4" "No error,Error"
|
|
bitfld.long 0x00 3. " QTHRXCD3 ,Queue threshold error for Q3" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " QTHRXCD2 ,Queue threshold error for Q2" "No error,Error"
|
|
bitfld.long 0x00 1. " QTHRXCD1 ,Queue threshold error for Q1" "No error,Error"
|
|
bitfld.long 0x00 0. " QTHRXCD0 ,Queue threshold error for Q0" "No error,Error"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
wgroup.long 0x31C++0x07
|
|
line.long 0x00 "CCERRCLR,CC Error Clear Register"
|
|
bitfld.long 0x00 16. " TCERR ,Transfer completion code error" "No effect,Clear"
|
|
bitfld.long 0x00 7. " QTHRXCD7 ,Clear error for CCERR.QTHRXCD7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " QTHRXCD6 ,Clear error for CCERR.QTHRXCD6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " QTHRXCD5 ,Clear error for CCERR.QTHRXCD5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " QTHRXCD4 ,Clear error for CCERR.QTHRXCD4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " QTHRXCD3 ,Clear error for CCERR.QTHRXCD3" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " QTHRXCD2 ,Clear error for CCERR.QTHRXCD2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " QTHRXCD1 ,Clear error for CCERR.QTHRXCD1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " QTHRXCD0 ,Clear error for CCERR.QTHRXCD0" "No effect,Clear"
|
|
line.long 0x04 "EEVAL,Error Eval Register"
|
|
bitfld.long 0x04 1. " SET ,Error interrupt set" "No error,Error"
|
|
bitfld.long 0x04 0. " EVAL ,Error interrupt evaluate" "No error,Error"
|
|
else
|
|
wgroup.long 0x31C++0x07
|
|
line.long 0x00 "CCERR,CC Error Clear Register"
|
|
bitfld.long 0x00 16. " TCERR ,Transfer completion code error" "No effect,Clear"
|
|
bitfld.long 0x00 7. " QTHRXCD7 ,Clear error for CCERR.QTHRXCD7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " QTHRXCD6 ,Clear error for CCERR.QTHRXCD6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " QTHRXCD5 ,Clear error for CCERR.QTHRXCD5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " QTHRXCD4 ,Clear error for CCERR.QTHRXCD4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " QTHRXCD3 ,Clear error for CCERR.QTHRXCD3" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " QTHRXCD2 ,Clear error for CCERR.QTHRXCD2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " QTHRXCD1 ,Clear error for CCERR.QTHRXCD1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " QTHRXCD0 ,Clear error for CCERR.QTHRXCD0" "No effect,Clear"
|
|
line.long 0x04 "CCERR,Error Eval Register"
|
|
bitfld.long 0x04 1. " SET ,Error interrupt set" "No error,Error"
|
|
bitfld.long 0x04 0. " EVAL ,Error interrupt evaluate" "No error,Error"
|
|
endif
|
|
group.long 0x340++0x07
|
|
line.long 0x00 "DRAEM,DMA Region Access Enable Register"
|
|
bitfld.long 0x00 31. " E31 ,DMA region access enable for region M bit #31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " E30 ,DMA region access enable for region M bit #30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " E29 ,DMA region access enable for region M bit #29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " E28 ,DMA region access enable for region M bit #28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " E27 ,DMA region access enable for region M bit #27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " E26 ,DMA region access enable for region M bit #26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " E25 ,DMA region access enable for region M bit #25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " E24 ,DMA region access enable for region M bit #24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " E23 ,DMA region access enable for region M bit #23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " E22 ,DMA region access enable for region M bit #22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " E21 ,DMA region access enable for region M bit #21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " E20 ,DMA region access enable for region M bit #20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " E19 ,DMA region access enable for region M bit #19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " E18 ,DMA region access enable for region M bit #18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " E17 ,DMA region access enable for region M bit #17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " E16 ,DMA region access enable for region M bit #16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " E15 ,DMA region access enable for region M bit #15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " E14 ,DMA region access enable for region M bit #14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " E13 ,DMA region access enable for region M bit #13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " E12 ,DMA region access enable for region M bit #12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " E11 ,DMA region access enable for region M bit #11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " E10 ,DMA region access enable for region M bit #10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " E9 ,DMA region access enable for region M bit #9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " E8 ,DMA region access enable for region M bit #8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " E7 ,DMA region access enable for region M bit #7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " E6 ,DMA region access enable for region M bit #6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E5 ,DMA region access enable for region M bit #5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " E4 ,DMA region access enable for region M bit #4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " E3 ,DMA region access enable for region M bit #3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " E2 ,DMA region access enable for region M bit #2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,DMA region access enable for region M bit #1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " E0 ,DMA region access enable for region M bit #0" "Disabled,Enabled"
|
|
line.long 0x04 "DRAEHM,DMA Region Access Enable Register"
|
|
bitfld.long 0x04 31. " E63 ,DMA region access enable for region M bit #63" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " E62 ,DMA region access enable for region M bit #62" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " E61 ,DMA region access enable for region M bit #61" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " E60 ,DMA region access enable for region M bit #60" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " E59 ,DMA region access enable for region M bit #59" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " E58 ,DMA region access enable for region M bit #58" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " E57 ,DMA region access enable for region M bit #57" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " E56 ,DMA region access enable for region M bit #56" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " E55 ,DMA region access enable for region M bit #55" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " E54 ,DMA region access enable for region M bit #54" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " E53 ,DMA region access enable for region M bit #53" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " E52 ,DMA region access enable for region M bit #52" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " E51 ,DMA region access enable for region M bit #51" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " E50 ,DMA region access enable for region M bit #50" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " E49 ,DMA region access enable for region M bit #49" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " E48 ,DMA region access enable for region M bit #48" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " E47 ,DMA region access enable for region M bit #47" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " E46 ,DMA region access enable for region M bit #46" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " E45 ,DMA region access enable for region M bit #45" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " E44 ,DMA region access enable for region M bit #44" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " E43 ,DMA region access enable for region M bit #43" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " E42 ,DMA region access enable for region M bit #42" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " E41 ,DMA region access enable for region M bit #41" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " E40 ,DMA region access enable for region M bit #40" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " E39 ,DMA region access enable for region M bit #39" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " E38 ,DMA region access enable for region M bit #38" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E37 ,DMA region access enable for region M bit #37" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " E36 ,DMA region access enable for region M bit #36" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " E35 ,DMA region access enable for region M bit #35" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " E34 ,DMA region access enable for region M bit #34" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " E33 ,DMA region access enable for region M bit #33" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " E32 ,DMA region access enable for region M bit #32" "Disabled,Enabled"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "QRAEN,QDMA Region Access Enable Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA region access enable for region M bit #7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " E6 ,QDMA region access enable for region M bit #6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E5 ,QDMA region access enable for region M bit #5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " E4 ,QDMA region access enable for region M bit #4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " E3 ,QDMA region access enable for region M bit #3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " E2 ,QDMA region access enable for region M bit #2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,QDMA region access enable for region M bit #1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " E0 ,QDMA region access enable for region M bit #0" "Disabled,Enabled"
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "QNE0,Event Queue Entry Diagram For Queue n - Entry 0"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x404++0x03
|
|
line.long 0x00 "QNE1,Event Queue Entry Diagram For Queue n - Entry 1"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x408++0x03
|
|
line.long 0x00 "QNE2,Event Queue Entry Diagram For Queue n - Entry 2"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "QNE3,Event Queue Entry Diagram For Queue n - Entry 3"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x410++0x03
|
|
line.long 0x00 "QNE4,Event Queue Entry Diagram For Queue n - Entry 4"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x414++0x03
|
|
line.long 0x00 "QNE5,Event Queue Entry Diagram For Queue n - Entry 5"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x418++0x03
|
|
line.long 0x00 "QNE6,Event Queue Entry Diagram For Queue n - Entry 6"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x41C++0x03
|
|
line.long 0x00 "QNE7,Event Queue Entry Diagram For Queue n - Entry 7"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x420++0x03
|
|
line.long 0x00 "QNE8,Event Queue Entry Diagram For Queue n - Entry 8"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x424++0x03
|
|
line.long 0x00 "QNE9,Event Queue Entry Diagram For Queue n - Entry 9"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x428++0x03
|
|
line.long 0x00 "QNE10,Event Queue Entry Diagram For Queue n - Entry 10"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x42C++0x03
|
|
line.long 0x00 "QNE11,Event Queue Entry Diagram For Queue n - Entry 11"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x430++0x03
|
|
line.long 0x00 "QNE12,Event Queue Entry Diagram For Queue n - Entry 12"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x434++0x03
|
|
line.long 0x00 "QNE13,Event Queue Entry Diagram For Queue n - Entry 13"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x438++0x03
|
|
line.long 0x00 "QNE14,Event Queue Entry Diagram For Queue n - Entry 14"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x43C++0x03
|
|
line.long 0x00 "QNE15,Event Queue Entry Diagram For Queue n - Entry 15"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x600++0x03
|
|
line.long 0x00 "QSTATN,QSTATn Register Set"
|
|
bitfld.long 0x00 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded"
|
|
bitfld.long 0x00 16.--20. " WM ,Watermark for maximum queue usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--12. " NUMVAL ,Number of valid entries in queueN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0.--3. " STRTPTR ,Start pointer" "0th,1th,2th,3th,4th,5th,6th,7th,8th,9th,10th,11th,12th,13th,14th,15th"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "QWMTHRA,Queue Threshold A For Q[3:0] Register"
|
|
bitfld.long 0x00 8.--12. " Q1 ,Queue threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x00 0.--4. " Q0 ,Queue threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
width 18.
|
|
newline
|
|
rgroup.long 0x640++0x03
|
|
line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register"
|
|
bitfld.long 0x00 23. " QUEACTV7 ,Queue 7 active QUEACTV7" "Not active,Active"
|
|
bitfld.long 0x00 22. " QUEACTV6 ,Queue 6 active QUEACTV6" "Not active,Active"
|
|
bitfld.long 0x00 21. " QUEACTV5 ,Queue 5 active QUEACTV5" "Not active,Active"
|
|
bitfld.long 0x00 20. " QUEACTV4 ,Queue 4 active QUEACTV4" "Not active,Active"
|
|
bitfld.long 0x00 19. " QUEACTV3 ,Queue 3 active QUEACTV3" "Not active,Active"
|
|
bitfld.long 0x00 18. " QUEACTV2 ,Queue 2 active QUEACTV2" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 17. " QUEACTV1 ,Queue 1 active QUEACTV1" "Not active,Active"
|
|
bitfld.long 0x00 16. " QUEACTV0 ,Queue 0 active QUEACTV0" "Not active,Active"
|
|
bitfld.long 0x00 8.--13. " COMPACTV ,Completion request active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4. " ACTV ,Channel controller active" "Idle,Busy"
|
|
bitfld.long 0x00 2. " TRACTV ,Transfer request active" "Not active,Active"
|
|
bitfld.long 0x00 1. " QEVTACTV ,QDMA event active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 0. " EVTACTV ,DMA event active" "Not active,Active"
|
|
newline
|
|
width 9.
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "AETCTL,Advanced Event Trigger Control Register"
|
|
bitfld.long 0x00 31. " EN ,AET enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
bitfld.long 0x00 8.--13. " ENDINT ,AET end interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,56,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 7. " ENDINT ,AET end interrupt" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 6. " TYPE ,AET event type" "DMA,QDMA"
|
|
bitfld.long 0x00 0.--5. " STRTEVT ,AET start event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x704++0x03
|
|
line.long 0x00 "AETSTAT,Advanced Event Trigger Status Register"
|
|
bitfld.long 0x00 0. " STAT ,AET status" "Low,High"
|
|
wgroup.long 0x708++0x03
|
|
line.long 0x00 "AETCMD,AET Command Register"
|
|
bitfld.long 0x00 0. " CLR ,AET clear command" "No effect,Clear"
|
|
newline
|
|
width 17.
|
|
group.long 0x1000++0x07
|
|
line.long 0x00 "ER_SET/CLR,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31 ,Event #31" "Inactive,Active"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30 ,Event #30" "Inactive,Active"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29 ,Event #29" "Inactive,Active"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28 ,Event #28" "Inactive,Active"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27 ,Event #27" "Inactive,Active"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26 ,Event #26" "Inactive,Active"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25 ,Event #25" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24 ,Event #24" "Inactive,Active"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23 ,Event #23" "Inactive,Active"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22 ,Event #22" "Inactive,Active"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21 ,Event #21" "Inactive,Active"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20 ,Event #20" "Inactive,Active"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19 ,Event #19" "Inactive,Active"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18 ,Event #18" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17 ,Event #17" "Inactive,Active"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16 ,Event #16" "Inactive,Active"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15 ,Event #15" "Inactive,Active"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14 ,Event #14" "Inactive,Active"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13 ,Event #13" "Inactive,Active"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12 ,Event #12" "Inactive,Active"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11 ,Event #11" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10 ,Event #10" "Inactive,Active"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9 ,Event #9" "Inactive,Active"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8 ,Event #8" "Inactive,Active"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7 ,Event #7" "Inactive,Active"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6 ,Event #6" "Inactive,Active"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5 ,Event #5" "Inactive,Active"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4 ,Event #4" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3 ,Event #3" "Inactive,Active"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2 ,Event #2" "Inactive,Active"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1 ,Event #1" "Inactive,Active"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0 ,Event #0" "Inactive,Active"
|
|
line.long 0x04 "ERH_SET/CLR,Event Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " E63 ,Event #63" "Inactive,Active"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " E62 ,Event #62" "Inactive,Active"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " E61 ,Event #61" "Inactive,Active"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " E60 ,Event #60" "Inactive,Active"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " E59 ,Event #59" "Inactive,Active"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " E58 ,Event #58" "Inactive,Active"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " E57 ,Event #57" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " E56 ,Event #56" "Inactive,Active"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " E55 ,Event #55" "Inactive,Active"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " E54 ,Event #54" "Inactive,Active"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " E53 ,Event #53" "Inactive,Active"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " E52 ,Event #52" "Inactive,Active"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " E51 ,Event #51" "Inactive,Active"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " E50 ,Event #50" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " E49 ,Event #49" "Inactive,Active"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " E48 ,Event #48" "Inactive,Active"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " E47 ,Event #47" "Inactive,Active"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " E46 ,Event #46" "Inactive,Active"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " E45 ,Event #45" "Inactive,Active"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " E44 ,Event #44" "Inactive,Active"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " E43 ,Event #43" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " E42 ,Event #42" "Inactive,Active"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " E41 ,Event #41" "Inactive,Active"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " E40 ,Event #40" "Inactive,Active"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " E39 ,Event #39" "Inactive,Active"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " E38 ,Event #38" "Inactive,Active"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " E37 ,Event #37" "Inactive,Active"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " E36 ,Event #36" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " E35 ,Event #35" "Inactive,Active"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " E34 ,Event #34" "Inactive,Active"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " E33 ,Event #33" "Inactive,Active"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " E32 ,Event #32" "Inactive,Active"
|
|
rgroup.long 0x1018++0x07
|
|
line.long 0x00 "CER,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "Not chained,Chained"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "Not chained,Chained"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "Not chained,Chained"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "Not chained,Chained"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "Not chained,Chained"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "Not chained,Chained"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "Not chained,Chained"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "Not chained,Chained"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "Not chained,Chained"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "Not chained,Chained"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "Not chained,Chained"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "Not chained,Chained"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "Not chained,Chained"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "Not chained,Chained"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "Not chained,Chained"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "Not chained,Chained"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "Not chained,Chained"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "Not chained,Chained"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "Not chained,Chained"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "Not chained,Chained"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "Not chained,Chained"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not chained,Chained"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not chained,Chained"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not chained,Chained"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not chained,Chained"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not chained,Chained"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not chained,Chained"
|
|
line.long 0x04 "CERH,Chained Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "Not chained,Chained"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "Not chained,Chained"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "Not chained,Chained"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "Not chained,Chained"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "Not chained,Chained"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "Not chained,Chained"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "Not chained,Chained"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "Not chained,Chained"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "Not chained,Chained"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "Not chained,Chained"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "Not chained,Chained"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "Not chained,Chained"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "Not chained,Chained"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "Not chained,Chained"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "Not chained,Chained"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "Not chained,Chained"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "Not chained,Chained"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "Not chained,Chained"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "Not chained,Chained"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "Not chained,Chained"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "Not chained,Chained"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "Not chained,Chained"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "Not chained,Chained"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "Not chained,Chained"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "Not chained,Chained"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "Not chained,Chained"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "Not chained,Chained"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "Not chained,Chained"
|
|
group.long 0x1020++0x07
|
|
line.long 0x00 "EER_SET/CLR,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31 ,Event #31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30 ,Event #30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29 ,Event #29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28 ,Event #28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27 ,Event #27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26 ,Event #26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25 ,Event #25" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24 ,Event #24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23 ,Event #23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22 ,Event #22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21 ,Event #21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20 ,Event #20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19 ,Event #19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18 ,Event #18" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17 ,Event #17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16 ,Event #16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15 ,Event #15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14 ,Event #14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13 ,Event #13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12 ,Event #12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11 ,Event #11" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10 ,Event #10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9 ,Event #9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8 ,Event #8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7 ,Event #7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6 ,Event #6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5 ,Event #5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4 ,Event #4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3 ,Event #3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2 ,Event #2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1 ,Event #1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0 ,Event #0" "Disabled,Enabled"
|
|
line.long 0x04 "EERH_SET/CLR,Event Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " E63 ,Event #63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " E62 ,Event #62" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " E61 ,Event #61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " E60 ,Event #60" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " E59 ,Event #59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " E58 ,Event #58" "Disabled,Enabled"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " E57 ,Event #57" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " E56 ,Event #56" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " E55 ,Event #55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " E54 ,Event #54" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " E53 ,Event #53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " E52 ,Event #52" "Disabled,Enabled"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " E51 ,Event #51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " E50 ,Event #50" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " E49 ,Event #49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " E48 ,Event #48" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " E47 ,Event #47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " E46 ,Event #46" "Disabled,Enabled"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " E45 ,Event #45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " E44 ,Event #44" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " E43 ,Event #43" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " E42 ,Event #42" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " E41 ,Event #41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " E40 ,Event #40" "Disabled,Enabled"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " E39 ,Event #39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " E38 ,Event #38" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " E37 ,Event #37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " E36 ,Event #36" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " E35 ,Event #35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " E34 ,Event #34" "Disabled,Enabled"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " E33 ,Event #33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " E32 ,Event #32" "Disabled,Enabled"
|
|
rgroup.long 0x1038++0x07
|
|
line.long 0x00 "SER,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "Not stored,Stored"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "Not stored,Stored"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "Not stored,Stored"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "Not stored,Stored"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "Not stored,Stored"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "Not stored,Stored"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "Not stored,Stored"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "Not stored,Stored"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "Not stored,Stored"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "Not stored,Stored"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "Not stored,Stored"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not stored,Stored"
|
|
line.long 0x04 "SERH,EDMA TPCC Secondary Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "Not stored,Stored"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "Not stored,Stored"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "Not stored,Stored"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "Not stored,Stored"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "Not stored,Stored"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "Not stored,Stored"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "Not stored,Stored"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "Not stored,Stored"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "Not stored,Stored"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "Not stored,Stored"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "Not stored,Stored"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "Not stored,Stored"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "Not stored,Stored"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "Not stored,Stored"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "Not stored,Stored"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "Not stored,Stored"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "Not stored,Stored"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "Not stored,Stored"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "Not stored,Stored"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "Not stored,Stored"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "Not stored,Stored"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "Not stored,Stored"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "Not stored,Stored"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "Not stored,Stored"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "Not stored,Stored"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "Not stored,Stored"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "Not stored,Stored"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "Not stored,Stored"
|
|
wgroup.long 0x1040++0x07
|
|
line.long 0x00 "SECR,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "No effect,Clear"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "No effect,Clear"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "No effect,Clear"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
line.long 0x04 "SECRH,Secondary Event Clear Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "No effect,Clear"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "No effect,Clear"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "No effect,Clear"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "No effect,Clear"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "No effect,Clear"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "No effect,Clear"
|
|
group.long 0x1050++0x07
|
|
line.long 0x00 "IER_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31 ,Interrupt associated with TCC #31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30 ,Interrupt associated with TCC #30" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29 ,Interrupt associated with TCC #29" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28 ,Interrupt associated with TCC #28" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27 ,Interrupt associated with TCC #27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26 ,Interrupt associated with TCC #26" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25 ,Interrupt associated with TCC #25" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24 ,Interrupt associated with TCC #24" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23 ,Interrupt associated with TCC #23" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22 ,Interrupt associated with TCC #22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21 ,Interrupt associated with TCC #21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20 ,Interrupt associated with TCC #20" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19 ,Interrupt associated with TCC #19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18 ,Interrupt associated with TCC #18" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17 ,Interrupt associated with TCC #17" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16 ,Interrupt associated with TCC #16" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15 ,Interrupt associated with TCC #15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14 ,Interrupt associated with TCC #14" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13 ,Interrupt associated with TCC #13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12 ,Interrupt associated with TCC #12" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11 ,Interrupt associated with TCC #11" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10 ,Interrupt associated with TCC #10" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9 ,Interrupt associated with TCC #9" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8 ,Interrupt associated with TCC #8" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I7 ,Interrupt associated with TCC #7" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I6 ,Interrupt associated with TCC #6" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I5 ,Interrupt associated with TCC #5" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I4 ,Interrupt associated with TCC #4" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3 ,Interrupt associated with TCC #3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2 ,Interrupt associated with TCC #2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1 ,Interrupt associated with TCC #1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0 ,Interrupt associated with TCC #0" "No interrupt,Interrupt"
|
|
line.long 0x04 "IERH_SET/CLR,EDMA TPCC Interrupts Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " I63 ,Interrupt associated with TCC #63" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " I62 ,Interrupt associated with TCC #62" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " I61 ,Interrupt associated with TCC #61" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " I60 ,Interrupt associated with TCC #60" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " I59 ,Interrupt associated with TCC #59" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " I58 ,Interrupt associated with TCC #58" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " I57 ,Interrupt associated with TCC #57" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " I56 ,Interrupt associated with TCC #56" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " I55 ,Interrupt associated with TCC #55" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " I54 ,Interrupt associated with TCC #54" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " I53 ,Interrupt associated with TCC #53" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " I52 ,Interrupt associated with TCC #52" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " I51 ,Interrupt associated with TCC #51" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " I50 ,Interrupt associated with TCC #50" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " I49 ,Interrupt associated with TCC #49" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " I48 ,Interrupt associated with TCC #48" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " I47 ,Interrupt associated with TCC #47" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " I46 ,Interrupt associated with TCC #46" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " I45 ,Interrupt associated with TCC #45" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " I44 ,Interrupt associated with TCC #44" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " I43 ,Interrupt associated with TCC #43" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " I42 ,Interrupt associated with TCC #42" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " I41 ,Interrupt associated with TCC #41" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " I40 ,Interrupt associated with TCC #40" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " I39 ,Interrupt associated with TCC #39" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " I38 ,Interrupt associated with TCC #38" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " I37 ,Interrupt associated with TCC #37" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " I36 ,Interrupt associated with TCC #36" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " I35 ,Interrupt associated with TCC #35" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " I34 ,Interrupt associated with TCC #34" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " I33 ,Interrupt associated with TCC #33" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " I32 ,Interrupt associated with TCC #32" "No interrupt,Interrupt"
|
|
rgroup.long 0x1068++0x07
|
|
line.long 0x00 "IPR,Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt associated with TCC #31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt associated with TCC #30" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " I29 ,Interrupt associated with TCC #29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt associated with TCC #28" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " I27 ,Interrupt associated with TCC #27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt associated with TCC #26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " I25 ,Interrupt associated with TCC #25" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 24. " I24 ,Interrupt associated with TCC #24" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " I23 ,Interrupt associated with TCC #23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt associated with TCC #22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " I21 ,Interrupt associated with TCC #21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt associated with TCC #20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " I19 ,Interrupt associated with TCC #19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt associated with TCC #18" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 17. " I17 ,Interrupt associated with TCC #17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt associated with TCC #16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " I15 ,Interrupt associated with TCC #15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt associated with TCC #14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " I13 ,Interrupt associated with TCC #13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt associated with TCC #12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " I11 ,Interrupt associated with TCC #11" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. " I10 ,Interrupt associated with TCC #10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " I9 ,Interrupt associated with TCC #9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt associated with TCC #8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " I7 ,Interrupt associated with TCC #7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt associated with TCC #6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " I5 ,Interrupt associated with TCC #5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt associated with TCC #4" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " I3 ,Interrupt associated with TCC #3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt associated with TCC #2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " I1 ,Interrupt associated with TCC #1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt associated with TCC #0" "No interrupt,Interrupt"
|
|
line.long 0x04 "IPRH,Interrupt Pending Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt associated with TCC #63" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt associated with TCC #62" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " I61 ,Interrupt associated with TCC #61" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt associated with TCC #60" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 27. " I59 ,Interrupt associated with TCC #59" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt associated with TCC #58" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " I57 ,Interrupt associated with TCC #57" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 24. " I56 ,Interrupt associated with TCC #56" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 23. " I55 ,Interrupt associated with TCC #55" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt associated with TCC #54" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " I53 ,Interrupt associated with TCC #53" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt associated with TCC #52" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 19. " I51 ,Interrupt associated with TCC #51" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt associated with TCC #50" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 17. " I49 ,Interrupt associated with TCC #49" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt associated with TCC #48" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 15. " I47 ,Interrupt associated with TCC #47" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt associated with TCC #46" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " I45 ,Interrupt associated with TCC #45" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt associated with TCC #44" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 11. " I43 ,Interrupt associated with TCC #43" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 10. " I42 ,Interrupt associated with TCC #42" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " I41 ,Interrupt associated with TCC #41" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt associated with TCC #40" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " I39 ,Interrupt associated with TCC #39" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt associated with TCC #38" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " I37 ,Interrupt associated with TCC #37" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt associated with TCC #36" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 3. " I35 ,Interrupt associated with TCC #35" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt associated with TCC #34" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " I33 ,Interrupt associated with TCC #33" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt associated with TCC #32" "No interrupt,Interrupt"
|
|
wgroup.long 0x1070++0x07
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt associated with TCC #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt associated with TCC #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " I29 ,Interrupt associated with TCC #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt associated with TCC #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " I27 ,Interrupt associated with TCC #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt associated with TCC #26" "No effect,Clear"
|
|
bitfld.long 0x00 25. " I25 ,Interrupt associated with TCC #25" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 24. " I24 ,Interrupt associated with TCC #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " I23 ,Interrupt associated with TCC #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt associated with TCC #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " I21 ,Interrupt associated with TCC #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt associated with TCC #20" "No effect,Clear"
|
|
bitfld.long 0x00 19. " I19 ,Interrupt associated with TCC #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt associated with TCC #18" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 17. " I17 ,Interrupt associated with TCC #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt associated with TCC #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " I15 ,Interrupt associated with TCC #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt associated with TCC #14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " I13 ,Interrupt associated with TCC #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt associated with TCC #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " I11 ,Interrupt associated with TCC #11" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 10. " I10 ,Interrupt associated with TCC #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " I9 ,Interrupt associated with TCC #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt associated with TCC #8" "No effect,Clear"
|
|
bitfld.long 0x00 7. " I7 ,Interrupt associated with TCC #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt associated with TCC #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " I5 ,Interrupt associated with TCC #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt associated with TCC #4" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " I3 ,Interrupt associated with TCC #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt associated with TCC #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " I1 ,Interrupt associated with TCC #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt associated with TCC #0" "No effect,Clear"
|
|
line.long 0x04 "ICRH,Interrupt Clear Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt associated with TCC #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt associated with TCC #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " I61 ,Interrupt associated with TCC #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt associated with TCC #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " I59 ,Interrupt associated with TCC #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt associated with TCC #58" "No effect,Clear"
|
|
bitfld.long 0x04 25. " I57 ,Interrupt associated with TCC #57" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 24. " I56 ,Interrupt associated with TCC #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " I55 ,Interrupt associated with TCC #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt associated with TCC #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " I53 ,Interrupt associated with TCC #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt associated with TCC #52" "No effect,Clear"
|
|
bitfld.long 0x04 19. " I51 ,Interrupt associated with TCC #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt associated with TCC #50" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 17. " I49 ,Interrupt associated with TCC #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt associated with TCC #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " I47 ,Interrupt associated with TCC #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt associated with TCC #46" "No effect,Clear"
|
|
bitfld.long 0x04 13. " I45 ,Interrupt associated with TCC #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt associated with TCC #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " I43 ,Interrupt associated with TCC #43" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10. " I42 ,Interrupt associated with TCC #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " I41 ,Interrupt associated with TCC #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt associated with TCC #40" "No effect,Clear"
|
|
bitfld.long 0x04 7. " I39 ,Interrupt associated with TCC #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt associated with TCC #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " I37 ,Interrupt associated with TCC #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt associated with TCC #36" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 3. " I35 ,Interrupt associated with TCC #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt associated with TCC #34" "No effect,Clear"
|
|
bitfld.long 0x04 1. " I33 ,Interrupt associated with TCC #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt associated with TCC #32" "No effect,Clear"
|
|
wgroup.long 0x1078++0x03
|
|
line.long 0x00 "IEVAL,Interrupt EVAL Register"
|
|
bitfld.long 0x00 1. " SET ,Interrupt set" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Interrupt evaluate" "Not set,Set"
|
|
rgroup.long 0x1080++0x03
|
|
line.long 0x00 "QER,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not occurred,Occurred"
|
|
group.long 0x1084++0x03
|
|
line.long 0x00 "QEER_SET/CLR,QDMA Event Enable Register"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7 ,Event #7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6 ,Event #6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5 ,Event #5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4 ,Event #4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3 ,Event #3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2 ,Event #2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1 ,Event #1" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0 ,Event #0" "Disabled,Enabled"
|
|
rgroup.long 0x1090++0x03
|
|
line.long 0x00 "QSER,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not stored,Stored"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not stored,Stored"
|
|
wgroup.long 0x1094++0x03
|
|
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
group.long 0x2000++0x07
|
|
line.long 0x00 "ER_RN_SET/CLR,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31 ,Event #31" "Inactive,Active"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30 ,Event #30" "Inactive,Active"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29 ,Event #29" "Inactive,Active"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28 ,Event #28" "Inactive,Active"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27 ,Event #27" "Inactive,Active"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26 ,Event #26" "Inactive,Active"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25 ,Event #25" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24 ,Event #24" "Inactive,Active"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23 ,Event #23" "Inactive,Active"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22 ,Event #22" "Inactive,Active"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21 ,Event #21" "Inactive,Active"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20 ,Event #20" "Inactive,Active"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19 ,Event #19" "Inactive,Active"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18 ,Event #18" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17 ,Event #17" "Inactive,Active"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16 ,Event #16" "Inactive,Active"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15 ,Event #15" "Inactive,Active"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14 ,Event #14" "Inactive,Active"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13 ,Event #13" "Inactive,Active"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12 ,Event #12" "Inactive,Active"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11 ,Event #11" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10 ,Event #10" "Inactive,Active"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9 ,Event #9" "Inactive,Active"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8 ,Event #8" "Inactive,Active"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7 ,Event #7" "Inactive,Active"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6 ,Event #6" "Inactive,Active"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5 ,Event #5" "Inactive,Active"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4 ,Event #4" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3 ,Event #3" "Inactive,Active"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2 ,Event #2" "Inactive,Active"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1 ,Event #1" "Inactive,Active"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0 ,Event #0" "Inactive,Active"
|
|
line.long 0x04 "ERH_RN_SET/CLR,Event Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " E63 ,Event #63" "Inactive,Active"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " E62 ,Event #62" "Inactive,Active"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " E61 ,Event #61" "Inactive,Active"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " E60 ,Event #60" "Inactive,Active"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " E59 ,Event #59" "Inactive,Active"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " E58 ,Event #58" "Inactive,Active"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " E57 ,Event #57" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " E56 ,Event #56" "Inactive,Active"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " E55 ,Event #55" "Inactive,Active"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " E54 ,Event #54" "Inactive,Active"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " E53 ,Event #53" "Inactive,Active"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " E52 ,Event #52" "Inactive,Active"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " E51 ,Event #51" "Inactive,Active"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " E50 ,Event #50" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " E49 ,Event #49" "Inactive,Active"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " E48 ,Event #48" "Inactive,Active"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " E47 ,Event #47" "Inactive,Active"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " E46 ,Event #46" "Inactive,Active"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " E45 ,Event #45" "Inactive,Active"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " E44 ,Event #44" "Inactive,Active"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " E43 ,Event #43" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x44 10. 0x0C 10. " E42 ,Event #42" "Inactive,Active"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " E41 ,Event #41" "Inactive,Active"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " E40 ,Event #40" "Inactive,Active"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " E39 ,Event #39" "Inactive,Active"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " E38 ,Event #38" "Inactive,Active"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " E37 ,Event #37" "Inactive,Active"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " E36 ,Event #36" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " E35 ,Event #35" "Inactive,Active"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " E34 ,Event #34" "Inactive,Active"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " E33 ,Event #33" "Inactive,Active"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " E32 ,Event #32" "Inactive,Active"
|
|
rgroup.long 0x2018++0x07
|
|
line.long 0x00 "CER_RN,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "Not chained,Chained"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "Not chained,Chained"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "Not chained,Chained"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "Not chained,Chained"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "Not chained,Chained"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "Not chained,Chained"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "Not chained,Chained"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "Not chained,Chained"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "Not chained,Chained"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "Not chained,Chained"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "Not chained,Chained"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "Not chained,Chained"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "Not chained,Chained"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "Not chained,Chained"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "Not chained,Chained"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "Not chained,Chained"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "Not chained,Chained"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "Not chained,Chained"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "Not chained,Chained"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "Not chained,Chained"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "Not chained,Chained"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not chained,Chained"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not chained,Chained"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not chained,Chained"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not chained,Chained"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not chained,Chained"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not chained,Chained"
|
|
line.long 0x04 "CERH_RN,Chained Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "Not chained,Chained"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "Not chained,Chained"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "Not chained,Chained"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "Not chained,Chained"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "Not chained,Chained"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "Not chained,Chained"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "Not chained,Chained"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "Not chained,Chained"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "Not chained,Chained"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "Not chained,Chained"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "Not chained,Chained"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "Not chained,Chained"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "Not chained,Chained"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "Not chained,Chained"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "Not chained,Chained"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "Not chained,Chained"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "Not chained,Chained"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "Not chained,Chained"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "Not chained,Chained"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "Not chained,Chained"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "Not chained,Chained"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "Not chained,Chained"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "Not chained,Chained"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "Not chained,Chained"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "Not chained,Chained"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "Not chained,Chained"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "Not chained,Chained"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "Not chained,Chained"
|
|
group.long 0x2020++0x07
|
|
line.long 0x00 "EER_RN_SET/CLR,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31 ,Event #31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30 ,Event #30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29 ,Event #29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28 ,Event #28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27 ,Event #27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26 ,Event #26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25 ,Event #25" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24 ,Event #24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23 ,Event #23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22 ,Event #22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21 ,Event #21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20 ,Event #20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19 ,Event #19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18 ,Event #18" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17 ,Event #17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16 ,Event #16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15 ,Event #15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14 ,Event #14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13 ,Event #13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12 ,Event #12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11 ,Event #11" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10 ,Event #10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9 ,Event #9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8 ,Event #8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7 ,Event #7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6 ,Event #6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5 ,Event #5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4 ,Event #4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3 ,Event #3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2 ,Event #2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1 ,Event #1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0 ,Event #0" "Disabled,Enabled"
|
|
line.long 0x04 "EERH_RN_SET/CLR,Event Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " E63 ,Event #63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " E62 ,Event #62" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " E61 ,Event #61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " E60 ,Event #60" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " E59 ,Event #59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " E58 ,Event #58" "Disabled,Enabled"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " E57 ,Event #57" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " E56 ,Event #56" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " E55 ,Event #55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " E54 ,Event #54" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " E53 ,Event #53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " E52 ,Event #52" "Disabled,Enabled"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " E51 ,Event #51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " E50 ,Event #50" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " E49 ,Event #49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " E48 ,Event #48" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " E47 ,Event #47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " E46 ,Event #46" "Disabled,Enabled"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " E45 ,Event #45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " E44 ,Event #44" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " E43 ,Event #43" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " E42 ,Event #42" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " E41 ,Event #41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " E40 ,Event #40" "Disabled,Enabled"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " E39 ,Event #39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " E38 ,Event #38" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " E37 ,Event #37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " E36 ,Event #36" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " E35 ,Event #35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " E34 ,Event #34" "Disabled,Enabled"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " E33 ,Event #33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " E32 ,Event #32" "Disabled,Enabled"
|
|
rgroup.long 0x2038++0x07
|
|
line.long 0x00 "SER_RN,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "Not stored,Stored"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "Not stored,Stored"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "Not stored,Stored"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "Not stored,Stored"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "Not stored,Stored"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "Not stored,Stored"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "Not stored,Stored"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "Not stored,Stored"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "Not stored,Stored"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "Not stored,Stored"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "Not stored,Stored"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not stored,Stored"
|
|
line.long 0x04 "SERH_RN,Secondary Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "Not stored,Stored"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "Not stored,Stored"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "Not stored,Stored"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "Not stored,Stored"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "Not stored,Stored"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "Not stored,Stored"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "Not stored,Stored"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "Not stored,Stored"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "Not stored,Stored"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "Not stored,Stored"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "Not stored,Stored"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "Not stored,Stored"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "Not stored,Stored"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "Not stored,Stored"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "Not stored,Stored"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "Not stored,Stored"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "Not stored,Stored"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "Not stored,Stored"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "Not stored,Stored"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "Not stored,Stored"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "Not stored,Stored"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "Not stored,Stored"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "Not stored,Stored"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "Not stored,Stored"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "Not stored,Stored"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "Not stored,Stored"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "Not stored,Stored"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "Not stored,Stored"
|
|
wgroup.long 0x2040++0x07
|
|
line.long 0x00 "SECR_RN,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "No effect,Clear"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "No effect,Clear"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "No effect,Clear"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
line.long 0x04 "SECRH_RN,Secondary Event Clear Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "No effect,Clear"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "No effect,Clear"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "No effect,Clear"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "No effect,Clear"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "No effect,Clear"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "No effect,Clear"
|
|
group.long 0x2050++0x07
|
|
line.long 0x00 "IER_RN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31 ,Interrupt associated with TCC #31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30 ,Interrupt associated with TCC #30" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29 ,Interrupt associated with TCC #29" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28 ,Interrupt associated with TCC #28" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27 ,Interrupt associated with TCC #27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26 ,Interrupt associated with TCC #26" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25 ,Interrupt associated with TCC #25" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24 ,Interrupt associated with TCC #24" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23 ,Interrupt associated with TCC #23" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22 ,Interrupt associated with TCC #22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21 ,Interrupt associated with TCC #21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20 ,Interrupt associated with TCC #20" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19 ,Interrupt associated with TCC #19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18 ,Interrupt associated with TCC #18" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17 ,Interrupt associated with TCC #17" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16 ,Interrupt associated with TCC #16" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15 ,Interrupt associated with TCC #15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14 ,Interrupt associated with TCC #14" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13 ,Interrupt associated with TCC #13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12 ,Interrupt associated with TCC #12" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11 ,Interrupt associated with TCC #11" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10 ,Interrupt associated with TCC #10" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9 ,Interrupt associated with TCC #9" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8 ,Interrupt associated with TCC #8" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I7 ,Interrupt associated with TCC #7" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I6 ,Interrupt associated with TCC #6" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I5 ,Interrupt associated with TCC #5" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I4 ,Interrupt associated with TCC #4" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3 ,Interrupt associated with TCC #3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2 ,Interrupt associated with TCC #2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1 ,Interrupt associated with TCC #1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0 ,Interrupt associated with TCC #0" "No interrupt,Interrupt"
|
|
line.long 0x04 "IERH_RN_SET/CLR,Interrupt Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " I63 ,Interrupt associated with TCC #63" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " I62 ,Interrupt associated with TCC #62" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " I61 ,Interrupt associated with TCC #61" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " I60 ,Interrupt associated with TCC #60" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " I59 ,Interrupt associated with TCC #59" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " I58 ,Interrupt associated with TCC #58" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " I57 ,Interrupt associated with TCC #57" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " I56 ,Interrupt associated with TCC #56" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " I55 ,Interrupt associated with TCC #55" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " I54 ,Interrupt associated with TCC #54" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " I53 ,Interrupt associated with TCC #53" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " I52 ,Interrupt associated with TCC #52" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " I51 ,Interrupt associated with TCC #51" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " I50 ,Interrupt associated with TCC #50" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " I49 ,Interrupt associated with TCC #49" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " I48 ,Interrupt associated with TCC #48" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " I47 ,Interrupt associated with TCC #47" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " I46 ,Interrupt associated with TCC #46" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " I45 ,Interrupt associated with TCC #45" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " I44 ,Interrupt associated with TCC #44" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " I43 ,Interrupt associated with TCC #43" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " I42 ,Interrupt associated with TCC #42" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " I41 ,Interrupt associated with TCC #41" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " I40 ,Interrupt associated with TCC #40" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " I39 ,Interrupt associated with TCC #39" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " I38 ,Interrupt associated with TCC #38" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " I37 ,Interrupt associated with TCC #37" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " I36 ,Interrupt associated with TCC #36" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " I35 ,Interrupt associated with TCC #35" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " I34 ,Interrupt associated with TCC #34" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " I33 ,Interrupt associated with TCC #33" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " I32 ,Interrupt associated with TCC #32" "No interrupt,Interrupt"
|
|
rgroup.long 0x2068++0x07
|
|
line.long 0x00 "IPR_RN,Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt associated with TCC #31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt associated with TCC #30" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " I29 ,Interrupt associated with TCC #29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt associated with TCC #28" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " I27 ,Interrupt associated with TCC #27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt associated with TCC #26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " I25 ,Interrupt associated with TCC #25" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 24. " I24 ,Interrupt associated with TCC #24" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " I23 ,Interrupt associated with TCC #23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt associated with TCC #22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " I21 ,Interrupt associated with TCC #21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt associated with TCC #20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " I19 ,Interrupt associated with TCC #19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt associated with TCC #18" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 17. " I17 ,Interrupt associated with TCC #17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt associated with TCC #16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " I15 ,Interrupt associated with TCC #15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt associated with TCC #14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " I13 ,Interrupt associated with TCC #13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt associated with TCC #12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " I11 ,Interrupt associated with TCC #11" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. " I10 ,Interrupt associated with TCC #10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " I9 ,Interrupt associated with TCC #9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt associated with TCC #8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " I7 ,Interrupt associated with TCC #7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt associated with TCC #6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " I5 ,Interrupt associated with TCC #5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt associated with TCC #4" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " I3 ,Interrupt associated with TCC #3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt associated with TCC #2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " I1 ,Interrupt associated with TCC #1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt associated with TCC #0" "No interrupt,Interrupt"
|
|
line.long 0x04 "IPRH_RN,Interrupt Pending Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt associated with TCC #63" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt associated with TCC #62" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " I61 ,Interrupt associated with TCC #61" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt associated with TCC #60" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 27. " I59 ,Interrupt associated with TCC #59" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt associated with TCC #58" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " I57 ,Interrupt associated with TCC #57" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 24. " I56 ,Interrupt associated with TCC #56" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 23. " I55 ,Interrupt associated with TCC #55" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt associated with TCC #54" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " I53 ,Interrupt associated with TCC #53" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt associated with TCC #52" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 19. " I51 ,Interrupt associated with TCC #51" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt associated with TCC #50" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 17. " I49 ,Interrupt associated with TCC #49" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt associated with TCC #48" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 15. " I47 ,Interrupt associated with TCC #47" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt associated with TCC #46" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " I45 ,Interrupt associated with TCC #45" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt associated with TCC #44" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 11. " I43 ,Interrupt associated with TCC #43" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 10. " I42 ,Interrupt associated with TCC #42" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " I41 ,Interrupt associated with TCC #41" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt associated with TCC #40" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " I39 ,Interrupt associated with TCC #39" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt associated with TCC #38" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " I37 ,Interrupt associated with TCC #37" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt associated with TCC #36" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 3. " I35 ,Interrupt associated with TCC #35" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt associated with TCC #34" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " I33 ,Interrupt associated with TCC #33" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt associated with TCC #32" "No interrupt,Interrupt"
|
|
wgroup.long 0x2070++0x0B
|
|
line.long 0x00 "ICR_RN,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt associated with TCC #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt associated with TCC #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " I29 ,Interrupt associated with TCC #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt associated with TCC #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " I27 ,Interrupt associated with TCC #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt associated with TCC #26" "No effect,Clear"
|
|
bitfld.long 0x00 25. " I25 ,Interrupt associated with TCC #25" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 24. " I24 ,Interrupt associated with TCC #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " I23 ,Interrupt associated with TCC #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt associated with TCC #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " I21 ,Interrupt associated with TCC #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt associated with TCC #20" "No effect,Clear"
|
|
bitfld.long 0x00 19. " I19 ,Interrupt associated with TCC #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt associated with TCC #18" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 17. " I17 ,Interrupt associated with TCC #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt associated with TCC #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " I15 ,Interrupt associated with TCC #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt associated with TCC #14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " I13 ,Interrupt associated with TCC #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt associated with TCC #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " I11 ,Interrupt associated with TCC #11" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 10. " I10 ,Interrupt associated with TCC #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " I9 ,Interrupt associated with TCC #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt associated with TCC #8" "No effect,Clear"
|
|
bitfld.long 0x00 7. " I7 ,Interrupt associated with TCC #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt associated with TCC #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " I5 ,Interrupt associated with TCC #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt associated with TCC #4" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " I3 ,Interrupt associated with TCC #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt associated with TCC #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " I1 ,Interrupt associated with TCC #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt associated with TCC #0" "No effect,Clear"
|
|
line.long 0x04 "ICRH_RN,Interrupt Clear Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt associated with TCC #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt associated with TCC #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " I61 ,Interrupt associated with TCC #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt associated with TCC #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " I59 ,Interrupt associated with TCC #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt associated with TCC #58" "No effect,Clear"
|
|
bitfld.long 0x04 25. " I57 ,Interrupt associated with TCC #57" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 24. " I56 ,Interrupt associated with TCC #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " I55 ,Interrupt associated with TCC #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt associated with TCC #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " I53 ,Interrupt associated with TCC #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt associated with TCC #52" "No effect,Clear"
|
|
bitfld.long 0x04 19. " I51 ,Interrupt associated with TCC #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt associated with TCC #50" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 17. " I49 ,Interrupt associated with TCC #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt associated with TCC #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " I47 ,Interrupt associated with TCC #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt associated with TCC #46" "No effect,Clear"
|
|
bitfld.long 0x04 13. " I45 ,Interrupt associated with TCC #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt associated with TCC #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " I43 ,Interrupt associated with TCC #43" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10. " I42 ,Interrupt associated with TCC #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " I41 ,Interrupt associated with TCC #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt associated with TCC #40" "No effect,Clear"
|
|
bitfld.long 0x04 7. " I39 ,Interrupt associated with TCC #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt associated with TCC #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " I37 ,Interrupt associated with TCC #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt associated with TCC #36" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 3. " I35 ,Interrupt associated with TCC #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt associated with TCC #34" "No effect,Clear"
|
|
bitfld.long 0x04 1. " I33 ,Interrupt associated with TCC #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt associated with TCC #32" "No effect,Clear"
|
|
line.long 0x08 "IEVAL_RN,Interrupt EVAL Register"
|
|
bitfld.long 0x08 1. " SET ,Interrupt set" "Not set,Set"
|
|
bitfld.long 0x08 0. " EVAL ,Interrupt evaluate" "Not set,Set"
|
|
rgroup.long 0x2080++0x07
|
|
line.long 0x00 "QER_RN,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not occurred,Occurred"
|
|
line.long 0x04 "QEER_RN,QDMA Event Enable Register"
|
|
bitfld.long 0x04 7. " E7 ,Event #7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " E6 ,Event #6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E5 ,Event #5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " E4 ,Event #4" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " E3 ,Event #3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " E2 ,Event #2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " E1 ,Event #1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " E0 ,Event #0" "Disabled,Enabled"
|
|
wgroup.long 0x2088++0x07
|
|
line.long 0x00 "QEECR_RN,QDMA Event Enable Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
line.long 0x04 "QEESR_RN,QDMA Event Enable Set Register"
|
|
bitfld.long 0x04 7. " E7 ,Event #7" "Not set,Set"
|
|
bitfld.long 0x04 6. " E6 ,Event #6" "Not set,Set"
|
|
bitfld.long 0x04 5. " E5 ,Event #5" "Not set,Set"
|
|
bitfld.long 0x04 4. " E4 ,Event #4" "Not set,Set"
|
|
bitfld.long 0x04 3. " E3 ,Event #3" "Not set,Set"
|
|
bitfld.long 0x04 2. " E2 ,Event #2" "Not set,Set"
|
|
bitfld.long 0x04 1. " E1 ,Event #1" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x04 0. " E0 ,Event #0" "Not set,Set"
|
|
rgroup.long 0x2090++0x03
|
|
line.long 0x00 "QSER_RN,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not stored,Stored"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not stored,Stored"
|
|
wgroup.long 0x2094++0x03
|
|
line.long 0x00 "QSECR_RN,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
width 7.
|
|
newline
|
|
group.long 0x4000++0x1F
|
|
line.long 0x00 "OPT,Options Parameter Register"
|
|
rbitfld.long 0x00 31. " PRIV ,Privilege level" "User,Supervisor"
|
|
rbitfld.long 0x00 24.--27. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " WIMODE ,Backward compatibility mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " STATIC ,Static entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-sync,Ab-sync"
|
|
newline
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
line.long 0x04 "SRC,Source Address Register"
|
|
line.long 0x08 "ABCNT,A And B Byte Count Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,BCNT"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,ACNT"
|
|
line.long 0x0C "DST,Destination Address Register"
|
|
line.long 0x10 "BIDX,BIDX"
|
|
hexmask.long.word 0x10 16.--31. 1. " DBIDX ,Destination 2nd dimension index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SBIDX ,Source 2nd dimension index"
|
|
line.long 0x14 "LNK,Link And Reload Parameters Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,BCNT reload"
|
|
hexmask.long.word 0x14 0.--15. 0x01 " LINK ,Link address"
|
|
line.long 0x18 "CIDX,CIDX"
|
|
hexmask.long.word 0x18 16.--31. 1. " DCIDX ,Destination frame index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SCIDX ,Source frame index"
|
|
line.long 0x1C "CCNT,C Byte Count"
|
|
hexmask.long.word 0x1C 0.--15. 1. " CCNT ,Count for 3rd dimension"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TPCC1"
|
|
base ad:0x020A0000
|
|
width 10.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "PID,Peripheral ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major revision"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision"
|
|
line.long 0x04 "CCCFG,CC Configuration Register"
|
|
bitfld.long 0x04 25. " MPEXIST ,Memory protection existence MPEXIST" "Not protected,Protected"
|
|
bitfld.long 0x04 24. " CHMAPEXIST ,Channel mapping existence" "Not mapped,Mapped"
|
|
bitfld.long 0x04 20.--21. " NUMREGN ,Number of MP and shadow regions" ",,,8 regions"
|
|
newline
|
|
sif cpuis("AWR1843*")
|
|
bitfld.long 0x04 16.--18. " NUM_EVQUE ,Number of queues/number of TCs" ",2 EDMA3TCs/Event,,4 EDMA3TCs/Event,?..."
|
|
elif cpuis("AWR6843*")
|
|
bitfld.long 0x04 16.--18. " NUM_EVQUE ,Number of queues/number of TCs" "1 TC/Event queue,2 TC/Event queue,3 TC/Event queue,4 TC/Event queue,5 TC/Event queue,6 TC/Event queue,7 TC/Event queue,8 TC/Event queue"
|
|
else
|
|
bitfld.long 0x04 16.--18. " NUMTC ,Number of queues/number of TCs" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("AWR6843*")
|
|
newline
|
|
bitfld.long 0x04 12.--14. " NUMPAENTRY ,Number of PARAM entries" ",,,128,256,?..."
|
|
bitfld.long 0x04 8.--10. " NUMINTCH ,Number of interrupt channels" ",,16,,64,?..."
|
|
bitfld.long 0x04 4.--6. " NUMQDMACH ,Number of QDMA channels" ",,,,8,?..."
|
|
bitfld.long 0x04 0.--2. " NUMDMACH ,Number of DMA channels" ",,,,,64,?..."
|
|
else
|
|
newline
|
|
bitfld.long 0x04 12.--14. " NUMPAENTRY ,Number of PARAM entries" ",,,128,,512,?..."
|
|
bitfld.long 0x04 8.--10. " NUMINTCH ,Number of interrupt channels" ",,16,,64,?..."
|
|
bitfld.long 0x04 4.--6. " NUMQDMACH ,Number of QDMA channels" ",,,,8,?..."
|
|
bitfld.long 0x04 0.--2. " NUMDMACH ,Number of DMA channels" ",,,16,,64,?..."
|
|
endif
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
|
|
hexmask.long.word 0x00 5.--13. 1. " PAENTRY ,PARAM entry number for QDMA channel N"
|
|
bitfld.long 0x00 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PARAM entry defined by PAENTRY" "OPT,SRC,BCNT/ACNT,DST,DBIDX/SBIDX,BCNTRLD/LINK,DCIDX/SCIDX,CCNT"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "DMAQNUMN,DMA Queue Number Register"
|
|
bitfld.long 0x00 28.--30. " E7 ,DMA queue number for event #7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " E6 ,DMA queue number for event #6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " E5 ,DMA queue number for event #5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " E4 ,DMA queue number for event #4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " E3 ,DMA queue number for event #3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " E2 ,DMA queue number for event #2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " E1 ,DMA queue number for event #1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " E0 ,DMA queue number for event #0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register"
|
|
bitfld.long 0x00 28.--30. " E7 ,QDMA queue number for event #7" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 24.--26. " E6 ,QDMA queue number for event #6" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20.--22. " E5 ,QDMA queue number for event #5" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. " E4 ,QDMA queue number for event #4" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 12.--14. " E3 ,QDMA queue number for event #3" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--10. " E2 ,QDMA queue number for event #2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " E1 ,QDMA queue number for event #1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " E0 ,QDMA queue number for event #0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x280++0x07
|
|
line.long 0x00 "QUETCMAP,Queue To TC Mapping Register"
|
|
bitfld.long 0x00 4.--6. " TCNUMQ1 ,TC number for queue N" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " TCNUMQ0 ,TC number for queue N" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "QUEPRI,Queue Priority Register"
|
|
bitfld.long 0x04 4.--6. " PRIQ1 ,Priority level for queue 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " PRIQ0 ,Priority level for queue 0" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "EMR,Event Missed Register"
|
|
bitfld.long 0x00 31. " E31 ,Event missed #31" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " E30 ,Event missed #30" "Not occurred,Occurred"
|
|
bitfld.long 0x00 29. " E29 ,Event missed #29" "Not occurred,Occurred"
|
|
bitfld.long 0x00 28. " E28 ,Event missed #28" "Not occurred,Occurred"
|
|
bitfld.long 0x00 27. " E27 ,Event missed #27" "Not occurred,Occurred"
|
|
bitfld.long 0x00 26. " E26 ,Event missed #26" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 25. " E25 ,Event missed #25" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " E24 ,Event missed #24" "Not occurred,Occurred"
|
|
bitfld.long 0x00 23. " E23 ,Event missed #23" "Not occurred,Occurred"
|
|
bitfld.long 0x00 22. " E22 ,Event missed #22" "Not occurred,Occurred"
|
|
bitfld.long 0x00 21. " E21 ,Event missed #21" "Not occurred,Occurred"
|
|
bitfld.long 0x00 20. " E20 ,Event missed #20" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 19. " E19 ,Event missed #19" "Not occurred,Occurred"
|
|
bitfld.long 0x00 18. " E18 ,Event missed #18" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " E17 ,Event missed #17" "Not occurred,Occurred"
|
|
bitfld.long 0x00 16. " E16 ,Event missed #16" "Not occurred,Occurred"
|
|
bitfld.long 0x00 15. " E15 ,Event missed #15" "Not occurred,Occurred"
|
|
bitfld.long 0x00 14. " E14 ,Event missed #14" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 13. " E13 ,Event missed #13" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " E12 ,Event missed #12" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " E11 ,Event missed #11" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " E10 ,Event missed #10" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " E9 ,Event missed #9" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " E8 ,Event missed #8" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 7. " E7 ,Event missed #7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " E6 ,Event missed #6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " E5 ,Event missed #5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " E4 ,Event missed #4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " E3 ,Event missed #3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " E2 ,Event missed #2" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,Event missed #1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " E0 ,Event missed #0" "Not occurred,Occurred"
|
|
line.long 0x04 "EMRH,Event Missed Register (High Part)"
|
|
bitfld.long 0x04 31. " E63 ,Event missed #63" "Not occurred,Occurred"
|
|
bitfld.long 0x04 30. " E62 ,Event missed #62" "Not occurred,Occurred"
|
|
bitfld.long 0x04 29. " E61 ,Event missed #61" "Not occurred,Occurred"
|
|
bitfld.long 0x04 28. " E60 ,Event missed #60" "Not occurred,Occurred"
|
|
bitfld.long 0x04 27. " E59 ,Event missed #59" "Not occurred,Occurred"
|
|
bitfld.long 0x04 26. " E58 ,Event missed #58" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 25. " E57 ,Event missed #57" "Not occurred,Occurred"
|
|
bitfld.long 0x04 24. " E56 ,Event missed #56" "Not occurred,Occurred"
|
|
bitfld.long 0x04 23. " E55 ,Event missed #55" "Not occurred,Occurred"
|
|
bitfld.long 0x04 22. " E54 ,Event missed #54" "Not occurred,Occurred"
|
|
bitfld.long 0x04 21. " E53 ,Event missed #53" "Not occurred,Occurred"
|
|
bitfld.long 0x04 20. " E52 ,Event missed #52" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 19. " E51 ,Event missed #51" "Not occurred,Occurred"
|
|
bitfld.long 0x04 18. " E50 ,Event missed #50" "Not occurred,Occurred"
|
|
bitfld.long 0x04 17. " E49 ,Event missed #49" "Not occurred,Occurred"
|
|
bitfld.long 0x04 16. " E48 ,Event missed #48" "Not occurred,Occurred"
|
|
bitfld.long 0x04 15. " E47 ,Event missed #47" "Not occurred,Occurred"
|
|
bitfld.long 0x04 14. " E46 ,Event missed #46" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 13. " E45 ,Event missed #45" "Not occurred,Occurred"
|
|
bitfld.long 0x04 12. " E44 ,Event missed #44" "Not occurred,Occurred"
|
|
bitfld.long 0x04 11. " E43 ,Event missed #43" "Not occurred,Occurred"
|
|
bitfld.long 0x04 10. " E42 ,Event missed #42" "Not occurred,Occurred"
|
|
bitfld.long 0x04 9. " E41 ,Event missed #41" "Not occurred,Occurred"
|
|
bitfld.long 0x04 8. " E40 ,Event missed #40" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 7. " E39 ,Event missed #39" "Not occurred,Occurred"
|
|
bitfld.long 0x04 6. " E38 ,Event missed #38" "Not occurred,Occurred"
|
|
bitfld.long 0x04 5. " E37 ,Event missed #37" "Not occurred,Occurred"
|
|
bitfld.long 0x04 4. " E36 ,Event missed #36" "Not occurred,Occurred"
|
|
bitfld.long 0x04 3. " E35 ,Event missed #35" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " E34 ,Event missed #34" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 1. " E33 ,Event missed #33" "Not occurred,Occurred"
|
|
bitfld.long 0x04 0. " E32 ,Event missed #32" "Not occurred,Occurred"
|
|
wgroup.long 0x308++0x07
|
|
line.long 0x00 "EMCR,Event Missed Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Event missed clear #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Event missed clear #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Event missed clear #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " E28 ,Event missed clear #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Event missed clear #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Event missed clear #26" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 25. " E25 ,Event missed clear #25" "No effect,Clear"
|
|
bitfld.long 0x00 24. " E24 ,Event missed clear #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Event missed clear #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " E22 ,Event missed clear #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Event missed clear #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Event missed clear #20" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 19. " E19 ,Event missed clear #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Event missed clear #18" "No effect,Clear"
|
|
bitfld.long 0x00 17. " E17 ,Event missed clear #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " E16 ,Event missed clear #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Event missed clear #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Event missed clear #14" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 13. " E13 ,Event missed clear #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Event missed clear #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Event missed clear #11" "No effect,Clear"
|
|
bitfld.long 0x00 10. " E10 ,Event missed clear #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Event missed clear #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Event missed clear #8" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 7. " E7 ,Event missed clear #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event missed clear #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event missed clear #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event missed clear #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event missed clear #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event missed clear #2" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,Event missed clear #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Event missed clear #0" "No effect,Clear"
|
|
line.long 0x04 "EMCRH,Event Missed Clear Register (High Part)"
|
|
bitfld.long 0x04 31. " E63 ,Event missed clear #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Event missed clear #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Event missed clear #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " E60 ,Event missed clear #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Event missed clear #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Event missed clear #58" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 25. " E57 ,Event missed clear #57" "No effect,Clear"
|
|
bitfld.long 0x04 24. " E56 ,Event missed clear #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Event missed clear #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " E54 ,Event missed clear #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Event missed clear #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Event missed clear #52" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 19. " E51 ,Event missed clear #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Event missed clear #50" "No effect,Clear"
|
|
bitfld.long 0x04 17. " E49 ,Event missed clear #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " E48 ,Event missed clear #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Event missed clear #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Event missed clear #46" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 13. " E45 ,Event missed clear #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Event missed clear #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Event missed clear #43" "No effect,Clear"
|
|
bitfld.long 0x04 10. " E42 ,Event missed clear #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Event missed clear #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Event missed clear #40" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 7. " E39 ,Event missed clear #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Event missed clear #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Event missed clear #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " E36 ,Event missed clear #36" "No effect,Clear"
|
|
bitfld.long 0x04 3. " E35 ,Event missed clear #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Event missed clear #34" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 1. " E33 ,Event missed clear #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Event missed clear #32" "No effect,Clear"
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "QEMR,QDMA Event Missed Register"
|
|
bitfld.long 0x00 7. " E7 ,Event missed #7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " E6 ,Event missed #6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " E5 ,Event missed #5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " E4 ,Event missed #4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " E3 ,Event missed #3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " E2 ,Event missed #2" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,Event missed #1" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " E0 ,Event missed #0" "Not occurred,Occurred"
|
|
wgroup.long 0x314++0x03
|
|
line.long 0x00 "QEMR,QDMA Event Missed Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,Event missed clear #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event missed clear #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event missed clear #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event missed clear #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event missed clear #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event missed clear #2" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,Event missed clear #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Event missed clear #0" "No effect,Clear"
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "CCERR,CC Error Register"
|
|
bitfld.long 0x00 16. " TCERR ,Transfer completion code error" "No error,Error"
|
|
bitfld.long 0x00 7. " QTHRXCD7 ,Queue threshold error for Q7" "No error,Error"
|
|
bitfld.long 0x00 6. " QTHRXCD6 ,Queue threshold error for Q6" "No error,Error"
|
|
bitfld.long 0x00 5. " QTHRXCD5 ,Queue threshold error for Q5" "No error,Error"
|
|
bitfld.long 0x00 4. " QTHRXCD4 ,Queue threshold error for Q4" "No error,Error"
|
|
bitfld.long 0x00 3. " QTHRXCD3 ,Queue threshold error for Q3" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " QTHRXCD2 ,Queue threshold error for Q2" "No error,Error"
|
|
bitfld.long 0x00 1. " QTHRXCD1 ,Queue threshold error for Q1" "No error,Error"
|
|
bitfld.long 0x00 0. " QTHRXCD0 ,Queue threshold error for Q0" "No error,Error"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
wgroup.long 0x31C++0x07
|
|
line.long 0x00 "CCERRCLR,CC Error Clear Register"
|
|
bitfld.long 0x00 16. " TCERR ,Transfer completion code error" "No effect,Clear"
|
|
bitfld.long 0x00 7. " QTHRXCD7 ,Clear error for CCERR.QTHRXCD7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " QTHRXCD6 ,Clear error for CCERR.QTHRXCD6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " QTHRXCD5 ,Clear error for CCERR.QTHRXCD5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " QTHRXCD4 ,Clear error for CCERR.QTHRXCD4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " QTHRXCD3 ,Clear error for CCERR.QTHRXCD3" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " QTHRXCD2 ,Clear error for CCERR.QTHRXCD2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " QTHRXCD1 ,Clear error for CCERR.QTHRXCD1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " QTHRXCD0 ,Clear error for CCERR.QTHRXCD0" "No effect,Clear"
|
|
line.long 0x04 "EEVAL,Error Eval Register"
|
|
bitfld.long 0x04 1. " SET ,Error interrupt set" "No error,Error"
|
|
bitfld.long 0x04 0. " EVAL ,Error interrupt evaluate" "No error,Error"
|
|
else
|
|
wgroup.long 0x31C++0x07
|
|
line.long 0x00 "CCERR,CC Error Clear Register"
|
|
bitfld.long 0x00 16. " TCERR ,Transfer completion code error" "No effect,Clear"
|
|
bitfld.long 0x00 7. " QTHRXCD7 ,Clear error for CCERR.QTHRXCD7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " QTHRXCD6 ,Clear error for CCERR.QTHRXCD6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " QTHRXCD5 ,Clear error for CCERR.QTHRXCD5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " QTHRXCD4 ,Clear error for CCERR.QTHRXCD4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " QTHRXCD3 ,Clear error for CCERR.QTHRXCD3" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " QTHRXCD2 ,Clear error for CCERR.QTHRXCD2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " QTHRXCD1 ,Clear error for CCERR.QTHRXCD1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " QTHRXCD0 ,Clear error for CCERR.QTHRXCD0" "No effect,Clear"
|
|
line.long 0x04 "CCERR,Error Eval Register"
|
|
bitfld.long 0x04 1. " SET ,Error interrupt set" "No error,Error"
|
|
bitfld.long 0x04 0. " EVAL ,Error interrupt evaluate" "No error,Error"
|
|
endif
|
|
group.long 0x340++0x07
|
|
line.long 0x00 "DRAEM,DMA Region Access Enable Register"
|
|
bitfld.long 0x00 31. " E31 ,DMA region access enable for region M bit #31" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " E30 ,DMA region access enable for region M bit #30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " E29 ,DMA region access enable for region M bit #29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " E28 ,DMA region access enable for region M bit #28" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " E27 ,DMA region access enable for region M bit #27" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " E26 ,DMA region access enable for region M bit #26" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " E25 ,DMA region access enable for region M bit #25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " E24 ,DMA region access enable for region M bit #24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " E23 ,DMA region access enable for region M bit #23" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " E22 ,DMA region access enable for region M bit #22" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " E21 ,DMA region access enable for region M bit #21" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " E20 ,DMA region access enable for region M bit #20" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " E19 ,DMA region access enable for region M bit #19" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " E18 ,DMA region access enable for region M bit #18" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " E17 ,DMA region access enable for region M bit #17" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " E16 ,DMA region access enable for region M bit #16" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " E15 ,DMA region access enable for region M bit #15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " E14 ,DMA region access enable for region M bit #14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " E13 ,DMA region access enable for region M bit #13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " E12 ,DMA region access enable for region M bit #12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " E11 ,DMA region access enable for region M bit #11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " E10 ,DMA region access enable for region M bit #10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " E9 ,DMA region access enable for region M bit #9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " E8 ,DMA region access enable for region M bit #8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " E7 ,DMA region access enable for region M bit #7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " E6 ,DMA region access enable for region M bit #6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E5 ,DMA region access enable for region M bit #5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " E4 ,DMA region access enable for region M bit #4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " E3 ,DMA region access enable for region M bit #3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " E2 ,DMA region access enable for region M bit #2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,DMA region access enable for region M bit #1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " E0 ,DMA region access enable for region M bit #0" "Disabled,Enabled"
|
|
line.long 0x04 "DRAEHM,DMA Region Access Enable Register"
|
|
bitfld.long 0x04 31. " E63 ,DMA region access enable for region M bit #63" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " E62 ,DMA region access enable for region M bit #62" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " E61 ,DMA region access enable for region M bit #61" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " E60 ,DMA region access enable for region M bit #60" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " E59 ,DMA region access enable for region M bit #59" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " E58 ,DMA region access enable for region M bit #58" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " E57 ,DMA region access enable for region M bit #57" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " E56 ,DMA region access enable for region M bit #56" "Disabled,Enabled"
|
|
bitfld.long 0x04 23. " E55 ,DMA region access enable for region M bit #55" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " E54 ,DMA region access enable for region M bit #54" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " E53 ,DMA region access enable for region M bit #53" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " E52 ,DMA region access enable for region M bit #52" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " E51 ,DMA region access enable for region M bit #51" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " E50 ,DMA region access enable for region M bit #50" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " E49 ,DMA region access enable for region M bit #49" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " E48 ,DMA region access enable for region M bit #48" "Disabled,Enabled"
|
|
bitfld.long 0x04 15. " E47 ,DMA region access enable for region M bit #47" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " E46 ,DMA region access enable for region M bit #46" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 13. " E45 ,DMA region access enable for region M bit #45" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " E44 ,DMA region access enable for region M bit #44" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " E43 ,DMA region access enable for region M bit #43" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " E42 ,DMA region access enable for region M bit #42" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " E41 ,DMA region access enable for region M bit #41" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " E40 ,DMA region access enable for region M bit #40" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " E39 ,DMA region access enable for region M bit #39" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " E38 ,DMA region access enable for region M bit #38" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E37 ,DMA region access enable for region M bit #37" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " E36 ,DMA region access enable for region M bit #36" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " E35 ,DMA region access enable for region M bit #35" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " E34 ,DMA region access enable for region M bit #34" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " E33 ,DMA region access enable for region M bit #33" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " E32 ,DMA region access enable for region M bit #32" "Disabled,Enabled"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "QRAEN,QDMA Region Access Enable Register"
|
|
bitfld.long 0x00 7. " E7 ,QDMA region access enable for region M bit #7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " E6 ,QDMA region access enable for region M bit #6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " E5 ,QDMA region access enable for region M bit #5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " E4 ,QDMA region access enable for region M bit #4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " E3 ,QDMA region access enable for region M bit #3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " E2 ,QDMA region access enable for region M bit #2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " E1 ,QDMA region access enable for region M bit #1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " E0 ,QDMA region access enable for region M bit #0" "Disabled,Enabled"
|
|
rgroup.long 0x400++0x03
|
|
line.long 0x00 "QNE0,Event Queue Entry Diagram For Queue n - Entry 0"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x404++0x03
|
|
line.long 0x00 "QNE1,Event Queue Entry Diagram For Queue n - Entry 1"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x408++0x03
|
|
line.long 0x00 "QNE2,Event Queue Entry Diagram For Queue n - Entry 2"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "QNE3,Event Queue Entry Diagram For Queue n - Entry 3"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x410++0x03
|
|
line.long 0x00 "QNE4,Event Queue Entry Diagram For Queue n - Entry 4"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x414++0x03
|
|
line.long 0x00 "QNE5,Event Queue Entry Diagram For Queue n - Entry 5"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x418++0x03
|
|
line.long 0x00 "QNE6,Event Queue Entry Diagram For Queue n - Entry 6"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x41C++0x03
|
|
line.long 0x00 "QNE7,Event Queue Entry Diagram For Queue n - Entry 7"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x420++0x03
|
|
line.long 0x00 "QNE8,Event Queue Entry Diagram For Queue n - Entry 8"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x424++0x03
|
|
line.long 0x00 "QNE9,Event Queue Entry Diagram For Queue n - Entry 9"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x428++0x03
|
|
line.long 0x00 "QNE10,Event Queue Entry Diagram For Queue n - Entry 10"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x42C++0x03
|
|
line.long 0x00 "QNE11,Event Queue Entry Diagram For Queue n - Entry 11"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x430++0x03
|
|
line.long 0x00 "QNE12,Event Queue Entry Diagram For Queue n - Entry 12"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x434++0x03
|
|
line.long 0x00 "QNE13,Event Queue Entry Diagram For Queue n - Entry 13"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x438++0x03
|
|
line.long 0x00 "QNE14,Event Queue Entry Diagram For Queue n - Entry 14"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x43C++0x03
|
|
line.long 0x00 "QNE15,Event Queue Entry Diagram For Queue n - Entry 15"
|
|
bitfld.long 0x00 6.--7. " ETYPE ,Event type" "Triggered,Manually-triggered,Chain-triggered,QDMA"
|
|
bitfld.long 0x00 0.--5. " ENUM ,Event number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x600++0x03
|
|
line.long 0x00 "QSTATN,QSTATn Register Set"
|
|
bitfld.long 0x00 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded"
|
|
bitfld.long 0x00 16.--20. " WM ,Watermark for maximum queue usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--12. " NUMVAL ,Number of valid entries in queueN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0.--3. " STRTPTR ,Start pointer" "0th,1th,2th,3th,4th,5th,6th,7th,8th,9th,10th,11th,12th,13th,14th,15th"
|
|
group.long 0x620++0x03
|
|
line.long 0x00 "QWMTHRA,Queue Threshold A For Q[3:0] Register"
|
|
bitfld.long 0x00 8.--12. " Q1 ,Queue threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x00 0.--4. " Q0 ,Queue threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
width 18.
|
|
newline
|
|
rgroup.long 0x640++0x03
|
|
line.long 0x00 "EDMA_TPCC_CCSTAT,CC Status Register"
|
|
bitfld.long 0x00 23. " QUEACTV7 ,Queue 7 active QUEACTV7" "Not active,Active"
|
|
bitfld.long 0x00 22. " QUEACTV6 ,Queue 6 active QUEACTV6" "Not active,Active"
|
|
bitfld.long 0x00 21. " QUEACTV5 ,Queue 5 active QUEACTV5" "Not active,Active"
|
|
bitfld.long 0x00 20. " QUEACTV4 ,Queue 4 active QUEACTV4" "Not active,Active"
|
|
bitfld.long 0x00 19. " QUEACTV3 ,Queue 3 active QUEACTV3" "Not active,Active"
|
|
bitfld.long 0x00 18. " QUEACTV2 ,Queue 2 active QUEACTV2" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 17. " QUEACTV1 ,Queue 1 active QUEACTV1" "Not active,Active"
|
|
bitfld.long 0x00 16. " QUEACTV0 ,Queue 0 active QUEACTV0" "Not active,Active"
|
|
bitfld.long 0x00 8.--13. " COMPACTV ,Completion request active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 4. " ACTV ,Channel controller active" "Idle,Busy"
|
|
bitfld.long 0x00 2. " TRACTV ,Transfer request active" "Not active,Active"
|
|
bitfld.long 0x00 1. " QEVTACTV ,QDMA event active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 0. " EVTACTV ,DMA event active" "Not active,Active"
|
|
newline
|
|
width 9.
|
|
group.long 0x700++0x03
|
|
line.long 0x00 "AETCTL,Advanced Event Trigger Control Register"
|
|
bitfld.long 0x00 31. " EN ,AET enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
bitfld.long 0x00 8.--13. " ENDINT ,AET end interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,56,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 7. " ENDINT ,AET end interrupt" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 6. " TYPE ,AET event type" "DMA,QDMA"
|
|
bitfld.long 0x00 0.--5. " STRTEVT ,AET start event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x704++0x03
|
|
line.long 0x00 "AETSTAT,Advanced Event Trigger Status Register"
|
|
bitfld.long 0x00 0. " STAT ,AET status" "Low,High"
|
|
wgroup.long 0x708++0x03
|
|
line.long 0x00 "AETCMD,AET Command Register"
|
|
bitfld.long 0x00 0. " CLR ,AET clear command" "No effect,Clear"
|
|
newline
|
|
width 17.
|
|
group.long 0x1000++0x07
|
|
line.long 0x00 "ER_SET/CLR,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31 ,Event #31" "Inactive,Active"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30 ,Event #30" "Inactive,Active"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29 ,Event #29" "Inactive,Active"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28 ,Event #28" "Inactive,Active"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27 ,Event #27" "Inactive,Active"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26 ,Event #26" "Inactive,Active"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25 ,Event #25" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24 ,Event #24" "Inactive,Active"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23 ,Event #23" "Inactive,Active"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22 ,Event #22" "Inactive,Active"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21 ,Event #21" "Inactive,Active"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20 ,Event #20" "Inactive,Active"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19 ,Event #19" "Inactive,Active"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18 ,Event #18" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17 ,Event #17" "Inactive,Active"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16 ,Event #16" "Inactive,Active"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15 ,Event #15" "Inactive,Active"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14 ,Event #14" "Inactive,Active"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13 ,Event #13" "Inactive,Active"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12 ,Event #12" "Inactive,Active"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11 ,Event #11" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10 ,Event #10" "Inactive,Active"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9 ,Event #9" "Inactive,Active"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8 ,Event #8" "Inactive,Active"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7 ,Event #7" "Inactive,Active"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6 ,Event #6" "Inactive,Active"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5 ,Event #5" "Inactive,Active"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4 ,Event #4" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3 ,Event #3" "Inactive,Active"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2 ,Event #2" "Inactive,Active"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1 ,Event #1" "Inactive,Active"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0 ,Event #0" "Inactive,Active"
|
|
line.long 0x04 "ERH_SET/CLR,Event Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " E63 ,Event #63" "Inactive,Active"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " E62 ,Event #62" "Inactive,Active"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " E61 ,Event #61" "Inactive,Active"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " E60 ,Event #60" "Inactive,Active"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " E59 ,Event #59" "Inactive,Active"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " E58 ,Event #58" "Inactive,Active"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " E57 ,Event #57" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " E56 ,Event #56" "Inactive,Active"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " E55 ,Event #55" "Inactive,Active"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " E54 ,Event #54" "Inactive,Active"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " E53 ,Event #53" "Inactive,Active"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " E52 ,Event #52" "Inactive,Active"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " E51 ,Event #51" "Inactive,Active"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " E50 ,Event #50" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " E49 ,Event #49" "Inactive,Active"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " E48 ,Event #48" "Inactive,Active"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " E47 ,Event #47" "Inactive,Active"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " E46 ,Event #46" "Inactive,Active"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " E45 ,Event #45" "Inactive,Active"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " E44 ,Event #44" "Inactive,Active"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " E43 ,Event #43" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " E42 ,Event #42" "Inactive,Active"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " E41 ,Event #41" "Inactive,Active"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " E40 ,Event #40" "Inactive,Active"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " E39 ,Event #39" "Inactive,Active"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " E38 ,Event #38" "Inactive,Active"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " E37 ,Event #37" "Inactive,Active"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " E36 ,Event #36" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " E35 ,Event #35" "Inactive,Active"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " E34 ,Event #34" "Inactive,Active"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " E33 ,Event #33" "Inactive,Active"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " E32 ,Event #32" "Inactive,Active"
|
|
rgroup.long 0x1018++0x07
|
|
line.long 0x00 "CER,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "Not chained,Chained"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "Not chained,Chained"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "Not chained,Chained"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "Not chained,Chained"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "Not chained,Chained"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "Not chained,Chained"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "Not chained,Chained"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "Not chained,Chained"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "Not chained,Chained"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "Not chained,Chained"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "Not chained,Chained"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "Not chained,Chained"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "Not chained,Chained"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "Not chained,Chained"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "Not chained,Chained"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "Not chained,Chained"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "Not chained,Chained"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "Not chained,Chained"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "Not chained,Chained"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "Not chained,Chained"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "Not chained,Chained"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not chained,Chained"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not chained,Chained"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not chained,Chained"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not chained,Chained"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not chained,Chained"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not chained,Chained"
|
|
line.long 0x04 "CERH,Chained Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "Not chained,Chained"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "Not chained,Chained"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "Not chained,Chained"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "Not chained,Chained"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "Not chained,Chained"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "Not chained,Chained"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "Not chained,Chained"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "Not chained,Chained"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "Not chained,Chained"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "Not chained,Chained"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "Not chained,Chained"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "Not chained,Chained"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "Not chained,Chained"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "Not chained,Chained"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "Not chained,Chained"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "Not chained,Chained"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "Not chained,Chained"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "Not chained,Chained"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "Not chained,Chained"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "Not chained,Chained"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "Not chained,Chained"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "Not chained,Chained"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "Not chained,Chained"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "Not chained,Chained"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "Not chained,Chained"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "Not chained,Chained"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "Not chained,Chained"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "Not chained,Chained"
|
|
group.long 0x1020++0x07
|
|
line.long 0x00 "EER_SET/CLR,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31 ,Event #31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30 ,Event #30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29 ,Event #29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28 ,Event #28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27 ,Event #27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26 ,Event #26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25 ,Event #25" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24 ,Event #24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23 ,Event #23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22 ,Event #22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21 ,Event #21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20 ,Event #20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19 ,Event #19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18 ,Event #18" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17 ,Event #17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16 ,Event #16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15 ,Event #15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14 ,Event #14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13 ,Event #13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12 ,Event #12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11 ,Event #11" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10 ,Event #10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9 ,Event #9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8 ,Event #8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7 ,Event #7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6 ,Event #6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5 ,Event #5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4 ,Event #4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3 ,Event #3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2 ,Event #2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1 ,Event #1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0 ,Event #0" "Disabled,Enabled"
|
|
line.long 0x04 "EERH_SET/CLR,Event Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " E63 ,Event #63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " E62 ,Event #62" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " E61 ,Event #61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " E60 ,Event #60" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " E59 ,Event #59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " E58 ,Event #58" "Disabled,Enabled"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " E57 ,Event #57" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " E56 ,Event #56" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " E55 ,Event #55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " E54 ,Event #54" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " E53 ,Event #53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " E52 ,Event #52" "Disabled,Enabled"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " E51 ,Event #51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " E50 ,Event #50" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " E49 ,Event #49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " E48 ,Event #48" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " E47 ,Event #47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " E46 ,Event #46" "Disabled,Enabled"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " E45 ,Event #45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " E44 ,Event #44" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " E43 ,Event #43" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " E42 ,Event #42" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " E41 ,Event #41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " E40 ,Event #40" "Disabled,Enabled"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " E39 ,Event #39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " E38 ,Event #38" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " E37 ,Event #37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " E36 ,Event #36" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " E35 ,Event #35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " E34 ,Event #34" "Disabled,Enabled"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " E33 ,Event #33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " E32 ,Event #32" "Disabled,Enabled"
|
|
rgroup.long 0x1038++0x07
|
|
line.long 0x00 "SER,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "Not stored,Stored"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "Not stored,Stored"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "Not stored,Stored"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "Not stored,Stored"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "Not stored,Stored"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "Not stored,Stored"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "Not stored,Stored"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "Not stored,Stored"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "Not stored,Stored"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "Not stored,Stored"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "Not stored,Stored"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not stored,Stored"
|
|
line.long 0x04 "SERH,EDMA TPCC Secondary Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "Not stored,Stored"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "Not stored,Stored"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "Not stored,Stored"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "Not stored,Stored"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "Not stored,Stored"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "Not stored,Stored"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "Not stored,Stored"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "Not stored,Stored"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "Not stored,Stored"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "Not stored,Stored"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "Not stored,Stored"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "Not stored,Stored"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "Not stored,Stored"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "Not stored,Stored"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "Not stored,Stored"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "Not stored,Stored"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "Not stored,Stored"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "Not stored,Stored"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "Not stored,Stored"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "Not stored,Stored"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "Not stored,Stored"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "Not stored,Stored"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "Not stored,Stored"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "Not stored,Stored"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "Not stored,Stored"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "Not stored,Stored"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "Not stored,Stored"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "Not stored,Stored"
|
|
wgroup.long 0x1040++0x07
|
|
line.long 0x00 "SECR,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "No effect,Clear"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "No effect,Clear"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "No effect,Clear"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
line.long 0x04 "SECRH,Secondary Event Clear Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "No effect,Clear"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "No effect,Clear"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "No effect,Clear"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "No effect,Clear"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "No effect,Clear"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "No effect,Clear"
|
|
group.long 0x1050++0x07
|
|
line.long 0x00 "IER_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31 ,Interrupt associated with TCC #31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30 ,Interrupt associated with TCC #30" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29 ,Interrupt associated with TCC #29" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28 ,Interrupt associated with TCC #28" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27 ,Interrupt associated with TCC #27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26 ,Interrupt associated with TCC #26" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25 ,Interrupt associated with TCC #25" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24 ,Interrupt associated with TCC #24" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23 ,Interrupt associated with TCC #23" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22 ,Interrupt associated with TCC #22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21 ,Interrupt associated with TCC #21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20 ,Interrupt associated with TCC #20" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19 ,Interrupt associated with TCC #19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18 ,Interrupt associated with TCC #18" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17 ,Interrupt associated with TCC #17" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16 ,Interrupt associated with TCC #16" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15 ,Interrupt associated with TCC #15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14 ,Interrupt associated with TCC #14" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13 ,Interrupt associated with TCC #13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12 ,Interrupt associated with TCC #12" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11 ,Interrupt associated with TCC #11" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10 ,Interrupt associated with TCC #10" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9 ,Interrupt associated with TCC #9" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8 ,Interrupt associated with TCC #8" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I7 ,Interrupt associated with TCC #7" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I6 ,Interrupt associated with TCC #6" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I5 ,Interrupt associated with TCC #5" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I4 ,Interrupt associated with TCC #4" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3 ,Interrupt associated with TCC #3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2 ,Interrupt associated with TCC #2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1 ,Interrupt associated with TCC #1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0 ,Interrupt associated with TCC #0" "No interrupt,Interrupt"
|
|
line.long 0x04 "IERH_SET/CLR,EDMA TPCC Interrupts Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " I63 ,Interrupt associated with TCC #63" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " I62 ,Interrupt associated with TCC #62" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " I61 ,Interrupt associated with TCC #61" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " I60 ,Interrupt associated with TCC #60" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " I59 ,Interrupt associated with TCC #59" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " I58 ,Interrupt associated with TCC #58" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " I57 ,Interrupt associated with TCC #57" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " I56 ,Interrupt associated with TCC #56" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " I55 ,Interrupt associated with TCC #55" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " I54 ,Interrupt associated with TCC #54" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " I53 ,Interrupt associated with TCC #53" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " I52 ,Interrupt associated with TCC #52" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " I51 ,Interrupt associated with TCC #51" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " I50 ,Interrupt associated with TCC #50" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " I49 ,Interrupt associated with TCC #49" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " I48 ,Interrupt associated with TCC #48" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " I47 ,Interrupt associated with TCC #47" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " I46 ,Interrupt associated with TCC #46" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " I45 ,Interrupt associated with TCC #45" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " I44 ,Interrupt associated with TCC #44" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " I43 ,Interrupt associated with TCC #43" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " I42 ,Interrupt associated with TCC #42" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " I41 ,Interrupt associated with TCC #41" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " I40 ,Interrupt associated with TCC #40" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " I39 ,Interrupt associated with TCC #39" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " I38 ,Interrupt associated with TCC #38" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " I37 ,Interrupt associated with TCC #37" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " I36 ,Interrupt associated with TCC #36" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " I35 ,Interrupt associated with TCC #35" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " I34 ,Interrupt associated with TCC #34" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " I33 ,Interrupt associated with TCC #33" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " I32 ,Interrupt associated with TCC #32" "No interrupt,Interrupt"
|
|
rgroup.long 0x1068++0x07
|
|
line.long 0x00 "IPR,Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt associated with TCC #31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt associated with TCC #30" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " I29 ,Interrupt associated with TCC #29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt associated with TCC #28" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " I27 ,Interrupt associated with TCC #27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt associated with TCC #26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " I25 ,Interrupt associated with TCC #25" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 24. " I24 ,Interrupt associated with TCC #24" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " I23 ,Interrupt associated with TCC #23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt associated with TCC #22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " I21 ,Interrupt associated with TCC #21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt associated with TCC #20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " I19 ,Interrupt associated with TCC #19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt associated with TCC #18" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 17. " I17 ,Interrupt associated with TCC #17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt associated with TCC #16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " I15 ,Interrupt associated with TCC #15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt associated with TCC #14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " I13 ,Interrupt associated with TCC #13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt associated with TCC #12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " I11 ,Interrupt associated with TCC #11" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. " I10 ,Interrupt associated with TCC #10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " I9 ,Interrupt associated with TCC #9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt associated with TCC #8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " I7 ,Interrupt associated with TCC #7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt associated with TCC #6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " I5 ,Interrupt associated with TCC #5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt associated with TCC #4" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " I3 ,Interrupt associated with TCC #3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt associated with TCC #2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " I1 ,Interrupt associated with TCC #1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt associated with TCC #0" "No interrupt,Interrupt"
|
|
line.long 0x04 "IPRH,Interrupt Pending Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt associated with TCC #63" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt associated with TCC #62" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " I61 ,Interrupt associated with TCC #61" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt associated with TCC #60" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 27. " I59 ,Interrupt associated with TCC #59" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt associated with TCC #58" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " I57 ,Interrupt associated with TCC #57" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 24. " I56 ,Interrupt associated with TCC #56" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 23. " I55 ,Interrupt associated with TCC #55" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt associated with TCC #54" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " I53 ,Interrupt associated with TCC #53" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt associated with TCC #52" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 19. " I51 ,Interrupt associated with TCC #51" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt associated with TCC #50" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 17. " I49 ,Interrupt associated with TCC #49" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt associated with TCC #48" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 15. " I47 ,Interrupt associated with TCC #47" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt associated with TCC #46" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " I45 ,Interrupt associated with TCC #45" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt associated with TCC #44" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 11. " I43 ,Interrupt associated with TCC #43" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 10. " I42 ,Interrupt associated with TCC #42" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " I41 ,Interrupt associated with TCC #41" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt associated with TCC #40" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " I39 ,Interrupt associated with TCC #39" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt associated with TCC #38" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " I37 ,Interrupt associated with TCC #37" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt associated with TCC #36" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 3. " I35 ,Interrupt associated with TCC #35" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt associated with TCC #34" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " I33 ,Interrupt associated with TCC #33" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt associated with TCC #32" "No interrupt,Interrupt"
|
|
wgroup.long 0x1070++0x07
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt associated with TCC #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt associated with TCC #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " I29 ,Interrupt associated with TCC #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt associated with TCC #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " I27 ,Interrupt associated with TCC #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt associated with TCC #26" "No effect,Clear"
|
|
bitfld.long 0x00 25. " I25 ,Interrupt associated with TCC #25" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 24. " I24 ,Interrupt associated with TCC #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " I23 ,Interrupt associated with TCC #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt associated with TCC #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " I21 ,Interrupt associated with TCC #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt associated with TCC #20" "No effect,Clear"
|
|
bitfld.long 0x00 19. " I19 ,Interrupt associated with TCC #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt associated with TCC #18" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 17. " I17 ,Interrupt associated with TCC #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt associated with TCC #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " I15 ,Interrupt associated with TCC #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt associated with TCC #14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " I13 ,Interrupt associated with TCC #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt associated with TCC #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " I11 ,Interrupt associated with TCC #11" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 10. " I10 ,Interrupt associated with TCC #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " I9 ,Interrupt associated with TCC #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt associated with TCC #8" "No effect,Clear"
|
|
bitfld.long 0x00 7. " I7 ,Interrupt associated with TCC #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt associated with TCC #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " I5 ,Interrupt associated with TCC #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt associated with TCC #4" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " I3 ,Interrupt associated with TCC #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt associated with TCC #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " I1 ,Interrupt associated with TCC #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt associated with TCC #0" "No effect,Clear"
|
|
line.long 0x04 "ICRH,Interrupt Clear Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt associated with TCC #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt associated with TCC #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " I61 ,Interrupt associated with TCC #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt associated with TCC #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " I59 ,Interrupt associated with TCC #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt associated with TCC #58" "No effect,Clear"
|
|
bitfld.long 0x04 25. " I57 ,Interrupt associated with TCC #57" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 24. " I56 ,Interrupt associated with TCC #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " I55 ,Interrupt associated with TCC #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt associated with TCC #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " I53 ,Interrupt associated with TCC #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt associated with TCC #52" "No effect,Clear"
|
|
bitfld.long 0x04 19. " I51 ,Interrupt associated with TCC #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt associated with TCC #50" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 17. " I49 ,Interrupt associated with TCC #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt associated with TCC #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " I47 ,Interrupt associated with TCC #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt associated with TCC #46" "No effect,Clear"
|
|
bitfld.long 0x04 13. " I45 ,Interrupt associated with TCC #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt associated with TCC #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " I43 ,Interrupt associated with TCC #43" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10. " I42 ,Interrupt associated with TCC #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " I41 ,Interrupt associated with TCC #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt associated with TCC #40" "No effect,Clear"
|
|
bitfld.long 0x04 7. " I39 ,Interrupt associated with TCC #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt associated with TCC #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " I37 ,Interrupt associated with TCC #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt associated with TCC #36" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 3. " I35 ,Interrupt associated with TCC #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt associated with TCC #34" "No effect,Clear"
|
|
bitfld.long 0x04 1. " I33 ,Interrupt associated with TCC #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt associated with TCC #32" "No effect,Clear"
|
|
wgroup.long 0x1078++0x03
|
|
line.long 0x00 "IEVAL,Interrupt EVAL Register"
|
|
bitfld.long 0x00 1. " SET ,Interrupt set" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Interrupt evaluate" "Not set,Set"
|
|
rgroup.long 0x1080++0x03
|
|
line.long 0x00 "QER,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not occurred,Occurred"
|
|
group.long 0x1084++0x03
|
|
line.long 0x00 "QEER_SET/CLR,QDMA Event Enable Register"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7 ,Event #7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6 ,Event #6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5 ,Event #5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4 ,Event #4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3 ,Event #3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2 ,Event #2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1 ,Event #1" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0 ,Event #0" "Disabled,Enabled"
|
|
rgroup.long 0x1090++0x03
|
|
line.long 0x00 "QSER,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not stored,Stored"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not stored,Stored"
|
|
wgroup.long 0x1094++0x03
|
|
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
group.long 0x2000++0x07
|
|
line.long 0x00 "ER_RN_SET/CLR,Event Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31 ,Event #31" "Inactive,Active"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30 ,Event #30" "Inactive,Active"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29 ,Event #29" "Inactive,Active"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28 ,Event #28" "Inactive,Active"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27 ,Event #27" "Inactive,Active"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26 ,Event #26" "Inactive,Active"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25 ,Event #25" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24 ,Event #24" "Inactive,Active"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23 ,Event #23" "Inactive,Active"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22 ,Event #22" "Inactive,Active"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21 ,Event #21" "Inactive,Active"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20 ,Event #20" "Inactive,Active"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19 ,Event #19" "Inactive,Active"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18 ,Event #18" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17 ,Event #17" "Inactive,Active"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16 ,Event #16" "Inactive,Active"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15 ,Event #15" "Inactive,Active"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14 ,Event #14" "Inactive,Active"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13 ,Event #13" "Inactive,Active"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12 ,Event #12" "Inactive,Active"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11 ,Event #11" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10 ,Event #10" "Inactive,Active"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9 ,Event #9" "Inactive,Active"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8 ,Event #8" "Inactive,Active"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7 ,Event #7" "Inactive,Active"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6 ,Event #6" "Inactive,Active"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5 ,Event #5" "Inactive,Active"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4 ,Event #4" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3 ,Event #3" "Inactive,Active"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2 ,Event #2" "Inactive,Active"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1 ,Event #1" "Inactive,Active"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0 ,Event #0" "Inactive,Active"
|
|
line.long 0x04 "ERH_RN_SET/CLR,Event Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " E63 ,Event #63" "Inactive,Active"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " E62 ,Event #62" "Inactive,Active"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " E61 ,Event #61" "Inactive,Active"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " E60 ,Event #60" "Inactive,Active"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " E59 ,Event #59" "Inactive,Active"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " E58 ,Event #58" "Inactive,Active"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " E57 ,Event #57" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " E56 ,Event #56" "Inactive,Active"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " E55 ,Event #55" "Inactive,Active"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " E54 ,Event #54" "Inactive,Active"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " E53 ,Event #53" "Inactive,Active"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " E52 ,Event #52" "Inactive,Active"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " E51 ,Event #51" "Inactive,Active"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " E50 ,Event #50" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " E49 ,Event #49" "Inactive,Active"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " E48 ,Event #48" "Inactive,Active"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " E47 ,Event #47" "Inactive,Active"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " E46 ,Event #46" "Inactive,Active"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " E45 ,Event #45" "Inactive,Active"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " E44 ,Event #44" "Inactive,Active"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " E43 ,Event #43" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x44 10. 0x0C 10. " E42 ,Event #42" "Inactive,Active"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " E41 ,Event #41" "Inactive,Active"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " E40 ,Event #40" "Inactive,Active"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " E39 ,Event #39" "Inactive,Active"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " E38 ,Event #38" "Inactive,Active"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " E37 ,Event #37" "Inactive,Active"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " E36 ,Event #36" "Inactive,Active"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " E35 ,Event #35" "Inactive,Active"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " E34 ,Event #34" "Inactive,Active"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " E33 ,Event #33" "Inactive,Active"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " E32 ,Event #32" "Inactive,Active"
|
|
rgroup.long 0x2018++0x07
|
|
line.long 0x00 "CER_RN,Chained Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "Not chained,Chained"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "Not chained,Chained"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "Not chained,Chained"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "Not chained,Chained"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "Not chained,Chained"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "Not chained,Chained"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "Not chained,Chained"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "Not chained,Chained"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "Not chained,Chained"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "Not chained,Chained"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "Not chained,Chained"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "Not chained,Chained"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "Not chained,Chained"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "Not chained,Chained"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "Not chained,Chained"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "Not chained,Chained"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "Not chained,Chained"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "Not chained,Chained"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "Not chained,Chained"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "Not chained,Chained"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "Not chained,Chained"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not chained,Chained"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not chained,Chained"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not chained,Chained"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not chained,Chained"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not chained,Chained"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not chained,Chained"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not chained,Chained"
|
|
line.long 0x04 "CERH_RN,Chained Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "Not chained,Chained"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "Not chained,Chained"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "Not chained,Chained"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "Not chained,Chained"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "Not chained,Chained"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "Not chained,Chained"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "Not chained,Chained"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "Not chained,Chained"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "Not chained,Chained"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "Not chained,Chained"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "Not chained,Chained"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "Not chained,Chained"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "Not chained,Chained"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "Not chained,Chained"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "Not chained,Chained"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "Not chained,Chained"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "Not chained,Chained"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "Not chained,Chained"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "Not chained,Chained"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "Not chained,Chained"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "Not chained,Chained"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "Not chained,Chained"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "Not chained,Chained"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "Not chained,Chained"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "Not chained,Chained"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "Not chained,Chained"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "Not chained,Chained"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "Not chained,Chained"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "Not chained,Chained"
|
|
group.long 0x2020++0x07
|
|
line.long 0x00 "EER_RN_SET/CLR,Event Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31 ,Event #31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30 ,Event #30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29 ,Event #29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28 ,Event #28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27 ,Event #27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26 ,Event #26" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25 ,Event #25" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24 ,Event #24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23 ,Event #23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22 ,Event #22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21 ,Event #21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20 ,Event #20" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19 ,Event #19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18 ,Event #18" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17 ,Event #17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16 ,Event #16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15 ,Event #15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14 ,Event #14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13 ,Event #13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12 ,Event #12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11 ,Event #11" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10 ,Event #10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9 ,Event #9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8 ,Event #8" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E7 ,Event #7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E6 ,Event #6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E5 ,Event #5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E4 ,Event #4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3 ,Event #3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2 ,Event #2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1 ,Event #1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0 ,Event #0" "Disabled,Enabled"
|
|
line.long 0x04 "EERH_RN_SET/CLR,Event Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " E63 ,Event #63" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " E62 ,Event #62" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " E61 ,Event #61" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " E60 ,Event #60" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " E59 ,Event #59" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " E58 ,Event #58" "Disabled,Enabled"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " E57 ,Event #57" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " E56 ,Event #56" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " E55 ,Event #55" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " E54 ,Event #54" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " E53 ,Event #53" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " E52 ,Event #52" "Disabled,Enabled"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " E51 ,Event #51" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " E50 ,Event #50" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " E49 ,Event #49" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " E48 ,Event #48" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " E47 ,Event #47" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " E46 ,Event #46" "Disabled,Enabled"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " E45 ,Event #45" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " E44 ,Event #44" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " E43 ,Event #43" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " E42 ,Event #42" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " E41 ,Event #41" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " E40 ,Event #40" "Disabled,Enabled"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " E39 ,Event #39" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " E38 ,Event #38" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " E37 ,Event #37" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " E36 ,Event #36" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " E35 ,Event #35" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " E34 ,Event #34" "Disabled,Enabled"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " E33 ,Event #33" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " E32 ,Event #32" "Disabled,Enabled"
|
|
rgroup.long 0x2038++0x07
|
|
line.long 0x00 "SER_RN,Secondary Event Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "Not stored,Stored"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "Not stored,Stored"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "Not stored,Stored"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "Not stored,Stored"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "Not stored,Stored"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "Not stored,Stored"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "Not stored,Stored"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "Not stored,Stored"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "Not stored,Stored"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "Not stored,Stored"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "Not stored,Stored"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "Not stored,Stored"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "Not stored,Stored"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "Not stored,Stored"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "Not stored,Stored"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "Not stored,Stored"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "Not stored,Stored"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "Not stored,Stored"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "Not stored,Stored"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "Not stored,Stored"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "Not stored,Stored"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not stored,Stored"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not stored,Stored"
|
|
line.long 0x04 "SERH_RN,Secondary Event Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "Not stored,Stored"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "Not stored,Stored"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "Not stored,Stored"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "Not stored,Stored"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "Not stored,Stored"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "Not stored,Stored"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "Not stored,Stored"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "Not stored,Stored"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "Not stored,Stored"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "Not stored,Stored"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "Not stored,Stored"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "Not stored,Stored"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "Not stored,Stored"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "Not stored,Stored"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "Not stored,Stored"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "Not stored,Stored"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "Not stored,Stored"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "Not stored,Stored"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "Not stored,Stored"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "Not stored,Stored"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "Not stored,Stored"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "Not stored,Stored"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "Not stored,Stored"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "Not stored,Stored"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "Not stored,Stored"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "Not stored,Stored"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "Not stored,Stored"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "Not stored,Stored"
|
|
wgroup.long 0x2040++0x07
|
|
line.long 0x00 "SECR_RN,Secondary Event Clear Register"
|
|
bitfld.long 0x00 31. " E31 ,Event #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " E30 ,Event #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " E29 ,Event #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " E28 ,Event #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " E27 ,Event #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " E26 ,Event #26" "No effect,Clear"
|
|
bitfld.long 0x00 25. " E25 ,Event #25" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 24. " E24 ,Event #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " E23 ,Event #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " E22 ,Event #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " E21 ,Event #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " E20 ,Event #20" "No effect,Clear"
|
|
bitfld.long 0x00 19. " E19 ,Event #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " E18 ,Event #18" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 17. " E17 ,Event #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " E16 ,Event #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " E15 ,Event #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " E14 ,Event #14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " E13 ,Event #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " E12 ,Event #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " E11 ,Event #11" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 10. " E10 ,Event #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " E9 ,Event #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " E8 ,Event #8" "No effect,Clear"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
line.long 0x04 "SECRH_RN,Secondary Event Clear Register High"
|
|
bitfld.long 0x04 31. " E63 ,Event #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " E62 ,Event #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " E61 ,Event #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " E60 ,Event #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " E59 ,Event #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " E58 ,Event #58" "No effect,Clear"
|
|
bitfld.long 0x04 25. " E57 ,Event #57" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 24. " E56 ,Event #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " E55 ,Event #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " E54 ,Event #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " E53 ,Event #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " E52 ,Event #52" "No effect,Clear"
|
|
bitfld.long 0x04 19. " E51 ,Event #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " E50 ,Event #50" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 17. " E49 ,Event #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " E48 ,Event #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " E47 ,Event #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " E46 ,Event #46" "No effect,Clear"
|
|
bitfld.long 0x04 13. " E45 ,Event #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " E44 ,Event #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " E43 ,Event #43" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10. " E42 ,Event #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " E41 ,Event #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " E40 ,Event #40" "No effect,Clear"
|
|
bitfld.long 0x04 7. " E39 ,Event #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " E38 ,Event #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " E37 ,Event #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " E36 ,Event #36" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 3. " E35 ,Event #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " E34 ,Event #34" "No effect,Clear"
|
|
bitfld.long 0x04 1. " E33 ,Event #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " E32 ,Event #32" "No effect,Clear"
|
|
group.long 0x2050++0x07
|
|
line.long 0x00 "IER_RN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31 ,Interrupt associated with TCC #31" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30 ,Interrupt associated with TCC #30" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29 ,Interrupt associated with TCC #29" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28 ,Interrupt associated with TCC #28" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27 ,Interrupt associated with TCC #27" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26 ,Interrupt associated with TCC #26" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25 ,Interrupt associated with TCC #25" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24 ,Interrupt associated with TCC #24" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23 ,Interrupt associated with TCC #23" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22 ,Interrupt associated with TCC #22" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21 ,Interrupt associated with TCC #21" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20 ,Interrupt associated with TCC #20" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19 ,Interrupt associated with TCC #19" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18 ,Interrupt associated with TCC #18" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17 ,Interrupt associated with TCC #17" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16 ,Interrupt associated with TCC #16" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15 ,Interrupt associated with TCC #15" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14 ,Interrupt associated with TCC #14" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13 ,Interrupt associated with TCC #13" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12 ,Interrupt associated with TCC #12" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11 ,Interrupt associated with TCC #11" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10 ,Interrupt associated with TCC #10" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9 ,Interrupt associated with TCC #9" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8 ,Interrupt associated with TCC #8" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I7 ,Interrupt associated with TCC #7" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I6 ,Interrupt associated with TCC #6" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I5 ,Interrupt associated with TCC #5" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I4 ,Interrupt associated with TCC #4" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3 ,Interrupt associated with TCC #3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2 ,Interrupt associated with TCC #2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1 ,Interrupt associated with TCC #1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0 ,Interrupt associated with TCC #0" "No interrupt,Interrupt"
|
|
line.long 0x04 "IERH_RN_SET/CLR,Interrupt Enable Register High"
|
|
setclrfld.long 0x04 31. 0x14 31. 0x0C 31. " I63 ,Interrupt associated with TCC #63" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 30. 0x14 30. 0x0C 30. " I62 ,Interrupt associated with TCC #62" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 29. 0x14 29. 0x0C 29. " I61 ,Interrupt associated with TCC #61" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 28. 0x14 28. 0x0C 28. " I60 ,Interrupt associated with TCC #60" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 27. 0x14 27. 0x0C 27. " I59 ,Interrupt associated with TCC #59" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 26. 0x14 26. 0x0C 26. " I58 ,Interrupt associated with TCC #58" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 25. 0x14 25. 0x0C 25. " I57 ,Interrupt associated with TCC #57" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 24. 0x14 24. 0x0C 24. " I56 ,Interrupt associated with TCC #56" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 23. 0x14 23. 0x0C 23. " I55 ,Interrupt associated with TCC #55" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 22. 0x14 22. 0x0C 22. " I54 ,Interrupt associated with TCC #54" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 21. 0x14 21. 0x0C 21. " I53 ,Interrupt associated with TCC #53" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 20. 0x14 20. 0x0C 20. " I52 ,Interrupt associated with TCC #52" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 19. 0x14 19. 0x0C 19. " I51 ,Interrupt associated with TCC #51" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 18. 0x14 18. 0x0C 18. " I50 ,Interrupt associated with TCC #50" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 17. 0x14 17. 0x0C 17. " I49 ,Interrupt associated with TCC #49" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 16. 0x14 16. 0x0C 16. " I48 ,Interrupt associated with TCC #48" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 15. 0x14 15. 0x0C 15. " I47 ,Interrupt associated with TCC #47" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 14. 0x14 14. 0x0C 14. " I46 ,Interrupt associated with TCC #46" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 13. 0x14 13. 0x0C 13. " I45 ,Interrupt associated with TCC #45" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 12. 0x14 12. 0x0C 12. " I44 ,Interrupt associated with TCC #44" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 11. 0x14 11. 0x0C 11. " I43 ,Interrupt associated with TCC #43" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 10. 0x14 10. 0x0C 10. " I42 ,Interrupt associated with TCC #42" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 9. 0x14 9. 0x0C 9. " I41 ,Interrupt associated with TCC #41" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 8. 0x14 8. 0x0C 8. " I40 ,Interrupt associated with TCC #40" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 7. 0x14 7. 0x0C 7. " I39 ,Interrupt associated with TCC #39" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 6. 0x14 6. 0x0C 6. " I38 ,Interrupt associated with TCC #38" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 5. 0x14 5. 0x0C 5. " I37 ,Interrupt associated with TCC #37" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 4. 0x14 4. 0x0C 4. " I36 ,Interrupt associated with TCC #36" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x04 3. 0x14 3. 0x0C 3. " I35 ,Interrupt associated with TCC #35" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 2. 0x14 2. 0x0C 2. " I34 ,Interrupt associated with TCC #34" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 1. 0x14 1. 0x0C 1. " I33 ,Interrupt associated with TCC #33" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 0. 0x14 0. 0x0C 0. " I32 ,Interrupt associated with TCC #32" "No interrupt,Interrupt"
|
|
rgroup.long 0x2068++0x07
|
|
line.long 0x00 "IPR_RN,Interrupt Pending Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt associated with TCC #31" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt associated with TCC #30" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " I29 ,Interrupt associated with TCC #29" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt associated with TCC #28" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 27. " I27 ,Interrupt associated with TCC #27" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt associated with TCC #26" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 25. " I25 ,Interrupt associated with TCC #25" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 24. " I24 ,Interrupt associated with TCC #24" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 23. " I23 ,Interrupt associated with TCC #23" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt associated with TCC #22" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " I21 ,Interrupt associated with TCC #21" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt associated with TCC #20" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " I19 ,Interrupt associated with TCC #19" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt associated with TCC #18" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 17. " I17 ,Interrupt associated with TCC #17" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt associated with TCC #16" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " I15 ,Interrupt associated with TCC #15" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt associated with TCC #14" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " I13 ,Interrupt associated with TCC #13" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt associated with TCC #12" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 11. " I11 ,Interrupt associated with TCC #11" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. " I10 ,Interrupt associated with TCC #10" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " I9 ,Interrupt associated with TCC #9" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt associated with TCC #8" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 7. " I7 ,Interrupt associated with TCC #7" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt associated with TCC #6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " I5 ,Interrupt associated with TCC #5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt associated with TCC #4" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " I3 ,Interrupt associated with TCC #3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt associated with TCC #2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " I1 ,Interrupt associated with TCC #1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt associated with TCC #0" "No interrupt,Interrupt"
|
|
line.long 0x04 "IPRH_RN,Interrupt Pending Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt associated with TCC #63" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt associated with TCC #62" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 29. " I61 ,Interrupt associated with TCC #61" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt associated with TCC #60" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 27. " I59 ,Interrupt associated with TCC #59" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt associated with TCC #58" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 25. " I57 ,Interrupt associated with TCC #57" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 24. " I56 ,Interrupt associated with TCC #56" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 23. " I55 ,Interrupt associated with TCC #55" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt associated with TCC #54" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 21. " I53 ,Interrupt associated with TCC #53" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt associated with TCC #52" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 19. " I51 ,Interrupt associated with TCC #51" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt associated with TCC #50" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 17. " I49 ,Interrupt associated with TCC #49" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt associated with TCC #48" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 15. " I47 ,Interrupt associated with TCC #47" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt associated with TCC #46" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " I45 ,Interrupt associated with TCC #45" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt associated with TCC #44" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 11. " I43 ,Interrupt associated with TCC #43" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 10. " I42 ,Interrupt associated with TCC #42" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " I41 ,Interrupt associated with TCC #41" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt associated with TCC #40" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " I39 ,Interrupt associated with TCC #39" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt associated with TCC #38" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " I37 ,Interrupt associated with TCC #37" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt associated with TCC #36" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x04 3. " I35 ,Interrupt associated with TCC #35" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt associated with TCC #34" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " I33 ,Interrupt associated with TCC #33" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt associated with TCC #32" "No interrupt,Interrupt"
|
|
wgroup.long 0x2070++0x0B
|
|
line.long 0x00 "ICR_RN,Interrupt Clear Register"
|
|
bitfld.long 0x00 31. " I31 ,Interrupt associated with TCC #31" "No effect,Clear"
|
|
bitfld.long 0x00 30. " I30 ,Interrupt associated with TCC #30" "No effect,Clear"
|
|
bitfld.long 0x00 29. " I29 ,Interrupt associated with TCC #29" "No effect,Clear"
|
|
bitfld.long 0x00 28. " I28 ,Interrupt associated with TCC #28" "No effect,Clear"
|
|
bitfld.long 0x00 27. " I27 ,Interrupt associated with TCC #27" "No effect,Clear"
|
|
bitfld.long 0x00 26. " I26 ,Interrupt associated with TCC #26" "No effect,Clear"
|
|
bitfld.long 0x00 25. " I25 ,Interrupt associated with TCC #25" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 24. " I24 ,Interrupt associated with TCC #24" "No effect,Clear"
|
|
bitfld.long 0x00 23. " I23 ,Interrupt associated with TCC #23" "No effect,Clear"
|
|
bitfld.long 0x00 22. " I22 ,Interrupt associated with TCC #22" "No effect,Clear"
|
|
bitfld.long 0x00 21. " I21 ,Interrupt associated with TCC #21" "No effect,Clear"
|
|
bitfld.long 0x00 20. " I20 ,Interrupt associated with TCC #20" "No effect,Clear"
|
|
bitfld.long 0x00 19. " I19 ,Interrupt associated with TCC #19" "No effect,Clear"
|
|
bitfld.long 0x00 18. " I18 ,Interrupt associated with TCC #18" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 17. " I17 ,Interrupt associated with TCC #17" "No effect,Clear"
|
|
bitfld.long 0x00 16. " I16 ,Interrupt associated with TCC #16" "No effect,Clear"
|
|
bitfld.long 0x00 15. " I15 ,Interrupt associated with TCC #15" "No effect,Clear"
|
|
bitfld.long 0x00 14. " I14 ,Interrupt associated with TCC #14" "No effect,Clear"
|
|
bitfld.long 0x00 13. " I13 ,Interrupt associated with TCC #13" "No effect,Clear"
|
|
bitfld.long 0x00 12. " I12 ,Interrupt associated with TCC #12" "No effect,Clear"
|
|
bitfld.long 0x00 11. " I11 ,Interrupt associated with TCC #11" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 10. " I10 ,Interrupt associated with TCC #10" "No effect,Clear"
|
|
bitfld.long 0x00 9. " I9 ,Interrupt associated with TCC #9" "No effect,Clear"
|
|
bitfld.long 0x00 8. " I8 ,Interrupt associated with TCC #8" "No effect,Clear"
|
|
bitfld.long 0x00 7. " I7 ,Interrupt associated with TCC #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " I6 ,Interrupt associated with TCC #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " I5 ,Interrupt associated with TCC #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " I4 ,Interrupt associated with TCC #4" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " I3 ,Interrupt associated with TCC #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " I2 ,Interrupt associated with TCC #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " I1 ,Interrupt associated with TCC #1" "No effect,Clear"
|
|
bitfld.long 0x00 0. " I0 ,Interrupt associated with TCC #0" "No effect,Clear"
|
|
line.long 0x04 "ICRH_RN,Interrupt Clear Register High"
|
|
bitfld.long 0x04 31. " I63 ,Interrupt associated with TCC #63" "No effect,Clear"
|
|
bitfld.long 0x04 30. " I62 ,Interrupt associated with TCC #62" "No effect,Clear"
|
|
bitfld.long 0x04 29. " I61 ,Interrupt associated with TCC #61" "No effect,Clear"
|
|
bitfld.long 0x04 28. " I60 ,Interrupt associated with TCC #60" "No effect,Clear"
|
|
bitfld.long 0x04 27. " I59 ,Interrupt associated with TCC #59" "No effect,Clear"
|
|
bitfld.long 0x04 26. " I58 ,Interrupt associated with TCC #58" "No effect,Clear"
|
|
bitfld.long 0x04 25. " I57 ,Interrupt associated with TCC #57" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 24. " I56 ,Interrupt associated with TCC #56" "No effect,Clear"
|
|
bitfld.long 0x04 23. " I55 ,Interrupt associated with TCC #55" "No effect,Clear"
|
|
bitfld.long 0x04 22. " I54 ,Interrupt associated with TCC #54" "No effect,Clear"
|
|
bitfld.long 0x04 21. " I53 ,Interrupt associated with TCC #53" "No effect,Clear"
|
|
bitfld.long 0x04 20. " I52 ,Interrupt associated with TCC #52" "No effect,Clear"
|
|
bitfld.long 0x04 19. " I51 ,Interrupt associated with TCC #51" "No effect,Clear"
|
|
bitfld.long 0x04 18. " I50 ,Interrupt associated with TCC #50" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 17. " I49 ,Interrupt associated with TCC #49" "No effect,Clear"
|
|
bitfld.long 0x04 16. " I48 ,Interrupt associated with TCC #48" "No effect,Clear"
|
|
bitfld.long 0x04 15. " I47 ,Interrupt associated with TCC #47" "No effect,Clear"
|
|
bitfld.long 0x04 14. " I46 ,Interrupt associated with TCC #46" "No effect,Clear"
|
|
bitfld.long 0x04 13. " I45 ,Interrupt associated with TCC #45" "No effect,Clear"
|
|
bitfld.long 0x04 12. " I44 ,Interrupt associated with TCC #44" "No effect,Clear"
|
|
bitfld.long 0x04 11. " I43 ,Interrupt associated with TCC #43" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 10. " I42 ,Interrupt associated with TCC #42" "No effect,Clear"
|
|
bitfld.long 0x04 9. " I41 ,Interrupt associated with TCC #41" "No effect,Clear"
|
|
bitfld.long 0x04 8. " I40 ,Interrupt associated with TCC #40" "No effect,Clear"
|
|
bitfld.long 0x04 7. " I39 ,Interrupt associated with TCC #39" "No effect,Clear"
|
|
bitfld.long 0x04 6. " I38 ,Interrupt associated with TCC #38" "No effect,Clear"
|
|
bitfld.long 0x04 5. " I37 ,Interrupt associated with TCC #37" "No effect,Clear"
|
|
bitfld.long 0x04 4. " I36 ,Interrupt associated with TCC #36" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x04 3. " I35 ,Interrupt associated with TCC #35" "No effect,Clear"
|
|
bitfld.long 0x04 2. " I34 ,Interrupt associated with TCC #34" "No effect,Clear"
|
|
bitfld.long 0x04 1. " I33 ,Interrupt associated with TCC #33" "No effect,Clear"
|
|
bitfld.long 0x04 0. " I32 ,Interrupt associated with TCC #32" "No effect,Clear"
|
|
line.long 0x08 "IEVAL_RN,Interrupt EVAL Register"
|
|
bitfld.long 0x08 1. " SET ,Interrupt set" "Not set,Set"
|
|
bitfld.long 0x08 0. " EVAL ,Interrupt evaluate" "Not set,Set"
|
|
rgroup.long 0x2080++0x07
|
|
line.long 0x00 "QER_RN,QDMA Event Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not occurred,Occurred"
|
|
line.long 0x04 "QEER_RN,QDMA Event Enable Register"
|
|
bitfld.long 0x04 7. " E7 ,Event #7" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " E6 ,Event #6" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " E5 ,Event #5" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " E4 ,Event #4" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " E3 ,Event #3" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " E2 ,Event #2" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " E1 ,Event #1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " E0 ,Event #0" "Disabled,Enabled"
|
|
wgroup.long 0x2088++0x07
|
|
line.long 0x00 "QEECR_RN,QDMA Event Enable Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
line.long 0x04 "QEESR_RN,QDMA Event Enable Set Register"
|
|
bitfld.long 0x04 7. " E7 ,Event #7" "Not set,Set"
|
|
bitfld.long 0x04 6. " E6 ,Event #6" "Not set,Set"
|
|
bitfld.long 0x04 5. " E5 ,Event #5" "Not set,Set"
|
|
bitfld.long 0x04 4. " E4 ,Event #4" "Not set,Set"
|
|
bitfld.long 0x04 3. " E3 ,Event #3" "Not set,Set"
|
|
bitfld.long 0x04 2. " E2 ,Event #2" "Not set,Set"
|
|
bitfld.long 0x04 1. " E1 ,Event #1" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x04 0. " E0 ,Event #0" "Not set,Set"
|
|
rgroup.long 0x2090++0x03
|
|
line.long 0x00 "QSER_RN,QDMA Secondary Event Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "Not stored,Stored"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "Not stored,Stored"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "Not stored,Stored"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "Not stored,Stored"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "Not stored,Stored"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "Not stored,Stored"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "Not stored,Stored"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "Not stored,Stored"
|
|
wgroup.long 0x2094++0x03
|
|
line.long 0x00 "QSECR_RN,QDMA Secondary Event Clear Register"
|
|
bitfld.long 0x00 7. " E7 ,Event #7" "No effect,Clear"
|
|
bitfld.long 0x00 6. " E6 ,Event #6" "No effect,Clear"
|
|
bitfld.long 0x00 5. " E5 ,Event #5" "No effect,Clear"
|
|
bitfld.long 0x00 4. " E4 ,Event #4" "No effect,Clear"
|
|
bitfld.long 0x00 3. " E3 ,Event #3" "No effect,Clear"
|
|
bitfld.long 0x00 2. " E2 ,Event #2" "No effect,Clear"
|
|
bitfld.long 0x00 1. " E1 ,Event #1" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 0. " E0 ,Event #0" "No effect,Clear"
|
|
width 7.
|
|
newline
|
|
group.long 0x4000++0x1F
|
|
line.long 0x00 "OPT,Options Parameter Register"
|
|
rbitfld.long 0x00 31. " PRIV ,Privilege level" "User,Supervisor"
|
|
rbitfld.long 0x00 24.--27. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " WIMODE ,Backward compatibility mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal,Early"
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " STATIC ,Static entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-sync,Ab-sync"
|
|
newline
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
line.long 0x04 "SRC,Source Address Register"
|
|
line.long 0x08 "ABCNT,A And B Byte Count Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " BCNT ,BCNT"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNT ,ACNT"
|
|
line.long 0x0C "DST,Destination Address Register"
|
|
line.long 0x10 "BIDX,BIDX"
|
|
hexmask.long.word 0x10 16.--31. 1. " DBIDX ,Destination 2nd dimension index"
|
|
hexmask.long.word 0x10 0.--15. 1. " SBIDX ,Source 2nd dimension index"
|
|
line.long 0x14 "LNK,Link And Reload Parameters Register"
|
|
hexmask.long.word 0x14 16.--31. 1. " BCNTRLD ,BCNT reload"
|
|
hexmask.long.word 0x14 0.--15. 0x01 " LINK ,Link address"
|
|
line.long 0x18 "CIDX,CIDX"
|
|
hexmask.long.word 0x18 16.--31. 1. " DCIDX ,Destination frame index"
|
|
hexmask.long.word 0x18 0.--15. 1. " SCIDX ,Source frame index"
|
|
line.long 0x1C "CCNT,C Byte Count"
|
|
hexmask.long.word 0x1C 0.--15. 1. " CCNT ,Count for 3rd dimension"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "TPTC"
|
|
tree "TPTC0"
|
|
base ad:0x02000000
|
|
width 17.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "PID,Peripheral ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major revision"
|
|
hexmask.long.byte 0x00 6.--7. 1. " CUSTOM ,Custom revision field"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision"
|
|
line.long 0x04 "TCCFG,TC Configuration Register"
|
|
bitfld.long 0x04 8.--9. " DREGDEPTH ,DST register FIFO depth parametrization" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parametrization" "0,1,2,3"
|
|
bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size parametrization" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "TCSTAT,TC Status Register"
|
|
bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3"
|
|
bitfld.long 0x00 8. " ACTV ,Channel active" "Idle,Busy"
|
|
bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,pending"
|
|
bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy"
|
|
bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "INT_SET/CLR,Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " TRDONE ,TR done event status" "Not detected,Detected"
|
|
setclrfld.long 0x00 0. 0x04 1. 0x08 1. " PROGEMPTY ,Program set empty event status" "Not detected,Detected"
|
|
wgroup.long 0x110++0x03
|
|
line.long 0x00 "INTCMD,Interrupt Command Register"
|
|
bitfld.long 0x00 1. " SET ,Set TPTC interrupt" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Evaluate state of TPTC interrupt" "Not set,Set"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "ERRSTAT_SET/CLR,Error Status Register"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " MMRAERR ,MMR address error" "No error,Error"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TRERR ,TR error" "No error,Error"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " BUSERR ,Bus error event" "No error,Error"
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "ERRDET,Error Details Register"
|
|
bitfld.long 0x00 17. " TCCHEN ,Error of OPT.TCCHEN value" "No error,Error"
|
|
bitfld.long 0x00 16. " TCINTEN ,Error of OPT.TCINTEN" "No error,Error"
|
|
bitfld.long 0x00 8.--13. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " STAT ,Transaction status" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
wgroup.long 0x130++0x03
|
|
line.long 0x00 "ERRCMD,Error Command Register"
|
|
bitfld.long 0x00 1. " SET ,Set TPTC interrupt" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Evaluate state of TPTC interrupt" "Not set,Set"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "RDRATE,Read Rate Register"
|
|
bitfld.long 0x00 0.--2. " RDRATE ,Read rate control" "0,1,2,3,4,5,6,7"
|
|
if (((per.l(ad:0x02000000+0x200)&0x03)==(0x01||0x02)))
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "POPT,Program Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "POPT,Program Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
group.long 0x204++0x0F
|
|
line.long 0x00 "PSRC,Program Set Source Address Register"
|
|
line.long 0x04 "PCNT,Program Set Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A-dimension count"
|
|
line.long 0x08 "PDST,Program Set Destination Address Register"
|
|
line.long 0x0C "PBIDX,Program Set B-Dim Idx Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "PMPPRXY,Program Set Memory Protect Proxy Register"
|
|
bitfld.long 0x00 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x00 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x00 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x02000000+0x240)&0x03)==(0x01||0x02)))
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "SAOPT,Source Active Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "SAOPT,Source Active Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
rgroup.long 0x244++0x07
|
|
line.long 0x00 "SASRC,Source Active Set Source Address Register"
|
|
line.long 0x04 "SACNT,Source Active Set Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A-dimension count"
|
|
rgroup.long 0x250++0x0F
|
|
line.long 0x00 "SABIDX,Source Active Set B-Dim Idx Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x00 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
line.long 0x04 "SAMPPRXY,Source Active Set Memory Protect Proxy Register"
|
|
bitfld.long 0x04 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x04 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x04 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "SACNTRLD,Source Active Set Count Reload Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNTRLD ,A-CNT reload value for source active register set"
|
|
line.long 0x0C "SASRCBREF,Source Active Set Source Address A-Reference Register"
|
|
rgroup.long 0x280++0x03
|
|
line.long 0x00 "DFCNTRLD,Destination FIFO Set Count Reload Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-CNT reload value for source active register set"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
rgroup.long 0x284++0x03
|
|
line.long 0x00 "DFSRCBREF,DFSRCBREF"
|
|
endif
|
|
if (((per.l(ad:0x02000000+0x300)&0x03)==(0x01||0x02)))
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "DFOPT,Destination FIFO Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "DFOPT,Destination FIFO Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "DFSRC,DFSRC"
|
|
endif
|
|
rgroup.long 0x308++0x0F
|
|
line.long 0x00 "DFCNT,Destination FIFO Set Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
|
|
line.long 0x04 "DFDST,Destination FIFO Set Destination Address"
|
|
line.long 0x08 "DFBIDX,Destination FIFO Set B-Dim Idx Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
line.long 0x0C "DFMPPRXY,Destination FIFO Memory Protect Proxy Register"
|
|
bitfld.long 0x0C 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TPTC1"
|
|
base ad:0x02000800
|
|
width 17.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "PID,Peripheral ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major revision"
|
|
hexmask.long.byte 0x00 6.--7. 1. " CUSTOM ,Custom revision field"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision"
|
|
line.long 0x04 "TCCFG,TC Configuration Register"
|
|
bitfld.long 0x04 8.--9. " DREGDEPTH ,DST register FIFO depth parametrization" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parametrization" "0,1,2,3"
|
|
bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size parametrization" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "TCSTAT,TC Status Register"
|
|
bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3"
|
|
bitfld.long 0x00 8. " ACTV ,Channel active" "Idle,Busy"
|
|
bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,pending"
|
|
bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy"
|
|
bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "INT_SET/CLR,Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " TRDONE ,TR done event status" "Not detected,Detected"
|
|
setclrfld.long 0x00 0. 0x04 1. 0x08 1. " PROGEMPTY ,Program set empty event status" "Not detected,Detected"
|
|
wgroup.long 0x110++0x03
|
|
line.long 0x00 "INTCMD,Interrupt Command Register"
|
|
bitfld.long 0x00 1. " SET ,Set TPTC interrupt" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Evaluate state of TPTC interrupt" "Not set,Set"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "ERRSTAT_SET/CLR,Error Status Register"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " MMRAERR ,MMR address error" "No error,Error"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TRERR ,TR error" "No error,Error"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " BUSERR ,Bus error event" "No error,Error"
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "ERRDET,Error Details Register"
|
|
bitfld.long 0x00 17. " TCCHEN ,Error of OPT.TCCHEN value" "No error,Error"
|
|
bitfld.long 0x00 16. " TCINTEN ,Error of OPT.TCINTEN" "No error,Error"
|
|
bitfld.long 0x00 8.--13. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " STAT ,Transaction status" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
wgroup.long 0x130++0x03
|
|
line.long 0x00 "ERRCMD,Error Command Register"
|
|
bitfld.long 0x00 1. " SET ,Set TPTC interrupt" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Evaluate state of TPTC interrupt" "Not set,Set"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "RDRATE,Read Rate Register"
|
|
bitfld.long 0x00 0.--2. " RDRATE ,Read rate control" "0,1,2,3,4,5,6,7"
|
|
if (((per.l(ad:0x02000800+0x200)&0x03)==(0x01||0x02)))
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "POPT,Program Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "POPT,Program Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
group.long 0x204++0x0F
|
|
line.long 0x00 "PSRC,Program Set Source Address Register"
|
|
line.long 0x04 "PCNT,Program Set Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A-dimension count"
|
|
line.long 0x08 "PDST,Program Set Destination Address Register"
|
|
line.long 0x0C "PBIDX,Program Set B-Dim Idx Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "PMPPRXY,Program Set Memory Protect Proxy Register"
|
|
bitfld.long 0x00 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x00 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x00 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x02000800+0x240)&0x03)==(0x01||0x02)))
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "SAOPT,Source Active Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "SAOPT,Source Active Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
rgroup.long 0x244++0x07
|
|
line.long 0x00 "SASRC,Source Active Set Source Address Register"
|
|
line.long 0x04 "SACNT,Source Active Set Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A-dimension count"
|
|
rgroup.long 0x250++0x0F
|
|
line.long 0x00 "SABIDX,Source Active Set B-Dim Idx Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x00 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
line.long 0x04 "SAMPPRXY,Source Active Set Memory Protect Proxy Register"
|
|
bitfld.long 0x04 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x04 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x04 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "SACNTRLD,Source Active Set Count Reload Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNTRLD ,A-CNT reload value for source active register set"
|
|
line.long 0x0C "SASRCBREF,Source Active Set Source Address A-Reference Register"
|
|
rgroup.long 0x280++0x03
|
|
line.long 0x00 "DFCNTRLD,Destination FIFO Set Count Reload Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-CNT reload value for source active register set"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
rgroup.long 0x284++0x03
|
|
line.long 0x00 "DFSRCBREF,DFSRCBREF"
|
|
endif
|
|
if (((per.l(ad:0x02000800+0x300)&0x03)==(0x01||0x02)))
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "DFOPT,Destination FIFO Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "DFOPT,Destination FIFO Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "DFSRC,DFSRC"
|
|
endif
|
|
rgroup.long 0x308++0x0F
|
|
line.long 0x00 "DFCNT,Destination FIFO Set Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
|
|
line.long 0x04 "DFDST,Destination FIFO Set Destination Address"
|
|
line.long 0x08 "DFBIDX,Destination FIFO Set B-Dim Idx Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
line.long 0x0C "DFMPPRXY,Destination FIFO Memory Protect Proxy Register"
|
|
bitfld.long 0x0C 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TPTC2"
|
|
base ad:0x02090000
|
|
width 17.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "PID,Peripheral ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major revision"
|
|
hexmask.long.byte 0x00 6.--7. 1. " CUSTOM ,Custom revision field"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision"
|
|
line.long 0x04 "TCCFG,TC Configuration Register"
|
|
bitfld.long 0x04 8.--9. " DREGDEPTH ,DST register FIFO depth parametrization" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parametrization" "0,1,2,3"
|
|
bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size parametrization" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "TCSTAT,TC Status Register"
|
|
bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3"
|
|
bitfld.long 0x00 8. " ACTV ,Channel active" "Idle,Busy"
|
|
bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,pending"
|
|
bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy"
|
|
bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "INT_SET/CLR,Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " TRDONE ,TR done event status" "Not detected,Detected"
|
|
setclrfld.long 0x00 0. 0x04 1. 0x08 1. " PROGEMPTY ,Program set empty event status" "Not detected,Detected"
|
|
wgroup.long 0x110++0x03
|
|
line.long 0x00 "INTCMD,Interrupt Command Register"
|
|
bitfld.long 0x00 1. " SET ,Set TPTC interrupt" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Evaluate state of TPTC interrupt" "Not set,Set"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "ERRSTAT_SET/CLR,Error Status Register"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " MMRAERR ,MMR address error" "No error,Error"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TRERR ,TR error" "No error,Error"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " BUSERR ,Bus error event" "No error,Error"
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "ERRDET,Error Details Register"
|
|
bitfld.long 0x00 17. " TCCHEN ,Error of OPT.TCCHEN value" "No error,Error"
|
|
bitfld.long 0x00 16. " TCINTEN ,Error of OPT.TCINTEN" "No error,Error"
|
|
bitfld.long 0x00 8.--13. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " STAT ,Transaction status" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
wgroup.long 0x130++0x03
|
|
line.long 0x00 "ERRCMD,Error Command Register"
|
|
bitfld.long 0x00 1. " SET ,Set TPTC interrupt" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Evaluate state of TPTC interrupt" "Not set,Set"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "RDRATE,Read Rate Register"
|
|
bitfld.long 0x00 0.--2. " RDRATE ,Read rate control" "0,1,2,3,4,5,6,7"
|
|
if (((per.l(ad:0x02090000+0x200)&0x03)==(0x01||0x02)))
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "POPT,Program Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "POPT,Program Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
group.long 0x204++0x0F
|
|
line.long 0x00 "PSRC,Program Set Source Address Register"
|
|
line.long 0x04 "PCNT,Program Set Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A-dimension count"
|
|
line.long 0x08 "PDST,Program Set Destination Address Register"
|
|
line.long 0x0C "PBIDX,Program Set B-Dim Idx Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "PMPPRXY,Program Set Memory Protect Proxy Register"
|
|
bitfld.long 0x00 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x00 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x00 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x02090000+0x240)&0x03)==(0x01||0x02)))
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "SAOPT,Source Active Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "SAOPT,Source Active Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
rgroup.long 0x244++0x07
|
|
line.long 0x00 "SASRC,Source Active Set Source Address Register"
|
|
line.long 0x04 "SACNT,Source Active Set Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A-dimension count"
|
|
rgroup.long 0x250++0x0F
|
|
line.long 0x00 "SABIDX,Source Active Set B-Dim Idx Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x00 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
line.long 0x04 "SAMPPRXY,Source Active Set Memory Protect Proxy Register"
|
|
bitfld.long 0x04 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x04 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x04 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "SACNTRLD,Source Active Set Count Reload Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNTRLD ,A-CNT reload value for source active register set"
|
|
line.long 0x0C "SASRCBREF,Source Active Set Source Address A-Reference Register"
|
|
rgroup.long 0x280++0x03
|
|
line.long 0x00 "DFCNTRLD,Destination FIFO Set Count Reload Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-CNT reload value for source active register set"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
rgroup.long 0x284++0x03
|
|
line.long 0x00 "DFSRCBREF,DFSRCBREF"
|
|
endif
|
|
if (((per.l(ad:0x02090000+0x300)&0x03)==(0x01||0x02)))
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "DFOPT,Destination FIFO Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "DFOPT,Destination FIFO Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "DFSRC,DFSRC"
|
|
endif
|
|
rgroup.long 0x308++0x0F
|
|
line.long 0x00 "DFCNT,Destination FIFO Set Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
|
|
line.long 0x04 "DFDST,Destination FIFO Set Destination Address"
|
|
line.long 0x08 "DFBIDX,Destination FIFO Set B-Dim Idx Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
line.long 0x0C "DFMPPRXY,Destination FIFO Memory Protect Proxy Register"
|
|
bitfld.long 0x0C 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TPTC3"
|
|
base ad:0x02090400
|
|
width 17.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "PID,Peripheral ID Register"
|
|
bitfld.long 0x00 30.--31. " SCHEME ,PID scheme" "0,1,2,3"
|
|
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family"
|
|
bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major revision"
|
|
hexmask.long.byte 0x00 6.--7. 1. " CUSTOM ,Custom revision field"
|
|
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor revision"
|
|
line.long 0x04 "TCCFG,TC Configuration Register"
|
|
bitfld.long 0x04 8.--9. " DREGDEPTH ,DST register FIFO depth parametrization" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parametrization" "0,1,2,3"
|
|
bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size parametrization" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "TCSTAT,TC Status Register"
|
|
bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3"
|
|
bitfld.long 0x00 8. " ACTV ,Channel active" "Idle,Busy"
|
|
bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pending,pending"
|
|
bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy"
|
|
bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle,Busy"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "INT_SET/CLR,Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " TRDONE ,TR done event status" "Not detected,Detected"
|
|
setclrfld.long 0x00 0. 0x04 1. 0x08 1. " PROGEMPTY ,Program set empty event status" "Not detected,Detected"
|
|
wgroup.long 0x110++0x03
|
|
line.long 0x00 "INTCMD,Interrupt Command Register"
|
|
bitfld.long 0x00 1. " SET ,Set TPTC interrupt" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Evaluate state of TPTC interrupt" "Not set,Set"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "ERRSTAT_SET/CLR,Error Status Register"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " MMRAERR ,MMR address error" "No error,Error"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TRERR ,TR error" "No error,Error"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " BUSERR ,Bus error event" "No error,Error"
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "ERRDET,Error Details Register"
|
|
bitfld.long 0x00 17. " TCCHEN ,Error of OPT.TCCHEN value" "No error,Error"
|
|
bitfld.long 0x00 16. " TCINTEN ,Error of OPT.TCINTEN" "No error,Error"
|
|
bitfld.long 0x00 8.--13. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " STAT ,Transaction status" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
wgroup.long 0x130++0x03
|
|
line.long 0x00 "ERRCMD,Error Command Register"
|
|
bitfld.long 0x00 1. " SET ,Set TPTC interrupt" "Not set,Set"
|
|
bitfld.long 0x00 0. " EVAL ,Evaluate state of TPTC interrupt" "Not set,Set"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "RDRATE,Read Rate Register"
|
|
bitfld.long 0x00 0.--2. " RDRATE ,Read rate control" "0,1,2,3,4,5,6,7"
|
|
if (((per.l(ad:0x02090400+0x200)&0x03)==(0x01||0x02)))
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "POPT,Program Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "POPT,Program Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
group.long 0x204++0x0F
|
|
line.long 0x00 "PSRC,Program Set Source Address Register"
|
|
line.long 0x04 "PCNT,Program Set Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A-dimension count"
|
|
line.long 0x08 "PDST,Program Set Destination Address Register"
|
|
line.long 0x0C "PBIDX,Program Set B-Dim Idx Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "PMPPRXY,Program Set Memory Protect Proxy Register"
|
|
bitfld.long 0x00 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x00 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x00 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x02090400+0x240)&0x03)==(0x01||0x02)))
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "SAOPT,Source Active Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "SAOPT,Source Active Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
rgroup.long 0x244++0x07
|
|
line.long 0x00 "SASRC,Source Active Set Source Address Register"
|
|
line.long 0x04 "SACNT,Source Active Set Count Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A-dimension count"
|
|
rgroup.long 0x250++0x0F
|
|
line.long 0x00 "SABIDX,Source Active Set B-Dim Idx Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x00 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
line.long 0x04 "SAMPPRXY,Source Active Set Memory Protect Proxy Register"
|
|
bitfld.long 0x04 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x04 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x04 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "SACNTRLD,Source Active Set Count Reload Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " ACNTRLD ,A-CNT reload value for source active register set"
|
|
line.long 0x0C "SASRCBREF,Source Active Set Source Address A-Reference Register"
|
|
rgroup.long 0x280++0x03
|
|
line.long 0x00 "DFCNTRLD,Destination FIFO Set Count Reload Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-CNT reload value for source active register set"
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
rgroup.long 0x284++0x03
|
|
line.long 0x00 "DFSRCBREF,DFSRCBREF"
|
|
endif
|
|
if (((per.l(ad:0x02090400+0x300)&0x03)==(0x01||0x02)))
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "DFOPT,Destination FIFO Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " FWID ,FIFO width control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
else
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "DFOPT,Destination FIFO Set Options Register"
|
|
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--17. " TCC ,Transfer complete code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
|
|
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,FIFO"
|
|
newline
|
|
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,FIFO"
|
|
endif
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "DFSRC,DFSRC"
|
|
endif
|
|
rgroup.long 0x308++0x0F
|
|
line.long 0x00 "DFCNT,Destination FIFO Set Count Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
|
|
line.long 0x04 "DFDST,Destination FIFO Set Destination Address"
|
|
line.long 0x08 "DFBIDX,Destination FIFO Set B-Dim Idx Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,DEST B-IDX for program register set"
|
|
hexmask.long.word 0x08 0.--15. 1. " SBIDX ,Source B-IDX for program register set"
|
|
line.long 0x0C "DFMPPRXY,Destination FIFO Memory Protect Proxy Register"
|
|
bitfld.long 0x0C 9. " SECURE ,Secure level" "Non-secure,Secure"
|
|
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User,Supervisor"
|
|
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree.open "RTI (Real Time Interrupt)"
|
|
tree "RTI1"
|
|
base ad:0x02020000
|
|
width 19.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "RTIGCTRL,RTI Global Control Register"
|
|
bitfld.long 0x00 16.--19. " NTUSEL ,Select NTU signal" "NTU0,,,,,NTU1,,,,,NTU2,,,,,NTU3"
|
|
bitfld.long 0x00 15. " COS ,Continue on suspend" "Stopped,Running"
|
|
bitfld.long 0x00 1. " CNT1EN ,Counter 1 enable" "Stopped,Running"
|
|
bitfld.long 0x00 0. " CNT0EN ,Counter 0 enable" "Stopped,Running"
|
|
line.long 0x04 "RTITBCTRL,RTI Timebase Control Register"
|
|
bitfld.long 0x04 1. " INC ,Increment free running counter 0" "Not incremented,Incremented"
|
|
bitfld.long 0x04 0. " TBEXT ,Timebase external" "RTIUC0,NTU"
|
|
line.long 0x08 "RTICAPCTRL,RTI Capture Control Register"
|
|
bitfld.long 0x08 1. " CAPCNTR1 ,Capture counter 1" "Source 0,Source 1"
|
|
bitfld.long 0x08 0. " CAPCNTR0 ,Capture counter 0" "Source 0,Source 1"
|
|
line.long 0x0C "RTICOMPCTRL,RTI Compare Control Register"
|
|
bitfld.long 0x0C 12. " COMPSEL3 ,Compare select 3" "RTIFRC0,RTIFRC1"
|
|
bitfld.long 0x0C 8. " COMPSEL2 ,Compare select 2" "RTIFRC0,RTIFRC1"
|
|
bitfld.long 0x0C 4. " COMPSEL1 ,Compare select 1" "RTIFRC0,RTIFRC1"
|
|
bitfld.long 0x0C 0. " COMPSEL0 ,Compare select 0" "RTIFRC0,RTIFRC1"
|
|
line.long 0x10 "RTIFRC0,RTI Free Running Counter 0 Register"
|
|
line.long 0x14 "RTIUC0,RTI Up Counter 0 Register"
|
|
line.long 0x18 "RTICPUC0,RTI Compare Up Counter 0 Register"
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RTICAFRC0,RTI Capture Free Running Counter 0 Register"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RTICAUC0,RTI Capture Up Counter 0 Register"
|
|
in
|
|
newline
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "RTIFRC1,RTI Free Running Counter 1 Register"
|
|
line.long 0x04 "RTIUC1,RTI Up Counter 1 Register"
|
|
line.long 0x08 "RTICPUC1,RTI Compare Up Counter 1 Register"
|
|
newline
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "RTICAFRC1,RTI Capture Free Running Counter 1 Register"
|
|
in
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "RTICAUC1,RTI Capture Up Counter 1 Register"
|
|
in
|
|
newline
|
|
group.long 0x50++0x27
|
|
line.long 0x00 "RTICOMP0,RTI Compare 0 Register"
|
|
line.long 0x04 "RTIUDCP0,RTI Update Compare 0 Register"
|
|
line.long 0x08 "RTICOMP1,RTI Compare 1 Register"
|
|
line.long 0x0C "RTIUDCP1,RTI Update Compare 1 Register"
|
|
line.long 0x10 "RTICOMP2,RTI Compare 2 Register"
|
|
line.long 0x14 "RTIUDCP2,RTI Update Compare 2 Register"
|
|
line.long 0x18 "RTICOMP3,RTI Compare 3 Register"
|
|
line.long 0x1C "RTIUDCP3,RTI Update Compare 3 Register"
|
|
line.long 0x20 "RTITBLCOMP,RTI Timebase Low Compare Register"
|
|
line.long 0x24 "RTITBHCOMP,RTI Timebase High Compare Register"
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "RTISETINTENA,RTI Set Interrupt Enable Register"
|
|
bitfld.long 0x00 11. " SETDMA3 ,Set compare DMA request 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " SETDMA2 ,Set compare DMA request 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " SETDMA1 ,Set compare DMA request 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SETDMA0 ,Set compare DMA request 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "RTICLEARINTENA,RTI Clear Interrupt Enable Register"
|
|
eventfld.long 0x04 11. " CLEARDMA3 ,Clear compare DMA request 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 10. " CLEARDMA2 ,Clear compare DMA request 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 9. " CLEARDMA1 ,Clear compare DMA request 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 8. " CLEARDMA0 ,Clear compare DMA request 0" "No interrupt,Interrupt"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RTIINTENA_SET/CLR,RTI Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " OVL1INT ,Free running counter 1 overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " OVL0INT ,Free running counter 1 overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " TBINT ,Timebase interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INT3 ,Compare interrupt 3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " INT2 ,Compare interrupt 2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " INT1 ,Compare interrupt 1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " INT0 ,Compare interrupt 0" "No interrupt,Interrupt"
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Register"
|
|
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DWDPRLD ,Digital watchdog preload value"
|
|
line.long 0x08 "RTIWDSTATUS,Watchdog Status Register"
|
|
eventfld.long 0x08 5. " DWWD_ST ,Windowed watchdog status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 4. " END_TIME_VIOL ,Windowed watchdog end time violation status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 3. " START_TIME_VIOL ,Windowed watchdog start time violation status" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 2. " KEY_ST ,Watchdog key status" "No wrong key,Wrong key"
|
|
eventfld.long 0x08 1. " DWD_ST ,DWD status" "No reset,Reset"
|
|
line.long 0x0C "RTIWDKEY,RTI Watchdog Key Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " WDKEY ,Watchdog key"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "RTIDWDCNTR,RTI Digital Watchdog Down Counter Register"
|
|
hexmask.long 0x00 0.--24. 1. " DWDCNTR ,DWD down counter"
|
|
group.long 0xA4++0x1B
|
|
line.long 0x00 "RTIWWDRXNCTRL,Digital Windowed Watchdog Reaction Control Register"
|
|
bitfld.long 0x00 0.--3. " WWDRXN ,The DWWD reaction" "Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Non-maskable interrupt,Reset,Reset,Reset,Reset,Reset"
|
|
line.long 0x04 "RTIWWDSIZECTRL,Digital Windowed Watchdog Window Size Control Register"
|
|
line.long 0x08 "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable Register"
|
|
bitfld.long 0x08 24.--27. " INTCLRENABLE3 ,Enable the auto-clear functionality on the compare 3 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 16.--19. " INTCLRENABLE2 ,Enable the auto-clear functionality on the compare 2 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 8.--11. " INTCLRENABLE1 ,Enable the auto-clear functionality on the compare 1 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 0.--3. " INTCLRENABLE0 ,Enable the auto-clear functionality on the compare 0 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x0C "RTICOMP0CLR,RTI Compare 0 Clear Register"
|
|
line.long 0x10 "RTICOMP1CLR,RTI Compare 1 Clear Register"
|
|
line.long 0x14 "RTICOMP2CLR,RTI Compare 2 Clear Register"
|
|
line.long 0x18 "RTICOMP3CLR,RTI Compare 3 Clear Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTI2"
|
|
base ad:0x020F0000
|
|
width 19.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "RTIGCTRL,RTI Global Control Register"
|
|
bitfld.long 0x00 16.--19. " NTUSEL ,Select NTU signal" "NTU0,,,,,NTU1,,,,,NTU2,,,,,NTU3"
|
|
bitfld.long 0x00 15. " COS ,Continue on suspend" "Stopped,Running"
|
|
bitfld.long 0x00 1. " CNT1EN ,Counter 1 enable" "Stopped,Running"
|
|
bitfld.long 0x00 0. " CNT0EN ,Counter 0 enable" "Stopped,Running"
|
|
line.long 0x04 "RTITBCTRL,RTI Timebase Control Register"
|
|
bitfld.long 0x04 1. " INC ,Increment free running counter 0" "Not incremented,Incremented"
|
|
bitfld.long 0x04 0. " TBEXT ,Timebase external" "RTIUC0,NTU"
|
|
line.long 0x08 "RTICAPCTRL,RTI Capture Control Register"
|
|
bitfld.long 0x08 1. " CAPCNTR1 ,Capture counter 1" "Source 0,Source 1"
|
|
bitfld.long 0x08 0. " CAPCNTR0 ,Capture counter 0" "Source 0,Source 1"
|
|
line.long 0x0C "RTICOMPCTRL,RTI Compare Control Register"
|
|
bitfld.long 0x0C 12. " COMPSEL3 ,Compare select 3" "RTIFRC0,RTIFRC1"
|
|
bitfld.long 0x0C 8. " COMPSEL2 ,Compare select 2" "RTIFRC0,RTIFRC1"
|
|
bitfld.long 0x0C 4. " COMPSEL1 ,Compare select 1" "RTIFRC0,RTIFRC1"
|
|
bitfld.long 0x0C 0. " COMPSEL0 ,Compare select 0" "RTIFRC0,RTIFRC1"
|
|
line.long 0x10 "RTIFRC0,RTI Free Running Counter 0 Register"
|
|
line.long 0x14 "RTIUC0,RTI Up Counter 0 Register"
|
|
line.long 0x18 "RTICPUC0,RTI Compare Up Counter 0 Register"
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RTICAFRC0,RTI Capture Free Running Counter 0 Register"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RTICAUC0,RTI Capture Up Counter 0 Register"
|
|
in
|
|
newline
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "RTIFRC1,RTI Free Running Counter 1 Register"
|
|
line.long 0x04 "RTIUC1,RTI Up Counter 1 Register"
|
|
line.long 0x08 "RTICPUC1,RTI Compare Up Counter 1 Register"
|
|
newline
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "RTICAFRC1,RTI Capture Free Running Counter 1 Register"
|
|
in
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "RTICAUC1,RTI Capture Up Counter 1 Register"
|
|
in
|
|
newline
|
|
group.long 0x50++0x27
|
|
line.long 0x00 "RTICOMP0,RTI Compare 0 Register"
|
|
line.long 0x04 "RTIUDCP0,RTI Update Compare 0 Register"
|
|
line.long 0x08 "RTICOMP1,RTI Compare 1 Register"
|
|
line.long 0x0C "RTIUDCP1,RTI Update Compare 1 Register"
|
|
line.long 0x10 "RTICOMP2,RTI Compare 2 Register"
|
|
line.long 0x14 "RTIUDCP2,RTI Update Compare 2 Register"
|
|
line.long 0x18 "RTICOMP3,RTI Compare 3 Register"
|
|
line.long 0x1C "RTIUDCP3,RTI Update Compare 3 Register"
|
|
line.long 0x20 "RTITBLCOMP,RTI Timebase Low Compare Register"
|
|
line.long 0x24 "RTITBHCOMP,RTI Timebase High Compare Register"
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "RTISETINTENA,RTI Set Interrupt Enable Register"
|
|
bitfld.long 0x00 11. " SETDMA3 ,Set compare DMA request 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " SETDMA2 ,Set compare DMA request 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " SETDMA1 ,Set compare DMA request 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " SETDMA0 ,Set compare DMA request 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "RTICLEARINTENA,RTI Clear Interrupt Enable Register"
|
|
eventfld.long 0x04 11. " CLEARDMA3 ,Clear compare DMA request 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 10. " CLEARDMA2 ,Clear compare DMA request 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 9. " CLEARDMA1 ,Clear compare DMA request 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 8. " CLEARDMA0 ,Clear compare DMA request 0" "No interrupt,Interrupt"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RTIINTENA_SET/CLR,RTI Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " OVL1INT ,Free running counter 1 overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " OVL0INT ,Free running counter 1 overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " TBINT ,Timebase interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " INT3 ,Compare interrupt 3" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " INT2 ,Compare interrupt 2" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " INT1 ,Compare interrupt 1" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " INT0 ,Compare interrupt 0" "No interrupt,Interrupt"
|
|
group.long 0x90++0x0F
|
|
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Register"
|
|
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DWDPRLD ,Digital watchdog preload value"
|
|
line.long 0x08 "RTIWDSTATUS,Watchdog Status Register"
|
|
eventfld.long 0x08 5. " DWWD_ST ,Windowed watchdog status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 4. " END_TIME_VIOL ,Windowed watchdog end time violation status" "Not occurred,Occurred"
|
|
eventfld.long 0x08 3. " START_TIME_VIOL ,Windowed watchdog start time violation status" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x08 2. " KEY_ST ,Watchdog key status" "No wrong key,Wrong key"
|
|
eventfld.long 0x08 1. " DWD_ST ,DWD status" "No reset,Reset"
|
|
line.long 0x0C "RTIWDKEY,RTI Watchdog Key Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " WDKEY ,Watchdog key"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "RTIDWDCNTR,RTI Digital Watchdog Down Counter Register"
|
|
hexmask.long 0x00 0.--24. 1. " DWDCNTR ,DWD down counter"
|
|
group.long 0xA4++0x1B
|
|
line.long 0x00 "RTIWWDRXNCTRL,Digital Windowed Watchdog Reaction Control Register"
|
|
bitfld.long 0x00 0.--3. " WWDRXN ,The DWWD reaction" "Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Non-maskable interrupt,Reset,Reset,Reset,Reset,Reset"
|
|
line.long 0x04 "RTIWWDSIZECTRL,Digital Windowed Watchdog Window Size Control Register"
|
|
line.long 0x08 "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable Register"
|
|
bitfld.long 0x08 24.--27. " INTCLRENABLE3 ,Enable the auto-clear functionality on the compare 3 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 16.--19. " INTCLRENABLE2 ,Enable the auto-clear functionality on the compare 2 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 8.--11. " INTCLRENABLE1 ,Enable the auto-clear functionality on the compare 1 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
bitfld.long 0x08 0.--3. " INTCLRENABLE0 ,Enable the auto-clear functionality on the compare 0 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled"
|
|
line.long 0x0C "RTICOMP0CLR,RTI Compare 0 Clear Register"
|
|
line.long 0x10 "RTICOMP1CLR,RTI Compare 1 Clear Register"
|
|
line.long 0x14 "RTICOMP2CLR,RTI Compare 2 Clear Register"
|
|
line.long 0x18 "RTICOMP3CLR,RTI Compare 3 Clear Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "HSI (High-Speed Interface)"
|
|
base ad:0x02070000
|
|
width 25.
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONFIG_REG_0,Basic Config Register"
|
|
bitfld.long 0x00 27. " CSWCRST ,CBUFF controller SW reset" "No reset,Reset"
|
|
bitfld.long 0x00 25. " CFG_FRAME_START_TRIG ,Generate frame start SW trigger" "No effect,Generate"
|
|
bitfld.long 0x00 24. " CFG_CHIRP_AVAIL_TRIG ,Generate a Chirp available SW trigger" "No effect,Generate"
|
|
bitfld.long 0x00 16.--17. " CVC3EN ,Generate VSYNC packet on virtual channel 3" "No effect,Start,End,Start/End"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CVC2EN ,Generate VSYNC packet on virtual channel 2" "No effect,Start,End,Start/End"
|
|
bitfld.long 0x00 12.--13. " CVC1EN ,Generate VSYNC packet on virtual channel 1" "No effect,Start,End,Start/End"
|
|
bitfld.long 0x00 10.--11. " CVC0EN ,Generate VSYNC packet on virtual channel 0" "No effect,Start,End,Start/End"
|
|
bitfld.long 0x00 3. " CFG_SW_TRIG_EN ,Chirp available trigger source" "HW,SW"
|
|
newline
|
|
bitfld.long 0x00 2. " CFTRIGEN ,Frame start trigger source" "HW,SW"
|
|
bitfld.long 0x00 1. " CFG_ECC_EN ,Enable ECC on the CBUF FIFO" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFG_1LVDS_0CSI ,Select source for sending data" ",LVDS"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONFIG_REG_0,Basic Config Register"
|
|
bitfld.long 0x00 27. " CSWCRST ,CBUFF controller SW reset" "No reset,Reset"
|
|
bitfld.long 0x00 25. " CFG_FRAME_START_TRIG ,Generate frame start SW trigger" "No effect,Generate"
|
|
bitfld.long 0x00 24. " CFG_CHIRP_AVAIL_TRIG ,Generate a Chirp available SW trigger" "No effect,Generate"
|
|
bitfld.long 0x00 16.--17. " CVC3EN ,Generate VSYNC packet on virtual channel 3" "No effect,Start,End,Start/End"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CVC2EN ,Generate VSYNC packet on virtual channel 2" "No effect,Start,End,Start/End"
|
|
bitfld.long 0x00 12.--13. " CVC1EN ,Generate VSYNC packet on virtual channel 1" "No effect,Start,End,Start/End"
|
|
bitfld.long 0x00 10.--11. " CVC0EN ,Generate VSYNC packet on virtual channel 0" "No effect,Start,End,Start/End"
|
|
bitfld.long 0x00 3. " CFG_SW_TRIG_EN ,Chirp available trigger source" "HW,SW"
|
|
newline
|
|
bitfld.long 0x00 2. " CFTRIGEN ,Frame start trigger source" "HW,SW"
|
|
bitfld.long 0x00 1. " CFG_ECC_EN ,Enable ECC on the CBUF FIFO" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFG_1LVDS_0CSI ,Select source for sending data" "CSI-2,LVDS"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONFIG_REG_0,Basic Config Register"
|
|
bitfld.long 0x00 27. " CSWCRST ,CBUFF controller SW reset" "No reset,Reset"
|
|
bitfld.long 0x00 25. " CFG_FRAME_START_TRIG ,SW trigger a frame start SW trigger" "Not generated,Generated"
|
|
bitfld.long 0x00 24. " CFG_CHIRP_AVAIL_TRIG ,SW trigger a chirp available generation" "Not generated,Generated"
|
|
bitfld.long 0x00 3. " CFG_SW_TRIG_EN ,Select chirp available trigger source" "HW1,SW"
|
|
newline
|
|
bitfld.long 0x00 2. " CFTRIGEN ,Select frame start trigger source" "HW1,SW"
|
|
bitfld.long 0x00 1. " CFG_ECC_EN ,Enable ECC on the CBUF FIFO" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFG_1LVDS_0CSI ,Select source for sending data" "CSI-2,LVDS"
|
|
endif
|
|
endif
|
|
group.long 0x04++0x17
|
|
line.long 0x00 "CFG_SPHDR_ADDRESS,Short Packet Header Address Register"
|
|
line.long 0x04 "CFG_CMD_HSVAL,HSYNC Value Register"
|
|
line.long 0x08 "CFG_CMD_HEVAL,HEND Value Register"
|
|
line.long 0x0C "CFG_CMD_VSVAL,VSYNC Value Register"
|
|
line.long 0x10 "CFG_CMD_VEVAL,VEND Value Register"
|
|
line.long 0x14 "CFG_LPHDR_ADDRESS,Long Packet Address Register"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CFG_CHIRPS_PER_FRAME,Number Of Chirps Per Frame Register"
|
|
sif cpuis("AWR6843*")
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "CFG_FIFO_FREE_THRESHOLD,CSI2 FIFO Threshold For Transferring Data From CBUFF To CSI2"
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "CFG_LPPYLD_ADDRESS,Long Payload Address Register"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "CFG_FIFO_FREE_THRESHOLD,CSI2 FIFO Threshold For Transferring Data From CBUFF To CSI2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CFF_THRESHOLD ,Threshold used to fill the FIFO0 in the CSI protocol engine"
|
|
line.long 0x04 "CFG_LPPYLD_ADDRESS,Long Payload Address Register"
|
|
else
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "CFG_FIFO_FREE_THRESHOLD,CSI2 FIFO Threshold For Transferring Data From CBUFF To CSI2"
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "CFG_LPPYLD_ADDRESS,Long Payload Address Register"
|
|
endif
|
|
endif
|
|
newline
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CFG_DATA_LL0,Linked List Entry 0"
|
|
bitfld.long 0x00 28. " LL0_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL0_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL0_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL0_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL0_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL0_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL0_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL0_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL0_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CFG_DATA_LL0,Linked List Entry 0 Register"
|
|
bitfld.long 0x00 28. " LL0_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL0_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL0_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL0_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL0_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL0_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL0_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL0_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL0_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CFG_DATA_LL0,Linked List Entry 0"
|
|
bitfld.long 0x00 28. " LL0_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL0_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL0_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL0_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL0_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL0_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL0_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL0_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL0_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x30+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL0_LPHDR_VAL,Linked List Entry 0"
|
|
line.long 0x04 "CFG_DATA_LL0_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL0DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL0_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL0_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CFG_DATA_LL1,Linked List Entry 1"
|
|
bitfld.long 0x00 28. " LL1_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL1_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL1_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL1_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL1_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL1_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL1_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL1_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL1_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CFG_DATA_LL1,Linked List Entry 1 Register"
|
|
bitfld.long 0x00 28. " LL1_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL1_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL1_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL1_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL1_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL1_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL1_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL1_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL1_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CFG_DATA_LL1,Linked List Entry 1"
|
|
bitfld.long 0x00 28. " LL1_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL1_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL1_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL1_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL1_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL1_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL1_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL1_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL1_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x3C+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL1_LPHDR_VAL,Linked List Entry 1"
|
|
line.long 0x04 "CFG_DATA_LL1_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL1DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL1_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL1_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CFG_DATA_LL2,Linked List Entry 2"
|
|
bitfld.long 0x00 28. " LL2_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL2_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL2_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL2_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL2_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL2_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL2_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL2_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL2_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CFG_DATA_LL2,Linked List Entry 2 Register"
|
|
bitfld.long 0x00 28. " LL2_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL2_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL2_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL2_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL2_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL2_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL2_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL2_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL2_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CFG_DATA_LL2,Linked List Entry 2"
|
|
bitfld.long 0x00 28. " LL2_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL2_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL2_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL2_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL2_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL2_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL2_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL2_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL2_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x48+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL2_LPHDR_VAL,Linked List Entry 2"
|
|
line.long 0x04 "CFG_DATA_LL2_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL2DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL2_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL2_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CFG_DATA_LL3,Linked List Entry 3"
|
|
bitfld.long 0x00 28. " LL3_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL3_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL3_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL3_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL3_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL3_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL3_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL3_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL3_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CFG_DATA_LL3,Linked List Entry 3 Register"
|
|
bitfld.long 0x00 28. " LL3_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL3_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL3_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL3_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL3_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL3_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL3_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL3_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL3_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CFG_DATA_LL3,Linked List Entry 3"
|
|
bitfld.long 0x00 28. " LL3_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL3_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL3_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL3_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL3_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL3_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL3_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL3_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL3_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x54+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL3_LPHDR_VAL,Linked List Entry 3"
|
|
line.long 0x04 "CFG_DATA_LL3_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL3DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL3_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL3_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CFG_DATA_LL4,Linked List Entry 4"
|
|
bitfld.long 0x00 28. " LL4_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL4_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL4_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL4_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL4_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL4_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL4_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL4_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL4_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CFG_DATA_LL4,Linked List Entry 4 Register"
|
|
bitfld.long 0x00 28. " LL4_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL4_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL4_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL4_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL4_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL4_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL4_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL4_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL4_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CFG_DATA_LL4,Linked List Entry 4"
|
|
bitfld.long 0x00 28. " LL4_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL4_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL4_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL4_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL4_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL4_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL4_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL4_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL4_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x60+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL4_LPHDR_VAL,Linked List Entry 4"
|
|
line.long 0x04 "CFG_DATA_LL4_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL4DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL4_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL4_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CFG_DATA_LL5,Linked List Entry 5"
|
|
bitfld.long 0x00 28. " LL5_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL5_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL5_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL5_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL5_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL5_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL5_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL5_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL5_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CFG_DATA_LL5,Linked List Entry 5 Register"
|
|
bitfld.long 0x00 28. " LL5_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL5_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL5_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL5_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL5_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL5_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL5_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL5_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL5_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CFG_DATA_LL5,Linked List Entry 5"
|
|
bitfld.long 0x00 28. " LL5_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL5_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL5_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL5_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL5_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL5_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL5_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL5_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL5_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x6C+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL5_LPHDR_VAL,Linked List Entry 5"
|
|
line.long 0x04 "CFG_DATA_LL5_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL5DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL5_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL5_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CFG_DATA_LL6,Linked List Entry 6"
|
|
bitfld.long 0x00 28. " LL6_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL6_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL6_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL6_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL6_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL6_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL6_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL6_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL6_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CFG_DATA_LL6,Linked List Entry 6 Register"
|
|
bitfld.long 0x00 28. " LL6_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL6_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL6_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL6_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL6_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL6_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL6_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL6_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL6_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CFG_DATA_LL6,Linked List Entry 6"
|
|
bitfld.long 0x00 28. " LL6_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL6_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL6_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL6_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL6_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL6_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL6_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL6_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL6_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x78+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL6_LPHDR_VAL,Linked List Entry 6"
|
|
line.long 0x04 "CFG_DATA_LL6_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL6DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL6_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL6_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CFG_DATA_LL7,Linked List Entry 7"
|
|
bitfld.long 0x00 28. " LL7_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL7_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL7_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL7_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL7_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL7_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL7_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL7_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL7_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CFG_DATA_LL7,Linked List Entry 7 Register"
|
|
bitfld.long 0x00 28. " LL7_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL7_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL7_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL7_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL7_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL7_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL7_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL7_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL7_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CFG_DATA_LL7,Linked List Entry 7"
|
|
bitfld.long 0x00 28. " LL7_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL7_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL7_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL7_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL7_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL7_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL7_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL7_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL7_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x84+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL7_LPHDR_VAL,Linked List Entry 7"
|
|
line.long 0x04 "CFG_DATA_LL7_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL7DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL7_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL7_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CFG_DATA_LL8,Linked List Entry 8"
|
|
bitfld.long 0x00 28. " LL8_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL8_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL8_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL8_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL8_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL8_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL8_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL8_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL8_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CFG_DATA_LL8,Linked List Entry 8 Register"
|
|
bitfld.long 0x00 28. " LL8_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL8_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL8_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL8_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL8_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL8_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL8_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL8_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL8_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CFG_DATA_LL8,Linked List Entry 8"
|
|
bitfld.long 0x00 28. " LL8_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL8_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL8_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL8_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL8_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL8_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL8_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL8_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL8_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x90+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL8_LPHDR_VAL,Linked List Entry 8"
|
|
line.long 0x04 "CFG_DATA_LL8_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL8DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL8_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL8_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CFG_DATA_LL9,Linked List Entry 9"
|
|
bitfld.long 0x00 28. " LL9_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL9_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL9_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL9_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL9_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL9_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL9_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL9_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL9_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CFG_DATA_LL9,Linked List Entry 9 Register"
|
|
bitfld.long 0x00 28. " LL9_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL9_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL9_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL9_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL9_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL9_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL9_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL9_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL9_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CFG_DATA_LL9,Linked List Entry 9"
|
|
bitfld.long 0x00 28. " LL9_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL9_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL9_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL9_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL9_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL9_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL9_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL9_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL9_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x9C+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL9_LPHDR_VAL,Linked List Entry 9"
|
|
line.long 0x04 "CFG_DATA_LL9_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL9DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL9_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL9_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
newline
|
|
sif cpuis("AWR6843*")
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CFG_DATA_LL10,Linked List Entry 10"
|
|
bitfld.long 0x00 28. " LL10_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL10_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL10_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL10_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL10_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL10_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL10_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL10_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL10_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CFG_DATA_LL10,Linked List Entry 10 Register"
|
|
bitfld.long 0x00 28. " LL10_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL10_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL10_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL10_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL10_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL10_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL10_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL10_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL10_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CFG_DATA_LL10,Linked List Entry 10"
|
|
bitfld.long 0x00 28. " LL10_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL10_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL10_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL10_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL10_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL10_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL10_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL10_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL10_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0xA8+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL10_LPHDR_VAL,Linked List Entry 10"
|
|
line.long 0x04 "CFG_DATA_LL10_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL10DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL10_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL10_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CFG_DATA_LL11,Linked List Entry 11"
|
|
bitfld.long 0x00 28. " LL11_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL11_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL11_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL11_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL11_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL11_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL11_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL11_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL11_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CFG_DATA_LL11,Linked List Entry 11 Register"
|
|
bitfld.long 0x00 28. " LL11_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL11_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL11_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL11_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL11_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL11_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL11_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL11_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL11_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CFG_DATA_LL11,Linked List Entry 11"
|
|
bitfld.long 0x00 28. " LL11_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL11_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL11_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL11_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL11_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL11_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL11_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL11_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL11_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0xB4+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL11_LPHDR_VAL,Linked List Entry 11"
|
|
line.long 0x04 "CFG_DATA_LL11_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL11DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL11_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL11_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CFG_DATA_LL12,Linked List Entry 12"
|
|
bitfld.long 0x00 28. " LL12_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL12_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL12_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL12_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL12_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL12_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL12_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL12_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL12_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CFG_DATA_LL12,Linked List Entry 12 Register"
|
|
bitfld.long 0x00 28. " LL12_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL12_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL12_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL12_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL12_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL12_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL12_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL12_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL12_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CFG_DATA_LL12,Linked List Entry 12"
|
|
bitfld.long 0x00 28. " LL12_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL12_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL12_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL12_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL12_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL12_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL12_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL12_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL12_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0xC0+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL12_LPHDR_VAL,Linked List Entry 12"
|
|
line.long 0x04 "CFG_DATA_LL12_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL12DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL12_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL12_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CFG_DATA_LL13,Linked List Entry 13"
|
|
bitfld.long 0x00 28. " LL13_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL13_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL13_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL13_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL13_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL13_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL13_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL13_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL13_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CFG_DATA_LL13,Linked List Entry 13 Register"
|
|
bitfld.long 0x00 28. " LL13_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL13_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL13_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL13_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL13_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL13_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL13_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL13_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL13_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CFG_DATA_LL13,Linked List Entry 13"
|
|
bitfld.long 0x00 28. " LL13_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL13_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL13_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL13_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL13_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL13_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL13_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL13_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL13_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0xCC+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL13_LPHDR_VAL,Linked List Entry 13"
|
|
line.long 0x04 "CFG_DATA_LL13_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL13DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL13_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL13_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CFG_DATA_LL14,Linked List Entry 14"
|
|
bitfld.long 0x00 28. " LL14_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL14_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL14_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL14_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL14_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL14_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL14_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL14_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL14_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CFG_DATA_LL14,Linked List Entry 14 Register"
|
|
bitfld.long 0x00 28. " LL14_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL14_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL14_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL14_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL14_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL14_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL14_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL14_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL14_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CFG_DATA_LL14,Linked List Entry 14"
|
|
bitfld.long 0x00 28. " LL14_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL14_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL14_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL14_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL14_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL14_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL14_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL14_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL14_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0xD8+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL14_LPHDR_VAL,Linked List Entry 14"
|
|
line.long 0x04 "CFG_DATA_LL14_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL14DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL14_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL14_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CFG_DATA_LL15,Linked List Entry 15"
|
|
bitfld.long 0x00 28. " LL15_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL15_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL15_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL15_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL15_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL15_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL15_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL15_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL15_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CFG_DATA_LL15,Linked List Entry 15 Register"
|
|
bitfld.long 0x00 28. " LL15_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL15_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL15_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL15_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL15_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL15_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL15_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL15_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL15_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CFG_DATA_LL15,Linked List Entry 15"
|
|
bitfld.long 0x00 28. " LL15_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL15_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL15_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL15_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL15_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL15_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL15_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL15_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL15_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0xE4+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL15_LPHDR_VAL,Linked List Entry 15"
|
|
line.long 0x04 "CFG_DATA_LL15_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL15DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL15_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL15_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CFG_DATA_LL16,Linked List Entry 16"
|
|
bitfld.long 0x00 28. " LL16_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL16_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL16_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL16_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL16_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL16_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL16_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL16_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL16_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CFG_DATA_LL16,Linked List Entry 16 Register"
|
|
bitfld.long 0x00 28. " LL16_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL16_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL16_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL16_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL16_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL16_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL16_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL16_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL16_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CFG_DATA_LL16,Linked List Entry 16"
|
|
bitfld.long 0x00 28. " LL16_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL16_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL16_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL16_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL16_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL16_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL16_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL16_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL16_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0xF0+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL16_LPHDR_VAL,Linked List Entry 16"
|
|
line.long 0x04 "CFG_DATA_LL16_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL16DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL16_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL16_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CFG_DATA_LL17,Linked List Entry 17"
|
|
bitfld.long 0x00 28. " LL17_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL17_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL17_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL17_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL17_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL17_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL17_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL17_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL17_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CFG_DATA_LL17,Linked List Entry 17 Register"
|
|
bitfld.long 0x00 28. " LL17_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL17_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL17_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL17_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL17_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL17_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL17_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL17_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL17_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CFG_DATA_LL17,Linked List Entry 17"
|
|
bitfld.long 0x00 28. " LL17_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL17_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL17_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL17_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL17_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL17_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL17_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL17_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL17_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0xFC+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL17_LPHDR_VAL,Linked List Entry 17"
|
|
line.long 0x04 "CFG_DATA_LL17_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL17DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL17_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL17_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CFG_DATA_LL18,Linked List Entry 18"
|
|
bitfld.long 0x00 28. " LL18_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL18_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL18_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL18_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL18_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL18_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL18_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL18_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL18_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CFG_DATA_LL18,Linked List Entry 18 Register"
|
|
bitfld.long 0x00 28. " LL18_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL18_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL18_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL18_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL18_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL18_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL18_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL18_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL18_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CFG_DATA_LL18,Linked List Entry 18"
|
|
bitfld.long 0x00 28. " LL18_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL18_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL18_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL18_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL18_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL18_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL18_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL18_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL18_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x108+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL18_LPHDR_VAL,Linked List Entry 18"
|
|
line.long 0x04 "CFG_DATA_LL18_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL18DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL18_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL18_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CFG_DATA_LL19,Linked List Entry 19"
|
|
bitfld.long 0x00 28. " LL19_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL19_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL19_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL19_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL19_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL19_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL19_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL19_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL19_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CFG_DATA_LL19,Linked List Entry 19 Register"
|
|
bitfld.long 0x00 28. " LL19_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL19_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL19_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL19_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL19_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL19_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL19_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL19_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL19_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CFG_DATA_LL19,Linked List Entry 19"
|
|
bitfld.long 0x00 28. " LL19_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL19_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL19_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL19_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL19_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL19_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL19_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL19_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL19_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x114+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL19_LPHDR_VAL,Linked List Entry 19"
|
|
line.long 0x04 "CFG_DATA_LL19_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL19DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL19_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL19_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CFG_DATA_LL20,Linked List Entry 20"
|
|
bitfld.long 0x00 28. " LL20_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL20_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL20_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL20_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL20_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL20_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL20_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL20_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL20_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CFG_DATA_LL20,Linked List Entry 20 Register"
|
|
bitfld.long 0x00 28. " LL20_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL20_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL20_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL20_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL20_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL20_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL20_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL20_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL20_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CFG_DATA_LL20,Linked List Entry 20"
|
|
bitfld.long 0x00 28. " LL20_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL20_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL20_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL20_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL20_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL20_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL20_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL20_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL20_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x120+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL20_LPHDR_VAL,Linked List Entry 20"
|
|
line.long 0x04 "CFG_DATA_LL20_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL20DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL20_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL20_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "CFG_DATA_LL21,Linked List Entry 21"
|
|
bitfld.long 0x00 28. " LL21_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL21_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL21_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL21_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL21_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL21_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL21_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL21_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL21_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "CFG_DATA_LL21,Linked List Entry 21 Register"
|
|
bitfld.long 0x00 28. " LL21_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL21_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL21_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL21_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL21_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL21_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL21_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL21_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL21_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "CFG_DATA_LL21,Linked List Entry 21"
|
|
bitfld.long 0x00 28. " LL21_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL21_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL21_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL21_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL21_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL21_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL21_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL21_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL21_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x12C+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL21_LPHDR_VAL,Linked List Entry 21"
|
|
line.long 0x04 "CFG_DATA_LL21_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL21DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL21_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL21_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "CFG_DATA_LL22,Linked List Entry 22"
|
|
bitfld.long 0x00 28. " LL22_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL22_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL22_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL22_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL22_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL22_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL22_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL22_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL22_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "CFG_DATA_LL22,Linked List Entry 22 Register"
|
|
bitfld.long 0x00 28. " LL22_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL22_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL22_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL22_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL22_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL22_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL22_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL22_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL22_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "CFG_DATA_LL22,Linked List Entry 22"
|
|
bitfld.long 0x00 28. " LL22_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL22_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL22_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL22_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL22_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL22_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL22_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL22_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL22_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x138+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL22_LPHDR_VAL,Linked List Entry 22"
|
|
line.long 0x04 "CFG_DATA_LL22_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL22DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL22_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL22_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "CFG_DATA_LL23,Linked List Entry 23"
|
|
bitfld.long 0x00 28. " LL23_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL23_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL23_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL23_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL23_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL23_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL23_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL23_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL23_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "CFG_DATA_LL23,Linked List Entry 23 Register"
|
|
bitfld.long 0x00 28. " LL23_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL23_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL23_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL23_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL23_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL23_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL23_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL23_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL23_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "CFG_DATA_LL23,Linked List Entry 23"
|
|
bitfld.long 0x00 28. " LL23_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL23_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL23_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL23_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL23_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL23_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL23_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL23_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL23_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x144+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL23_LPHDR_VAL,Linked List Entry 23"
|
|
line.long 0x04 "CFG_DATA_LL23_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL23DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL23_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL23_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CFG_DATA_LL24,Linked List Entry 24"
|
|
bitfld.long 0x00 28. " LL24_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL24_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL24_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL24_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL24_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL24_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL24_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL24_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL24_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CFG_DATA_LL24,Linked List Entry 24 Register"
|
|
bitfld.long 0x00 28. " LL24_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL24_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL24_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL24_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL24_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL24_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL24_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL24_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL24_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CFG_DATA_LL24,Linked List Entry 24"
|
|
bitfld.long 0x00 28. " LL24_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL24_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL24_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL24_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL24_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL24_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL24_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL24_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL24_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x150+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL24_LPHDR_VAL,Linked List Entry 24"
|
|
line.long 0x04 "CFG_DATA_LL24_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL24DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL24_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL24_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "CFG_DATA_LL25,Linked List Entry 25"
|
|
bitfld.long 0x00 28. " LL25_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL25_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL25_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL25_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL25_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL25_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL25_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL25_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL25_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "CFG_DATA_LL25,Linked List Entry 25 Register"
|
|
bitfld.long 0x00 28. " LL25_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL25_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL25_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL25_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL25_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL25_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL25_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL25_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL25_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "CFG_DATA_LL25,Linked List Entry 25"
|
|
bitfld.long 0x00 28. " LL25_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL25_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL25_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL25_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL25_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL25_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL25_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL25_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL25_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x15C+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL25_LPHDR_VAL,Linked List Entry 25"
|
|
line.long 0x04 "CFG_DATA_LL25_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL25DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL25_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL25_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "CFG_DATA_LL26,Linked List Entry 26"
|
|
bitfld.long 0x00 28. " LL26_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL26_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL26_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL26_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL26_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL26_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL26_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL26_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL26_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "CFG_DATA_LL26,Linked List Entry 26 Register"
|
|
bitfld.long 0x00 28. " LL26_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL26_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL26_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL26_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL26_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL26_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL26_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL26_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL26_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "CFG_DATA_LL26,Linked List Entry 26"
|
|
bitfld.long 0x00 28. " LL26_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL26_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL26_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL26_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL26_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL26_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL26_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL26_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL26_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x168+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL26_LPHDR_VAL,Linked List Entry 26"
|
|
line.long 0x04 "CFG_DATA_LL26_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL26DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL26_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL26_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "CFG_DATA_LL27,Linked List Entry 27"
|
|
bitfld.long 0x00 28. " LL27_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL27_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL27_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL27_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL27_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL27_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL27_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL27_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL27_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "CFG_DATA_LL27,Linked List Entry 27 Register"
|
|
bitfld.long 0x00 28. " LL27_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL27_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL27_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL27_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL27_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL27_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL27_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL27_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL27_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "CFG_DATA_LL27,Linked List Entry 27"
|
|
bitfld.long 0x00 28. " LL27_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL27_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL27_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL27_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL27_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL27_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL27_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL27_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL27_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x174+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL27_LPHDR_VAL,Linked List Entry 27"
|
|
line.long 0x04 "CFG_DATA_LL27_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL27DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL27_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL27_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CFG_DATA_LL28,Linked List Entry 28"
|
|
bitfld.long 0x00 28. " LL28_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL28_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL28_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL28_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL28_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL28_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL28_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL28_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL28_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CFG_DATA_LL28,Linked List Entry 28 Register"
|
|
bitfld.long 0x00 28. " LL28_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL28_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL28_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL28_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL28_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL28_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL28_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL28_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL28_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CFG_DATA_LL28,Linked List Entry 28"
|
|
bitfld.long 0x00 28. " LL28_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL28_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL28_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL28_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL28_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL28_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL28_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL28_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL28_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x180+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL28_LPHDR_VAL,Linked List Entry 28"
|
|
line.long 0x04 "CFG_DATA_LL28_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL28DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL28_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL28_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "CFG_DATA_LL29,Linked List Entry 29"
|
|
bitfld.long 0x00 28. " LL29_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL29_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL29_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL29_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL29_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL29_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL29_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL29_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL29_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "CFG_DATA_LL29,Linked List Entry 29 Register"
|
|
bitfld.long 0x00 28. " LL29_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL29_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL29_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL29_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL29_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL29_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL29_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL29_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL29_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "CFG_DATA_LL29,Linked List Entry 29"
|
|
bitfld.long 0x00 28. " LL29_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL29_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL29_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL29_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL29_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL29_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL29_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL29_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL29_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x18C+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL29_LPHDR_VAL,Linked List Entry 29"
|
|
line.long 0x04 "CFG_DATA_LL29_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL29DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL29_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL29_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "CFG_DATA_LL30,Linked List Entry 30"
|
|
bitfld.long 0x00 28. " LL30_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL30_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL30_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL30_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL30_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL30_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL30_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL30_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL30_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "CFG_DATA_LL30,Linked List Entry 30 Register"
|
|
bitfld.long 0x00 28. " LL30_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL30_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL30_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL30_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL30_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL30_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL30_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL30_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL30_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "CFG_DATA_LL30,Linked List Entry 30"
|
|
bitfld.long 0x00 28. " LL30_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL30_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL30_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL30_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL30_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL30_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL30_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL30_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL30_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x198+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL30_LPHDR_VAL,Linked List Entry 30"
|
|
line.long 0x04 "CFG_DATA_LL30_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL30DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL30_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL30_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
sif cpuis("AWR6843*")
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "CFG_DATA_LL31,Linked List Entry 31"
|
|
bitfld.long 0x00 28. " LL31_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL31_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL31_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL31_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL31_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL31_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL31_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL31_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL31_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
if (((per.l(ad:0x02070000))&0x01)==0x00)
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "CFG_DATA_LL31,Linked List Entry 31 Register"
|
|
bitfld.long 0x00 28. " LL31_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL31_LPHDR_EN ,Entry start source" "Not started,CSI-2 packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL31_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL31_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 5.--6. " LL31_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 3.--4. " LL31_VCNUM ,Configure the virtual channel number for the long packet over which this data is sent" "0,1,2,3"
|
|
bitfld.long 0x00 2. " LL31_HS ,Enable sending Hsync start packet" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL31_HE ,Enable sending Hsync end packet" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " LL31_VALID ,Linklist entry status" "Invalid,Valid"
|
|
else
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "CFG_DATA_LL31,Linked List Entry 31"
|
|
bitfld.long 0x00 28. " LL31_CRC_EN ,Enable the CRC check from ADC buffer to CBUFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " LL31_LPHDR_EN ,Entry start source" "Not started,LVDS packet"
|
|
hexmask.long.word 0x00 9.--22. 1. " LL31_SIZE ,Size of the data in terms of the number of samples"
|
|
bitfld.long 0x00 8. " LL31_FMT_IN ,Align the incoming data sources for this linklist" "128-bit,96-bit"
|
|
newline
|
|
bitfld.long 0x00 7. " LL31_FMT_MAP ,Mapping" "0,1"
|
|
bitfld.long 0x00 5.--6. " LL31_FMT ,Specify the LVDS/CSI2 output format" "16bit,14bit,12bit,?..."
|
|
bitfld.long 0x00 2. " LL31_HS ,LVDS frame as first data" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LL31_HE ,LVDS frame as last data" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " LL31_VALID ,Linklist entry status" "Invalid,Valid"
|
|
endif
|
|
endif
|
|
group.long (0x1A4+0x04)++0x07
|
|
line.long 0x00 "CFG_DATA_LL31_LPHDR_VAL,Linked List Entry 31"
|
|
line.long 0x04 "CFG_DATA_LL31_THRESHOLD,Linked List Threshold Register"
|
|
bitfld.long 0x04 16.--18. " LL31DMAN ,DMA request to trigger the DMA transfer for the new packet on DMA HW req output line" "0,1,2,3,4,5,6,No line"
|
|
hexmask.long.byte 0x04 8.--14. 1. " LL31_WR_THRESHOLD ,Configure the CBUFF FIFO write threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " LL31_RD_THRESHOLD ,Configure the CBUFF read threshold"
|
|
if (((per.l(ad:0x02070000))&0x01)==0x01)
|
|
width 31.
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "CFG_LVDS_MAPPING_LANE0_FMT_0,Lane 0 Mapping Register"
|
|
bitfld.long 0x00 31. " CFG_LVDS_MAPPING_LANE0_FMT_0_H_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 28.--30. " CFG_LVDS_MAPPING_LANE0_FMT_0_H_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27. " CFG_LVDS_MAPPING_LANE0_FMT_0_G_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 24.--26. " CFG_LVDS_MAPPING_LANE0_FMT_0_G_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. " CFG_LVDS_MAPPING_LANE0_FMT_0_F_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--22. " CFG_LVDS_MAPPING_LANE0_FMT_0_F_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19. " CFG_LVDS_MAPPING_LANE0_FMT_0_E_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " CFG_LVDS_MAPPING_LANE0_FMT_0_E_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " CFG_LVDS_MAPPING_LANE0_FMT_0_D_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 12.--14. " CFG_LVDS_MAPPING_LANE0_FMT_0_D_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. " CFG_LVDS_MAPPING_LANE0_FMT_0_C_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " CFG_LVDS_MAPPING_LANE0_FMT_0_C_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. " CFG_LVDS_MAPPING_LANE0_FMT_0_B_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 4.--6. " CFG_LVDS_MAPPING_LANE0_FMT_0_B_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. " CFG_LVDS_MAPPING_LANE0_FMT_0_A_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--2. " CFG_LVDS_MAPPING_LANE0_FMT_0_A_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "CFG_LVDS_MAPPING_LANE1_FMT_0,Lane 1 Mapping Register"
|
|
bitfld.long 0x00 31. " CFG_LVDS_MAPPING_LANE1_FMT_0_H_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 28.--30. " CFG_LVDS_MAPPING_LANE1_FMT_0_H_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27. " CFG_LVDS_MAPPING_LANE1_FMT_0_G_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 24.--26. " CFG_LVDS_MAPPING_LANE1_FMT_0_G_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. " CFG_LVDS_MAPPING_LANE1_FMT_0_F_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--22. " CFG_LVDS_MAPPING_LANE1_FMT_0_F_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19. " CFG_LVDS_MAPPING_LANE1_FMT_0_E_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " CFG_LVDS_MAPPING_LANE1_FMT_0_E_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " CFG_LVDS_MAPPING_LANE1_FMT_0_D_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 12.--14. " CFG_LVDS_MAPPING_LANE1_FMT_0_D_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. " CFG_LVDS_MAPPING_LANE1_FMT_0_C_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " CFG_LVDS_MAPPING_LANE1_FMT_0_C_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. " CFG_LVDS_MAPPING_LANE1_FMT_0_B_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 4.--6. " CFG_LVDS_MAPPING_LANE1_FMT_0_B_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. " CFG_LVDS_MAPPING_LANE1_FMT_0_A_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--2. " CFG_LVDS_MAPPING_LANE1_FMT_0_A_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "CFG_LVDS_MAPPING_LANE2_FMT_0,Lane 2 Mapping Register"
|
|
bitfld.long 0x00 31. " CFG_LVDS_MAPPING_LANE2_FMT_0_H_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 28.--30. " CFG_LVDS_MAPPING_LANE2_FMT_0_H_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27. " CFG_LVDS_MAPPING_LANE2_FMT_0_G_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 24.--26. " CFG_LVDS_MAPPING_LANE2_FMT_0_G_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. " CFG_LVDS_MAPPING_LANE2_FMT_0_F_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--22. " CFG_LVDS_MAPPING_LANE2_FMT_0_F_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19. " CFG_LVDS_MAPPING_LANE2_FMT_0_E_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " CFG_LVDS_MAPPING_LANE2_FMT_0_E_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " CFG_LVDS_MAPPING_LANE2_FMT_0_D_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 12.--14. " CFG_LVDS_MAPPING_LANE2_FMT_0_D_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. " CFG_LVDS_MAPPING_LANE2_FMT_0_C_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " CFG_LVDS_MAPPING_LANE2_FMT_0_C_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. " CFG_LVDS_MAPPING_LANE2_FMT_0_B_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 4.--6. " CFG_LVDS_MAPPING_LANE2_FMT_0_B_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. " CFG_LVDS_MAPPING_LANE2_FMT_0_A_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--2. " CFG_LVDS_MAPPING_LANE2_FMT_0_A_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "CFG_LVDS_MAPPING_LANE3_FMT_0,Lane 3 Mapping Register"
|
|
bitfld.long 0x00 31. " CFG_LVDS_MAPPING_LANE3_FMT_0_H_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 28.--30. " CFG_LVDS_MAPPING_LANE3_FMT_0_H_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27. " CFG_LVDS_MAPPING_LANE3_FMT_0_G_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 24.--26. " CFG_LVDS_MAPPING_LANE3_FMT_0_G_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. " CFG_LVDS_MAPPING_LANE3_FMT_0_F_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--22. " CFG_LVDS_MAPPING_LANE3_FMT_0_F_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19. " CFG_LVDS_MAPPING_LANE3_FMT_0_E_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " CFG_LVDS_MAPPING_LANE3_FMT_0_E_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " CFG_LVDS_MAPPING_LANE3_FMT_0_D_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 12.--14. " CFG_LVDS_MAPPING_LANE3_FMT_0_D_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. " CFG_LVDS_MAPPING_LANE3_FMT_0_C_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " CFG_LVDS_MAPPING_LANE3_FMT_0_C_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. " CFG_LVDS_MAPPING_LANE3_FMT_0_B_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 4.--6. " CFG_LVDS_MAPPING_LANE3_FMT_0_B_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. " CFG_LVDS_MAPPING_LANE3_FMT_0_A_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--2. " CFG_LVDS_MAPPING_LANE3_FMT_0_A_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "CFG_LVDS_MAPPING_LANE0_FMT_1,Lane 0 Mapping Register"
|
|
bitfld.long 0x00 31. " CFG_LVDS_MAPPING_LANE0_FMT_1_H_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 28.--30. " CFG_LVDS_MAPPING_LANE0_FMT_1_H_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27. " CFG_LVDS_MAPPING_LANE0_FMT_1_G_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 24.--26. " CFG_LVDS_MAPPING_LANE0_FMT_1_G_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. " CFG_LVDS_MAPPING_LANE0_FMT_1_F_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--22. " CFG_LVDS_MAPPING_LANE0_FMT_1_F_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x00 19. " CFG_LVDS_MAPPING_LANE0_FMT_1_E_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " CFG_LVDS_MAPPING_LANE0_FMT_1_E_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x00 15. " CFG_LVDS_MAPPING_LANE0_FMT_1_D_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 12.--14. " CFG_LVDS_MAPPING_LANE0_FMT_1_D_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x00 11. " CFG_LVDS_MAPPING_LANE0_FMT_1_C_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " CFG_LVDS_MAPPING_LANE0_FMT_1_C_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x00 7. " CFG_LVDS_MAPPING_LANE0_FMT_1_B_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 4.--6. " CFG_LVDS_MAPPING_LANE0_FMT_1_B_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x00 3. " CFG_LVDS_MAPPING_LANE0_FMT_1_A ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--2. " CFG_LVDS_MAPPING_LANE0_FMT_1_A ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "CFG_LVDS_MAPPING_LANE1_FMT_1,Lane 1 Mapping Register"
|
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bitfld.long 0x00 31. " CFG_LVDS_MAPPING_LANE1_FMT_1_H_[3] ,Entry" "Invalid,Valid"
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bitfld.long 0x00 28.--30. " CFG_LVDS_MAPPING_LANE1_FMT_1_H_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x00 27. " CFG_LVDS_MAPPING_LANE1_FMT_1_G_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 24.--26. " CFG_LVDS_MAPPING_LANE1_FMT_1_G_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x00 23. " CFG_LVDS_MAPPING_LANE1_FMT_1_F_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--22. " CFG_LVDS_MAPPING_LANE1_FMT_1_F_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x00 19. " CFG_LVDS_MAPPING_LANE1_FMT_1_E_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " CFG_LVDS_MAPPING_LANE1_FMT_1_E_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x00 15. " CFG_LVDS_MAPPING_LANE1_FMT_1_D_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 12.--14. " CFG_LVDS_MAPPING_LANE1_FMT_1_D_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x00 11. " CFG_LVDS_MAPPING_LANE1_FMT_1_C_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " CFG_LVDS_MAPPING_LANE1_FMT_1_C_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. " CFG_LVDS_MAPPING_LANE1_FMT_1_B_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 4.--6. " CFG_LVDS_MAPPING_LANE1_FMT_1_B_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. " CFG_LVDS_MAPPING_LANE1_FMT_1_A ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--2. " CFG_LVDS_MAPPING_LANE1_FMT_1_A ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "CFG_LVDS_MAPPING_LANE2_FMT_1,Lane 2 Mapping Register"
|
|
bitfld.long 0x00 31. " CFG_LVDS_MAPPING_LANE2_FMT_1_H_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 28.--30. " CFG_LVDS_MAPPING_LANE2_FMT_1_H_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27. " CFG_LVDS_MAPPING_LANE2_FMT_1_G_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 24.--26. " CFG_LVDS_MAPPING_LANE2_FMT_1_G_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. " CFG_LVDS_MAPPING_LANE2_FMT_1_F_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--22. " CFG_LVDS_MAPPING_LANE2_FMT_1_F_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19. " CFG_LVDS_MAPPING_LANE2_FMT_1_E_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " CFG_LVDS_MAPPING_LANE2_FMT_1_E_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " CFG_LVDS_MAPPING_LANE2_FMT_1_D_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 12.--14. " CFG_LVDS_MAPPING_LANE2_FMT_1_D_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. " CFG_LVDS_MAPPING_LANE2_FMT_1_C_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " CFG_LVDS_MAPPING_LANE2_FMT_1_C_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. " CFG_LVDS_MAPPING_LANE2_FMT_1_B_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 4.--6. " CFG_LVDS_MAPPING_LANE2_FMT_1_B_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. " CFG_LVDS_MAPPING_LANE2_FMT_1_A ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--2. " CFG_LVDS_MAPPING_LANE2_FMT_1_A ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "CFG_LVDS_MAPPING_LANE3_FMT_1,Lane 3 Mapping Register"
|
|
bitfld.long 0x00 31. " CFG_LVDS_MAPPING_LANE3_FMT_1_H_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 28.--30. " CFG_LVDS_MAPPING_LANE3_FMT_1_H_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 27. " CFG_LVDS_MAPPING_LANE3_FMT_1_G_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 24.--26. " CFG_LVDS_MAPPING_LANE3_FMT_1_G_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 23. " CFG_LVDS_MAPPING_LANE3_FMT_1_F_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 20.--22. " CFG_LVDS_MAPPING_LANE3_FMT_1_F_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 19. " CFG_LVDS_MAPPING_LANE3_FMT_1_E_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " CFG_LVDS_MAPPING_LANE3_FMT_1_E_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. " CFG_LVDS_MAPPING_LANE3_FMT_1_D_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 12.--14. " CFG_LVDS_MAPPING_LANE3_FMT_1_D_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. " CFG_LVDS_MAPPING_LANE3_FMT_1_C_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 8.--10. " CFG_LVDS_MAPPING_LANE3_FMT_1_C_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. " CFG_LVDS_MAPPING_LANE3_FMT_1_B_[3] ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 4.--6. " CFG_LVDS_MAPPING_LANE3_FMT_1_B_[0:2] ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 3. " CFG_LVDS_MAPPING_LANE3_FMT_1_A ,Entry" "Invalid,Valid"
|
|
bitfld.long 0x00 0.--2. " CFG_LVDS_MAPPING_LANE3_FMT_1_A ,CBUFF unit to be sent" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
width 19.
|
|
group.long 0x1D0++0x0B
|
|
line.long 0x00 "CFG_LVDS_GEN_0,CFG_LVDS_GEN_0 Register"
|
|
bitfld.long 0x00 30.--31. " CPZ ,LVDS enable internal clock alignment" "Disabled,Enabled,Disabled,Disabled"
|
|
bitfld.long 0x00 28. " CBCRCEN ,LVDS frame CRC" "Not sent,Sent"
|
|
bitfld.long 0x00 24.--27. " CFDLY ,LVDS FIFO initial threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " CMSBF ,First bit of sent data" "LSB,MSB"
|
|
newline
|
|
bitfld.long 0x00 22. " CPOSSEL ,Align first sample start when new chirp is starting" "NEGEDGE,POSEDGE"
|
|
bitfld.long 0x00 15. " CCLKSEL1 ,Clock mode select" "DDR,SDR"
|
|
bitfld.long 0x00 11. " CCSMEN ,Continuous streaming mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CFG_BIT_CLK_MODE ,Bit clock mode" "SDR,DDR"
|
|
newline
|
|
bitfld.long 0x00 3. " CFG_LVDS_LANE3_EN ,Enable LVDS lane 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CFG_LVDS_LANE2_EN ,Enable LVDS lane 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CFG_LVDS_LANE1_EN ,Enable LVDS lane 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFG_LVDS_LANE0_EN ,Enable LVDS lane 0" "Disabled,Enabled"
|
|
line.long 0x04 "CFG_LVDS_GEN_1,CFG_LVDS_GEN_1 Register"
|
|
bitfld.long 0x04 2. " C3C3L ,Enable 3Ch3Lane mode in LVDS" "Disabled,Enabled"
|
|
line.long 0x08 "CFG_LVDS_GEN_2,CFG_LVDS_GEN_2 Register"
|
|
else
|
|
newline
|
|
width 31.
|
|
hgroup.long 0x1B0++0x03
|
|
hide.long 0x00 "CFG_LVDS_MAPPING_LANE0_FMT_0,Lane 0 Mapping Register"
|
|
hgroup.long 0x1B4++0x03
|
|
hide.long 0x00 "CFG_LVDS_MAPPING_LANE1_FMT_0,Lane 1 Mapping Register"
|
|
hgroup.long 0x1B8++0x03
|
|
hide.long 0x00 "CFG_LVDS_MAPPING_LANE2_FMT_0,Lane 2 Mapping Register"
|
|
hgroup.long 0x1BC++0x03
|
|
hide.long 0x00 "CFG_LVDS_MAPPING_LANE3_FMT_0,Lane 3 Mapping Register"
|
|
hgroup.long 0x1C0++0x03
|
|
hide.long 0x00 "CFG_LVDS_MAPPING_LANE0_FMT_1,Lane 0 Mapping Register"
|
|
hgroup.long 0x1C4++0x03
|
|
hide.long 0x00 "CFG_LVDS_MAPPING_LANE1_FMT_1,Lane 1 Mapping Register"
|
|
hgroup.long 0x1C8++0x03
|
|
hide.long 0x00 "CFG_LVDS_MAPPING_LANE2_FMT_1,Lane 2 Mapping Register"
|
|
hgroup.long 0x1CC++0x03
|
|
hide.long 0x00 "CFG_LVDS_MAPPING_LANE3_FMT_1,Lane 3 Mapping Register"
|
|
newline
|
|
width 19.
|
|
hgroup.long 0x1D0++0x03
|
|
hide.long 0x00 "CFG_LVDS_GEN_0,CFG_LVDS_GEN_0 Register"
|
|
hgroup.long 0x1D4++0x03
|
|
hide.long 0x00 "CFG_LVDS_GEN_1,CFG_LVDS_GEN_1 Register"
|
|
hgroup.long 0x1D8++0x03
|
|
hide.long 0x00 "CFG_LVDS_GEN_2,CFG_LVDS_GEN_2 Register"
|
|
endif
|
|
group.long 0x1DC++0x0B
|
|
line.long 0x00 "CFG_MASK_REG0,Mask 0 Register"
|
|
bitfld.long 0x00 12. " S_FRAME_DONE ,CBUFF has completed sending out data for the current frame" "Not masked,Masked"
|
|
bitfld.long 0x00 11. " S_CHIRP_DONE ,CBUFF has completed sending out data for the current chirp" "Not masked,Masked"
|
|
line.long 0x04 "CFG_MASK_REG1,Mask 1 Register"
|
|
bitfld.long 0x04 12. " S_FRAME_ERR ,CBUFF has completed sending out data for the current frame" "Not masked,Masked"
|
|
bitfld.long 0x04 11. " S_CHIRP_ERR ,CBUFF has completed sending out data for the current chirp" "Not masked,Masked"
|
|
line.long 0x08 "CFG_MASK_REG2,Mask 2 Register"
|
|
rgroup.long 0x1EC++0x07
|
|
line.long 0x00 "STAT_CBUFF_REG0,CBUFF Status Register 0"
|
|
bitfld.long 0x00 12. " S_FRAME_DONE ,CBUFF has completed sending out data for the current frame" "No,Yes"
|
|
bitfld.long 0x00 11. " S_CHIRP_DONE ,CBUFF has completed sending out data for the current chirp" "No,Yes"
|
|
line.long 0x04 "STAT_CBUFF_REG1,CBUFF Status Register 1"
|
|
bitfld.long 0x04 17. " S_FRAME_ERR ,CBUFF has completed sending out data for the current frame" "No error,Error"
|
|
bitfld.long 0x04 16. " S_CHIRP_ERR ,CBUFF has completed sending out data for the current chirp" "No error,Error"
|
|
wgroup.long 0x20C++0x03
|
|
line.long 0x00 "CLR_CBUFF_REG0,CBUFF Clear Register 0"
|
|
bitfld.long 0x00 12. " S_FRAME_DONE ,CBUFF has completed sending out data for the current frame" "No effect,Clear"
|
|
bitfld.long 0x00 11. " S_CHIRP_DONE ,CBUFF has completed sending out data for the current chirp" "No effect,Clear"
|
|
rgroup.long 0x21C++0x03
|
|
line.long 0x00 "STAT_CBUFF_ECC_REG,CBUFF Status ECC Register"
|
|
bitfld.long 0x00 9. " SECCDBE ,Double bit error" "No error,Error"
|
|
bitfld.long 0x00 8. " SECCSBE ,Single bit error" "No error,Error"
|
|
hexmask.long.byte 0x00 0.--5. 0x01 " SECCADD ,6-bit address where the ECC error occurred"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "MASK_CBUFF_ECC_REG,CBUFF Mask ECC Register"
|
|
bitfld.long 0x00 9. " MECCDBE ,Mask double bit error" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " MECCSBE ,Mask single bit error" "Not masked,Masked"
|
|
wgroup.long 0x224++0x03
|
|
line.long 0x00 "CLR_CBUFF_ECC_REG,CBUFF Clear ECC Register"
|
|
bitfld.long 0x00 9. " CECCDBE ,Double bit error" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CECCSBE ,Single bit error" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CECCADD ,6-bit address where the ECC error occurred" "No effect,Clear"
|
|
rgroup.long 0x228++0x03
|
|
line.long 0x00 "STAT_SAFETY,Safety Status Register"
|
|
bitfld.long 0x00 8. " SAF_CHIRP_ERR ,Safety error" "No error,Error"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAF_CRC ,CRC error between ADCB and CBUFF"
|
|
group.long 0x22C++0x07
|
|
line.long 0x00 "MASK_SAFETY,Safety Mask Register"
|
|
line.long 0x04 "CLR_SAFETY,Safety Clear Register"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843")
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tree.open "HWA (Hardware Accelerator)"
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tree "ACC_PARAM Registers"
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base ad:0x02080000
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width 11.
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tree "PARAM1"
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group.long 0x0++0x1F
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line.long 0x00 "PARAM1_0,Parameter-Set 0 Register 0"
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bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
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bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
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bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
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newline
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bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
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bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
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bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
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newline
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bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
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bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
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bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
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|
newline
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bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
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bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
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bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
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line.long 0x04 "PARAM1_1,Parameter-Set 0 Register 1"
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hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
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hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
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line.long 0x08 "PARAM1_2,Parameter-Set 0 Register 2"
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bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
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bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
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bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
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newline
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bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
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hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
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bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
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newline
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bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
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bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
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bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
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newline
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hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
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line.long 0x0C "PARAM1_3,Parameter-Set 0 Register 3"
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hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
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hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
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line.long 0x10 "PARAM1_4,Parameter-Set 0 Register 4"
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hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
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hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
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line.long 0x14 "PARAM1_5,Parameter-Set 0 Register 5"
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hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
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bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
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bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
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newline
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hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
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line.long 0x18 "PARAM1_6,Parameter-Set 0 Register 6"
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hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
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hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
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bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
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bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
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bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
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line.long 0x1C "PARAM1_7,Parameter-Set 0 Register 7"
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bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
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bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
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hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
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newline
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hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
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tree.end
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tree "PARAM2"
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group.long 0x20++0x1F
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line.long 0x00 "PARAM2_0,Parameter-Set 1 Register 0"
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bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
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bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
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bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
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newline
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bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
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bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
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bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
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newline
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bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
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bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
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bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
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newline
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bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
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bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
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bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
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line.long 0x04 "PARAM2_1,Parameter-Set 1 Register 1"
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hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
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hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
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line.long 0x08 "PARAM2_2,Parameter-Set 1 Register 2"
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bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
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bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
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bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
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newline
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bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
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hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
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bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
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newline
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bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
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bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
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bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
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newline
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hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
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line.long 0x0C "PARAM2_3,Parameter-Set 1 Register 3"
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hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
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hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
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line.long 0x10 "PARAM2_4,Parameter-Set 1 Register 4"
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hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
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hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
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line.long 0x14 "PARAM2_5,Parameter-Set 1 Register 5"
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hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
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bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
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bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
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newline
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hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
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line.long 0x18 "PARAM2_6,Parameter-Set 1 Register 6"
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hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
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hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
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bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
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bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
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bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
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line.long 0x1C "PARAM2_7,Parameter-Set 1 Register 7"
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bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
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bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
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hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
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newline
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hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
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tree.end
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tree "PARAM3"
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group.long 0x40++0x1F
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line.long 0x00 "PARAM3_0,Parameter-Set 2 Register 0"
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bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
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bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
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bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
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newline
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bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
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bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
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bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
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newline
|
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bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
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bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
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bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
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line.long 0x04 "PARAM3_1,Parameter-Set 2 Register 1"
|
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hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
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hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
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line.long 0x08 "PARAM3_2,Parameter-Set 2 Register 2"
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bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
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bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
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bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
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newline
|
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bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
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hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
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bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
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newline
|
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bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
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bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
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bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
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newline
|
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hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
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line.long 0x0C "PARAM3_3,Parameter-Set 2 Register 3"
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hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
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hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
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line.long 0x10 "PARAM3_4,Parameter-Set 2 Register 4"
|
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hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
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hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
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line.long 0x14 "PARAM3_5,Parameter-Set 2 Register 5"
|
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hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
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bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
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bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
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newline
|
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hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
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line.long 0x18 "PARAM3_6,Parameter-Set 2 Register 6"
|
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hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
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hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM3_7,Parameter-Set 2 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM4"
|
|
group.long 0x60++0x1F
|
|
line.long 0x00 "PARAM4_0,Parameter-Set 3 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM4_1,Parameter-Set 3 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM4_2,Parameter-Set 3 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM4_3,Parameter-Set 3 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM4_4,Parameter-Set 3 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM4_5,Parameter-Set 3 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM4_6,Parameter-Set 3 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM4_7,Parameter-Set 3 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM5"
|
|
group.long 0x80++0x1F
|
|
line.long 0x00 "PARAM5_0,Parameter-Set 4 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM5_1,Parameter-Set 4 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM5_2,Parameter-Set 4 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM5_3,Parameter-Set 4 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM5_4,Parameter-Set 4 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM5_5,Parameter-Set 4 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM5_6,Parameter-Set 4 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM5_7,Parameter-Set 4 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM6"
|
|
group.long 0xA0++0x1F
|
|
line.long 0x00 "PARAM6_0,Parameter-Set 5 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM6_1,Parameter-Set 5 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM6_2,Parameter-Set 5 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM6_3,Parameter-Set 5 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM6_4,Parameter-Set 5 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM6_5,Parameter-Set 5 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM6_6,Parameter-Set 5 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM6_7,Parameter-Set 5 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM7"
|
|
group.long 0xC0++0x1F
|
|
line.long 0x00 "PARAM7_0,Parameter-Set 6 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM7_1,Parameter-Set 6 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM7_2,Parameter-Set 6 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM7_3,Parameter-Set 6 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM7_4,Parameter-Set 6 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM7_5,Parameter-Set 6 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM7_6,Parameter-Set 6 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM7_7,Parameter-Set 6 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM8"
|
|
group.long 0xE0++0x1F
|
|
line.long 0x00 "PARAM8_0,Parameter-Set 7 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM8_1,Parameter-Set 7 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM8_2,Parameter-Set 7 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM8_3,Parameter-Set 7 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM8_4,Parameter-Set 7 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM8_5,Parameter-Set 7 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM8_6,Parameter-Set 7 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM8_7,Parameter-Set 7 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM9"
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "PARAM9_0,Parameter-Set 8 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM9_1,Parameter-Set 8 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM9_2,Parameter-Set 8 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM9_3,Parameter-Set 8 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM9_4,Parameter-Set 8 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM9_5,Parameter-Set 8 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM9_6,Parameter-Set 8 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM9_7,Parameter-Set 8 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM10"
|
|
group.long 0x120++0x1F
|
|
line.long 0x00 "PARAM10_0,Parameter-Set 9 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM10_1,Parameter-Set 9 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM10_2,Parameter-Set 9 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM10_3,Parameter-Set 9 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM10_4,Parameter-Set 9 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM10_5,Parameter-Set 9 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM10_6,Parameter-Set 9 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM10_7,Parameter-Set 9 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM11"
|
|
group.long 0x140++0x1F
|
|
line.long 0x00 "PARAM11_0,Parameter-Set 10 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM11_1,Parameter-Set 10 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM11_2,Parameter-Set 10 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM11_3,Parameter-Set 10 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM11_4,Parameter-Set 10 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM11_5,Parameter-Set 10 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM11_6,Parameter-Set 10 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM11_7,Parameter-Set 10 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM12"
|
|
group.long 0x160++0x1F
|
|
line.long 0x00 "PARAM12_0,Parameter-Set 11 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM12_1,Parameter-Set 11 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM12_2,Parameter-Set 11 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM12_3,Parameter-Set 11 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM12_4,Parameter-Set 11 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM12_5,Parameter-Set 11 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM12_6,Parameter-Set 11 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM12_7,Parameter-Set 11 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM13"
|
|
group.long 0x180++0x1F
|
|
line.long 0x00 "PARAM13_0,Parameter-Set 12 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM13_1,Parameter-Set 12 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM13_2,Parameter-Set 12 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM13_3,Parameter-Set 12 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM13_4,Parameter-Set 12 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM13_5,Parameter-Set 12 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM13_6,Parameter-Set 12 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM13_7,Parameter-Set 12 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM14"
|
|
group.long 0x1A0++0x1F
|
|
line.long 0x00 "PARAM14_0,Parameter-Set 13 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM14_1,Parameter-Set 13 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM14_2,Parameter-Set 13 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM14_3,Parameter-Set 13 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM14_4,Parameter-Set 13 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM14_5,Parameter-Set 13 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM14_6,Parameter-Set 13 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM14_7,Parameter-Set 13 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM15"
|
|
group.long 0x1C0++0x1F
|
|
line.long 0x00 "PARAM15_0,Parameter-Set 14 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM15_1,Parameter-Set 14 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM15_2,Parameter-Set 14 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM15_3,Parameter-Set 14 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM15_4,Parameter-Set 14 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM15_5,Parameter-Set 14 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM15_6,Parameter-Set 14 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM15_7,Parameter-Set 14 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
tree "PARAM16"
|
|
group.long 0x1E0++0x1F
|
|
line.long 0x00 "PARAM16_0,Parameter-Set 15 Register 0"
|
|
bitfld.long 0x00 23.--24. " FFT_OUTPUT_MODE ,Output mode of the FFT engine path" "Default,Default,Max statistic,Sum statistic"
|
|
bitfld.long 0x00 21.--22. " ACCEL_MODE ,Accelerator operation mode" "FFT,CFAR,,NULL"
|
|
bitfld.long 0x00 18.--20. " CMULT_MODE ,Complex multiplier block configuration (mode)" "Disabled,Frequency shifter,Frequency shifter/auto-increment,FFT Stitching,Magnitude squared,Scalar multiplication,Vector multiplication,Vector multiplication 2"
|
|
newline
|
|
bitfld.long 0x00 17. " ABS_EN ,Magnitude computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOG2EN ,Log2 computation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " WINDOW_EN ,Windowing operation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " FFT_EN ,FTT operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BPM_EN ,BPM removal operation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--12. " ACC2DMA_CHANNEL_TRIGDST ,DMA channel trigger select (upon accelerator operation)" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15"
|
|
newline
|
|
bitfld.long 0x00 8. " DMATRIGEN ,Trigger to DMA upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CR4INTREN ,R4F interrupt upon computational operations enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3.--6. " DMA2ACC_CHANNEL_TRIGSRC ,State machine operation trigger select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " TRIGMODE ,Trigger mode configuration" "Immediate,R4F,Ping-pong switch,DMA,?..."
|
|
line.long 0x04 "PARAM16_1,Parameter-Set 15 Register 1"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " DSTADDR ,Destination memory start address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SRCADDR ,Source memory start address"
|
|
line.long 0x08 "PARAM16_2,Parameter-Set 15 Register 2"
|
|
bitfld.long 0x08 31. " DSTCONJ ,Conjugation of the output samples enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " DSTSIGNED ,Signed/unsigned data in the destination memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 29. " DST16B32B ,Data alignment in destination memory" "16-bit,32-bit"
|
|
newline
|
|
bitfld.long 0x08 28. " DSTREAL ,Data output in the destination memory" "Complex,Real"
|
|
hexmask.long.word 0x08 16.--27. 1. " DSTACNT ,Destination sample count"
|
|
bitfld.long 0x08 15. " SRCCONJ ,Conjugation of the input samples enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 14. " SRCSIGNED ,Signed/unsigned data in the source memory" "Unsigned,Signed"
|
|
bitfld.long 0x08 13. " SRC16B32B ,Data alignment in source memory" "16-bit,32-bit"
|
|
bitfld.long 0x08 12. " SRCREAL ,Data input in the source memory" "Complex,Real"
|
|
newline
|
|
hexmask.long.word 0x08 0.--11. 1. " SRCACNT ,Source sample count"
|
|
line.long 0x0C "PARAM16_3,Parameter-Set 15 Register 3"
|
|
hexmask.long.word 0x0C 16.--31. 1. " DSTAINDX ,Destination sample index increment"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SRCAINDX ,Source sample index increment"
|
|
line.long 0x10 "PARAM16_4,Parameter-Set 15 Register 4"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " DSTBINDX ,Destination offset across successive iterations"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " SRCBINDX ,Source offset across successive iterations"
|
|
line.long 0x14 "PARAM16_5,Parameter-Set 15 Register 5"
|
|
hexmask.long.word 0x14 20.--29. 1. " REG_DST_SKIP_INIT ,Destination skip sample count"
|
|
bitfld.long 0x14 16.--19. " REG_DSTSCAL ,Output scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x14 12.--15. " REG_SRCSCAL ,Input scaling" "0,1,2,3,4,5,6,7,8,?..."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. " REG_BCNT ,Number of iterations"
|
|
line.long 0x18 "PARAM16_6,Parameter-Set 15 Register 6"
|
|
hexmask.long.word 0x18 22.--31. 1. " BFLY_SCALING ,Butterfly scaling for each of the 10 butterfly stages"
|
|
hexmask.long.word 0x18 12.--21. 0x10 " WINDOW_START ,Starting address of the window function in the window RAM"
|
|
bitfld.long 0x18 8.--11. " BPMPHASE ,Starting phase of the BPM pattern" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x18 7. " INTERF_THRESH_EN ,Interference zeroing out enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 6. " WINSYMM ,Symmetry of window function" "Not set,Set"
|
|
bitfld.long 0x18 2.--5. " FFTSIZE ,FFT size" ",2,4,8,16,32,64,128,256,512,1024,?..."
|
|
line.long 0x1C "PARAM16_7,Parameter-Set 15 Register 7"
|
|
bitfld.long 0x1C 28.--31. " CIRCSHIFTWRAP ,Sample counter wraparound value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
|
|
bitfld.long 0x1C 26.--27. " WINDOW_INTERP_FRACTION ,Window coefficients linear interpolation configuration" "0,1,2,3"
|
|
hexmask.long.word 0x1C 12.--25. 1. " TWIDINCR ,Frequency de-rotation nature configuration"
|
|
newline
|
|
hexmask.long.word 0x1C 0.--11. 0x01 " CIRCIRSHIFT ,Circular shift (offset in samples)"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "ACC_STATIC Registers"
|
|
base ad:0x02080800
|
|
width 16.
|
|
group.long 0x00++0x3F
|
|
line.long 0x00 "HWACCREG1,Hardware Accelerator Register 1"
|
|
bitfld.long 0x00 28. " FFT1DEN ,FFT1DEN" "0,1"
|
|
bitfld.long 0x00 24.--27. " PARAMSTOP ,PARAMSTOP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " PARAMSTART ,PARAMSTART" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 8.--19. 1. " NLOOPS ,NLOOPS"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " ACCRESET ,Reset" "0,1,2,3,4,5,6,Reset"
|
|
bitfld.long 0x00 3. " ACCCLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " ACCENABLE ,ACCENABLE" "Disabled,,,,,,,Enabled"
|
|
line.long 0x04 "HWACCREG2,Hardware Accelerator Register 2"
|
|
bitfld.long 0x04 15. " DMA2ACCTRIG[15] ,DMA channel 15 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 14. " [14] ,DMA channel 14 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 13. " [13] ,DMA channel 13 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 12. " [12] ,DMA channel 12 completion indication" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,DMA channel 11 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 10. " [10] ,DMA channel 10 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 9. " [9] ,DMA channel 9 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 8. " [8] ,DMA channel 8 completion indication" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,DMA channel 7 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 6. " [6] ,DMA channel 6 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 5. " [5] ,DMA channel 5 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 4. " [4] ,DMA channel 4 completion indication" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,DMA channel 3 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 2. " [2] ,DMA channel 2 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 1. " [1] ,DMA channel 1 completion indication" "Not completed,Completed"
|
|
bitfld.long 0x04 0. " [0] ,DMA channel 0 completion indication" "Not completed,Completed"
|
|
line.long 0x08 "HWACCREG3,Hardware Accelerator Register 3"
|
|
hexmask.long.word 0x08 16.--31. 1. " CR42DMATRIG ,Trigger from CR4 to DMA"
|
|
bitfld.long 0x08 0. " CR42ACCTRIG ,Trigger from CR4 to accelerator" "Not triggered,Triggered"
|
|
line.long 0x0C "HWACCREG4,Hardware Accelerator Register 4"
|
|
hexmask.long.word 0x0C 16.--31. 1. " PARAMDONECLR ,Clear from CR4"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PARAMDONESTAT ,Status to CR4"
|
|
line.long 0x10 "HWACCREG5,Hardware Accelerator Register 5"
|
|
line.long 0x14 "HWACCREG6,Hardware Accelerator Register 6"
|
|
line.long 0x18 "HWACCREG7,Hardware Accelerator Register 7"
|
|
bitfld.long 0x18 24. " STG1LUTSELWR ,Bus matrix write function select" "Window LUT,FFT 1st stage RAM"
|
|
bitfld.long 0x18 16. " DITHERTWIDEN ,DITHERTWIDEN" "0,1"
|
|
hexmask.long.word 0x18 0.--9. 1. " BPMRATE ,BPMRATE"
|
|
line.long 0x1C "HWACCREG8,Hardware Accelerator Register 8"
|
|
bitfld.long 0x1C 24.--28. " FFTSUMDIV ,FFTSUMDIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. " INTERFTHRESH ,INTERFTHRESH"
|
|
line.long 0x20 "HWACCREG9,Hardware Accelerator Register 9"
|
|
hexmask.long.tbyte 0x20 0.--20. 1. " ICMULTSCALE ,ICMULTSCALE"
|
|
line.long 0x24 "HWACCREG10,Hardware Accelerator Register 10"
|
|
hexmask.long.tbyte 0x24 0.--20. 1. " QCMULTSCALE ,QCMULTSCALE"
|
|
line.long 0x28 "HWACCREG11,Hardware Accelerator Register 11"
|
|
bitfld.long 0x28 31. " LFSRLOAD ,LFSRLOAD" "0,1"
|
|
hexmask.long 0x28 0.--28. 1. " LFSRSEED ,LFSRSEED"
|
|
line.long 0x2C "HWACCREG12,Hardware Accelerator Register 12"
|
|
bitfld.long 0x2C 24. " ACC_TRIGGER_IN_CLR ,ACC_TRIGGER_IN_CLR" "0,1"
|
|
hexmask.long.tbyte 0x2C 0.--18. 1. " ACC_TRIGGER_IN_STAT ,ACC_TRIGGER_IN_STAT"
|
|
line.long 0x30 "HWACCREG13,Hardware Accelerator Register 13"
|
|
hexmask.long.tbyte 0x30 0.--17. 1. " CFAR_THRESH ,CFAR threshold"
|
|
line.long 0x34 "HWACCREG14,Hardware Accelerator Register 14"
|
|
bitfld.long 0x34 8.--10. " OUTRAMAONIN ,Two output RAMS array control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 4.--6. " OUTRAMAGOODIN ,Two output RAMS array control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x34 0.--2. " OUTRAMISO ,Two output RAMS isolation control" "0,1,2,3,4,5,6,7"
|
|
line.long 0x38 "HWACCREG15,Hardware Accelerator Register 15"
|
|
line.long 0x3C "HWACCREG16,Hardware Accelerator Register 16"
|
|
rgroup.long 0x40++0x17
|
|
line.long 0x00 "MAX1VALUE,Max 1 Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " MAX1VALUE ,MAX1VALUE"
|
|
line.long 0x04 "MAX1INDEX,Max 1 Index Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " MAX1INDEX ,MAX1INDEX"
|
|
line.long 0x08 "ISUM1LSB,ISUM1LSB Register"
|
|
line.long 0x0C "ISUM1MSB,ISUM1MSB Register"
|
|
bitfld.long 0x0C 0.--3. " ISUM1MSB ,ISUM1MSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "QSUM1LSB,QSUM1LSB Register"
|
|
line.long 0x14 "QSUM1MSB,QSUM1MSB Register"
|
|
bitfld.long 0x14 0.--3. " QSUM1MSB ,QSUM1MSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x58++0x17
|
|
line.long 0x00 "MAX2VALUE,Max 2 Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " MAX2VALUE ,MAX2VALUE"
|
|
line.long 0x04 "MAX2INDEX,Max 2 Index Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " MAX2INDEX ,MAX2INDEX"
|
|
line.long 0x08 "ISUM2LSB,ISUM2LSB Register"
|
|
line.long 0x0C "ISUM2MSB,ISUM2MSB Register"
|
|
bitfld.long 0x0C 0.--3. " ISUM2MSB ,ISUM2MSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "QSUM2LSB,QSUM2LSB Register"
|
|
line.long 0x14 "QSUM2MSB,QSUM2MSB Register"
|
|
bitfld.long 0x14 0.--3. " QSUM2MSB ,QSUM2MSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x70++0x17
|
|
line.long 0x00 "MAX3VALUE,Max 3 Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " MAX3VALUE ,MAX3VALUE"
|
|
line.long 0x04 "MAX3INDEX,Max 3 Index Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " MAX3INDEX ,MAX3INDEX"
|
|
line.long 0x08 "ISUM3LSB,ISUM3LSB Register"
|
|
line.long 0x0C "ISUM3MSB,ISUM3MSB Register"
|
|
bitfld.long 0x0C 0.--3. " ISUM3MSB ,ISUM3MSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "QSUM3LSB,QSUM3LSB Register"
|
|
line.long 0x14 "QSUM3MSB,QSUM3MSB Register"
|
|
bitfld.long 0x14 0.--3. " QSUM3MSB ,QSUM3MSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x88++0x17
|
|
line.long 0x00 "MAX4VALUE,Max 4 Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " MAX4VALUE ,MAX4VALUE"
|
|
line.long 0x04 "MAX4INDEX,Max 4 Index Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " MAX4INDEX ,MAX4INDEX"
|
|
line.long 0x08 "ISUM4LSB,ISUM4LSB Register"
|
|
line.long 0x0C "ISUM4MSB,ISUM4MSB Register"
|
|
bitfld.long 0x0C 0.--3. " ISUM4MSB ,ISUM4MSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "QSUM4LSB,QSUM4LSB Register"
|
|
line.long 0x14 "QSUM4MSB,QSUM4MSB Register"
|
|
bitfld.long 0x14 0.--3. " QSUM4MSB ,QSUM4MSB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xA0++0x0B
|
|
line.long 0x00 "DCOFFSETI,DCOFFSETI Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 0x01 " DCOFFSETI ,DCOFFSETI"
|
|
line.long 0x04 "DCOFFSETQ,DCOFFSETQ Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 0x01 " DCOFFSETQ ,DCOFFSETQ"
|
|
line.long 0x08 "CFARTEST,CFARTEST Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CFARTEST ,CFARTEST"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "RDSTATUS,RDSTATUS Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " LOOPCNT ,LOOPCNT"
|
|
hexmask.long.byte 0x00 0.--3. 0x01 " PARAMADDR ,PARAMADDR"
|
|
rgroup.long 0xB0++0x03
|
|
line.long 0x00 "SIGDMACH1DONE,SIGDMACH1DONE Register"
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "SIGDMACH2DONE,SIGDMACH2DONE Register"
|
|
rgroup.long 0xB8++0x03
|
|
line.long 0x00 "SIGDMACH3DONE,SIGDMACH3DONE Register"
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "SIGDMACH4DONE,SIGDMACH4DONE Register"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "SIGDMACH5DONE,SIGDMACH5DONE Register"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "SIGDMACH6DONE,SIGDMACH6DONE Register"
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "SIGDMACH7DONE,SIGDMACH7DONE Register"
|
|
rgroup.long 0xCC++0x03
|
|
line.long 0x00 "SIGDMACH8DONE,SIGDMACH8DONE Register"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "SIGDMACH9DONE,SIGDMACH9DONE Register"
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "SIGDMACH10DONE,SIGDMACH10DONE Register"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "SIGDMACH11DONE,SIGDMACH11DONE Register"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "SIGDMACH12DONE,SIGDMACH12DONE Register"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "SIGDMACH13DONE,SIGDMACH13DONE Register"
|
|
rgroup.long 0xE4++0x03
|
|
line.long 0x00 "SIGDMACH14DONE,SIGDMACH14DONE Register"
|
|
rgroup.long 0xE8++0x03
|
|
line.long 0x00 "SIGDMACH15DONE,SIGDMACH15DONE Register"
|
|
rgroup.long 0xEC++0x03
|
|
line.long 0x00 "SIGDMACH16DONE,SIGDMACH16DONE Register"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "MEMACCESSERR,MEMACCESSERR Register"
|
|
rbitfld.long 0x00 16.--19. " STATERRCODE ,Error status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--11. 1. " ERRCODEMASK ,Mask for STATERRCODE"
|
|
rbitfld.long 0x00 0.--3. " ERRCODECLR ,Error code clear" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xF4++0x13
|
|
line.long 0x00 "FFTCLIP,FFTCLIP Register"
|
|
bitfld.long 0x00 16. " CLRFFTCLIPSTAT ,CLRFFTCLIPSTAT" "0,1"
|
|
hexmask.long.word 0x00 0.--9. 1. " FFTCLCIPSTAT ,FFTCLCIPSTAT"
|
|
line.long 0x04 "FFTPEAKCNT,FFTPEAKCNT Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " FFTPEAKCNT ,FFTPEAKCNT"
|
|
line.long 0x08 "HWACCREG1RD,HWACCREG1RD Register"
|
|
line.long 0x0C "HWACCREG2RD,HWACCREG2RD Register"
|
|
line.long 0x10 "HWACCREG3RD,HWACCREG3RD Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.open "MAILBOX (Mailbox)"
|
|
tree "BSS_MBOX4MSS"
|
|
base ad:0x04608000
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INT_MASK_SET/CLR,INT_MASK Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " MAILBOX_ACK_INT_MASK ,Mailbox acknowledge interrupt mask" "Unmasked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " MAILBOX_INT_MASK ,Mailbox interrupt mask" "Unmasked,Masked"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "INT_STS_CLR,INT_STS_CLR Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_STS_CLR ,Acknowledge interrupt status register clear" "Clear,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_CLR ,Interrupt status register clear" "Clear,Clear"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "INT_ACK,INT_ACK Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "INT_TRIG,INT_TRIG Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_TRIG ,Indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_TRIG ,Trigger interrupt and indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "INT_STS_MASKED,INT_STS_MASKED Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_MASKED ,Current status of mailbox empty interrupt if it is not masked" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_MASKED ,Current status of mailbox full interrupt if it is not masked" "No interrupt,Interrupt"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "INT_STS_RAW,INT_STS_RAW Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_RAW ,Current status of mailbox empty interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_RAW ,Current status of mailbox full interrupt" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BSS_MBOX4GEM"
|
|
base ad:0x04608100
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INT_MASK_SET/CLR,INT_MASK Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " MAILBOX_ACK_INT_MASK ,Mailbox acknowledge interrupt mask" "Unmasked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " MAILBOX_INT_MASK ,Mailbox interrupt mask" "Unmasked,Masked"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "INT_STS_CLR,INT_STS_CLR Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_STS_CLR ,Acknowledge interrupt status register clear" "Clear,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_CLR ,Interrupt status register clear" "Clear,Clear"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "INT_ACK,INT_ACK Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "INT_TRIG,INT_TRIG Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_TRIG ,Indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_TRIG ,Trigger interrupt and indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "INT_STS_MASKED,INT_STS_MASKED Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_MASKED ,Current status of mailbox empty interrupt if it is not masked" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_MASKED ,Current status of mailbox full interrupt if it is not masked" "No interrupt,Interrupt"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "INT_STS_RAW,INT_STS_RAW Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_RAW ,Current status of mailbox empty interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_RAW ,Current status of mailbox full interrupt" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GEM_MBOX4BSS"
|
|
base ad:0x04608200
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INT_MASK_SET/CLR,INT_MASK Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " MAILBOX_ACK_INT_MASK ,Mailbox acknowledge interrupt mask" "Unmasked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " MAILBOX_INT_MASK ,Mailbox interrupt mask" "Unmasked,Masked"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "INT_STS_CLR,INT_STS_CLR Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_STS_CLR ,Acknowledge interrupt status register clear" "Clear,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_CLR ,Interrupt status register clear" "Clear,Clear"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "INT_ACK,INT_ACK Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "INT_TRIG,INT_TRIG Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_TRIG ,Indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_TRIG ,Trigger interrupt and indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "INT_STS_MASKED,INT_STS_MASKED Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_MASKED ,Current status of mailbox empty interrupt if it is not masked" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_MASKED ,Current status of mailbox full interrupt if it is not masked" "No interrupt,Interrupt"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "INT_STS_RAW,INT_STS_RAW Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_RAW ,Current status of mailbox empty interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_RAW ,Current status of mailbox full interrupt" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MSS_MBOX4GEM"
|
|
base ad:0x04608300
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INT_MASK_SET/CLR,INT_MASK Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " MAILBOX_ACK_INT_MASK ,Mailbox acknowledge interrupt mask" "Unmasked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " MAILBOX_INT_MASK ,Mailbox interrupt mask" "Unmasked,Masked"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "INT_STS_CLR,INT_STS_CLR Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_STS_CLR ,Acknowledge interrupt status register clear" "Clear,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_CLR ,Interrupt status register clear" "Clear,Clear"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "INT_ACK,INT_ACK Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "INT_TRIG,INT_TRIG Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_TRIG ,Indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_TRIG ,Trigger interrupt and indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "INT_STS_MASKED,INT_STS_MASKED Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_MASKED ,Current status of mailbox empty interrupt if it is not masked" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_MASKED ,Current status of mailbox full interrupt if it is not masked" "No interrupt,Interrupt"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "INT_STS_RAW,INT_STS_RAW Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_RAW ,Current status of mailbox empty interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_RAW ,Current status of mailbox full interrupt" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GEM_MBOX4MSS"
|
|
base ad:0x04608400
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INT_MASK_SET/CLR,INT_MASK Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " MAILBOX_ACK_INT_MASK ,Mailbox acknowledge interrupt mask" "Unmasked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " MAILBOX_INT_MASK ,Mailbox interrupt mask" "Unmasked,Masked"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "INT_STS_CLR,INT_STS_CLR Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_STS_CLR ,Acknowledge interrupt status register clear" "Clear,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_CLR ,Interrupt status register clear" "Clear,Clear"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "INT_ACK,INT_ACK Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "INT_TRIG,INT_TRIG Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_TRIG ,Indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_TRIG ,Trigger interrupt and indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "INT_STS_MASKED,INT_STS_MASKED Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_MASKED ,Current status of mailbox empty interrupt if it is not masked" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_MASKED ,Current status of mailbox full interrupt if it is not masked" "No interrupt,Interrupt"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "INT_STS_RAW,INT_STS_RAW Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_RAW ,Current status of mailbox empty interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_RAW ,Current status of mailbox full interrupt" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree "MSS_MBOX4BSS"
|
|
base ad:0x04608600
|
|
width 18.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INT_MASK_SET/CLR,INT_MASK Set/Clear Register"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " MAILBOX_ACK_INT_MASK ,Mailbox acknowledge interrupt mask" "Unmasked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " MAILBOX_INT_MASK ,Mailbox interrupt mask" "Unmasked,Masked"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "INT_STS_CLR,INT_STS_CLR Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_STS_CLR ,Acknowledge interrupt status register clear" "Clear,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_CLR ,Interrupt status register clear" "Clear,Clear"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "INT_ACK,INT_ACK Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_ACK ,Corresponding bit in status register clear" "No effect,Clear"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "INT_TRIG,INT_TRIG Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_TRIG ,Indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_TRIG ,Trigger interrupt and indicate to other system that read from mailbox is complete" "Not completed,Completed"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "INT_STS_MASKED,INT_STS_MASKED Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_MASKED ,Current status of mailbox empty interrupt if it is not masked" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_MASKED ,Current status of mailbox full interrupt if it is not masked" "No interrupt,Interrupt"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "INT_STS_RAW,INT_STS_RAW Register"
|
|
bitfld.long 0x00 1. " MAILBOX_ACK_STS_RAW ,Current status of mailbox empty interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MAILBOX_INT_STS_RAW ,Current status of mailbox full interrupt" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif cpuis("AWR1843*")||cpuis("AWR6843*")
|
|
tree "SCI (Serial Communication Interface)"
|
|
base ad:0x02030000
|
|
width 22.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "SCIGCR0,SCI Global Control Register 0"
|
|
bitfld.long 0x00 0. " RESET ,SCI module reset" "Reset,No reset"
|
|
line.long 0x04 "SCIGCR1,SCI Global Control Register 1"
|
|
bitfld.long 0x04 25. " TXENA ,Transmit enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " RXENA ,Receive enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CONT ,Continue on suspend" "Frozen,Continued"
|
|
bitfld.long 0x04 16. " LOOPBACK ,Loopback enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " POWERDOWN ,Low-power mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 8. " SLEEP ,Sleep mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " SWNRST ,Software reset enable" "Low,High"
|
|
bitfld.long 0x04 5. " CLOCK ,SCI internal clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " STOP ,SCI number of stop bits per frame" "One,Two"
|
|
bitfld.long 0x04 3. " PARITY ,SCI parity odd/even selection" "Odd,Even"
|
|
newline
|
|
bitfld.long 0x04 2. " PARITY_ENA ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TIMING_MODE ,SCI timing mode bit" "Synchronous,Asynchronous"
|
|
bitfld.long 0x04 0. " COMM_MODE ,SCI communication mode bit" "Idle-line,Address-bit"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SCISETINT_SET/CLR,SCI Set/Clear Interrupt Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FEINT ,Framing-error interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OEINT ,Overrun-error interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PEINT ,Parity interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RXDMAALL ,Receive DMA all" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RXDMA ,Receive DMA" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TXDMA ,Transmit DMA" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RXINT ,Receiver interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TXINT ,Transmitter interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUPINT ,Wakeup interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDTINT ,Break detect interrupt" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SCISETINTLVL_SET/CLR,SCI Set/Clear Interrupt Level Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FEINT ,Framing-error interrupt level" "0,1"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OEINT ,Overrun-error interrupt level" "0,1"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PEINT ,Parity interrupt level" "0,1"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RXDMAALL ,Receive DMA all level" "0,1"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RXDMA ,Receive DMA level" "0,1"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TXDMA ,Transmit DMA level" "0,1"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RXINT ,Receiver interrupt enable level" "0,1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TXINT ,Transmitter interrupt level" "0,1"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUPINT ,Wakeup interrupt level" "0,1"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDTINT ,Break detect interrupt level" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SCIFLR,SCI Flags Register"
|
|
eventfld.long 0x00 26. " FE ,Framing error flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 25. " OE ,Overrun error flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 24. " PE ,Parity error flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " RXWAKE ,Receiver wakeup detect flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 11. " TXEMPTY ,Transmitter empty flag" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 10. " TXWAKE ,Transmitter wakeup method select" "Data,Address"
|
|
eventfld.long 0x00 9. " RXRDY ,Receiver ready flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 8. " TXRDY ,Transmitter buffer register ready flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " BUSY ,Bus busy flag" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " IDLE ,SCI receiver in idle state" "Idle,Not idle"
|
|
newline
|
|
eventfld.long 0x00 1. " WAKEUP ,Wakeup flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 0. " BRKDT ,SCI break-detect flag" "Not occurred,Occurred"
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "SCIINTVECT0,SCI Interrupt Vector Offset 0"
|
|
bitfld.long 0x00 0.--3. " INVECT0 ,Interrupt vector offset for INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "SCIINTVECT1,SCI Interrupt Vector Offset 1"
|
|
bitfld.long 0x04 0.--3. " INVECT1 ,Interrupt vector offset for INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "SCIFORMAT,SCI Format Control Register"
|
|
bitfld.long 0x00 0.--2. " CHAR ,Character length control bits" "1,2,3,4,5,6,7,8"
|
|
line.long 0x04 "BRS,Baud Rate Selection Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " BAUD ,SCI 24-bit baud rate"
|
|
width 7.
|
|
rgroup.long 0x30++0x07 "SCI Data Buffers"
|
|
line.long 0x00 "SCIED,Receiver Emulation Data Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulator data"
|
|
line.long 0x04 "SCIRD,Receiver Data Buffer"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RD ,Receiver data"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SCITD,Transmit Data Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit data"
|
|
width 9.
|
|
group.long 0x3C++0x07 "SCI Pin I/O Control Registers"
|
|
line.long 0x00 "SCIPIO0,SCI Pin I/O Control Register 0"
|
|
bitfld.long 0x00 2. " TXFUNC ,Transfer function" "Digital I/O,Transmit pin"
|
|
bitfld.long 0x00 1. " RXFUNC ,Receive function" "Digital I/O,Receive pin"
|
|
line.long 0x04 "SCIPIO1,SCI Pin I/O Control Register 1"
|
|
bitfld.long 0x04 2. " TXDIR ,Transfer pin direction" "Input,Output"
|
|
bitfld.long 0x04 1. " RXDIR ,Receive pin direction" "Input,Output"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "SCIPIO2,SCI Pin I/O Control Register 2"
|
|
bitfld.long 0x00 2. " TXIN ,Transfer pin in" "Low,High"
|
|
bitfld.long 0x00 1. " RXIN ,Receive pin in" "Low,High"
|
|
group.long 0x48++0x17
|
|
line.long 0x00 "SCIPIO3,SCI Pin I/O Control Register 3"
|
|
bitfld.long 0x00 2. " TXOUT ,Transfer pin out" "Low,High"
|
|
bitfld.long 0x00 1. " RXOUT ,Receive pin out" "Low,High"
|
|
line.long 0x04 "SCIPIO4,SCI Pin I/O Control Register 4"
|
|
bitfld.long 0x04 2. " TXSET ,Transfer pin set" "Low,High"
|
|
bitfld.long 0x04 1. " RXSET ,Receive pin set" "Low,High"
|
|
line.long 0x08 "SCIPIO5,SCI Pin I/O Control Register 5"
|
|
bitfld.long 0x08 2. " TXCLR ,Transfer pin clear" "Low,High"
|
|
bitfld.long 0x08 1. " RXCLR ,Receive pin clear" "Low,High"
|
|
line.long 0x0C "SCIPIO6,SCI Pin I/O Control Register 6"
|
|
bitfld.long 0x0C 2. " TXPDR ,Transfer pin open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " RXPDR ,Receive pin open drain enable" "Disabled,Enabled"
|
|
line.long 0x10 "SCIPIO7,SCI Pin I/O Control Register 7"
|
|
bitfld.long 0x10 2. " TXPD ,Transfer pin pull control disable" "No,Yes"
|
|
bitfld.long 0x10 1. " RXPD ,Receive pin pull control disable" "No,Yes"
|
|
line.long 0x14 "SCIPIO8,SCI Pin I/O Control Register 8"
|
|
bitfld.long 0x14 2. " TXPSL ,Transfer pin pull select" "Down,Up"
|
|
bitfld.long 0x14 1. " RXPSL ,Receive pin pull select" "Down,Up"
|
|
newline
|
|
width 11.
|
|
if (((per.l(ad:0x02030000+0x90))&0xF00)==0xA00)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "IODFTCTRL,Input/Output Error Enable Register"
|
|
bitfld.long 0x00 26. " FEN ,Frame error enable" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " PEN ,Parity error enable" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " BRKD_TENA ,Break detect error enable" "Not occurred,Occurred"
|
|
bitfld.long 0x00 19.--20. " PIN_SAMPLE_MASK ,Pin sample mask" "No mask,7th SCLK,8th SCLK,9th SCLK"
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Pin sample mask" "No delay,/1SCLK,/2SCLK,/3SCLK,/4SCLK,/5SCLK,/6SCLK,/7SCLK"
|
|
newline
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IODFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXPENA ,Module analog loopback through receive pin enable" "Transmit,Receive"
|
|
else
|
|
hgroup.long 0x90++0x03
|
|
hide.long 0x00 "IODFTCTRL,Input/Output Error Enable Register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "SCI (Serial Communication Interface)"
|
|
base ad:0x02030000
|
|
width 11.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GCR0,SCI Global Control Register 0"
|
|
bitfld.long 0x00 0. " RESET ,SCI module reset" "Reset,No reset"
|
|
if (((per.l(ad:0x02030000+0x04))&0x04)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GCR1,SCI Global Control Register 1"
|
|
bitfld.long 0x00 25. " TXENA ,SCI transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CONT ,Continue on suspend" "Frozen,Continued"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,Loop back mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POWERDOWN ,Power down" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI sleep enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SW_NRESET ,Software reset" "Reset,Ready"
|
|
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 4. " STOP ,SCI number of stop bits per frame" "1 bit,2 bits"
|
|
bitfld.long 0x00 3. " PARITY ,SCI parity odd/even selection" "Odd,Even"
|
|
bitfld.long 0x00 2. " PARITY_ENA ,Parity enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI timing mode" "Synchronous,Asynchronous"
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI communication mode" "Idle-line,Address-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GCR1,SCI Global Control Register 1"
|
|
bitfld.long 0x00 25. " TXENA ,SCI transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " RXENA ,SCI receiver enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CONT ,Continue on suspend" "Frozen,Continued"
|
|
bitfld.long 0x00 16. " LOOP_BACK ,Loop back mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POWERDOWN ,Power down" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SLEEP ,SCI sleep enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SW_NRESET ,Software reset" "Reset,Ready"
|
|
bitfld.long 0x00 5. " CLOCK ,SCI internal clock enable" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 4. " STOP ,SCI number of stop bits per frame" "1 bit,2 bits"
|
|
bitfld.long 0x00 2. " PARITY_ENA ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMING_MODE ,SCI timing mode" "Synchronous,Asynchronous"
|
|
textline " "
|
|
bitfld.long 0x00 0. " COMM_MODE ,SCI communication mode" "Idle-line,Address-bit"
|
|
endif
|
|
textline " "
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SETINT,SCI Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_SET/CLR ,Framing-error interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_SET/CLR ,Overrun-error interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_SET/CLR ,Parity interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_SET/CLR ,Receive DMA all" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_SET/CLR ,Receive DMA" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_SET/CLR ,Transmit DMA" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_SET/CLR ,Receiver interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_SET/CLR ,Transmitter interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_SET/CLR ,Wake-up interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_SET/CLR ,Break-detect interrupt" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SETINTLVL,SCI Interrupt Level Set/Clear Register"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_SET/CLR ,Framing-error interrupt level" "INT0,INT1"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_SET/CLR ,Overrun-error interrupt level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_SET/CLR ,Parity error interrupt level" "INT0,INT1"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_INT_LVL_SET/CLR ,Receive DMA all interrupt level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_SET/CLR ,Receiver interrupt level" "INT0,INT1"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_SET/CLR ,Transmitter interrupt level" "INT0,INT1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_SET/CLR ,Wake-up interrupt level" "INT0,INT1"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_SET/CLR ,Break-detect interrupt level" "INT0,INT1"
|
|
textline " "
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FLR,SCI Flags Register"
|
|
eventfld.long 0x00 26. " FE ,Framing error flag" "No error,Error"
|
|
eventfld.long 0x00 25. " OE ,Overrun error flag" "No error,Error"
|
|
eventfld.long 0x00 24. " PE ,Parity error flag" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RXWAKE ,Receiver wakeup detect flag" "Not address,Address"
|
|
bitfld.long 0x00 11. " TX_EMPTY ,Transmitter empty flag" "Not empty,Empty"
|
|
bitfld.long 0x00 10. " TXWAKE ,SCI transmitter wakeup method select" "Data,Address"
|
|
textline " "
|
|
eventfld.long 0x00 9. " RXRDY ,Receiver ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " TXRDY ,Transmitter buffer register ready flag" "Full,Ready"
|
|
bitfld.long 0x00 3. " BUSY ,BUSY flag" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLE ,SCI receiver in idle state" "Detected,Not detected"
|
|
eventfld.long 0x00 1. " WAKEUP ,Wake-up flag" "No wake up,Wake up"
|
|
eventfld.long 0x00 0. " BRKDT ,SCI break-detect flag" "Not detected,Detected"
|
|
textline " "
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "INVECT0,SCI Interrupt Vector Offset 0"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "INVECT1,SCI Interrupt Vector Offset 1"
|
|
in
|
|
textline " "
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "FORMAT,SCI Format Control Register"
|
|
bitfld.long 0x00 0.--2. " CHAR ,SCI character length" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
|
|
line.long 0x04 "BRS,Baud Rate Selection Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " BAUD ,SCI 24-bit baud selection"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "ED,Receiver Emulation Data Buffer"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulator data"
|
|
textline " "
|
|
hgroup.long 0x34++0x03
|
|
hide.long 0x00 "RD,Receiver Data Buffer"
|
|
in
|
|
textline " "
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "TD,Transmit Data Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit data"
|
|
line.long 0x04 "PIO0,SCI Pin I/O Control Register 0"
|
|
bitfld.long 0x04 2. " TX_FUNC ,Defines the function of pin SCITX" "GPIO,SCI"
|
|
bitfld.long 0x04 1. " RX_FUNC ,Defines the function of pin SCIRX" "GPIO,SCI"
|
|
if (((per.l(ad:0x02030000+0x3C))&0x06)==0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PIO1,SCI Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit direction" "Input,Output"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive direction" "Input,Output"
|
|
elif (((per.l(ad:0x02030000+0x3C))&0x06)==0x02)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PIO1,SCI Pin I/O Control Register 1"
|
|
bitfld.long 0x00 2. " TX_DIR ,Transmit direction" "Input,Output"
|
|
elif (((per.l(ad:0x02030000+0x3C))&0x06)==0x04)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PIO1,SCI Pin I/O Control Register 1"
|
|
bitfld.long 0x00 1. " RX_DIR ,Receive direction" "Input,Output"
|
|
else
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "PIO1,SCI Pin I/O Control Register 1"
|
|
endif
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "PIO2,SCI Pin I/O Control Register 2"
|
|
bitfld.long 0x00 2. " TX_IN ,Current value on the SCITX pin" "Low,High"
|
|
bitfld.long 0x00 1. " RX_IN ,Current value on the SCIRX pin" "Low,High"
|
|
if (((per.l(ad:0x02030000+0x3C))&0x06)==0x00)&&(((per.l(ad:0x02030000+0x40))&0x06)==0x06)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO3,SCI Pin I/O Control Register 3"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX_OUT_SET/CLR ,SCITX pin data output" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX_OUT_SET/CLR ,SCIRX pin data output" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PIO6,SCI Pin I/O Control Register 6"
|
|
bitfld.long 0x00 2. " TX_PDR ,TX pin open drain enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RX_PDR ,RX pin open drain enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x02030000+0x3C))&0x04)==0x00)&&(((per.l(ad:0x02030000+0x40))&0x04)==0x04)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO3,SCI Pin I/O Control Register 3"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX_OUT_SET/CLR ,SCITX pin data output" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PIO6,SCI Pin I/O Control Register 6"
|
|
bitfld.long 0x00 2. " TX_PDR ,TX pin open drain enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x02030000+0x3C))&0x02)==0x00)&&(((per.l(ad:0x02030000+0x40))&0x02)==0x02)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PIO3,SCI Pin I/O Control Register 3"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX_OUT_SET/CLR ,SCIRX pin data output" "Low,High"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PIO6,SCI Pin I/O Control Register 6"
|
|
bitfld.long 0x00 1. " RX_PDR ,RX pin open drain enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "PIO3,SCI Pin I/O Control Register 3"
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "PIO6,SCI Pin I/O Control Register 6"
|
|
endif
|
|
group.long 0x58++0x07
|
|
line.long 0x00 "PIO7,SCI Pin I/O Control Register 7"
|
|
bitfld.long 0x00 2. " TX_PD ,TX pin pull control disable" "No,Yes"
|
|
bitfld.long 0x00 1. " RX_PD ,RX pin pull control disable" "No,Yes"
|
|
line.long 0x04 "PIO8,SCI Pin I/O Control Register 8"
|
|
bitfld.long 0x04 2. " TX_PSL ,TX pin pull select" "Pull down,Pull up"
|
|
bitfld.long 0x04 1. " RX_PSL ,RX pin pull select" "Pull down,Pull up"
|
|
textline " "
|
|
if (((per.l(ad:0x02030000+0x90))&0xF00)==0xA00)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "IODFTCTRL,Input/Output Error Enable Register"
|
|
bitfld.long 0x00 26. " FEN ,Frame error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PEN ,Parity error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " BRKD_TENA ,Break detect error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--20. " PSM ,Pin sample mask" "Not used,Inverted at 7th SCLK,Inverted at 8th SCLK,Inverted at 9th SCLK"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit shift" "No delay,1 SCLK,2 SCLK,3 SCLK,4 SCLK,5 SCLK,6 SCLK,No delay"
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IODFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,Analog"
|
|
bitfld.long 0x00 0. " RXPENA ,Module analog loopback through receive/transmit pin enable" "Transmit,Receive"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "IODFTCTRL,Input/Output Error Enable Register"
|
|
bitfld.long 0x00 26. " FEN ,Frame error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PEN ,Parity error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " BRKD_TENA ,Break detect error enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "Not used,Inverted at 7th SCLK,Inverted at 8th SCLK,Inverted at 9th SCLK"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit shift" "No delay,1 SCLK,2 SCLK,3 SCLK,4 SCLK,5 SCLK,6 SCLK,No delay"
|
|
bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LPBENA ,Module loopback enable" "Digital,?..."
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "ESM (Error Signaling Module)"
|
|
base ad:0x020D0000
|
|
width 19.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ESMIEPSR1_SET/CLR,ESM Influence Error Pin Set/Status Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " IEPSET[31] ,Set/Clear influence on error pin 31" "No influence,Influence"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear influence on error pin 30" "No influence,Influence"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Set/Clear influence on error pin 29" "No influence,Influence"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear influence on error pin 28" "No influence,Influence"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear influence on error pin 27" "No influence,Influence"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear influence on error pin 26" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Set/Clear influence on error pin 25" "No influence,Influence"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear influence on error pin 24" "No influence,Influence"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear influence on error pin 23" "No influence,Influence"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear influence on error pin 22" "No influence,Influence"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear influence on error pin 21" "No influence,Influence"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/Clear influence on error pin 20" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear influence on error pin 19" "No influence,Influence"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear influence on error pin 18" "No influence,Influence"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear influence on error pin 17" "No influence,Influence"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear influence on error pin 16" "No influence,Influence"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear influence on error pin 15" "No influence,Influence"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear influence on error pin 14" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear influence on error pin 13" "No influence,Influence"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear influence on error pin 12" "No influence,Influence"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear influence on error pin 11" "No influence,Influence"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear influence on error pin 10" "No influence,Influence"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear influence on error pin 9" "No influence,Influence"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear influence on error pin 8" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear influence on error pin 7" "No influence,Influence"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear influence on error pin 6" "No influence,Influence"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear influence on error pin 5" "No influence,Influence"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/Clear influence on error pin 4" "No influence,Influence"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear influence on error pin 3" "No influence,Influence"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear influence on error pin 2" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear influence on error pin 1" "No influence,Influence"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set/Clear influence on error pin 0" "No influence,Influence"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ESMIESR1_SET/CLR,ESM Interrupt Enable Set/Status Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTENSET[31] ,Set/Clear interrupt enable 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear interrupt enable 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Set/Clear interrupt enable 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear interrupt enable 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear interrupt enable 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear interrupt enable 26" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Set/Clear interrupt enable 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear interrupt enable 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear interrupt enable 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear interrupt enable 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear interrupt enable 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/Clear interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear interrupt enable 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear interrupt enable 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear interrupt enable 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear interrupt enable 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear interrupt enable 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear interrupt enable 14" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear interrupt enable 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear interrupt enable 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear interrupt enable 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear interrupt enable 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt enable 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear interrupt enable 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear interrupt enable 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear interrupt enable 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/Clear interrupt enable 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear interrupt enable 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear interrupt enable 2" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear interrupt enable 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set/Clear interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ESMILSR1_SET/CLR,ESM Interrupt Level Set/Status Register 1"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVLSET[31] ,Set/Clear interrupt level 31" "Low,High"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear interrupt level 30" "Low,High"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Set/Clear interrupt level 29" "Low,High"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear interrupt level 28" "Low,High"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear interrupt level 27" "Low,High"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear interrupt level 26" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Set/Clear interrupt level 25" "Low,High"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear interrupt level 24" "Low,High"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear interrupt level 23" "Low,High"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear interrupt level 22" "Low,High"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear interrupt level 21" "Low,High"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/Clear interrupt level 20" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear interrupt level 19" "Low,High"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear interrupt level 18" "Low,High"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear interrupt level 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear interrupt level 16" "Low,High"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear interrupt level 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear interrupt level 14" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear interrupt level 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear interrupt level 12" "Low,High"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear interrupt level 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear interrupt level 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt level 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt level 8" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear interrupt level 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear interrupt level 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear interrupt level 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/Clear interrupt level 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear interrupt level 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear interrupt level 2" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear interrupt level 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set/Clear interrupt level 0" "Low,High"
|
|
group.long 0x18++0x0B
|
|
line.long 0x00 "ESMSR1,ESM Status Register 1"
|
|
eventfld.long 0x00 31. " ESF[31] ,Error status flag 31" "No error,Error"
|
|
eventfld.long 0x00 30. " [30] ,Error status flag 30" "No error,Error"
|
|
eventfld.long 0x00 29. " [29] ,Error status flag 29" "No error,Error"
|
|
eventfld.long 0x00 28. " [28] ,Error status flag 28" "No error,Error"
|
|
eventfld.long 0x00 27. " [27] ,Error status flag 27" "No error,Error"
|
|
eventfld.long 0x00 26. " [26] ,Error status flag 26" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 25. " [25] ,Error status flag 25" "No error,Error"
|
|
eventfld.long 0x00 24. " [24] ,Error status flag 24" "No error,Error"
|
|
eventfld.long 0x00 23. " [23] ,Error status flag 23" "No error,Error"
|
|
eventfld.long 0x00 22. " [22] ,Error status flag 22" "No error,Error"
|
|
eventfld.long 0x00 21. " [21] ,Error status flag 21" "No error,Error"
|
|
eventfld.long 0x00 20. " [20] ,Error status flag 20" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Error status flag 19" "No error,Error"
|
|
eventfld.long 0x00 18. " [18] ,Error status flag 18" "No error,Error"
|
|
eventfld.long 0x00 17. " [17] ,Error status flag 17" "No error,Error"
|
|
eventfld.long 0x00 16. " [16] ,Error status flag 16" "No error,Error"
|
|
eventfld.long 0x00 15. " [15] ,Error status flag 15" "No error,Error"
|
|
eventfld.long 0x00 14. " [14] ,Error status flag 14" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 13. " [13] ,Error status flag 13" "No error,Error"
|
|
eventfld.long 0x00 12. " [12] ,Error status flag 12" "No error,Error"
|
|
eventfld.long 0x00 11. " [11] ,Error status flag 11" "No error,Error"
|
|
eventfld.long 0x00 10. " [10] ,Error status flag 10" "No error,Error"
|
|
eventfld.long 0x00 9. " [9] ,Error status flag 9" "No error,Error"
|
|
eventfld.long 0x00 8. " [8] ,Error status flag 8" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Error status flag 7" "No error,Error"
|
|
eventfld.long 0x00 6. " [6] ,Error status flag 6" "No error,Error"
|
|
eventfld.long 0x00 5. " [5] ,Error status flag 5" "No error,Error"
|
|
eventfld.long 0x00 4. " [4] ,Error status flag 4" "No error,Error"
|
|
eventfld.long 0x00 3. " [3] ,Error status flag 3" "No error,Error"
|
|
eventfld.long 0x00 2. " [2] ,Error status flag 2" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 1. " [1] ,Error status flag 1" "No error,Error"
|
|
eventfld.long 0x00 0. " [0] ,Error status flag 0" "No error,Error"
|
|
line.long 0x04 "ESMSR2,ESM Status Register 2"
|
|
eventfld.long 0x04 31. " ESF[31] ,Error status flag 31" "No error,Error"
|
|
eventfld.long 0x04 30. " [30] ,Error status flag 30" "No error,Error"
|
|
eventfld.long 0x04 29. " [29] ,Error status flag 29" "No error,Error"
|
|
eventfld.long 0x04 28. " [28] ,Error status flag 28" "No error,Error"
|
|
eventfld.long 0x04 27. " [27] ,Error status flag 27" "No error,Error"
|
|
eventfld.long 0x04 26. " [26] ,Error status flag 26" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 25. " [25] ,Error status flag 25" "No error,Error"
|
|
eventfld.long 0x04 24. " [24] ,Error status flag 24" "No error,Error"
|
|
eventfld.long 0x04 23. " [23] ,Error status flag 23" "No error,Error"
|
|
eventfld.long 0x04 22. " [22] ,Error status flag 22" "No error,Error"
|
|
eventfld.long 0x04 21. " [21] ,Error status flag 21" "No error,Error"
|
|
eventfld.long 0x04 20. " [20] ,Error status flag 20" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 19. " [19] ,Error status flag 19" "No error,Error"
|
|
eventfld.long 0x04 18. " [18] ,Error status flag 18" "No error,Error"
|
|
eventfld.long 0x04 17. " [17] ,Error status flag 17" "No error,Error"
|
|
eventfld.long 0x04 16. " [16] ,Error status flag 16" "No error,Error"
|
|
eventfld.long 0x04 15. " [15] ,Error status flag 15" "No error,Error"
|
|
eventfld.long 0x04 14. " [14] ,Error status flag 14" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 13. " [13] ,Error status flag 13" "No error,Error"
|
|
eventfld.long 0x04 12. " [12] ,Error status flag 12" "No error,Error"
|
|
eventfld.long 0x04 11. " [11] ,Error status flag 11" "No error,Error"
|
|
eventfld.long 0x04 10. " [10] ,Error status flag 10" "No error,Error"
|
|
eventfld.long 0x04 9. " [9] ,Error status flag 9" "No error,Error"
|
|
eventfld.long 0x04 8. " [8] ,Error status flag 8" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 7. " [7] ,Error status flag 7" "No error,Error"
|
|
eventfld.long 0x04 6. " [6] ,Error status flag 6" "No error,Error"
|
|
eventfld.long 0x04 5. " [5] ,Error status flag 5" "No error,Error"
|
|
eventfld.long 0x04 4. " [4] ,Error status flag 4" "No error,Error"
|
|
eventfld.long 0x04 3. " [3] ,Error status flag 3" "No error,Error"
|
|
eventfld.long 0x04 2. " [2] ,Error status flag 2" "No error,Error"
|
|
newline
|
|
eventfld.long 0x04 1. " [1] ,Error status flag 1" "No error,Error"
|
|
eventfld.long 0x04 0. " [0] ,Error status flag 0" "No error,Error"
|
|
line.long 0x08 "ESMSR3,ESM Status Register 3"
|
|
eventfld.long 0x08 31. " ESF[31] ,Error status flag 31" "No error,Error"
|
|
eventfld.long 0x08 30. " [30] ,Error status flag 30" "No error,Error"
|
|
eventfld.long 0x08 29. " [29] ,Error status flag 29" "No error,Error"
|
|
eventfld.long 0x08 28. " [28] ,Error status flag 28" "No error,Error"
|
|
eventfld.long 0x08 27. " [27] ,Error status flag 27" "No error,Error"
|
|
eventfld.long 0x08 26. " [26] ,Error status flag 26" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 25. " [25] ,Error status flag 25" "No error,Error"
|
|
eventfld.long 0x08 24. " [24] ,Error status flag 24" "No error,Error"
|
|
eventfld.long 0x08 23. " [23] ,Error status flag 23" "No error,Error"
|
|
eventfld.long 0x08 22. " [22] ,Error status flag 22" "No error,Error"
|
|
eventfld.long 0x08 21. " [21] ,Error status flag 21" "No error,Error"
|
|
eventfld.long 0x08 20. " [20] ,Error status flag 20" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 19. " [19] ,Error status flag 19" "No error,Error"
|
|
eventfld.long 0x08 18. " [18] ,Error status flag 18" "No error,Error"
|
|
eventfld.long 0x08 17. " [17] ,Error status flag 17" "No error,Error"
|
|
eventfld.long 0x08 16. " [16] ,Error status flag 16" "No error,Error"
|
|
eventfld.long 0x08 15. " [15] ,Error status flag 15" "No error,Error"
|
|
eventfld.long 0x08 14. " [14] ,Error status flag 14" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 13. " [13] ,Error status flag 13" "No error,Error"
|
|
eventfld.long 0x08 12. " [12] ,Error status flag 12" "No error,Error"
|
|
eventfld.long 0x08 11. " [11] ,Error status flag 11" "No error,Error"
|
|
eventfld.long 0x08 10. " [10] ,Error status flag 10" "No error,Error"
|
|
eventfld.long 0x08 9. " [9] ,Error status flag 9" "No error,Error"
|
|
eventfld.long 0x08 8. " [8] ,Error status flag 8" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 7. " [7] ,Error status flag 7" "No error,Error"
|
|
eventfld.long 0x08 6. " [6] ,Error status flag 6" "No error,Error"
|
|
eventfld.long 0x08 5. " [5] ,Error status flag 5" "No error,Error"
|
|
eventfld.long 0x08 4. " [4] ,Error status flag 4" "No error,Error"
|
|
eventfld.long 0x08 3. " [3] ,Error status flag 3" "No error,Error"
|
|
eventfld.long 0x08 2. " [2] ,Error status flag 2" "No error,Error"
|
|
newline
|
|
eventfld.long 0x08 1. " [1] ,Error status flag 1" "No error,Error"
|
|
eventfld.long 0x08 0. " [0] ,Error status flag 0" "No error,Error"
|
|
rgroup.long 0x24++0x0B
|
|
line.long 0x00 "ESMEPSR,ESM Error Pin Status Register"
|
|
bitfld.long 0x00 0. " EPSF ,Error pin status flag" "Occurred,Not Occurred"
|
|
line.long 0x04 "ESMIOFFHR,ESM Interrupt Offset High Register"
|
|
hexmask.long.byte 0x04 0.--6. 1. " INTOFFH ,Offset high level interrupt"
|
|
line.long 0x08 "ESMIOFFLR,ESM Interrupt Offset Low Register"
|
|
hexmask.long.byte 0x08 0.--6. 1. " INTOFFL ,Offset low level interrupt"
|
|
group.long 0x30++0x13
|
|
line.long 0x00 "ESMLTCR,ESM Low-Time Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " LTCP ,Error Pin Low-Time Counter"
|
|
line.long 0x04 "ESMLTCPR,ESM Low-Time Counter Preload Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " LTCP ,Low-time counter pre-load value"
|
|
line.long 0x08 "ESMEKR,ESM Error Key Register"
|
|
bitfld.long 0x08 0.--3. " EKEY ,Error Key" "Normal,Normal,Normal,Normal,Normal,LTC,Normal,Normal,Normal,Normal,Forced,Normal,Normal,Normal,Normal,Normal"
|
|
line.long 0x0C "ESMSSR2,ESM Status Shadow Register 2"
|
|
eventfld.long 0x0C 31. " ESF[31] ,Error status flag 31" "No error,Error"
|
|
eventfld.long 0x0C 30. " [30] ,Error status flag 30" "No error,Error"
|
|
eventfld.long 0x0C 29. " [29] ,Error status flag 29" "No error,Error"
|
|
eventfld.long 0x0C 28. " [28] ,Error status flag 28" "No error,Error"
|
|
eventfld.long 0x0C 27. " [27] ,Error status flag 27" "No error,Error"
|
|
eventfld.long 0x0C 26. " [26] ,Error status flag 26" "No error,Error"
|
|
newline
|
|
eventfld.long 0x0C 25. " [25] ,Error status flag 25" "No error,Error"
|
|
eventfld.long 0x0C 24. " [24] ,Error status flag 24" "No error,Error"
|
|
eventfld.long 0x0C 23. " [23] ,Error status flag 23" "No error,Error"
|
|
eventfld.long 0x0C 22. " [22] ,Error status flag 22" "No error,Error"
|
|
eventfld.long 0x0C 21. " [21] ,Error status flag 21" "No error,Error"
|
|
eventfld.long 0x0C 20. " [20] ,Error status flag 20" "No error,Error"
|
|
newline
|
|
eventfld.long 0x0C 19. " [19] ,Error status flag 19" "No error,Error"
|
|
eventfld.long 0x0C 18. " [18] ,Error status flag 18" "No error,Error"
|
|
eventfld.long 0x0C 17. " [17] ,Error status flag 17" "No error,Error"
|
|
eventfld.long 0x0C 16. " [16] ,Error status flag 16" "No error,Error"
|
|
eventfld.long 0x0C 15. " [15] ,Error status flag 15" "No error,Error"
|
|
eventfld.long 0x0C 14. " [14] ,Error status flag 14" "No error,Error"
|
|
newline
|
|
eventfld.long 0x0C 13. " [13] ,Error status flag 13" "No error,Error"
|
|
eventfld.long 0x0C 12. " [12] ,Error status flag 12" "No error,Error"
|
|
eventfld.long 0x0C 11. " [11] ,Error status flag 11" "No error,Error"
|
|
eventfld.long 0x0C 10. " [10] ,Error status flag 10" "No error,Error"
|
|
eventfld.long 0x0C 9. " [9] ,Error status flag 9" "No error,Error"
|
|
eventfld.long 0x0C 8. " [8] ,Error status flag 8" "No error,Error"
|
|
newline
|
|
eventfld.long 0x0C 7. " [7] ,Error status flag 7" "No error,Error"
|
|
eventfld.long 0x0C 6. " [6] ,Error status flag 6" "No error,Error"
|
|
eventfld.long 0x0C 5. " [5] ,Error status flag 5" "No error,Error"
|
|
eventfld.long 0x0C 4. " [4] ,Error status flag 4" "No error,Error"
|
|
eventfld.long 0x0C 3. " [3] ,Error status flag 3" "No error,Error"
|
|
eventfld.long 0x0C 2. " [2] ,Error status flag 2" "No error,Error"
|
|
newline
|
|
eventfld.long 0x0C 1. " [1] ,Error status flag 1" "No error,Error"
|
|
eventfld.long 0x0C 0. " [0] ,Error status flag 0" "No error,Error"
|
|
line.long 0x10 "ESMIEPSR4_SET/CLR,ESM Influence Error Pin Set/Status Register 4"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x04 31. " IEPSET[31] ,Set/Clear influence on error pin 31" "No influence,Influence"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x04 30. " [30] ,Set/Clear influence on error pin 30" "No influence,Influence"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x04 29. " [29] ,Set/Clear influence on error pin 29" "No influence,Influence"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x04 28. " [28] ,Set/Clear influence on error pin 28" "No influence,Influence"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x04 27. " [27] ,Set/Clear influence on error pin 27" "No influence,Influence"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x04 26. " [26] ,Set/Clear influence on error pin 26" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x10 25. 0x10 25. 0x04 25. " [25] ,Set/Clear influence on error pin 25" "No influence,Influence"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x04 24. " [24] ,Set/Clear influence on error pin 24" "No influence,Influence"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x04 23. " [23] ,Set/Clear influence on error pin 23" "No influence,Influence"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x04 22. " [22] ,Set/Clear influence on error pin 22" "No influence,Influence"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x04 21. " [21] ,Set/Clear influence on error pin 21" "No influence,Influence"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x04 20. " [20] ,Set/Clear influence on error pin 20" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x10 19. 0x10 19. 0x04 19. " [19] ,Set/Clear influence on error pin 19" "No influence,Influence"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x04 18. " [18] ,Set/Clear influence on error pin 18" "No influence,Influence"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x04 17. " [17] ,Set/Clear influence on error pin 17" "No influence,Influence"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x04 16. " [16] ,Set/Clear influence on error pin 16" "No influence,Influence"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x04 15. " [15] ,Set/Clear influence on error pin 15" "No influence,Influence"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x04 14. " [14] ,Set/Clear influence on error pin 14" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x10 13. 0x10 13. 0x04 13. " [13] ,Set/Clear influence on error pin 13" "No influence,Influence"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x04 12. " [12] ,Set/Clear influence on error pin 12" "No influence,Influence"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x04 11. " [11] ,Set/Clear influence on error pin 11" "No influence,Influence"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x04 10. " [10] ,Set/Clear influence on error pin 10" "No influence,Influence"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x04 9. " [9] ,Set/Clear influence on error pin 9" "No influence,Influence"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x04 8. " [8] ,Set/Clear influence on error pin 8" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x10 7. 0x10 7. 0x04 7. " [7] ,Set/Clear influence on error pin 7" "No influence,Influence"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x04 6. " [6] ,Set/Clear influence on error pin 6" "No influence,Influence"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x04 5. " [5] ,Set/Clear influence on error pin 5" "No influence,Influence"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x04 4. " [4] ,Set/Clear influence on error pin 4" "No influence,Influence"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x04 3. " [3] ,Set/Clear influence on error pin 3" "No influence,Influence"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x04 2. " [2] ,Set/Clear influence on error pin 2" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x10 1. 0x10 1. 0x04 1. " [1] ,Set/Clear influence on error pin 1" "No influence,Influence"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x04 0. " [0] ,Set/Clear influence on error pin 0" "No influence,Influence"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "ESMIESR4_SET/CLR,ESM Interrupt Enable Set/Status Register 4"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTENSET[31] ,Set/Clear interrupt enable 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear interrupt enable 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Set/Clear interrupt enable 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear interrupt enable 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear interrupt enable 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear interrupt enable 26" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Set/Clear interrupt enable 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear interrupt enable 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear interrupt enable 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear interrupt enable 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear interrupt enable 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/Clear interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear interrupt enable 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear interrupt enable 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear interrupt enable 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear interrupt enable 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear interrupt enable 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear interrupt enable 14" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear interrupt enable 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear interrupt enable 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear interrupt enable 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear interrupt enable 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt enable 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear interrupt enable 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear interrupt enable 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear interrupt enable 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/Clear interrupt enable 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear interrupt enable 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear interrupt enable 2" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear interrupt enable 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set/Clear interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "ESMILSR4_SET/CLR,ESM Interrupt Level Set/Status Register 4"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVLSET[31] ,Set/Clear interrupt level 31" "Low,High"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear interrupt level 30" "Low,High"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Set/Clear interrupt level 29" "Low,High"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear interrupt level 28" "Low,High"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear interrupt level 27" "Low,High"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear interrupt level 26" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Set/Clear interrupt level 25" "Low,High"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear interrupt level 24" "Low,High"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear interrupt level 23" "Low,High"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear interrupt level 22" "Low,High"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear interrupt level 21" "Low,High"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/Clear interrupt level 20" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear interrupt level 19" "Low,High"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear interrupt level 18" "Low,High"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear interrupt level 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear interrupt level 16" "Low,High"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear interrupt level 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear interrupt level 14" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear interrupt level 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear interrupt level 12" "Low,High"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear interrupt level 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear interrupt level 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt level 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt level 8" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear interrupt level 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear interrupt level 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear interrupt level 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/Clear interrupt level 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear interrupt level 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear interrupt level 2" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear interrupt level 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set/Clear interrupt level 0" "Low,High"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "ESMSR4,ESM Status Register 4"
|
|
eventfld.long 0x00 31. " ESF[31] ,Error status flag 31" "No error,Error"
|
|
eventfld.long 0x00 30. " [30] ,Error status flag 30" "No error,Error"
|
|
eventfld.long 0x00 29. " [29] ,Error status flag 29" "No error,Error"
|
|
eventfld.long 0x00 28. " [28] ,Error status flag 28" "No error,Error"
|
|
eventfld.long 0x00 27. " [27] ,Error status flag 27" "No error,Error"
|
|
eventfld.long 0x00 26. " [26] ,Error status flag 26" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 25. " [25] ,Error status flag 25" "No error,Error"
|
|
eventfld.long 0x00 24. " [24] ,Error status flag 24" "No error,Error"
|
|
eventfld.long 0x00 23. " [23] ,Error status flag 23" "No error,Error"
|
|
eventfld.long 0x00 22. " [22] ,Error status flag 22" "No error,Error"
|
|
eventfld.long 0x00 21. " [21] ,Error status flag 21" "No error,Error"
|
|
eventfld.long 0x00 20. " [20] ,Error status flag 20" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Error status flag 19" "No error,Error"
|
|
eventfld.long 0x00 18. " [18] ,Error status flag 18" "No error,Error"
|
|
eventfld.long 0x00 17. " [17] ,Error status flag 17" "No error,Error"
|
|
eventfld.long 0x00 16. " [16] ,Error status flag 16" "No error,Error"
|
|
eventfld.long 0x00 15. " [15] ,Error status flag 15" "No error,Error"
|
|
eventfld.long 0x00 14. " [14] ,Error status flag 14" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 13. " [13] ,Error status flag 13" "No error,Error"
|
|
eventfld.long 0x00 12. " [12] ,Error status flag 12" "No error,Error"
|
|
eventfld.long 0x00 11. " [11] ,Error status flag 11" "No error,Error"
|
|
eventfld.long 0x00 10. " [10] ,Error status flag 10" "No error,Error"
|
|
eventfld.long 0x00 9. " [9] ,Error status flag 9" "No error,Error"
|
|
eventfld.long 0x00 8. " [8] ,Error status flag 8" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Error status flag 7" "No error,Error"
|
|
eventfld.long 0x00 6. " [6] ,Error status flag 6" "No error,Error"
|
|
eventfld.long 0x00 5. " [5] ,Error status flag 5" "No error,Error"
|
|
eventfld.long 0x00 4. " [4] ,Error status flag 4" "No error,Error"
|
|
eventfld.long 0x00 3. " [3] ,Error status flag 3" "No error,Error"
|
|
eventfld.long 0x00 2. " [2] ,Error status flag 2" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 1. " [1] ,Error status flag 1" "No error,Error"
|
|
eventfld.long 0x00 0. " [0] ,Error status flag 0" "No error,Error"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ESMIEPSR7_SET/CLR,ESM Influence Error Pin Set/Status Register 7"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " IEPSET[31] ,Set/Clear influence on error pin 31" "No influence,Influence"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear influence on error pin 30" "No influence,Influence"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Set/Clear influence on error pin 29" "No influence,Influence"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear influence on error pin 28" "No influence,Influence"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear influence on error pin 27" "No influence,Influence"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear influence on error pin 26" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Set/Clear influence on error pin 25" "No influence,Influence"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear influence on error pin 24" "No influence,Influence"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear influence on error pin 23" "No influence,Influence"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear influence on error pin 22" "No influence,Influence"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear influence on error pin 21" "No influence,Influence"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/Clear influence on error pin 20" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear influence on error pin 19" "No influence,Influence"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear influence on error pin 18" "No influence,Influence"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear influence on error pin 17" "No influence,Influence"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear influence on error pin 16" "No influence,Influence"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear influence on error pin 15" "No influence,Influence"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear influence on error pin 14" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear influence on error pin 13" "No influence,Influence"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear influence on error pin 12" "No influence,Influence"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear influence on error pin 11" "No influence,Influence"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear influence on error pin 10" "No influence,Influence"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear influence on error pin 9" "No influence,Influence"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear influence on error pin 8" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear influence on error pin 7" "No influence,Influence"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear influence on error pin 6" "No influence,Influence"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear influence on error pin 5" "No influence,Influence"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/Clear influence on error pin 4" "No influence,Influence"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear influence on error pin 3" "No influence,Influence"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear influence on error pin 2" "No influence,Influence"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear influence on error pin 1" "No influence,Influence"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set/Clear influence on error pin 0" "No influence,Influence"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "ESMIESR7_SET/CLR,ESM Interrupt Enable Set/Status Register 7"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTENSET[31] ,Set/Clear interrupt enable 31" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear interrupt enable 30" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Set/Clear interrupt enable 29" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear interrupt enable 28" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear interrupt enable 27" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear interrupt enable 26" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Set/Clear interrupt enable 25" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear interrupt enable 24" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear interrupt enable 23" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear interrupt enable 22" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear interrupt enable 21" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/Clear interrupt enable 20" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear interrupt enable 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear interrupt enable 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear interrupt enable 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear interrupt enable 16" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear interrupt enable 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear interrupt enable 14" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear interrupt enable 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear interrupt enable 12" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear interrupt enable 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear interrupt enable 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt enable 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt enable 8" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear interrupt enable 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear interrupt enable 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear interrupt enable 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/Clear interrupt enable 4" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear interrupt enable 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear interrupt enable 2" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear interrupt enable 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set/Clear interrupt enable 0" "Disabled,Enabled"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "ESMILSR7_SET/CLR,ESM Interrupt Level Set/Status Register 7"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVLSET[31] ,Set/Clear interrupt level 31" "Low,High"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Set/Clear interrupt level 30" "Low,High"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Set/Clear interrupt level 29" "Low,High"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Set/Clear interrupt level 28" "Low,High"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Set/Clear interrupt level 27" "Low,High"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Set/Clear interrupt level 26" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Set/Clear interrupt level 25" "Low,High"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Set/Clear interrupt level 24" "Low,High"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Set/Clear interrupt level 23" "Low,High"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Set/Clear interrupt level 22" "Low,High"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Set/Clear interrupt level 21" "Low,High"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Set/Clear interrupt level 20" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Set/Clear interrupt level 19" "Low,High"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Set/Clear interrupt level 18" "Low,High"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Set/Clear interrupt level 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Set/Clear interrupt level 16" "Low,High"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Set/Clear interrupt level 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Set/Clear interrupt level 14" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Set/Clear interrupt level 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Set/Clear interrupt level 12" "Low,High"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Set/Clear interrupt level 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Set/Clear interrupt level 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Set/Clear interrupt level 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Set/Clear interrupt level 8" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Set/Clear interrupt level 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set/Clear interrupt level 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set/Clear interrupt level 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set/Clear interrupt level 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set/Clear interrupt level 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set/Clear interrupt level 2" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set/Clear interrupt level 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set/Clear interrupt level 0" "Low,High"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "ESMSR7,ESM Status Register 7"
|
|
eventfld.long 0x00 31. " ESF[31] ,Error status flag 31" "No error,Error"
|
|
eventfld.long 0x00 30. " [30] ,Error status flag 30" "No error,Error"
|
|
eventfld.long 0x00 29. " [29] ,Error status flag 29" "No error,Error"
|
|
eventfld.long 0x00 28. " [28] ,Error status flag 28" "No error,Error"
|
|
eventfld.long 0x00 27. " [27] ,Error status flag 27" "No error,Error"
|
|
eventfld.long 0x00 26. " [26] ,Error status flag 26" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 25. " [25] ,Error status flag 25" "No error,Error"
|
|
eventfld.long 0x00 24. " [24] ,Error status flag 24" "No error,Error"
|
|
eventfld.long 0x00 23. " [23] ,Error status flag 23" "No error,Error"
|
|
eventfld.long 0x00 22. " [22] ,Error status flag 22" "No error,Error"
|
|
eventfld.long 0x00 21. " [21] ,Error status flag 21" "No error,Error"
|
|
eventfld.long 0x00 20. " [20] ,Error status flag 20" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Error status flag 19" "No error,Error"
|
|
eventfld.long 0x00 18. " [18] ,Error status flag 18" "No error,Error"
|
|
eventfld.long 0x00 17. " [17] ,Error status flag 17" "No error,Error"
|
|
eventfld.long 0x00 16. " [16] ,Error status flag 16" "No error,Error"
|
|
eventfld.long 0x00 15. " [15] ,Error status flag 15" "No error,Error"
|
|
eventfld.long 0x00 14. " [14] ,Error status flag 14" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 13. " [13] ,Error status flag 13" "No error,Error"
|
|
eventfld.long 0x00 12. " [12] ,Error status flag 12" "No error,Error"
|
|
eventfld.long 0x00 11. " [11] ,Error status flag 11" "No error,Error"
|
|
eventfld.long 0x00 10. " [10] ,Error status flag 10" "No error,Error"
|
|
eventfld.long 0x00 9. " [9] ,Error status flag 9" "No error,Error"
|
|
eventfld.long 0x00 8. " [8] ,Error status flag 8" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Error status flag 7" "No error,Error"
|
|
eventfld.long 0x00 6. " [6] ,Error status flag 6" "No error,Error"
|
|
eventfld.long 0x00 5. " [5] ,Error status flag 5" "No error,Error"
|
|
eventfld.long 0x00 4. " [4] ,Error status flag 4" "No error,Error"
|
|
eventfld.long 0x00 3. " [3] ,Error status flag 3" "No error,Error"
|
|
eventfld.long 0x00 2. " [2] ,Error status flag 2" "No error,Error"
|
|
newline
|
|
eventfld.long 0x00 1. " [1] ,Error status flag 1" "No error,Error"
|
|
eventfld.long 0x00 0. " [0] ,Error status flag 0" "No error,Error"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
base ad:0x22000000
|
|
width 17.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL0,Global Control Register 0"
|
|
bitfld.long 0x00 30. " CH4_BYTE_SWAP ,Byte swap enable across data size" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " CH4_BIT_SWAP ,MSB/LSB swapping" "MSB,LSB"
|
|
bitfld.long 0x00 27.--28. 31. " CH4_CRC_SEL ,CRC type select" "CRC-64,CRC-16,CRC-32,E2E Profile 4,VDA CAN/SAE-J1850 CRC-8,H2F/Autosar 4.0,CASTAGNOLI/iSCSI,E2E Profile 4"
|
|
bitfld.long 0x00 25.--26. " CH4_DW_SEL ,CRC data size select" "64 bit,16 bit,32 Bit,?..."
|
|
bitfld.long 0x00 24. " CH4_PSA_SWREST ,Channel 4 PSA software reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 22. " CH3_BYTE_SWAP ,Byte swap enable across data size" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CH3_BIT_SWAP ,MSB/LSB swapping" "MSB,LSB"
|
|
bitfld.long 0x00 19.--20. 23. " CH3_CRC_SEL ,CRC type select" "CRC-64,CRC-16,CRC-32,E2E Profile 4,VDA CAN/SAE-J1850 CRC-8,H2F/Autosar 4.0,CASTAGNOLI/iSCSI,E2E Profile 4"
|
|
bitfld.long 0x00 17.--18. " CH3_DW_SEL ,CRC data size select" "64 bit,16 bit,32 Bit,?..."
|
|
bitfld.long 0x00 16. " CH3_PSA_SWREST ,Channel 3 PSA software reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 14. " CH2_BYTE_SWAP ,Byte swap enable across data size" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CH2_BIT_SWAP ,MSB/LSB swapping" "MSB,LSB"
|
|
bitfld.long 0x00 11.--12. 15. " CH2_CRC_SEL ,CRC type select" "CRC-64,CRC-16,CRC-32,E2E Profile 4,VDA CAN/SAE-J1850 CRC-8,H2F/Autosar 4.0,CASTAGNOLI/iSCSI,E2E Profile 4"
|
|
bitfld.long 0x00 9.--10. " CH2_DW_SEL ,CRC data size select" "64 bit,16 bit,32 Bit,?..."
|
|
bitfld.long 0x00 8. " CH2_PSA_SWREST ,Channel 2 PSA software reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 6. " CH1_BYTE_SWAP ,Byte swap enable across data size" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CH1_BIT_SWAP ,MSB/LSB swapping" "MSB,LSB"
|
|
bitfld.long 0x00 3.--4. 7. " CH1_CRC_SEL ,CRC type select" "CRC-64,CRC-16,CRC-32,E2E Profile 4,VDA CAN/SAE-J1850 CRC-8,H2F/Autosar 4.0,CASTAGNOLI/iSCSI,E2E Profile 4"
|
|
bitfld.long 0x00 1.--2. " CH1_DW_SEL ,CRC data size select" "64 bit,16 bit,32 Bit,?..."
|
|
bitfld.long 0x00 0. " CH1_PSA_SWREST ,Channel 1 PSA software reset" "No reset,Reset"
|
|
newline
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL1,Global Control Register 1"
|
|
bitfld.long 0x00 0. " PWDN ,Power down" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CTRL2,Global Control Register 2"
|
|
bitfld.long 0x00 24.--25. " CH4_MODE ,Channel 4 mode" "Data Capture mode,Auto mode,,Full-CPU mode"
|
|
bitfld.long 0x00 16.--17. " CH3_MODE ,Channel 3 mode" "Data Capture mode,Auto mode,,Full-CPU mode"
|
|
bitfld.long 0x00 8.--9. " CH2_MODE ,Channel 2 mode" "Data Capture mode,Auto mode,,Full-CPU mode"
|
|
bitfld.long 0x00 4. " CH1_TRACEEN ,Channel 1 data trace enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CH1_MODE ,Channel 1 mode" "Data Capture mode,Auto mode,,Full-CPU mode"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "INT_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 28. -0x10 28. -0x08 28. " CH4_TIMEOUT ,Channel 4 timeout status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x10 27. -0x08 27. " CH4_UNDER ,Channel 4 underrun status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x10 26. -0x08 26. " CH4_OVER ,Channel 4 overrun status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x10 25. -0x08 25. " CH4_CRCFAIL ,Channel 4 fail status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 20. -0x10 20. -0x08 20. " CH3_TIMEOUT ,Channel 3 timeout status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x10 19. -0x08 19. " CH3_UNDER ,Channel 3 underrun status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x10 18. -0x08 18. " CH3_OVER ,Channel 3 overrun status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x10 17. -0x08 17. " CH3_CRCFAIL ,Channel 3 fail status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x10 12. -0x08 12. " CH2_TIMEOUT ,Channel 2 timeout status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x10 11. -0x08 11. " CH2_UNDER ,Channel 2 underrun status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x10 10. -0x08 10. " CH2_OVER ,Channel 2 overrun status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x10 9. -0x08 9. " CH2_CRCFAIL ,Channel 2 fail status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x10 4. -0x08 4. " CH1_TIMEOUT ,Channel 1 timeout status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x10 3. -0x08 3. " CH1_UNDER ,Channel 1 underrun status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x10 2. -0x08 2. " CH1_OVER ,Channel 1 overrun status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x10 1. -0x08 1. " CH1_CRCFAIL ,Channel 1 compare fail status" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "INT_OFFSET_REG,Interrupt Offset Register"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " OFSTREG ,CRC interrupt offset"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "BUSY,Busy Register During Auto Mode"
|
|
bitfld.long 0x00 24. " CH4_BUSY ,Channel 4 busy flag" "Not busy,Busy"
|
|
bitfld.long 0x00 16. " CH3_BUSY ,Channel 3 busy flag" "Not busy,Busy"
|
|
bitfld.long 0x00 8. " CH2_BUSY ,Channel 2 busy flag" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " CH1_BUSY ,Channel 1 busy flag" "Not busy,Busy"
|
|
group.long 0x40++0x13
|
|
line.long 0x00 "PCOUNT_REG1,Pattern Counter Pre-load Register 1"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT1 ,Number of data patterns in one sector to be compressed before a CRC is performed"
|
|
line.long 0x04 "SCOUNT_REG1,Sector Counter Pre-load Register 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT1 ,The number of sectors in one block of memory"
|
|
line.long 0x08 "CURSEC_REG1,Current Sector Register 1"
|
|
hexmask.long.word 0x08 0.--15. 1. " CRC_CURSEC1 ,Current sector number of which the signature verification fails"
|
|
line.long 0x0C "WDTOPLD1,Channel 1 Watchdog Timeout Preload Register A"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " CRC_WDTOPLD1 ,Number of clock cycles within which the DMA must transfer the next block of data patterns"
|
|
line.long 0x10 "BCTOPLD1,Channel 1 Block Complete Timeout Preload Register B"
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|
hexmask.long.tbyte 0x10 0.--23. 1. " CRC_BCTOPLD1 ,Number of clock cycles within which the CRC for an entire block needs to complete"
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|
group.long (0x40+0x20)++0x0F
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|
line.long 0x00 "PSA_SIGREGL1,Channel 1 PSA Signature Low Register"
|
|
line.long 0x04 "PSA_SIGREGH1,Channel 1 PSA Signature High Register"
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|
line.long 0x08 "CRC_REGL1,Channel 1 CRC Value Low Register"
|
|
line.long 0x0C "CRC_REGH1,Channel 1 CRC Value High Register"
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|
rgroup.long (0x40+0x30)++0x0F
|
|
line.long 0x00 "PSA_SECSIGREGL1,Channel 1 PSA Sector Signature Low Register"
|
|
line.long 0x04 "PSA_SECSIGREGH1,Channel 1 PSA Sector Signature High Register"
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|
line.long 0x08 "RAW_DATAREGL1,Channel 1 Raw Data Low Register"
|
|
line.long 0x0C "RAW_DATAREGH1,Channel 1 Raw Data High Register"
|
|
group.long 0x80++0x13
|
|
line.long 0x00 "PCOUNT_REG2,Pattern Counter Pre-load Register 2"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT2 ,Number of data patterns in one sector to be compressed before a CRC is performed"
|
|
line.long 0x04 "SCOUNT_REG2,Sector Counter Pre-load Register 2"
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|
hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT2 ,The number of sectors in one block of memory"
|
|
line.long 0x08 "CURSEC_REG2,Current Sector Register 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " CRC_CURSEC2 ,Current sector number of which the signature verification fails"
|
|
line.long 0x0C "WDTOPLD2,Channel 2 Watchdog Timeout Preload Register A"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " CRC_WDTOPLD2 ,Number of clock cycles within which the DMA must transfer the next block of data patterns"
|
|
line.long 0x10 "BCTOPLD2,Channel 2 Block Complete Timeout Preload Register B"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " CRC_BCTOPLD2 ,Number of clock cycles within which the CRC for an entire block needs to complete"
|
|
group.long (0x80+0x20)++0x0F
|
|
line.long 0x00 "PSA_SIGREGL2,Channel 2 PSA Signature Low Register"
|
|
line.long 0x04 "PSA_SIGREGH2,Channel 2 PSA Signature High Register"
|
|
line.long 0x08 "CRC_REGL2,Channel 2 CRC Value Low Register"
|
|
line.long 0x0C "CRC_REGH2,Channel 2 CRC Value High Register"
|
|
rgroup.long (0x80+0x30)++0x0F
|
|
line.long 0x00 "PSA_SECSIGREGL2,Channel 2 PSA Sector Signature Low Register"
|
|
line.long 0x04 "PSA_SECSIGREGH2,Channel 2 PSA Sector Signature High Register"
|
|
line.long 0x08 "RAW_DATAREGL2,Channel 2 Raw Data Low Register"
|
|
line.long 0x0C "RAW_DATAREGH2,Channel 2 Raw Data High Register"
|
|
group.long 0xC0++0x13
|
|
line.long 0x00 "PCOUNT_REG3,Pattern Counter Pre-load Register 3"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT3 ,Number of data patterns in one sector to be compressed before a CRC is performed"
|
|
line.long 0x04 "SCOUNT_REG3,Sector Counter Pre-load Register 3"
|
|
hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT3 ,The number of sectors in one block of memory"
|
|
line.long 0x08 "CURSEC_REG3,Current Sector Register 3"
|
|
hexmask.long.word 0x08 0.--15. 1. " CRC_CURSEC3 ,Current sector number of which the signature verification fails"
|
|
line.long 0x0C "WDTOPLD3,Channel 3 Watchdog Timeout Preload Register A"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " CRC_WDTOPLD3 ,Number of clock cycles within which the DMA must transfer the next block of data patterns"
|
|
line.long 0x10 "BCTOPLD3,Channel 3 Block Complete Timeout Preload Register B"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " CRC_BCTOPLD3 ,Number of clock cycles within which the CRC for an entire block needs to complete"
|
|
group.long (0xC0+0x20)++0x0F
|
|
line.long 0x00 "PSA_SIGREGL3,Channel 3 PSA Signature Low Register"
|
|
line.long 0x04 "PSA_SIGREGH3,Channel 3 PSA Signature High Register"
|
|
line.long 0x08 "CRC_REGL3,Channel 3 CRC Value Low Register"
|
|
line.long 0x0C "CRC_REGH3,Channel 3 CRC Value High Register"
|
|
rgroup.long (0xC0+0x30)++0x0F
|
|
line.long 0x00 "PSA_SECSIGREGL3,Channel 3 PSA Sector Signature Low Register"
|
|
line.long 0x04 "PSA_SECSIGREGH3,Channel 3 PSA Sector Signature High Register"
|
|
line.long 0x08 "RAW_DATAREGL3,Channel 3 Raw Data Low Register"
|
|
line.long 0x0C "RAW_DATAREGH3,Channel 3 Raw Data High Register"
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "PCOUNT_REG4,Pattern Counter Pre-load Register 4"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT4 ,Number of data patterns in one sector to be compressed before a CRC is performed"
|
|
line.long 0x04 "SCOUNT_REG4,Sector Counter Pre-load Register 4"
|
|
hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT4 ,The number of sectors in one block of memory"
|
|
line.long 0x08 "CURSEC_REG4,Current Sector Register 4"
|
|
hexmask.long.word 0x08 0.--15. 1. " CRC_CURSEC4 ,Current sector number of which the signature verification fails"
|
|
line.long 0x0C "WDTOPLD4,Channel 4 Watchdog Timeout Preload Register A"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " CRC_WDTOPLD4 ,Number of clock cycles within which the DMA must transfer the next block of data patterns"
|
|
line.long 0x10 "BCTOPLD4,Channel 4 Block Complete Timeout Preload Register B"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " CRC_BCTOPLD4 ,Number of clock cycles within which the CRC for an entire block needs to complete"
|
|
group.long (0x100+0x20)++0x0F
|
|
line.long 0x00 "PSA_SIGREGL4,Channel 4 PSA Signature Low Register"
|
|
line.long 0x04 "PSA_SIGREGH4,Channel 4 PSA Signature High Register"
|
|
line.long 0x08 "CRC_REGL4,Channel 4 CRC Value Low Register"
|
|
line.long 0x0C "CRC_REGH4,Channel 4 CRC Value High Register"
|
|
rgroup.long (0x100+0x30)++0x0F
|
|
line.long 0x00 "PSA_SECSIGREGL4,Channel 4 PSA Sector Signature Low Register"
|
|
line.long 0x04 "PSA_SECSIGREGH4,Channel 4 PSA Sector Signature High Register"
|
|
line.long 0x08 "RAW_DATAREGL4,Channel 4 Raw Data Low Register"
|
|
line.long 0x0C "RAW_DATAREGH4,Channel 4 Raw Data High Register"
|
|
newline
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "MCRC_BUS_SEL,Data Bus Tracing Selection Register"
|
|
bitfld.long 0x00 2. " ME ,Enable the tracing of VBUSM" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DTCME ,Enable the tracing of data TCM" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ITCME ,Enable the tracing of instruction" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
newline
|