41254 lines
2.6 MiB
41254 lines
2.6 MiB
; --------------------------------------------------------------------------------
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; @Title: ATSAMS7x On-Chip Peripherals
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; @Props: Released
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; @Author: GAJ, MRO, PID
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; @Changelog: 2015-12-07 GAJ
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; 2020-05-28 PID
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; @Manufacturer: ATMEL - Atmel Corporation
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; @Doc: Atmel-11242-32-bit-Cortex-M7-Microcontroller-SAM-S70Q-SAM-S70N-SAM-S70J_Datasheet.pdf (rev. 2015-06-19)
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; SAM-E70-S70-V70-V71-Family-Data-Sheet-DS60001527D.pdf (rev. D, 2019-02)
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; @Core: Cortex-M7F
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; @Chip: ATSAMS70J19, ATSAMS70J20, ATSAMS70J21, ATSAMS70N19, ATSAMS70N20,
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; ATSAMS70N21, ATSAMS70Q19, ATSAMS70Q20, ATSAMS70Q21
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; @Copyright: (C) 1989-2020 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: peratsams7x.per 17736 2024-04-08 09:26:07Z kwisniewski $
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; Known problems:
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; MODULE REGISTER DESCRIPTION
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; RTC CALR CENT field is in fact BCD value of hundreds and thousands of year - field had been merged with YEAR
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; GPBR GPBR Misleading informations about register number - implementation based on "29.1. Description" chapter
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; PMC PMC_PCSR1 PID0-PID24 are included in PMC_PCSR0, register has been described according to PMC_PCER1 / PMC_PCDR1
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; PIO ALL 100-pin packages has not all PINs assigned (3 pins missing), implementation based on PINOUT
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; PIO ALL 64-pin packages has too many PINs assigned (1 additional pin), implementation based on PINOUT
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; PIO ALL Misleading informations about PIO controllers for 64-pin packages, implementation based on PINOUT
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; SMC SETUP,PULSE,CYCLE,MODE Overlapped offsets
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tree.close "Core Registers (Cortex-M7F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 28. " DISFPUISSOPT ,DISFPUISSOPT" "No,Yes"
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bitfld.long 0x00 27. " DISCRITAXIRUW ,Disables critical AXI read-under-write" "No,Yes"
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bitfld.long 0x00 26. " DISDYNADD ,Disables dynamic allocation of ADD and SUB instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 21.--25. " DISISSCH1 ,DISISSCH1" "Normal,Not issued in ch1,,,,,,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
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bitfld.long 0x00 16.--20. " DISDI ,DISDI" "Normal,ch1,,,,,,,,,,,,,,,Direct branches,Indirect branches,Loaded to PC,Integer MAC and MUL,VFP,?..."
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bitfld.long 0x00 15. " DISCRITAXIRUR ,Disables critical AXI read-under-read" "No,Yes"
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textline " "
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bitfld.long 0x00 14. " DISBTACALLOC ,DISBTACALLOC" "No,Yes"
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bitfld.long 0x00 13. " DISBTACREAD ,DISBTACREAD" "No,Yes"
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bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
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textline " "
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bitfld.long 0x00 11. " DISRAMODE ,Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions" "No,Yes"
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bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes"
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textline ""
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group.long 0x10++0x03
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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group.long 0x14++0x07
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line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x04 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPUID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,Revision 1,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Patch 0,Patch 1,Patch 2,?..."
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,On writes, makes the NMI exception active. On reads, indicates the state of the exception" "Inactive,Active"
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setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes, sets the PendSV exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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textline " "
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rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
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rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
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textline " "
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rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
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rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,Writing 1 to this bit causes a local system reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration and Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,Determines whether the exception entry sequence guarantees 8-byte stack frame alignment, adjusting the SP if necessary before saving state" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise data access faults on handlers running at priority -1 or priority -2" "Lockup,Ignored"
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bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
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bitfld.long 0x10 0. " NONBASETHRDENA ,Controls whether the processor can enter Thread mode at an execution priority level other than base level" "Disabled,Enabled"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,MemManage" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall status" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault status" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage status" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault status" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick status" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV status" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor status" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall status" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault status" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault status" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage status" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x13
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line.long 0x00 "HFSR,HardFault Status Register"
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eventfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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eventfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
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eventfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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eventfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not occurred,Occurred"
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eventfld.long 0x04 3. " VCATCH ,Indicates triggering of a Vector catch" "Not occurred,Occurred"
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eventfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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eventfld.long 0x04 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not occurred,Occurred"
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eventfld.long 0x04 0. " HALTED ,Indicates a debug event generated by a C_HALT or C_STEP request or a step request triggered by setting DEMCR.MON_STEP to 1" "Not occurred,Occurred"
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line.long 0x08 "MMFAR,MemManage Fault Address Register"
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line.long 0x0C "BFAR,BusFault Address Register"
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line.long 0x10 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Denied,Privileged,,Full"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Triggered Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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tree "Memory System"
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width 10.
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rgroup.long 0xD78++0x0B
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line.long 0x00 "CLIDR,Cache Level ID Register"
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bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,level 2,?..."
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bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,level 2,?..."
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bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,?..."
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textline " "
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bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..."
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bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..."
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bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..."
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textline " "
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bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..."
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bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..."
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bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
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line.long 0x04 "CTR,Cache Type Register"
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bitfld.long 0x04 29.--31. " FORMAT ,Indicates the implemented CTR format" ",,,,ARMv7,?..."
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bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
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bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
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textline " "
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bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "CCSIDR,Cache Size ID Register"
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bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
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bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
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bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
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textline " "
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bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
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hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
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hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
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textline " "
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bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
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group.long 0xD84++0x03
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line.long 0x00 "CSSELR,Cache Size Selection Register"
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bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,?..."
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bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data,Instruction"
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wgroup.long 0xF50++0x03
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line.long 0x00 "ICIALLU,Instruction cache invalidate all to Point of Unification"
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wgroup.long 0xF58++0x1F
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line.long 0x00 "ICIMVAU,Instruction cache invalidate by address to PoU"
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line.long 0x04 "DCIMVAC,Data cache invalidate by address to Point of Coherency (PoC)"
|
|
line.long 0x08 "DCISW,Data cache invalidate by set/way"
|
|
line.long 0x0C "DCCMVAU,Data cache by address to PoU"
|
|
line.long 0x10 "DCCMVAC,Data cache clean by address to PoC"
|
|
line.long 0x14 "DCCSW,Data cache clean by set/way"
|
|
line.long 0x18 "DCCIMVAC,Data cache clean and invalidate by address to PoC"
|
|
line.long 0x1C "DCCISW,Data cache clean and invalidate by set/way"
|
|
group.long 0xF90++0x13
|
|
line.long 0x00 "ITCMCR,Instruction Tightly-Coupled Memory Control Register"
|
|
bitfld.long 0x00 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
|
|
bitfld.long 0x00 2. " RETEN ,Retry phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,TCM enable" "Disabled,Enabled"
|
|
line.long 0x04 "DTCMCR,Data Tightly-Coupled Memory Control Register"
|
|
bitfld.long 0x04 3.--6. " SZ ,TCM size" "Not implemented,,,4 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,512 KB,1 MB,2 MB,4 MB,8 MB,16 MB"
|
|
bitfld.long 0x04 2. " RETEN ,Retry phase enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " RMW ,Read-Modify-Write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EN ,TCM enable" "Disabled,Enabled"
|
|
line.long 0x08 "AHBPCR,AHBP control register"
|
|
bitfld.long 0x08 1.--3. " SZ ,AHBP size" "AHBP disabled,64 MB,128 MB,256 MB,512 MB,?..."
|
|
bitfld.long 0x08 0. " EN ,AHBP enable" "Disabled,Enabled"
|
|
line.long 0x0C "CACR,L1 Cache Control Register"
|
|
bitfld.long 0x0C 2. " FORCEWT ,Enables Force Write-through in the data cache" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " ECCDIS ,Disables ECC in the instruction and data cache" "No,Yes"
|
|
bitfld.long 0x0C 0. " SIWT ,Enables limited cache coherency usage" "Disabled,Enabled"
|
|
line.long 0x10 "AHBSCR,AHB Slave Control Register"
|
|
bitfld.long 0x10 11.--15. " INITCOUNT ,Fairness counter initialization value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x10 2.--10. 1. " TPRI ,Threshold execution priority for AHBS traffic demotion"
|
|
bitfld.long 0x10 0.--1. " CTL ,AHBS prioritization control" "AHBS,Software,AHBSCR.INITCOUNT,AHBSPRI"
|
|
group.long 0xFA8++0x03
|
|
line.long 0x00 "ABFSR,Auxiliary Bus Fault Status Register"
|
|
bitfld.long 0x00 8.--9. " AXIMTYPE ,Indicates the type of fault on the AXIM interface" "OKAY,EXOKAY,SLVERR,DECERR"
|
|
bitfld.long 0x00 4. " EPPB ,Asynchronous fault on EPPB interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " AXIM ,Asynchronous fault on AXIM interface" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AHBP ,Asynchronous fault on AHBP interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " DTCM ,Asynchronous fault on DTCM interface" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " ITCM ,Asynchronous fault on ITCM interface" "Not occurred,Occurred"
|
|
group.long 0xFB0++0x03
|
|
line.long 0x00 "IEBR0,Instruction Error bank Register 0"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFB4++0x03
|
|
line.long 0x00 "IEBR1,Instruction Error bank Register 1"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFB8++0x03
|
|
line.long 0x00 "DEBR0,Data Error bank Register 0"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
group.long 0xFBC++0x03
|
|
line.long 0x00 "DEBR1,Data Error bank Register 1"
|
|
bitfld.long 0x00 30.--31. " UD ,User-defined" "0,1,2,3"
|
|
bitfld.long 0x00 17. " TOE ,Indicates the error type" "Correctable,Non-correctable"
|
|
bitfld.long 0x00 16. " RB ,Indicates which RAM bank to use" "Tag,Data"
|
|
textline " "
|
|
hexmask.long.word 0x00 2.--15. 0x4 " RL ,Indicates the location in instruction cache RAM"
|
|
bitfld.long 0x00 1. " LOCKED ,Indicates whether the location is locked or not locked" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " VALID ,Indicates whether the entry is valid or not" "Not valid,Valid"
|
|
tree.end
|
|
tree "Feature Registers"
|
|
width 10.
|
|
rgroup.long 0xD40++0x0B
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
|
|
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
|
|
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
|
|
hgroup.long 0xD4C++0x03
|
|
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
|
|
bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
|
|
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
|
|
hgroup.long 0xD54++0x03
|
|
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
|
|
rgroup.long 0xD60++0x13
|
|
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
|
|
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
|
|
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
|
|
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
|
|
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
|
|
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
|
|
bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
|
|
bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
|
|
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
|
|
bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
|
|
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
tree "CoreSight Identification Registers"
|
|
width 6.
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM7F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x0B
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
newline
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
|
|
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
newline
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
newline
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
newline
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
newline
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "MATRIX (Bus Matrix)"
|
|
base ad:0x40088000
|
|
width 15.
|
|
tree "Bus Matrix Master Configuration Registers"
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "MATRIX_MCFG0,Bus Matrix Master Configuration Register 0"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined length burst type" "Unlimited,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
else
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "MATRIX_MCFG0,Bus Matrix Master Configuration Register 0"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined length burst type" "Unlimited,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "MATRIX_MCFG1,Bus Matrix Master Configuration Register 1"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined length burst type" "Unlimited,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
else
|
|
rgroup.long 0x4++0x03
|
|
line.long 0x00 "MATRIX_MCFG1,Bus Matrix Master Configuration Register 1"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined length burst type" "Unlimited,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "MATRIX_MCFG2,Bus Matrix Master Configuration Register 2"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined length burst type" "Unlimited,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
else
|
|
rgroup.long 0x8++0x03
|
|
line.long 0x00 "MATRIX_MCFG2,Bus Matrix Master Configuration Register 2"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined length burst type" "Unlimited,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "MATRIX_MCFG3,Bus Matrix Master Configuration Register 3"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined length burst type" "Unlimited,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
else
|
|
rgroup.long 0xC++0x03
|
|
line.long 0x00 "MATRIX_MCFG3,Bus Matrix Master Configuration Register 3"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined length burst type" "Unlimited,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MATRIX_MCFG4,Bus Matrix Master Configuration Register 4"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined length burst type" "Unlimited,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "MATRIX_MCFG4,Bus Matrix Master Configuration Register 4"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined length burst type" "Unlimited,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MATRIX_MCFG5,Bus Matrix Master Configuration Register 5"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined length burst type" "Unlimited,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "MATRIX_MCFG5,Bus Matrix Master Configuration Register 5"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined length burst type" "Unlimited,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MATRIX_MCFG6,Bus Matrix Master Configuration Register 6"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined length burst type" "Unlimited,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "MATRIX_MCFG6,Bus Matrix Master Configuration Register 6"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined length burst type" "Unlimited,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MATRIX_MCFG8,Bus Matrix Master Configuration Register 8"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined length burst type" "Unlimited,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "MATRIX_MCFG8,Bus Matrix Master Configuration Register 8"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined length burst type" "Unlimited,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "MATRIX_MCFG12,Bus Matrix Master Configuration Register 12"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined length burst type" "Unlimited,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "MATRIX_MCFG12,Bus Matrix Master Configuration Register 12"
|
|
bitfld.long 0x00 0.--2. " ULBT ,Undefined length burst type" "Unlimited,Single,4-beat,8-beat,16-beat,32-beat,64-beat,128-beat"
|
|
endif
|
|
tree.end
|
|
tree "Bus Matrix Slave Configuration Registers"
|
|
if ((per.l(ad:0x40088000+0x40)&0x30000)==0x20000)
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default master fixed index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default master fixed index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
textfld " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "MATRIX_SCFG0,Bus Matrix Slave Configuration Register 0"
|
|
textfld " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x44)&0x30000)==0x20000)
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default master fixed index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default master fixed index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
textfld " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "MATRIX_SCFG1,Bus Matrix Slave Configuration Register 1"
|
|
textfld " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x48)&0x30000)==0x20000)
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default master fixed index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default master fixed index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
textfld " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "MATRIX_SCFG2,Bus Matrix Slave Configuration Register 2"
|
|
textfld " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x4C)&0x30000)==0x20000)
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default master fixed index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default master fixed index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
textfld " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "MATRIX_SCFG3,Bus Matrix Slave Configuration Register 3"
|
|
textfld " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x50)&0x30000)==0x20000)
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MATRIX_SCFG4,Bus Matrix Slave Configuration Register 4"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default master fixed index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "MATRIX_SCFG4,Bus Matrix Slave Configuration Register 4"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default master fixed index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MATRIX_SCFG4,Bus Matrix Slave Configuration Register 4"
|
|
textfld " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "MATRIX_SCFG4,Bus Matrix Slave Configuration Register 4"
|
|
textfld " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x54)&0x30000)==0x20000)
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MATRIX_SCFG5,Bus Matrix Slave Configuration Register 5"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default master fixed index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "MATRIX_SCFG5,Bus Matrix Slave Configuration Register 5"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default master fixed index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MATRIX_SCFG5,Bus Matrix Slave Configuration Register 5"
|
|
textfld " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "MATRIX_SCFG5,Bus Matrix Slave Configuration Register 5"
|
|
textfld " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x58)&0x30000)==0x20000)
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MATRIX_SCFG6,Bus Matrix Slave Configuration Register 6"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default master fixed index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "MATRIX_SCFG6,Bus Matrix Slave Configuration Register 6"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default master fixed index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MATRIX_SCFG6,Bus Matrix Slave Configuration Register 6"
|
|
textfld " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "MATRIX_SCFG6,Bus Matrix Slave Configuration Register 6"
|
|
textfld " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x5C)&0x30000)==0x20000)
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "MATRIX_SCFG7,Bus Matrix Slave Configuration Register 7"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default master fixed index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
else
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MATRIX_SCFG7,Bus Matrix Slave Configuration Register 7"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default master fixed index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "MATRIX_SCFG7,Bus Matrix Slave Configuration Register 7"
|
|
textfld " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
else
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MATRIX_SCFG7,Bus Matrix Slave Configuration Register 7"
|
|
textfld " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x60)&0x30000)==0x20000)
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "MATRIX_SCFG8,Bus Matrix Slave Configuration Register 8"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default master fixed index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
else
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "MATRIX_SCFG8,Bus Matrix Slave Configuration Register 8"
|
|
bitfld.long 0x00 18.--21. " FIXED_DEFMSTR ,Default master fixed index" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "MATRIX_SCFG8,Bus Matrix Slave Configuration Register 8"
|
|
textfld " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
else
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "MATRIX_SCFG8,Bus Matrix Slave Configuration Register 8"
|
|
textfld " "
|
|
bitfld.long 0x00 16.--17. " DEFMSTR_TYPE ,Default master type" "No master,Last,Fixed,?..."
|
|
hexmask.long.word 0x00 1.--9. 1. " SLOT_CYCLE ,Maximum bus grant duration for masters"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Bus Matrix Priority Registers"
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "MATRIX_PRAS0,Bus Matrix Priority Register A For Slave 0"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 priority" "Lowest,1,2,Highest"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 priority" "Lowest,1,2,Highest"
|
|
line.long 0x04 "MATRIX_PRBS0,Bus Matrix Priority Register B For Slave 0"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 priority" "Lowest,1,2,Highest"
|
|
else
|
|
rgroup.long 0x80++0x07
|
|
line.long 0x00 "MATRIX_PRAS0,Bus Matrix Priority Register A For Slave 0"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 priority" "Lowest,1,2,Highest"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 priority" "Lowest,1,2,Highest"
|
|
line.long 0x04 "MATRIX_PRBS0,Bus Matrix Priority Register B For Slave 0"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 priority" "Lowest,1,2,Highest"
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x88++0x07
|
|
line.long 0x00 "MATRIX_PRAS1,Bus Matrix Priority Register A For Slave 1"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 priority" "Lowest,1,2,Highest"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 priority" "Lowest,1,2,Highest"
|
|
line.long 0x04 "MATRIX_PRBS1,Bus Matrix Priority Register B For Slave 1"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 priority" "Lowest,1,2,Highest"
|
|
else
|
|
rgroup.long 0x88++0x07
|
|
line.long 0x00 "MATRIX_PRAS1,Bus Matrix Priority Register A For Slave 1"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 priority" "Lowest,1,2,Highest"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 priority" "Lowest,1,2,Highest"
|
|
line.long 0x04 "MATRIX_PRBS1,Bus Matrix Priority Register B For Slave 1"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 priority" "Lowest,1,2,Highest"
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x90++0x07
|
|
line.long 0x00 "MATRIX_PRAS2,Bus Matrix Priority Register A For Slave 2"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 priority" "Lowest,1,2,Highest"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 priority" "Lowest,1,2,Highest"
|
|
line.long 0x04 "MATRIX_PRBS2,Bus Matrix Priority Register B For Slave 2"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 priority" "Lowest,1,2,Highest"
|
|
else
|
|
rgroup.long 0x90++0x07
|
|
line.long 0x00 "MATRIX_PRAS2,Bus Matrix Priority Register A For Slave 2"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 priority" "Lowest,1,2,Highest"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 priority" "Lowest,1,2,Highest"
|
|
line.long 0x04 "MATRIX_PRBS2,Bus Matrix Priority Register B For Slave 2"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 priority" "Lowest,1,2,Highest"
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x98++0x07
|
|
line.long 0x00 "MATRIX_PRAS3,Bus Matrix Priority Register A For Slave 3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 priority" "Lowest,1,2,Highest"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 priority" "Lowest,1,2,Highest"
|
|
line.long 0x04 "MATRIX_PRBS3,Bus Matrix Priority Register B For Slave 3"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 priority" "Lowest,1,2,Highest"
|
|
else
|
|
rgroup.long 0x98++0x07
|
|
line.long 0x00 "MATRIX_PRAS3,Bus Matrix Priority Register A For Slave 3"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 priority" "Lowest,1,2,Highest"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 priority" "Lowest,1,2,Highest"
|
|
line.long 0x04 "MATRIX_PRBS3,Bus Matrix Priority Register B For Slave 3"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 priority" "Lowest,1,2,Highest"
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0xA0++0x07
|
|
line.long 0x00 "MATRIX_PRAS4,Bus Matrix Priority Register A For Slave 4"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 priority" "Lowest,1,2,Highest"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 priority" "Lowest,1,2,Highest"
|
|
line.long 0x04 "MATRIX_PRBS4,Bus Matrix Priority Register B For Slave 4"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 priority" "Lowest,1,2,Highest"
|
|
else
|
|
rgroup.long 0xA0++0x07
|
|
line.long 0x00 "MATRIX_PRAS4,Bus Matrix Priority Register A For Slave 4"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 priority" "Lowest,1,2,Highest"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 priority" "Lowest,1,2,Highest"
|
|
line.long 0x04 "MATRIX_PRBS4,Bus Matrix Priority Register B For Slave 4"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 priority" "Lowest,1,2,Highest"
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0xA8++0x07
|
|
line.long 0x00 "MATRIX_PRAS5,Bus Matrix Priority Register A For Slave 5"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 priority" "Lowest,1,2,Highest"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 priority" "Lowest,1,2,Highest"
|
|
line.long 0x04 "MATRIX_PRBS5,Bus Matrix Priority Register B For Slave 5"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 priority" "Lowest,1,2,Highest"
|
|
else
|
|
rgroup.long 0xA8++0x07
|
|
line.long 0x00 "MATRIX_PRAS5,Bus Matrix Priority Register A For Slave 5"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 priority" "Lowest,1,2,Highest"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 priority" "Lowest,1,2,Highest"
|
|
line.long 0x04 "MATRIX_PRBS5,Bus Matrix Priority Register B For Slave 5"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 priority" "Lowest,1,2,Highest"
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0xB0++0x07
|
|
line.long 0x00 "MATRIX_PRAS6,Bus Matrix Priority Register A For Slave 6"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 priority" "Lowest,1,2,Highest"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 priority" "Lowest,1,2,Highest"
|
|
line.long 0x04 "MATRIX_PRBS6,Bus Matrix Priority Register B For Slave 6"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 priority" "Lowest,1,2,Highest"
|
|
else
|
|
rgroup.long 0xB0++0x07
|
|
line.long 0x00 "MATRIX_PRAS6,Bus Matrix Priority Register A For Slave 6"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 priority" "Lowest,1,2,Highest"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 priority" "Lowest,1,2,Highest"
|
|
line.long 0x04 "MATRIX_PRBS6,Bus Matrix Priority Register B For Slave 6"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 priority" "Lowest,1,2,Highest"
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0xB8++0x07
|
|
line.long 0x00 "MATRIX_PRAS7,Bus Matrix Priority Register A For Slave 7"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 priority" "Lowest,1,2,Highest"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 priority" "Lowest,1,2,Highest"
|
|
line.long 0x04 "MATRIX_PRBS7,Bus Matrix Priority Register B For Slave 7"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 priority" "Lowest,1,2,Highest"
|
|
else
|
|
rgroup.long 0xB8++0x07
|
|
line.long 0x00 "MATRIX_PRAS7,Bus Matrix Priority Register A For Slave 7"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 priority" "Lowest,1,2,Highest"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 priority" "Lowest,1,2,Highest"
|
|
line.long 0x04 "MATRIX_PRBS7,Bus Matrix Priority Register B For Slave 7"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 priority" "Lowest,1,2,Highest"
|
|
endif
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0xC0++0x07
|
|
line.long 0x00 "MATRIX_PRAS8,Bus Matrix Priority Register A For Slave 8"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 priority" "Lowest,1,2,Highest"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 priority" "Lowest,1,2,Highest"
|
|
line.long 0x04 "MATRIX_PRBS8,Bus Matrix Priority Register B For Slave 8"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 priority" "Lowest,1,2,Highest"
|
|
else
|
|
rgroup.long 0xC0++0x07
|
|
line.long 0x00 "MATRIX_PRAS8,Bus Matrix Priority Register A For Slave 8"
|
|
bitfld.long 0x00 24.--25. " M6PR ,Master 6 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 20.--21. " M5PR ,Master 5 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 16.--17. " M4PR ,Master 4 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 12.--13. " M3PR ,Master 3 priority" "Lowest,1,2,Highest"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " M2PR ,Master 2 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 4.--5. " M1PR ,Master 1 priority" "Lowest,1,2,Highest"
|
|
bitfld.long 0x00 0.--1. " M0PR ,Master 0 priority" "Lowest,1,2,Highest"
|
|
line.long 0x04 "MATRIX_PRBS8,Bus Matrix Priority Register B For Slave 8"
|
|
bitfld.long 0x04 0.--1. " M8PR ,Master 8 priority" "Lowest,1,2,Highest"
|
|
endif
|
|
tree.end
|
|
newline
|
|
if ((per.l(ad:0x40088000+0x1E4)&0x01)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MATRIX_MRCR,Bus Matrix Master Remap Control Register"
|
|
bitfld.long 0x00 8. " RCB8 ,Remap command bit for master 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCB6 ,Remap command bit for master 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RCB5 ,Remap command bit for master 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCB4 ,Remap command bit for master 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " RCB3 ,Remap command bit for master 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCB2 ,Remap command bit for master 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RCB1 ,Remap command bit for master 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCB0 ,Remap command bit for master 0" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "MATRIX_MRCR,Bus Matrix Master Remap Control Register"
|
|
bitfld.long 0x00 8. " RCB8 ,Remap command bit for master 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCB6 ,Remap command bit for master 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " RCB5 ,Remap command bit for master 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCB4 ,Remap command bit for master 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " RCB3 ,Remap command bit for master 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCB2 ,Remap command bit for master 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RCB1 ,Remap command bit for master 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCB0 ,Remap command bit for master 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x114++0x0B
|
|
line.long 0x00 "CCFG_SYSIO,System I/O And CAN1 Configuration Register"
|
|
bitfld.long 0x00 12. " SYSIO12 ,PB12 or ERASE assignment" "Erase,PB12"
|
|
bitfld.long 0x00 7. " SYSIO7 ,PB7 or TCK/SWCLK assignment" "TCK/SWCLK,PB7"
|
|
bitfld.long 0x00 6. " SYSIO6 ,PB6 or TMS/SWDIO assignment" "TMS/SWDIO,PB6"
|
|
newline
|
|
bitfld.long 0x00 5. " SYSIO5 ,PB5 or TDO/TRACESWO assignment" "TDO/TRACESWO,PB5"
|
|
bitfld.long 0x00 4. " SYSIO4 ,PB4 or TDI assignment" "TDI,PB4"
|
|
line.long 0x04 "CCFG_PCCR,Peripheral Clock Configuration Register"
|
|
sif cpuis("ATSAMS70Q*")
|
|
bitfld.long 0x04 22. " I2SC1CC ,I2SC1 clock configuration" "Peripheral,GCLK"
|
|
bitfld.long 0x04 21. " I2SC0CC ,I2SC0 clock configuration" "Peripheral,GCLK"
|
|
newline
|
|
elif cpuis("ATSAMS70N*")
|
|
bitfld.long 0x04 21. " I2SC0CC ,I2SC0 clock configuration" "Peripheral,GCLK"
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 20. " TC0CC ,TC0 clock configuration" "PCK6,PCK7"
|
|
line.long 0x08 "CCFG_DYNCKG,Dynamic Clock Gating Register"
|
|
bitfld.long 0x08 2. " EFCCKG ,EFC dynamic clock gating disable" "No,Yes"
|
|
bitfld.long 0x08 1. " BRIDCKG ,Bridge dynamic clock gating disable" "No,Yes"
|
|
bitfld.long 0x08 0. " MATCKG ,MATRIX dynamic clock gating disable" "No,Yes"
|
|
if ((per.l(ad:0x40088000+0x124)&0x12)==0x00)
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CCFG_SMCNFCS,SMC NAND Flash Chip Select Configuration Register"
|
|
bitfld.long 0x00 4. " SDRAMEN ,SDRAM enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SMC_NFCS3 ,SMC NAND flash chip select 3 assignment" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " SMC_NFCS2 ,SMC NAND flash chip select 2 assignment" "Not assigned,Assigned"
|
|
newline
|
|
bitfld.long 0x00 1. " SMC_NFCS1 ,SMC NAND flash chip select 1 assignment" "Not assigned,Assigned"
|
|
bitfld.long 0x00 0. " SMC_NFCS0 ,SMC NAND flash chip select 0 assignment" "Not assigned,Assigned"
|
|
elif ((per.l(ad:0x40088000+0x124)&0x12)==0x02)
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CCFG_SMCNFCS,SMC NAND Flash Chip Select Configuration Register"
|
|
textfld " "
|
|
bitfld.long 0x00 3. " SMC_NFCS3 ,SMC NAND flash chip select 3 assignment" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " SMC_NFCS2 ,SMC NAND flash chip select 2 assignment" "Not assigned,Assigned"
|
|
newline
|
|
bitfld.long 0x00 1. " SMC_NFCS1 ,SMC NAND flash chip select 1 assignment" "Not assigned,Assigned"
|
|
bitfld.long 0x00 0. " SMC_NFCS0 ,SMC NAND flash chip select 0 assignment" "Not assigned,Assigned"
|
|
elif ((per.l(ad:0x40088000+0x124)&0x12)==0x10)
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CCFG_SMCNFCS,SMC NAND Flash Chip Select Configuration Register"
|
|
bitfld.long 0x00 4. " SDRAMEN ,SDRAM enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SMC_NFCS3 ,SMC NAND flash chip select 3 assignment" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " SMC_NFCS2 ,SMC NAND flash chip select 2 assignment" "Not assigned,Assigned"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 0. " SMC_NFCS0 ,SMC NAND flash chip select 0 assignment" "Not assigned,Assigned"
|
|
else
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CCFG_SMCNFCS,SMC NAND Flash Chip Select Configuration Register"
|
|
textfld " "
|
|
bitfld.long 0x00 3. " SMC_NFCS3 ,SMC NAND flash chip select 3 assignment" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " SMC_NFCS2 ,SMC NAND flash chip select 2 assignment" "Not assigned,Assigned"
|
|
newline
|
|
textfld " "
|
|
bitfld.long 0x00 0. " SMC_NFCS0 ,SMC NAND flash chip select 0 assignment" "Not assigned,Assigned"
|
|
endif
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "MATRIX_WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
rgroup.long 0x1E8++0x03
|
|
line.long 0x00 "MATRIX_WPSR,Write Protect Status Register"
|
|
hexmask.long.word 0x00 8.--23. 1. " WPVSRC ,Write protect violation source"
|
|
bitfld.long 0x00 0. " WPVS ,Write protect violation status" "Not occurred,Occurred"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UTMI (USB Transmitter Macrocell Interface)"
|
|
base ad:0x400E0400
|
|
width 9.
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "OHCIICR,OHCI Interrupt Configuration Register"
|
|
bitfld.long 0x00 23. " UDPPUDIS ,USB device pull-up disable" "No,Yes"
|
|
bitfld.long 0x00 4. " ARIE ,OHCI asynchronous resume interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RES0 ,USB PORT0 reset" "Reset,No reset"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CKTRIM,UTMI Clock Trimming Register"
|
|
bitfld.long 0x00 0.--1. " FREQ ,UTMI reference clock frequency" "12 MHz,16 MHz,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "CHIPID (Chip Identifier)"
|
|
base ad:0x400E0940
|
|
width 6.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CIDR,Chip ID Register"
|
|
bitfld.long 0x00 31. " EXT ,Extension flag" "Not implemented,Implemented"
|
|
bitfld.long 0x00 28.--30. " NVPTYP ,Nonvolatile program memory type" "ROM,ROMless/flash,Embedded flash,ROM & embedded flash,SRAM emulating ROM,?..."
|
|
hexmask.long.byte 0x00 20.--27. 1. " ARCH ,Architecture identifier"
|
|
bitfld.long 0x00 16.--19. " SRAMSIZ ,Internal SRAM size" "48 KB,192 KB,384 KB,6 KB,24 KB,4 KB,80 KB,160 KB,8 KB,16 KB,32 KB,64 KB,128 KB,256 KB,96 KB,512 KB"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " NVPSIZ2 ,Second nonvolatile program memory size" "Disabled,8 KB,16 KB,32 KB,,64 KB,,128 KB,,256 KB,512 KB,,1024 KB,,2048 KB,?..."
|
|
bitfld.long 0x00 8.--11. " NVPSIZ ,Nonvolatile program memory size" "Disabled,8 KB,16 KB,32 KB,,64 KB,,128 KB,160 KB,256 KB,512 KB,,1024 KB,,2048 KB,?..."
|
|
bitfld.long 0x00 5.--7. " EPROC ,Embedded processor" "Cortex-M7,ARM946ES,ARM7TDMI,Cortex-M3,ARM920T,ARM926EJS,Cortex-A5,Cortex-M4"
|
|
hexmask.long.byte 0x00 0.--4. 1. " VERSION ,Device version"
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "EXID,Chip ID Extension Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "EEFC (Enhanced Embedded Flash Controller)"
|
|
base ad:0x400E0C00
|
|
width 6.
|
|
if ((per.l(ad:0x400E0C00+0xE4)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FMR,EEFC Flash Mode Register"
|
|
bitfld.long 0x00 26. " CLOE ,Code loop optimization enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SCOD ,Sequential code optimization disable" "No,Yes"
|
|
bitfld.long 0x00 8.--11. " FWS ,Flash wait state" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 0. " FRDY ,Flash ready interrupt enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "FMR,EEFC Flash Mode Register"
|
|
bitfld.long 0x00 26. " CLOE ,Code loop optimization enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " SCOD ,Sequential code optimization disable" "No,Yes"
|
|
bitfld.long 0x00 8.--11. " FWS ,Flash wait state" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 0. " FRDY ,Flash ready interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "FCR,EEFC Flash Command Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " FKEY ,Flash writing protection key"
|
|
hexmask.long.word 0x00 8.--23. 1. " FARG ,Flash command argument"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FCMD ,Flash command"
|
|
newline
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "FSR,EEFC Flash Status Register"
|
|
in
|
|
newline
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "FRR,EEFC Flash Result Register"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,EEFC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect key"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
tree "GPNVM"
|
|
sgroup.long
|
|
set 0x4 %Long 0x5a00000d
|
|
getx 0xc %Long 0x0
|
|
line.long 0x0 "GPNVM"
|
|
bitfld.long 0x0 7.--8. "ITCM+DTCM=,TCM configuration" "0k,32k,64k,128k"
|
|
bitfld.long 0x0 1. " BOOT ,Boot mode selection" "ROM,FLASH"
|
|
bitfld.long 0x0 0. " SECURITY ,Security bit" "0,1"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "SUPC (Supply Controller)"
|
|
base ad:0x400E1810
|
|
width 12.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SUPC_CR,Supply Controller Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password key"
|
|
bitfld.long 0x00 3. " XTALSEL ,Crystal oscillator select" "No effect,Select"
|
|
bitfld.long 0x00 2. " VROFF ,Voltage regulator off" "No effect,Off"
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "SUPC_SMMR,Supply Controller Supply Monitor Mode Register"
|
|
bitfld.long 0x00 13. " SMIEN ,Supply monitor interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SMRSTEN ,Supply monitor reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " SMSMPL ,Supply monitor sampling period" "Disabled,Continuous,32 SLCK,256 SLCK,2048 SLCK,?..."
|
|
bitfld.long 0x00 0.--3. " SMTH ,Supply monitor threshold" "1.6 V,1.72 V,1.84 V,1.96 V,2.08 V,2.2 V,2.32 V,2.44 V,2.56 V,2.68 V,2.8 V,2.92 V,3.04 V,3.16 V,3.28 V,3.4 V"
|
|
line.long 0x04 "SUPC_MR,Supply Controller Mode Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " KEY ,Password key"
|
|
bitfld.long 0x04 20. " OSCBYPASS ,Oscillator bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x04 17. " BKUPRETON ,SRAM on in backup mode" "Off,On"
|
|
newline
|
|
bitfld.long 0x04 14. " ONREG ,Voltage regulator enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " BODDIS ,Brownout detector disable" "No,Yes"
|
|
bitfld.long 0x04 12. " BODRSTEN ,Brownout detector reset enable" "Disabled,Enabled"
|
|
line.long 0x08 "SUPC_WUMR,Supply Controller Wake Up Mode Register"
|
|
bitfld.long 0x08 16.--18. " LPDBC ,Low power debouncer period" "Disabled,2 RTCOUT,3 RTCOUT,4 RTCOUT ,5 RTCOUT,6 RTCOUT,7 RTCOUT,8 RTCOUT"
|
|
bitfld.long 0x08 12.--14. " WKUPDBC ,Wake up inputs debouncer" "IMMEDIATE,3 SLCK,32 SLCK,512 SLCK,4096 SLCK,32768 SLCK,?..."
|
|
bitfld.long 0x08 7. " LPDBCCLR ,Low power debouncer clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 6. " LPDBCEN1 ,Low power debouncer enable WKUP1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " LPDBCEN0 ,Low power debouncer enable WKUP0" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " RTCEN ,Real time clock wake up enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " RTTEN ,Real time timer wake up enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " SMEN ,Supply monitor wake up enable" "Disabled,Enabled"
|
|
if ((per.l(ad:0x400E1810+0xE4)&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SUPC_WUIR,System Controller Wake Up Inputs Register"
|
|
bitfld.long 0x00 29. " WKUPT[13] ,Wake up input 13 transition" "Low,High"
|
|
bitfld.long 0x00 28. " [12] ,Wake up input 12 transition" "Low,High"
|
|
bitfld.long 0x00 27. " [11] ,Wake up input 11 transition" "Low,High"
|
|
bitfld.long 0x00 26. " [10] ,Wake up input 10 transition" "Low,High"
|
|
bitfld.long 0x00 25. " [9] ,Wake up input 9 transition" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 24. " [8] ,Wake up input 8 transition" "Low,High"
|
|
bitfld.long 0x00 23. " [7] ,Wake up input 7 transition" "Low,High"
|
|
bitfld.long 0x00 22. " [6] ,Wake up input 6 transition" "Low,High"
|
|
bitfld.long 0x00 21. " [5] ,Wake up input 5 transition" "Low,High"
|
|
bitfld.long 0x00 20. " [4] ,Wake up input 4 transition" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Wake up input 3 transition" "Low,High"
|
|
bitfld.long 0x00 18. " [2] ,Wake up input 2 transition" "Low,High"
|
|
bitfld.long 0x00 17. " [1] ,Wake up input 1 transition" "Low,High"
|
|
bitfld.long 0x00 16. " [0] ,Wake up input 0 transition" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " WKUPEN[13] ,Wake up input 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Wake up input 12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Wake up input 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Wake up input 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Wake up input 9 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " [8] ,Wake up input 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Wake up input 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Wake up input 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Wake up input 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Wake up input 4 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Wake up input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Wake up input 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Wake up input 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Wake up input 0 enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "SUPC_WUIR,System Controller Wake Up Inputs Register"
|
|
bitfld.long 0x00 29. " WKUPT[13] ,Wake up input 13 transition" "Low,High"
|
|
bitfld.long 0x00 28. " [12] ,Wake up input 12 transition" "Low,High"
|
|
bitfld.long 0x00 27. " [11] ,Wake up input 11 transition" "Low,High"
|
|
bitfld.long 0x00 26. " [10] ,Wake up input 10 transition" "Low,High"
|
|
bitfld.long 0x00 25. " [9] ,Wake up input 9 transition" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 24. " [8] ,Wake up input 8 transition" "Low,High"
|
|
bitfld.long 0x00 23. " [7] ,Wake up input 7 transition" "Low,High"
|
|
bitfld.long 0x00 22. " [6] ,Wake up input 6 transition" "Low,High"
|
|
bitfld.long 0x00 21. " [5] ,Wake up input 5 transition" "Low,High"
|
|
bitfld.long 0x00 20. " [4] ,Wake up input 4 transition" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Wake up input 3 transition" "Low,High"
|
|
bitfld.long 0x00 18. " [2] ,Wake up input 2 transition" "Low,High"
|
|
bitfld.long 0x00 17. " [1] ,Wake up input 1 transition" "Low,High"
|
|
bitfld.long 0x00 16. " [0] ,Wake up input 0 transition" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " WKUPEN[13] ,Wake up input 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Wake up input 12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Wake up input 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Wake up input 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Wake up input 9 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " [8] ,Wake up input 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Wake up input 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Wake up input 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Wake up input 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Wake up input 4 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Wake up input 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Wake up input 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Wake up input 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Wake up input 0 enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "SUPC_SR,Supply Controller Status Register"
|
|
in
|
|
newline
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "SYSC_WPMR,System Controller Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protection key"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x400E1850
|
|
width 4.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 0. " WDRSTT ,Watchdog restart" "No effect,Restart"
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D4*")||cpuis("ATSAMA5D2*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog idle halt" "Not halted,Halted"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog debug halt" "Not halted,Halted"
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog delta value"
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog fault interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog counter value"
|
|
else
|
|
if ((per.l(ad:0x400E1850+0x04)&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog idle halt" "Running,Stopped"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog debug halt" "Running,Stopped"
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog delta value"
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog disable" "No,Yes"
|
|
bitfld.long 0x00 14. " WDRPROC ,Watchdog reset processor" "All resets,Processor reset"
|
|
newline
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog fault interrupt enable" "No effect,Interrupt"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog counter value"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog idle halt" "Running,Stopped"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog debug halt" "Running,Stopped"
|
|
hexmask.long.word 0x00 16.--27. 1. " WDD ,Watchdog delta value"
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog fault interrupt enable" "No effect,Interrupt"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog counter value"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SR,Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "RSWDT (Reinforced Safety Watchdog Timer)"
|
|
base ad:0x400E1900
|
|
width 4.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 0. " WDRSTT ,Watchdog restart" "No effect,Restart"
|
|
sif cpuis("ATSAME70*")||cpuis("ATSAMS7*")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Reinforced Safety Watchdog Timer Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog idle halt" "Not halted,Halted"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog debug halt" "Not halted,Halted"
|
|
hexmask.long.word 0x00 16.--27. 1. " ALLONES ,Must always be written with 0xFFF"
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog fault interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog counter value"
|
|
else
|
|
if ((per.l(ad:0x400E1900+0x04)&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Reinforced Safety Watchdog Timer Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog idle halt" "Run,Stopped"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog debug halt" "Run,Stopped"
|
|
hexmask.long.word 0x00 16.--27. 1. " ALLONES ,Must always be written with 0xFFF"
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 14. " WDRPROC ,Watchdog reset processor" "All resets,Processor reset"
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog fault interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog counter value"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Reinforced Safety Watchdog Timer Mode Register"
|
|
bitfld.long 0x00 29. " WDIDLEHLT ,Watchdog idle halt" "Run,Stopped"
|
|
bitfld.long 0x00 28. " WDDBGHLT ,Watchdog debug halt" "Run,Stopped"
|
|
hexmask.long.word 0x00 16.--27. 1. " ALLONES ,Must always be written with 0xFFF"
|
|
newline
|
|
bitfld.long 0x00 15. " WDDIS ,Watchdog disable" "No,Yes"
|
|
bitfld.long 0x00 13. " WDRSTEN ,Watchdog reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WDFIEN ,Watchdog fault interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--11. 1. " WDV ,Watchdog counter value"
|
|
endif
|
|
endif
|
|
sif cpuis("ATSAMS7*")
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SR,Reinforced Safety Watchdog Timer Status Register"
|
|
bitfld.long 0x00 0. " WDUNF ,Watchdog underflow" "No underflow,Underflow"
|
|
else
|
|
newline
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "SR,Reinforced Safety Watchdog Timer Status Register"
|
|
in
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "RSTC (Reset Controller)"
|
|
base ad:0x400E1800
|
|
width 4.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 3. " EXTRST ,External reset" "No effect,NRST assert"
|
|
bitfld.long 0x00 0. " PROCRST ,Processor reset" "No effect,Reset"
|
|
newline
|
|
hgroup.long 0x04++0x03
|
|
hide.long 0x00 "SR,Status Register"
|
|
in
|
|
newline
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " KEY ,Password"
|
|
bitfld.long 0x00 8.--11. " ERSTL ,External reset length" "2 SCLK (60 us),4 SCLK (120 us),8 SCLK (240 us),16 SCLK (480 us),32 SCLK (960 us),64 SCLK (1.92 ms),128 SCLK (3.84 ms),256 SCLK (7.68 ms),512 SCLK (15.36 ms),1024 SCLK (30.72 ms),2048 SCLK (61.44 ms),4096 SCLK (122.88 ms),8192 SCLK (245.76 ms),16384 SCLK (491.52 ms),32768 SCLK (0.98304 s),65536 SCLK (1.96608 s)"
|
|
bitfld.long 0x00 4. " URSTIEN ,User reset interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " URSTEN ,User reset enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTC (Real-time Clock)"
|
|
base ad:0x400E1860
|
|
width 8.
|
|
if (((per.l(ad:0x400E1810+0xE4))&0x01)==0x00)
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 16.--17. " CALEVSEL ,Calendar event selection" "Week changed,Month changed,Year changed,?..."
|
|
bitfld.long 0x00 8.--9. " TIMEVSEL ,Time event selection" "Minute changed,Hour changed,Every midnight,Every noon"
|
|
bitfld.long 0x00 1. " UPDCAL ,Update request calendar register" "No effect,Stopped"
|
|
bitfld.long 0x00 0. " UPDTIM ,Update request time register" "No effect,Stopped"
|
|
line.long 0x04 "MR,Mode Register"
|
|
bitfld.long 0x04 28.--29. " TPERIOD ,Period of the output pulse" "1 s,500 ms,250 ms,125 ms"
|
|
bitfld.long 0x04 24.--26. " THIGH ,High duration of the output pulse" "31.2 ms,15.6 ms,3.91 ms,967 us,488 us,122 us,30.5 us,15.2 us"
|
|
bitfld.long 0x04 20.--22. " OUT1 ,RTCOUT1 output source selection" "No waveform,1 Hz,32 Hz,64 Hz,512 Hz,Alarm toggle,Alarm flag,Programmable"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " OUT0 ,RTCOUT0 output source selection" "No waveform,1 Hz,32 Hz,64 Hz,512 Hz,Alarm toggle,Alarm flag,Programmable"
|
|
bitfld.long 0x04 15. " HIGHPPM ,High PPM correction range" "Lower,Higher"
|
|
hexmask.long.byte 0x04 8.--14. 1. " CORRECTION ,Slow clock correction"
|
|
newline
|
|
bitfld.long 0x04 4. " NEGPPM ,Negative PPM correction" "Positive,Negative"
|
|
bitfld.long 0x04 1. " PERSIAN ,Persian calendar" "Gregorian,Persian"
|
|
bitfld.long 0x04 0. " HRMOD ,12/24 hour mode" "24,12"
|
|
else
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 16.--17. " CALEVSEL ,Calendar event selection" "Week changed,Month changed,Year changed,?..."
|
|
bitfld.long 0x00 8.--9. " TIMEVSEL ,Time event selection" "Minute changed,Hour changed,Every midnight,Every noon"
|
|
bitfld.long 0x00 1. " UPDCAL ,Update request calendar register" "No effect,Stopped"
|
|
bitfld.long 0x00 0. " UPDTIM ,Update request time register" "No effect,Stopped"
|
|
line.long 0x04 "MR,Mode Register"
|
|
bitfld.long 0x04 28.--29. " TPERIOD ,Period of the output pulse" "1 s,500 ms,250 ms,125 ms"
|
|
bitfld.long 0x04 24.--26. " THIGH ,High duration of the output pulse" "31.2 ms,15.6 ms,3.91 ms,967 us,488 us,122 us,30.5 us,15.2 us"
|
|
bitfld.long 0x04 20.--22. " OUT1 ,RTCOUT1 output source selection" "No waveform,1 Hz,32 Hz,64 Hz,512 Hz,Alarm toggle,Alarm flag,Programmable"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " OUT0 ,RTCOUT0 output source selection" "No waveform,1 Hz,32 Hz,64 Hz,512 Hz,Alarm toggle,Alarm flag,Programmable"
|
|
bitfld.long 0x04 15. " HIGHPPM ,High PPM correction range" "Lower,Higher"
|
|
hexmask.long.byte 0x04 8.--14. 1. " CORRECTION ,Slow clock correction"
|
|
newline
|
|
bitfld.long 0x04 4. " NEGPPM ,Negative PPM correction" "Positive,Negative"
|
|
bitfld.long 0x04 1. " PERSIAN ,Persian calendar" "Gregorian,Persian"
|
|
bitfld.long 0x04 0. " HRMOD ,12/24 hour mode" "24,12"
|
|
endif
|
|
if (((per.l(ad:0x400E1860+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1860+0x08)&0x300000)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante meridiem / post meridiem indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour (tens)" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Current hour (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current minute (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current second (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1860+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1860+0x08)&0x300000)==0x100000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante meridiem / post meridiem indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hou (tens)r" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Current hour (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current minute (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current second (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1860+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1860+0x08)&0x300000)==(0x200000||0x300000))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 22. " AMPM ,Ante meridiem / post meridiem indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour (tens)" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Current hour (units)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current minute (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current second (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1860+0x04)&0x01)==0x00)&&(per.l(ad:0x400E1860+0x08)&0x300000)==0x200000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour (tens)" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Current hour (units)" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current minute (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current second (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1860+0x04)&0x01)==0x00)&&(per.l(ad:0x400E1860+0x08)&0x300000)==(0x00||0x100000))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour (tens)" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Current hour (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current minute (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current second (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMR,Time Register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Current hour (tens)" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Current hour (units)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " MIN ,Current minute (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current minute (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 4.--6. " SEC ,Current second (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current second (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
if (((per.l(ad:0x400E1860+0x04)&0x02)==0x00))
|
|
if ((per.l(ad:0x400E1860+0x0C)&0x1F0000)==0x20000)
|
|
if ((per.l(ad:0x400E1860+0x0C)&0x30000000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "0,-,-,-,-,-,-,-,-,-,9,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "0,-,-,-,-,-,-,-,-,-,9,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1860+0x0C)&0x1F0000)==(0x10000||0x30000||0x50000||0x70000||0x80000))
|
|
if ((per.l(ad:0x400E1860+0x0C)&0x30000000)==0x30000000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "0,-,-,-,-,-,-,-,-,-,9,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1860+0x0C)&0x30000000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "0,-,-,-,-,-,-,-,-,-,9,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "0,-,-,-,-,-,-,-,-,-,9,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1860+0x0C)&0x1F0000)==(0x40000||0x60000||0x90000))
|
|
if ((per.l(ad:0x400E1860+0x0C)&0x30000000)==0x30000000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "0,-,-,-,-,-,-,-,-,-,9,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1860+0x0C)&0x30000000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "0,-,-,-,-,-,-,-,-,-,9,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "0,-,-,-,-,-,-,-,-,-,9,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1860+0x0C)&0x1F0000)==(0x110000))
|
|
if ((per.l(ad:0x400E1860+0x0C)&0x30000000)==0x30000000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "0,-,-,-,-,-,-,-,-,-,9,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1860+0x0C)&0x30000000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "0,-,-,-,-,-,-,-,-,-,9,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "0,-,-,-,-,-,-,-,-,-,9,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x400E1860+0x0C)&0x30000000)==0x30000000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "0,-,-,-,-,-,-,-,-,-,9,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1860+0x0C)&0x30000000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "0,-,-,-,-,-,-,-,-,-,9,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,2,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "0,-,-,-,-,-,-,-,-,-,9,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x400E1860+0x0C)&0x1F0000)==(0x10000||0x20000||0x30000||0x40000||0x50000||0x60000))
|
|
if ((per.l(ad:0x400E1860+0x0C)&0x30000000)==0x30000000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,-,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1860+0x0C)&0x30000000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,-,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,-,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1860+0x0C)&0x1F0000)==(0x70000||0x80000||0x90000))
|
|
if ((per.l(ad:0x400E1860+0x0C)&0x30000000)==0x30000000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,-,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1860+0x0C)&0x30000000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,-,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,-,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x400E1860+0x0C)&0x30000000)==0x30000000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,-,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1860+0x0C)&0x30000000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,-,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CALR,Calendar Register"
|
|
bitfld.long 0x00 28.--29. " DATE ,Current date (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Current date (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 21.--23. " DAY ,Current day in current week" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 20. " MONTH ,Current month (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Current month (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " YEAR ,Current year (thousands)" "-,1,-,-,-,-,-,-"
|
|
bitfld.long 0x00 0.--3. ",Current year (hundreds)" "-,-,-,3,4,-,-,-,-,-,-,-,-,-,-,-"
|
|
bitfld.long 0x00 12.--15. ",Current year (tens)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.long 0x00 8.--11. ",Current year (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
endif
|
|
endif
|
|
newline
|
|
if (((per.l(ad:0x400E1810+0xE4))&0x01)==0x00)
|
|
width 8.
|
|
if (((per.l(ad:0x400E1860+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1860+0x10)&0x300000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour alarm (tens)" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour alarm (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Minute alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Second alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1860+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1860+0x10)&0x300000)==0x100000)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour alarm (tens)" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour alarm (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Minute alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Second alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1860+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1860+0x10)&0x300000)==(0x200000||0x300000))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour alarm (tens)" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour alarm (units)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Minute alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Second alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1860+0x04)&0x01)==0x00)&&(per.l(ad:0x400E1860+0x10)&0x300000)==0x200000)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour alarm (tens)" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour alarm (units)" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Minute alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Second alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1860+0x04)&0x01)==0x00)&&(per.l(ad:0x400E1860+0x10)&0x300000)==(0x00||0x100000))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour alarm (tens)" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Minute alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Second alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour alarm (tens)" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour alarm (units)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Minute alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Second alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
if ((per.l(ad:0x400E1860+0x04)&0x08)==0x00)
|
|
if ((per.l(ad:0x400E1860+0x14)&0x1F0000)==0x20000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1860+0x14)&0x30000000)==0x30100000)
|
|
if ((per.l(ad:0x400E1860+0x14)&0x1F0000)==(0x10000||0x30000||0x50000||0x70000||0x70000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1860+0x14)&0x1F0000)==(0x40000||0x60000||0x90000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1860+0x14)&0x1F0000)==(0x110000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1860+0x14)&0x1F0000)==(0x100000||0x120000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1860+0x14)&0x100000)==0x100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x400E1860+0x14)&0x30000000)==0x30100000)
|
|
if ((per.l(ad:0x400E1860+0x14)&0x1F0000)==(0x10000||0x20000||0x30000||0x40000||0x50000||0x60000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1860+0x14)&0x1F0000)==(0x70000||0x80000||0x90000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1860+0x14)&0x1F0000)==(0x100000||0x110000||0x120000))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1860+0x14)&0x100000)==0x100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 8.
|
|
if (((per.l(ad:0x400E1860+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1860+0x10)&0x300000)==0x00)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour alarm (tens)" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour alarm (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Minute alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Second alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1860+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1860+0x10)&0x300000)==0x100000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour alarm (tens)" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour alarm (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Minute alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Second alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1860+0x04)&0x01)==0x01)&&(per.l(ad:0x400E1860+0x10)&0x300000)==(0x200000||0x300000))
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " AMPM ,AM/PM indicator" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour alarm (tens)" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. ",Hour alarm (units)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Minute alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Second alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1860+0x04)&0x01)==0x00)&&(per.l(ad:0x400E1860+0x10)&0x300000)==0x200000)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour alarm (tens)" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour alarm (units)" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Minute alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Second alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.l(ad:0x400E1860+0x04)&0x01)==0x00)&&(per.l(ad:0x400E1860+0x10)&0x300000)==(0x00||0x100000))
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour alarm (tens)" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Minute alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Second alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x00 23. " HOUREN ,Hour alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour alarm (tens)" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. ",Hour alarm (units)" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 15. " MINEN ,Minute alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--14. " MIN ,Minute alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. ",Minute alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 7. " SECEN ,Second alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " SEC ,Second alarm (tens)" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. ",Second alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
if ((per.l(ad:0x400E1860+0x04)&0x08)==0x00)
|
|
if ((per.l(ad:0x400E1860+0x14)&0x1F0000)==0x20000)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,-"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1860+0x14)&0x30000000)==0x30100000)
|
|
if ((per.l(ad:0x400E1860+0x14)&0x1F0000)==(0x10000||0x30000||0x50000||0x70000||0x70000))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1860+0x14)&0x1F0000)==(0x40000||0x60000||0x90000))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1860+0x14)&0x1F0000)==(0x110000))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1860+0x14)&0x1F0000)==(0x100000||0x120000))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1860+0x14)&0x100000)==0x100000)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x400E1860+0x14)&0x30000000)==0x30100000)
|
|
if ((per.l(ad:0x400E1860+0x14)&0x1F0000)==(0x10000||0x20000||0x30000||0x40000||0x50000||0x60000))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1860+0x14)&0x1F0000)==(0x70000||0x80000||0x90000))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif ((per.l(ad:0x400E1860+0x14)&0x1F0000)==(0x100000||0x110000||0x120000))
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
elif ((per.l(ad:0x400E1860+0x14)&0x100000)==0x100000)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x00 31. " DATEEN ,Date alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date alarm (tens)" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. ",Date alarm (units)" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
newline
|
|
bitfld.long 0x00 23. " MTHEN ,Month alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MONTH ,Month alarm (tens)" "0,1"
|
|
bitfld.long 0x00 16.--19. ",Month alarm (units)" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
width 13.
|
|
newline
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 5. " TDERR ,Time and/or date free running error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " CALEV ,Calendar event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " TIMEV ,Time event" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 2. " SEC ,Second event" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " ALARM ,Alarm flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " ACKUPD ,Acknowledge for update" "Disabled,Enabled"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "SCCR,Status Clear Command Register"
|
|
bitfld.long 0x00 5. " TDERR ,Time and/or date free running error clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CALCLR ,Calendar event clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " TIMCLR ,Time event clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 2. " SECCLR ,Second event clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " ALRCLR ,Alarm flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " ACKCLR ,Acknowledge for update clear" "No effect,Clear"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " TDERR ,Time and/or date event interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CAL ,Calendar event interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " TIM ,Time event interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " SEC ,Second event interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ALR ,Alarm interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ACK ,Acknowledge for update interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "VER,Valid Entry Register"
|
|
bitfld.long 0x00 3. " NVCALALR ,Non-valid calendar alarm" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " NVTIMALR ,Non-valid time alarm" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " NVCAL ,Non-valid calendar" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " NVTIM ,Non-valid time" "Not detected,Detected"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTT (Real-time Timer)"
|
|
base ad:0x400E1830
|
|
width 4.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "MR,Real-Time Timer Mode Register"
|
|
sif (cpuis("ATSAM4E*")||cpuis("ATSAM4N*")||cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*"))
|
|
bitfld.long 0x00 24. " RTC1HZ ,Real-time clock 1Hz clock selection" "16-bit prescaler,RTC 1 Hz clock"
|
|
bitfld.long 0x00 20. " RTTDIS ,Real-time timer disable" "No,Yes"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 18. " RTTRST ,Real-time timer restart" "No restart,Restart"
|
|
bitfld.long 0x00 17. " RTTINCIEN ,Real-time timer increment interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ALMIEN ,Alarm interrupt enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--15. 1. " RTPRES ,Real-time timer prescaler value"
|
|
line.long 0x04 "AR,Real-Time Timer Alarm Register"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "VR,Real-Time Timer Value Register"
|
|
newline
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "SR,Real-Time Timer Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPBR (General Purpose Backup Registers)"
|
|
base ad:0x400E1890
|
|
width 8.
|
|
sif (cpuis("AT91SAM3S8*")||cpuis("AT91SAM3N*")||cpuis("ATSAM4N*")||cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMG5*"))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "GPBR0,General Purpose Backup Register 0"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "GPBR1,General Purpose Backup Register 1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "GPBR2,General Purpose Backup Register 2"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GPBR3,General Purpose Backup Register 3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPBR4,General Purpose Backup Register 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPBR5,General Purpose Backup Register 5"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPBR6,General Purpose Backup Register 6"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPBR7,General Purpose Backup Register 7"
|
|
elif (cpuis("ATSAM4E*"))
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "GPBR0,General Purpose Backup Register 0"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "GPBR1,General Purpose Backup Register 1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "GPBR2,General Purpose Backup Register 2"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GPBR3,General Purpose Backup Register 3"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "GPBR4,General Purpose Backup Register 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPBR5,General Purpose Backup Register 5"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "GPBR6,General Purpose Backup Register 6"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPBR7,General Purpose Backup Register 7"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPBR8,General Purpose Backup Register 8"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPBR9,General Purpose Backup Register 9"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "GPBR10,General Purpose Backup Register 10"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "GPBR11,General Purpose Backup Register 11"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "GPBR12,General Purpose Backup Register 12"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "GPBR13,General Purpose Backup Register 13"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "GPBR14,General Purpose Backup Register 14"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "GPBR15,General Purpose Backup Register 15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "GPBR16,General Purpose Backup Register 16"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "GPBR17,General Purpose Backup Register 17"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "GPBR18,General Purpose Backup Register 18"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "GPBR19,General Purpose Backup Register 19"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "GPBR0,General Purpose Backup Register 0"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "GPBR1,General Purpose Backup Register 1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "GPBR2,General Purpose Backup Register 2"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "GPBR3,General Purpose Backup Register 3"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0x400E0600
|
|
width 23.
|
|
if ((per.l(ad:0x400E0600+0xE4)&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PMC_SCSR_SET/CLR,PMC System Clock Set/Clear Register"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " PCK[7] ,Programmable clock 7 output status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [6] ,Programmable clock 6 output status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [5] ,Programmable clock 5 output status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [4] ,Programmable clock 4 output status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [3] ,Programmable clock 3 output status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " USBCLK ,USB FS clock status" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PMC_SCSR,PMC System Clock Status Register"
|
|
bitfld.long 0x00 15. " PCK[7] ,Programmable clock 7 output status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [6] ,Programmable clock 6 output status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [5] ,Programmable clock 5 output status" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [4] ,Programmable clock 4 output status" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [3] ,Programmable clock 3 output status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " USBCLK ,USB FS clock status" "Disabled,Enabled"
|
|
endif
|
|
if ((per.l(ad:0x400E0600+0xE4)&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PMC_PCSR0_SET/CLR,PMC Peripheral Clock Set/Clear Register 0"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " PWM0 ,Pulse width modulation controller 0 (peripheral ID 31) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " DACC ,Digital to analog converter (peripheral ID 30) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " AFEC0 ,Analog front-end controller 0 (peripheral ID 29) clock status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " TC1_2 ,Timer counter 1 channel 2 controller (peripheral ID 28) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " TC1_1 ,Timer counter 1 channel 1 controller (peripheral ID 27) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " TC1_0 ,Timer counter 1 channel 0 controller (peripheral ID 26) clock status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " TC0_2 ,Timer counter 0 channel 2 (peripheral ID 25) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " TC0_1 ,Timer counter 0 channel 1 (peripheral ID 24) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " TC0_0 ,Timer counter 0 channel 0 (peripheral ID 23) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " SSC ,Synchronous serial controller (peripheral ID 22) clock status" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("ATSAMS70J*")
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " SPI0 ,Serial peripheral interface 0 (peripheral ID 21) clock status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " TWIHS1 ,Two-Wire interface 1 (peripheral ID 20) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " TWIHS0 ,Two-Wire interface 0 (peripheral ID 19) clock status" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("ATSAMS70J*")
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " HSMCI ,High speed multimedia card interface (peripheral ID 18) clock status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " PIOE ,Parallel I/O controller E (peripheral ID 12) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " PIOD ,Parallel I/O controller D (peripheral ID 11) clock status" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("ATSAMS70J*")
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " USART2 ,USART 2 (peripheral ID 15) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " USART1 ,USART 1 (peripheral ID 14) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " USART0 ,USART 0 (peripheral ID 13) clock status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " PIOC ,Parallel I/O controller C (peripheral ID 12) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " PIOB ,Parallel I/O controller B (peripheral ID 11) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " PIOA ,Parallel I/O controller A (peripheral ID 10) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " SMC ,Static memory controller (peripheral ID 9) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " UART1 ,Universal asynchronous receiver transmitter 1 (peripheral ID 8) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " UART0 ,Universal asynchronous receiver transmitter 0 (peripheral ID 7) clock status" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "PMC_PCSR0,PMC Peripheral Clock Status Register 0"
|
|
bitfld.long 0x00 31. " PWM0 ,Pulse width modulation controller 0 (peripheral ID 31) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DACC ,Digital to analog converter (peripheral ID 30) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " AFEC0 ,Analog front-end controller 0 (peripheral ID 29) clock status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " TC1_2 ,Timer counter 1 channel 2 controller (peripheral ID 28) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TC1_1 ,Timer counter 1 channel 1 controller (peripheral ID 27) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TC1_0 ,Timer counter 1 channel 0 controller (peripheral ID 26) clock status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " TC0_2 ,Timer counter 0 channel 2 (peripheral ID 25) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " TC0_1 ,Timer counter 0 channel 1 (peripheral ID 24) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TC0_0 ,Timer counter 0 channel 0 (peripheral ID 23) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " SSC ,Synchronous serial controller (peripheral ID 22) clock status" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("ATSAMS70J*")
|
|
bitfld.long 0x00 21. " SPI0 ,Serial peripheral interface 0 (peripheral ID 21) clock status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 20. " TWIHS1 ,Two-Wire interface 1 (peripheral ID 20) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TWIHS0 ,Two-Wire interface 0 (peripheral ID 19) clock status" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("ATSAMS70J*")
|
|
bitfld.long 0x00 18. " HSMCI ,High speed multimedia card interface (peripheral ID 18) clock status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 17. " PIOE ,Parallel I/O controller E (peripheral ID 12) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PIOD ,Parallel I/O controller D (peripheral ID 11) clock status" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("ATSAMS70J*")
|
|
bitfld.long 0x00 15. " USART2 ,USART 2 (peripheral ID 15) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " USART1 ,USART 1 (peripheral ID 14) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " USART0 ,USART 0 (peripheral ID 13) clock status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 12. " PIOC ,Parallel I/O controller C (peripheral ID 12) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PIOB ,Parallel I/O controller B (peripheral ID 11) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PIOA ,Parallel I/O controller A (peripheral ID 10) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SMC ,Static memory controller (peripheral ID 9) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " UART1 ,Universal asynchronous receiver transmitter 1 (peripheral ID 8) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " UART0 ,Universal asynchronous receiver transmitter 0 (peripheral ID 7) clock status" "Disabled,Enabled"
|
|
endif
|
|
if ((per.l(ad:0x400E0600+0xE4)&0x01)==0x00)
|
|
group.long 0x1C++0x0F
|
|
line.long 0x00 "CKGR_UCKR,PMC UTMI Clock Configuration Register"
|
|
bitfld.long 0x00 20.--23. " UPLLCOUNT ,UTMI PLL start-up time" "0 cycles,8 cycles,16 cycles,24 cycles,32 cycles,40 cycles,48 cycles,56 cycles,64 cycles,72 cycles,80 cycles,88 cycles,96 cycles,104 cycles,112 cycles,120 cycles"
|
|
bitfld.long 0x00 16. " UPLLEN ,UTMI PLL enable" "Disabled,Enabled"
|
|
line.long 0x04 "CKGR_MOR,PMC Clock Generator Main Oscillator Register"
|
|
bitfld.long 0x04 26. " XT32KFME ,Slow crystal oscillator frequency monitoring enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " CFDEN ,Clock failure detector enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " MOSCSEL ,Main oscillator selection" "On-Chip RC,Crystal"
|
|
hexmask.long.byte 0x04 16.--23. 1. " KEY ,Write access password"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. " MOSCXTST ,Main crystal oscillator start-up time"
|
|
bitfld.long 0x04 4.--6. " MOSCRCF ,Main on-chip RC oscillator frequency selection" "4 MHz,8 MHz,12 MHz,?..."
|
|
bitfld.long 0x04 3. " MOSCRCEN ,Main on-chip RC oscillator enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " WAITMODE ,Wait mode command" "No effect,Wait"
|
|
bitfld.long 0x04 1. " MOSCXTBY ,Main crystal oscillator bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x04 0. " MOSCXTEN ,Main crystal oscillator enable" "Disabled,Enabled"
|
|
line.long 0x08 "CKGR_MCFR,PMC Clock Generator Main Clock Frequency Register"
|
|
bitfld.long 0x08 24. " CCSS ,Counter clock source selection" "RC oscillator,Crystal oscillator"
|
|
bitfld.long 0x08 20. " RCMEAS ,RC oscillator frequency measure" "No effect,Restart"
|
|
bitfld.long 0x08 16. " MAINFRDY ,Main clock ready" "Not ready,Ready"
|
|
hexmask.long.word 0x08 0.--15. 1. " MAINF ,Main clock frequency"
|
|
line.long 0x0C "CKGR_PLLAR,PMC Clock Generator PLLA Register"
|
|
bitfld.long 0x0C 29. " ONE ,Must be set to 1" ",1"
|
|
hexmask.long.word 0x0C 16.--26. 1. " MULA ,PLLA multiplier"
|
|
bitfld.long 0x0C 8.--13. " PLLACOUNT ,PLLA counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " DIVA ,Divider A"
|
|
else
|
|
rgroup.long 0x1C++0x0F
|
|
line.long 0x00 "CKGR_UCKR,PMC UTMI Clock Configuration Register"
|
|
bitfld.long 0x00 20.--23. " UPLLCOUNT ,UTMI PLL start-up time" "0 cycles,8 cycles,16 cycles,24 cycles,32 cycles,40 cycles,48 cycles,56 cycles,64 cycles,72 cycles,80 cycles,88 cycles,96 cycles,104 cycles,112 cycles,120 cycles"
|
|
bitfld.long 0x00 16. " UPLLEN ,UTMI PLL enable" "Disabled,Enabled"
|
|
line.long 0x04 "CKGR_MOR,PMC Clock Generator Main Oscillator Register"
|
|
bitfld.long 0x04 26. " XT32KFME ,Slow crystal oscillator frequency monitoring enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " CFDEN ,Clock failure detector enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " MOSCSEL ,Main oscillator selection" "On-chip RC,Crystal"
|
|
hexmask.long.byte 0x04 16.--23. 1. " KEY ,Write access password"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--15. 1. " MOSCXTST ,Main crystal oscillator start-up time"
|
|
bitfld.long 0x04 4.--6. " MOSCRCF ,Main on-chip RC oscillator frequency selection" "4 MHz,8 MHz,12 MHz,?..."
|
|
bitfld.long 0x04 3. " MOSCRCEN ,Main on-chip RC oscillator enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " WAITMODE ,Wait mode command" "No effect,Wait"
|
|
bitfld.long 0x04 1. " MOSCXTBY ,Main crystal oscillator bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x04 0. " MOSCXTEN ,Main crystal oscillator enable" "Disabled,Enabled"
|
|
line.long 0x08 "CKGR_MCFR,PMC Clock Generator Main Clock Frequency Register"
|
|
bitfld.long 0x08 24. " CCSS ,Counter clock source selection" "RC oscillator,Crystal oscillator"
|
|
bitfld.long 0x08 20. " RCMEAS ,RC oscillator frequency measure" "No effect,Restart"
|
|
bitfld.long 0x08 16. " MAINFRDY ,Main clock ready" "Not ready,Ready"
|
|
hexmask.long.word 0x08 0.--15. 1. " MAINF ,Main clock frequency"
|
|
line.long 0x0C "CKGR_PLLAR,PMC Clock Generator PLLA Register"
|
|
bitfld.long 0x0C 29. " ONE ,Must be set to 1" ",1"
|
|
hexmask.long.word 0x0C 16.--26. 1. " MULA ,PLLA multiplier"
|
|
bitfld.long 0x0C 8.--13. " PLLACOUNT ,PLLA counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " DIVA ,PLLA front end divider"
|
|
endif
|
|
if ((per.l(ad:0x400E0600+0xE4)&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PMC_MCKR,PMC Master Clock Register"
|
|
bitfld.long 0x00 13. " UPLLDIV2 ,UPLL divisor by 2" "/1,/2"
|
|
bitfld.long 0x00 8.--9. " MDIV ,Master clock division" "/1,/2,/4,/3"
|
|
bitfld.long 0x00 4.--6. " PRES ,Processor clock prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,Clock/3"
|
|
bitfld.long 0x00 0.--1. " CSS ,Master clock source selection" "Slow,Main,PLLA,UPLL"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PMC_USB,PMC USB Clock Register"
|
|
bitfld.long 0x00 8.--11. " USBDIV ,Divider for USB clock" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0. " USBS ,USB input clock selection" "PLLA,UPLL"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "PMC_MCKR,PMC Master Clock Register"
|
|
bitfld.long 0x00 13. " UPLLDIV2 ,UPLL divisor by 2" "/1,/2"
|
|
bitfld.long 0x00 8.--9. " MDIV ,Master clock division" "/1,/2,/4,/3"
|
|
bitfld.long 0x00 4.--6. " PRES ,Processor clock prescaler" "Clock,Clock/2,Clock/4,Clock/8,Clock/16,Clock/32,Clock/64,Clock/3"
|
|
bitfld.long 0x00 0.--1. " CSS ,Master clock source selection" "Slow,Main,PLLA,UPLL"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "PMC_USB,PMC USB Clock Register"
|
|
bitfld.long 0x00 8.--11. " USBDIV ,Divider for USB clock" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
bitfld.long 0x00 0. " USBS ,USB input clock selection" "PLLA,UPLL"
|
|
endif
|
|
if ((per.l(ad:0x400E0600+0xE4)&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PMC_PCK3,PMC Programmable Clock For ETM Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable clock prescaler"
|
|
bitfld.long 0x00 0.--2. " CSS ,Programmable clock selection" "Slow,Main,PLLA,UPLL,Master,Audio,?..."
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PMC_PCK4,PMC Programmable Clock For UART/USART Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable clock prescaler"
|
|
bitfld.long 0x00 0.--2. " CSS ,Programmable clock selection" "Slow,Main,PLLA,UPLL,Master,Audio,?..."
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PMC_PCK5,PMC Programmable Clock For MCAN Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable clock prescaler"
|
|
bitfld.long 0x00 0.--2. " CSS ,Programmable clock selection" "Slow,Main,PLLA,UPLL,Master,Audio,?..."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PMC_PCK6,PMC Programmable Clock For TCx Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable clock prescaler"
|
|
bitfld.long 0x00 0.--2. " CSS ,Programmable clock selection" "Slow,Main,PLLA,UPLL,Master,Audio,?..."
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PMC_PCK7,PMC Programmable Clock For TC0 Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable clock prescaler"
|
|
bitfld.long 0x00 0.--2. " CSS ,Programmable clock selection" "Slow,Main,PLLA,UPLL,Master,Audio,?..."
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "PMC_PCK0,PMC Programmable Clock For ETM Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable clock prescaler"
|
|
bitfld.long 0x00 0.--2. " CSS ,Programmable clock selection" "Slow,Main,PLLA,UPLL,Master,Audio,?..."
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "PMC_PCK1,PMC Programmable Clock For UART/USART Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable clock prescaler"
|
|
bitfld.long 0x00 0.--2. " CSS ,Programmable clock selection" "Slow,Main,PLLA,UPLL,Master,Audio,?..."
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "PMC_PCK2,PMC Programmable Clock For MCAN Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable clock prescaler"
|
|
bitfld.long 0x00 0.--2. " CSS ,Programmable clock selection" "Slow,Main,PLLA,UPLL,Master,Audio,?..."
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "PMC_PCK3,PMC Programmable Clock For TCx Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable clock prescaler"
|
|
bitfld.long 0x00 0.--2. " CSS ,Programmable clock selection" "Slow,Main,PLLA,UPLL,Master,Audio,?..."
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "PMC_PCK4,PMC Programmable Clock For TC0 Register"
|
|
hexmask.long.byte 0x00 4.--11. 1. " PRES ,Programmable clock prescaler"
|
|
bitfld.long 0x00 0.--2. " CSS ,Programmable clock selection" "Slow,Main,PLLA,UPLL,Master,Audio,?..."
|
|
endif
|
|
newline
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "PMC_SR,PMC Status Register"
|
|
in
|
|
newline
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PMC_IMR_SET/CLR,PMC Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 21. -0x0C 21. -0x08 21. " XT32KERR ,Slow crystal oscillator error interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x0C 18. -0x08 18. " CFDEV ,Clock failure detector event interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x0C 17. -0x08 17. " MOSCRCS ,Main on-chip RC status interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x0C 16. -0x08 16. " MOSCSELS ,Main oscillator selection status interrupt mask" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 14. -0x0C 14. -0x08 14. " PCKRDY[6] ,Programmable clock ready 6 interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x0C 13. -0x08 13. " [5] ,Programmable clock ready 5 interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x0C 12. -0x08 12. " [4] ,Programmable clock ready 4 interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x0C 11. -0x08 11. " [3] ,Programmable clock ready 3 interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x0C 10. -0x08 10. " [2] ,Programmable clock ready 2 interrupt mask" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x0C 6. -0x08 6. " LOCKU ,UTMI PLL lock interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x0C 3. -0x08 3. " MCKRDY ,Master clock ready interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x0C 1. -0x08 1. " LOCKA ,PLLA lock interrupt mask" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x0C 0. -0x08 0. " MOSCXTS ,Main crystal oscillator status interrupt mask" "Disabled,Enabled"
|
|
if ((per.l(ad:0x400E0600+0xE4)&0x01)==0x00)
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "PMC_FSMR,PMC Fast Startup Mode Register"
|
|
bitfld.long 0x00 23. " FFLPM ,Force flash low-power mode" "In wait,Immediately"
|
|
bitfld.long 0x00 21.--22. " FLPM ,Flash low power mode" "Standby,Deep powerdown,Idle,?..."
|
|
bitfld.long 0x00 20. " LPM ,Low power mode" "Sleep,Wait"
|
|
bitfld.long 0x00 18. " USBAL ,USB alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " RTCAL ,RTC alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RTTAL ,RTT alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " FSTT[15] ,Fast startup input enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Fast startup input enable 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Fast startup input enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Fast startup input enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Fast startup input enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Fast startup input enable 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Fast startup input enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Fast startup input enable 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Fast startup input enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Fast startup input enable 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Fast startup input enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Fast startup input enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Fast startup input enable 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Fast startup input enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Fast startup input enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Fast startup input enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "PMC_FSPR,PMC Fast Startup Polarity Register"
|
|
bitfld.long 0x04 15. " FSTP[15] ,Fast startup input polarity 15" "Low,High"
|
|
bitfld.long 0x04 14. " [14] ,Fast startup input polarity 14" "Low,High"
|
|
bitfld.long 0x04 13. " [13] ,Fast startup input polarity 13" "Low,High"
|
|
bitfld.long 0x04 12. " [12] ,Fast startup input polarity 12" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Fast startup input polarity 11" "Low,High"
|
|
bitfld.long 0x04 10. " [10] ,Fast startup input polarity 10" "Low,High"
|
|
bitfld.long 0x04 9. " [9] ,Fast startup input polarity 9" "Low,High"
|
|
bitfld.long 0x04 8. " [8] ,Fast startup input polarity 8" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Fast startup input polarity 7" "Low,High"
|
|
bitfld.long 0x04 6. " [6] ,Fast startup input polarity 6" "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,Fast startup input polarity 5" "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,Fast startup input polarity 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Fast startup input polarity 3" "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,Fast startup input polarity 2" "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,Fast startup input polarity 1" "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,Fast startup input polarity 0" "Low,High"
|
|
else
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "PMC_FSMR,PMC Fast Startup Mode Register"
|
|
bitfld.long 0x00 23. " FFLPM ,Force flash low-power mode" "In wait,Immediately"
|
|
bitfld.long 0x00 21.--22. " FLPM ,Flash low power mode" "Standby,Deep powerdown,Idle,?..."
|
|
bitfld.long 0x00 20. " LPM ,Low power mode" "Sleep,Wait"
|
|
bitfld.long 0x00 18. " USBAL ,USB alarm enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " RTCAL ,RTC alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " RTTAL ,RTT alarm enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " FSTT[15] ,Fast startup input enable 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Fast startup input enable 14" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Fast startup input enable 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Fast startup input enable 12" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Fast startup input enable 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Fast startup input enable 10" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Fast startup input enable 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Fast startup input enable 8" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Fast startup input enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Fast startup input enable 6" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Fast startup input enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Fast startup input enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Fast startup input enable 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Fast startup input enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Fast startup input enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Fast startup input enable 0" "Disabled,Enabled"
|
|
line.long 0x04 "PMC_FSPR,PMC Fast Startup Polarity Register"
|
|
bitfld.long 0x04 15. " FSTP[15] ,Fast startup input polarity 15" "Low,High"
|
|
bitfld.long 0x04 14. " [14] ,Fast startup input polarity 14" "Low,High"
|
|
bitfld.long 0x04 13. " [13] ,Fast startup input polarity 13" "Low,High"
|
|
bitfld.long 0x04 12. " [12] ,Fast startup input polarity 12" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Fast startup input polarity 11" "Low,High"
|
|
bitfld.long 0x04 10. " [10] ,Fast startup input polarity 10" "Low,High"
|
|
bitfld.long 0x04 9. " [9] ,Fast startup input polarity 9" "Low,High"
|
|
bitfld.long 0x04 8. " [8] ,Fast startup input polarity 8" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,Fast startup input polarity 7" "Low,High"
|
|
bitfld.long 0x04 6. " [6] ,Fast startup input polarity 6" "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,Fast startup input polarity 5" "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,Fast startup input polarity 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Fast startup input polarity 3" "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,Fast startup input polarity 2" "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,Fast startup input polarity 1" "Low,High"
|
|
bitfld.long 0x04 0. " [0] ,Fast startup input polarity 0" "Low,High"
|
|
endif
|
|
wgroup.long 0x78++0x03
|
|
line.long 0x00 "PMC_FOCR,PMC Fault Output Clear Register"
|
|
bitfld.long 0x00 0. " FOCLR ,Fault output clear" "No effect,Clear"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PMC_WPMR,PMC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protection KEY password"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "PMC_WPSR,Write Protect Status Register"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x400E0600+0xE4)&0x01)==0x00)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "PMC_PCSR1_SET/CLR,PMC Peripheral Clock Set/Clear Register 1"
|
|
sif cpuis("ATSAMS70Q*")
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " SDRAMC ,SDRAM controller (peripheral ID 60) clock status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " PWM1 ,Pulse width modulation controller 1 (peripheral ID 60) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " ISI ,Image sensor interface (peripheral ID 59) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " XDMAC ,DMA controller (peripheral ID 58) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " TRNG ,True random number generator (peripheral ID 57) clock status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " AES ,Advanced encryption standard (peripheral ID 56) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " MLB0 ,MediaLB IRQ 0 (peripheral ID 53) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " TC3_2 ,Timer counter 3 channel 2 (peripheral ID 52) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " TC3_1 ,Timer counter 3 channel 1 (peripheral ID 51) clock status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " TC3_0 ,Timer counter 3 channel 0 (peripheral ID 50) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " TC2_2 ,Timer counter 2 channel 2 (peripheral ID 49) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " TC2_1 ,Timer counter 2 channel 1 (peripheral ID 48) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " TC2_0 ,Timer counter 2 channel 0 (peripheral ID 47) clock status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " UART4 ,Universal asynchronous receiver/transmitter 4 (peripheral ID 46) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " UART3 ,Universal asynchronous receiver/transmitter 3 (peripheral ID 45) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " UART2 ,Universal asynchronous receiver/transmitter 2 (peripheral ID 44) clock status" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("ATSAMS70Q*")
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " QSPI ,Quad I/O serial peripheral interface (peripheral ID 43) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SPI1 ,Serial peripheral interface 1 (peripheral ID 42) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TWIHS2 ,Two-wire interface (peripheral ID 41) clock status" "Disabled,Enabled"
|
|
newline
|
|
elif !cpuis("ATSAMS70J*")
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " QSPI ,Quad I/O serial peripheral interface (peripheral ID 43) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TWIHS2 ,Two-wire interface (peripheral ID 41) clock status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " AFEC1 ,Analog front end controller (peripheral ID 40) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " GMAC ,Ethernet MAC (peripheral ID 39) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " MCAN1 ,CAN IRQ line 1 (peripheral ID 37) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " MCAN0 ,CAN IRQ line 0 (peripheral ID 35) clock status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " USBHS ,USB host / device controller (peripheral ID 34) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ACC ,Analog comparator controller (peripheral ID 33) clock status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ICM ,Integrity check monitor (peripheral ID 32) clock status" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "PMC_PCSR1,PMC Peripheral Clock Status Register 1"
|
|
sif cpuis("ATSAMS70Q*")
|
|
bitfld.long 0x00 30. " SDRAMC ,SDRAM controller (peripheral ID 60) clock status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 28. " PWM1 ,Pulse width modulation controller 1 (peripheral ID 60) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ISI ,Image sensor interface (peripheral ID 59) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " XDMAC ,DMA controller (peripheral ID 58) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " TRNG ,True random number generator (peripheral ID 57) clock status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " AES ,Advanced encryption standard (peripheral ID 56) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " MLB0 ,MediaLB IRQ 0 (peripheral ID 53) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TC3_2 ,Timer counter 3 channel 2 (peripheral ID 52) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TC3_1 ,Timer counter 3 channel 1 (peripheral ID 51) clock status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " TC3_0 ,Timer counter 3 channel 0 (peripheral ID 50) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TC2_2 ,Timer counter 2 channel 2 (peripheral ID 49) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TC2_1 ,Timer counter 2 channel 1 (peripheral ID 48) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " TC2_0 ,Timer counter 2 channel 0 (peripheral ID 47) clock status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " UART4 ,Universal asynchronous receiver/transmitter 4 (peripheral ID 46) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " UART3 ,Universal asynchronous receiver/transmitter 3 (peripheral ID 45) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UART2 ,Universal asynchronous receiver/transmitter 2 (peripheral ID 44) clock status" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("ATSAMS70Q*")
|
|
bitfld.long 0x00 11. " QSPI ,Quad I/O serial peripheral interface (peripheral ID 43) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SPI1 ,Serial peripheral interface 1 (peripheral ID 42) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TWIHS2 ,Two-wire interface (peripheral ID 41) clock status" "Disabled,Enabled"
|
|
newline
|
|
elif !cpuis("ATSAMS70J*")
|
|
bitfld.long 0x00 11. " QSPI ,Quad I/O serial peripheral interface (peripheral ID 43) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TWIHS2 ,Two-wire interface (peripheral ID 41) clock status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8. " AFEC1 ,Analog front end controller (peripheral ID 40) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " GMAC ,Ethernet MAC (peripheral ID 39) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MCAN1 ,CAN IRQ line 1 (peripheral ID 37) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MCAN0 ,CAN IRQ line 0 (peripheral ID 35) clock status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " USBHS ,USB host / device controller (peripheral ID 34) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ACC ,Analog comparator controller (peripheral ID 33) clock status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ICM ,Integrity check monitor (peripheral ID 32) clock status" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "PMC_PCR,PMC Peripheral Control Register"
|
|
bitfld.long 0x00 29. " GCLKEN ,Generic clock enable" "Disable,Enable"
|
|
bitfld.long 0x00 28. " EN ,Enable" "Disable,Enable"
|
|
hexmask.long.byte 0x00 20.--27. 1. " GCLKDIV ,Generic clock division ratio"
|
|
newline
|
|
bitfld.long 0x00 12. " CMD ,Command" "Read,Write"
|
|
bitfld.long 0x00 8.--10. " GCLKCSS ,Generic clock source selection" "Slow,Main,PLLA,UPLL,Master,Audio,?..."
|
|
hexmask.long.byte 0x00 0.--6. 1. " PID ,Peripheral ID"
|
|
if ((per.l(ad:0x400E0600+0xE4)&0x01)==0x00)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,Selection of RC oscillator calibration bits for 12 mhz" "Flash memory,CAL12"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAL12 ,RC oscillator calibration bits for 12 mhz"
|
|
bitfld.long 0x00 15. " SEL8 ,Selection of RC oscillator calibration bits for 8 mhz" "Flash memory,CAL8"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CAL8 ,RC oscillator calibration bits for 8 mhz"
|
|
newline
|
|
bitfld.long 0x00 7. " SEL4 ,Selection of RC oscillator calibration bits for 4 mhz" "Flash memory,CAL4"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAL4 ,RC oscillator calibration bits for 4 mhz"
|
|
else
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "PMC_OCR,PMC Oscillator Calibration Register"
|
|
bitfld.long 0x00 23. " SEL12 ,Selection of RC oscillator calibration bits for 12 mhz" "Flash memory,CAL12"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CAL12 ,RC oscillator calibration bits for 12 mhz"
|
|
bitfld.long 0x00 15. " SEL8 ,Selection of RC oscillator calibration bits for 8 mhz" "Flash memory,CAL8"
|
|
hexmask.long.byte 0x00 8.--14. 1. " CAL8 ,RC oscillator calibration bits for 8 mhz"
|
|
newline
|
|
bitfld.long 0x00 7. " SEL4 ,Selection of RC oscillator calibration bits for 4 mhz" "Flash memory,CAL4"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CAL4 ,RC oscillator calibration bits for 4 mhz"
|
|
endif
|
|
if ((per.l(ad:0x400E0600+0xE4)&0x01)==0x00)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "PMC_SLPWK_SR0_SET/CLR,PMC SleepWalking Set/Clear Register 0"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " PWM0 ,Pulse width modulation controller 0 (peripheral ID 31) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " DACC ,Digital to analog converter (peripheral ID 30) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " AFEC0 ,Analog front-end controller 0 (peripheral ID 29) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " TC1_2 ,Timer counter 1 channel 2 controller (peripheral ID 28) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " TC1_1 ,Timer counter 1 channel 1 controller (peripheral ID 27) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " TC1_0 ,Timer counter 1 channel 0 controller (peripheral ID 26) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " TC0_2 ,Timer counter 0 channel 2 (peripheral ID 25) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " TC0_1 ,Timer counter 0 channel 1 (peripheral ID 24) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " TC0_0 ,Timer counter 0 channel 0 (peripheral ID 23) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " SSC ,Synchronous serial controller (peripheral ID 22) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("ATSAMS70J*")
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " SPI0 ,Serial peripheral interface 0 (peripheral ID 21) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " TWIHS1 ,Two-Wire interface 1 (peripheral ID 20) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " TWIHS0 ,Two-Wire interface 0 (peripheral ID 19) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("ATSAMS70J*")
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " HSMCI ,High speed multimedia card interface (peripheral ID 18) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " PIOE ,Parallel I/O controller E (peripheral ID 12) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " PIOD ,Parallel I/O controller D (peripheral ID 11) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("ATSAMS70J*")
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " USART2 ,USART 2 (peripheral ID 15) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " USART1 ,USART 1 (peripheral ID 14) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " USART0 ,USART 0 (peripheral ID 13) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " PIOC ,Parallel I/O controller C (peripheral ID 12) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " PIOB ,Parallel I/O controller B (peripheral ID 11) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " PIOA ,Parallel I/O controller A (peripheral ID 10) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " SMC ,Static memory controller (peripheral ID 9) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " UART1 ,Universal asynchronous receiver transmitter 1 (peripheral ID 8) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " UART0 ,Universal asynchronous receiver transmitter 0 (peripheral ID 7) sleepwalking status" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "PMC_SLPWK_SR0,PMC SleepWalking Status Register 0"
|
|
bitfld.long 0x00 31. " PWM0 ,Pulse width modulation controller 0 (peripheral ID 31) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DACC ,Digital to analog converter (peripheral ID 30) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " AFEC0 ,Analog front-end controller 0 (peripheral ID 29) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 28. " TC1_2 ,Timer counter 1 channel 2 controller (peripheral ID 28) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TC1_1 ,Timer counter 1 channel 1 controller (peripheral ID 27) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TC1_0 ,Timer counter 1 channel 0 controller (peripheral ID 26) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " TC0_2 ,Timer counter 0 channel 2 (peripheral ID 25) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " TC0_1 ,Timer counter 0 channel 1 (peripheral ID 24) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TC0_0 ,Timer counter 0 channel 0 (peripheral ID 23) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " SSC ,Synchronous serial controller (peripheral ID 22) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("ATSAMS70J*")
|
|
bitfld.long 0x00 21. " SPI0 ,Serial peripheral interface 0 (peripheral ID 21) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 20. " TWIHS1 ,Two-Wire interface 1 (peripheral ID 20) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TWIHS0 ,Two-Wire interface 0 (peripheral ID 19) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("ATSAMS70J*")
|
|
bitfld.long 0x00 18. " HSMCI ,High speed multimedia card interface (peripheral ID 18) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 17. " PIOE ,Parallel I/O controller E (peripheral ID 12) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PIOD ,Parallel I/O controller D (peripheral ID 11) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("ATSAMS70J*")
|
|
bitfld.long 0x00 15. " USART2 ,USART 2 (peripheral ID 15) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " USART1 ,USART 1 (peripheral ID 14) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " USART0 ,USART 0 (peripheral ID 13) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 12. " PIOC ,Parallel I/O controller C (peripheral ID 12) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PIOB ,Parallel I/O controller B (peripheral ID 11) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PIOA ,Parallel I/O controller A (peripheral ID 10) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SMC ,Static memory controller (peripheral ID 9) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " UART1 ,Universal asynchronous receiver transmitter 1 (peripheral ID 8) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " UART0 ,Universal asynchronous receiver transmitter 0 (peripheral ID 7) sleepwalking status" "Disabled,Enabled"
|
|
endif
|
|
if ((per.l(ad:0x400E0600+0xE4)&0x01)==0x00)
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "PMC_SLPWK_SR1_SET/CLR,PMC SleepWalking Set/Clear Register 1"
|
|
sif cpuis("ATSAMS70Q*")
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " SDRAMC ,SDRAM controller (peripheral ID 60) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " PWM1 ,Pulse width modulation controller 1 (peripheral ID 60) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " ISI ,Image sensor interface (peripheral ID 59) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " XDMAC ,DMA controller (peripheral ID 58) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " TRNG ,True random number generator (peripheral ID 57) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " AES ,Advanced encryption standard (peripheral ID 56) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " MLB0 ,MediaLB IRQ 0 (peripheral ID 53) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " TC3_2 ,Timer counter 3 channel 2 (peripheral ID 52) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " TC3_1 ,Timer counter 3 channel 1 (peripheral ID 51) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " TC3_0 ,Timer counter 3 channel 0 (peripheral ID 50) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " TC2_2 ,Timer counter 2 channel 2 (peripheral ID 49) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " TC2_1 ,Timer counter 2 channel 1 (peripheral ID 48) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " TC2_0 ,Timer counter 2 channel 0 (peripheral ID 47) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " UART4 ,Universal asynchronous receiver/transmitter 4 (peripheral ID 46) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " UART3 ,Universal asynchronous receiver/transmitter 3 (peripheral ID 45) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " UART2 ,Universal asynchronous receiver/transmitter 2 (peripheral ID 44) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("ATSAMS70Q*")
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " QSPI ,Quad I/O serial peripheral interface (peripheral ID 43) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SPI1 ,Serial peripheral interface 1 (peripheral ID 42) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TWIHS2 ,Two-wire interface (peripheral ID 41) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
elif !cpuis("ATSAMS70J*")
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " QSPI ,Quad I/O serial peripheral interface (peripheral ID 43) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TWIHS2 ,Two-wire interface (peripheral ID 41) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " AFEC1 ,Analog front end controller (peripheral ID 40) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " GMAC ,Ethernet MAC (peripheral ID 39) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " MCAN1 ,CAN IRQ line 1 (peripheral ID 37) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " MCAN0 ,CAN IRQ line 0 (peripheral ID 35) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " USBHS ,USB host / device controller (peripheral ID 34) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " ACC ,Analog comparator controller (peripheral ID 33) sleepwalking status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " ICM ,Integrity check monitor (peripheral ID 32) sleepwalking status" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "PMC_SLPWK_SR1,PMC SleepWalking Status Register 1"
|
|
sif cpuis("ATSAMS70Q*")
|
|
bitfld.long 0x00 30. " SDRAMC ,SDRAM controller (peripheral ID 60) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 28. " PWM1 ,Pulse width modulation controller 1 (peripheral ID 60) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " ISI ,Image sensor interface (peripheral ID 59) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " XDMAC ,DMA controller (peripheral ID 58) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " TRNG ,True random number generator (peripheral ID 57) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " AES ,Advanced encryption standard (peripheral ID 56) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " MLB0 ,MediaLB IRQ 0 (peripheral ID 53) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TC3_2 ,Timer counter 3 channel 2 (peripheral ID 52) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TC3_1 ,Timer counter 3 channel 1 (peripheral ID 51) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 18. " TC3_0 ,Timer counter 3 channel 0 (peripheral ID 50) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TC2_2 ,Timer counter 2 channel 2 (peripheral ID 49) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TC2_1 ,Timer counter 2 channel 1 (peripheral ID 48) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " TC2_0 ,Timer counter 2 channel 0 (peripheral ID 47) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " UART4 ,Universal asynchronous receiver/transmitter 4 (peripheral ID 46) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " UART3 ,Universal asynchronous receiver/transmitter 3 (peripheral ID 45) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " UART2 ,Universal asynchronous receiver/transmitter 2 (peripheral ID 44) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("ATSAMS70Q*")
|
|
bitfld.long 0x00 11. " QSPI ,Quad I/O serial peripheral interface (peripheral ID 43) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SPI1 ,Serial peripheral interface 1 (peripheral ID 42) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TWIHS2 ,Two-wire interface (peripheral ID 41) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
elif !cpuis("ATSAMS70J*")
|
|
bitfld.long 0x00 11. " QSPI ,Quad I/O serial peripheral interface (peripheral ID 43) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TWIHS2 ,Two-wire interface (peripheral ID 41) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8. " AFEC1 ,Analog front end controller (peripheral ID 40) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " GMAC ,Ethernet MAC (peripheral ID 39) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MCAN1 ,CAN IRQ line 1 (peripheral ID 37) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MCAN0 ,CAN IRQ line 0 (peripheral ID 35) sleepwalking status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " USBHS ,USB host / device controller (peripheral ID 34) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ACC ,Analog comparator controller (peripheral ID 33) sleepwalking status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ICM ,Integrity check monitor (peripheral ID 32) sleepwalking status" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "PMC_SLPWK_ASR0,PMC SleepWalking Activity Status Register 0"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " PWM0 ,Pulse width modulation controller 0 (peripheral ID 31) sleepwalking activity status" "Not activated,Activated"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " DACC ,Digital to analog converter (peripheral ID 30) sleepwalking activity status" "Not activated,Activated"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " AFEC0 ,Analog front-end controller 0 (peripheral ID 29) sleepwalking activity status" "Not activated,Activated"
|
|
newline
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " TC1_2 ,Timer counter 1 channel 2 controller (peripheral ID 28) sleepwalking activity status" "Not activated,Activated"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " TC1_1 ,Timer counter 1 channel 1 controller (peripheral ID 27) sleepwalking activity status" "Not activated,Activated"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " TC1_0 ,Timer counter 1 channel 0 controller (peripheral ID 26) sleepwalking activity status" "Not activated,Activated"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " TC0_2 ,Timer counter 0 channel 2 (peripheral ID 25) sleepwalking activity status" "Not activated,Activated"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " TC0_1 ,Timer counter 0 channel 1 (peripheral ID 24) sleepwalking activity status" "Not activated,Activated"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " TC0_0 ,Timer counter 0 channel 0 (peripheral ID 23) sleepwalking activity status" "Not activated,Activated"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " SSC ,Synchronous serial controller (peripheral ID 22) sleepwalking activity status" "Not activated,Activated"
|
|
newline
|
|
sif !cpuis("ATSAMS70J*")
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " SPI0 ,Serial peripheral interface 0 (peripheral ID 21) sleepwalking activity status" "Not activated,Activated"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " TWIHS1 ,Two-Wire interface 1 (peripheral ID 20) sleepwalking activity status" "Not activated,Activated"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " TWIHS0 ,Two-Wire interface 0 (peripheral ID 19) sleepwalking activity status" "Not activated,Activated"
|
|
newline
|
|
sif !cpuis("ATSAMS70J*")
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " HSMCI ,High speed multimedia card interface (peripheral ID 18) sleepwalking activity status" "Not activated,Activated"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " PIOE ,Parallel I/O controller E (peripheral ID 12) sleepwalking activity status" "Not activated,Activated"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " PIOD ,Parallel I/O controller D (peripheral ID 11) sleepwalking activity status" "Not activated,Activated"
|
|
newline
|
|
sif !cpuis("ATSAMS70J*")
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " USART2 ,USART 2 (peripheral ID 15) sleepwalking activity status" "Not activated,Activated"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " USART1 ,USART 1 (peripheral ID 14) sleepwalking activity status" "Not activated,Activated"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " USART0 ,USART 0 (peripheral ID 13) sleepwalking activity status" "Not activated,Activated"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " PIOC ,Parallel I/O controller C (peripheral ID 12) sleepwalking activity status" "Not activated,Activated"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " PIOB ,Parallel I/O controller B (peripheral ID 11) sleepwalking activity status" "Not activated,Activated"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " PIOA ,Parallel I/O controller A (peripheral ID 10) sleepwalking activity status" "Not activated,Activated"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " SMC ,Static memory controller (peripheral ID 9) sleepwalking activity status" "Not activated,Activated"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " UART1 ,Universal asynchronous receiver transmitter 1 (peripheral ID 8) sleepwalking activity status" "Not activated,Activated"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " UART0 ,Universal asynchronous receiver transmitter 0 (peripheral ID 7) sleepwalking activity status" "Not activated,Activated"
|
|
if ((per.l(ad:0x400E0600+0xE4)&0x01)==0x00)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "PMC_PMMR,PLL Maximum Multiplier Value Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " PLLA_MMAX ,PLLA maximum allowed multiplier value"
|
|
else
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "PMC_PMMR,PLL Maximum Multiplier Value Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " PLLA_MMAX ,PLLA maximum allowed multiplier value"
|
|
endif
|
|
rgroup.long 0x140++0x07
|
|
line.long 0x00 "PMC_SLPWK_ASR1,PMC SleepWalking Activity Status Register 1"
|
|
sif cpuis("ATSAMS70Q*")
|
|
bitfld.long 0x00 30. " SDRAMC ,SDRAM controller (peripheral ID 60) sleepwalking activity status" "Not activated,Activated"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 28. " PWM1 ,Pulse width modulation controller 1 (peripheral ID 60) sleepwalking activity status" "Not activated,Activated"
|
|
bitfld.long 0x00 27. " ISI ,Image sensor interface (peripheral ID 59) sleepwalking activity status" "Not activated,Activated"
|
|
bitfld.long 0x00 26. " XDMAC ,DMA controller (peripheral ID 58) sleepwalking activity status" "Not activated,Activated"
|
|
bitfld.long 0x00 25. " TRNG ,True random number generator (peripheral ID 57) sleepwalking activity status" "Not activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 24. " AES ,Advanced encryption standard (peripheral ID 56) sleepwalking activity status" "Not activated,Activated"
|
|
bitfld.long 0x00 21. " MLB0 ,MediaLB IRQ 0 (peripheral ID 53) sleepwalking activity status" "Not activated,Activated"
|
|
bitfld.long 0x00 20. " TC3_2 ,Timer counter 3 channel 2 (peripheral ID 52) sleepwalking activity status" "Not activated,Activated"
|
|
bitfld.long 0x00 19. " TC3_1 ,Timer counter 3 channel 1 (peripheral ID 51) sleepwalking activity status" "Not activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 18. " TC3_0 ,Timer counter 3 channel 0 (peripheral ID 50) sleepwalking activity status" "Not activated,Activated"
|
|
bitfld.long 0x00 17. " TC2_2 ,Timer counter 2 channel 2 (peripheral ID 49) sleepwalking activity status" "Not activated,Activated"
|
|
bitfld.long 0x00 16. " TC2_1 ,Timer counter 2 channel 1 (peripheral ID 48) sleepwalking activity status" "Not activated,Activated"
|
|
bitfld.long 0x00 15. " TC2_0 ,Timer counter 2 channel 0 (peripheral ID 47) sleepwalking activity status" "Not activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 14. " UART4 ,Universal asynchronous receiver/transmitter 4 (peripheral ID 46) sleepwalking activity status" "Not activated,Activated"
|
|
bitfld.long 0x00 13. " UART3 ,Universal asynchronous receiver/transmitter 3 (peripheral ID 45) sleepwalking activity status" "Not activated,Activated"
|
|
bitfld.long 0x00 12. " UART2 ,Universal asynchronous receiver/transmitter 2 (peripheral ID 44) sleepwalking activity status" "Not activated,Activated"
|
|
newline
|
|
sif cpuis("ATSAMS70Q*")
|
|
bitfld.long 0x00 11. " QSPI ,Quad I/O serial peripheral interface (peripheral ID 43) sleepwalking activity status" "Not activated,Activated"
|
|
bitfld.long 0x00 10. " SPI1 ,Serial peripheral interface 1 (peripheral ID 42) sleepwalking activity status" "Not activated,Activated"
|
|
bitfld.long 0x00 9. " TWIHS2 ,Two-wire interface (peripheral ID 41) sleepwalking activity status" "Not activated,Activated"
|
|
newline
|
|
elif !cpuis("ATSAMS70J*")
|
|
bitfld.long 0x00 11. " QSPI ,Quad I/O serial peripheral interface (peripheral ID 43) sleepwalking activity status" "Not activated,Activated"
|
|
bitfld.long 0x00 9. " TWIHS2 ,Two-wire interface (peripheral ID 41) sleepwalking activity status" "Not activated,Activated"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8. " AFEC1 ,Analog front end controller (peripheral ID 40) sleepwalking activity status" "Not activated,Activated"
|
|
bitfld.long 0x00 7. " GMAC ,Ethernet MAC (peripheral ID 39) sleepwalking activity status" "Not activated,Activated"
|
|
bitfld.long 0x00 5. " MCAN1 ,CAN IRQ line 1 (peripheral ID 37) sleepwalking activity status" "Not activated,Activated"
|
|
bitfld.long 0x00 3. " MCAN0 ,CAN IRQ line 0 (peripheral ID 35) sleepwalking activity status" "Not activated,Activated"
|
|
newline
|
|
bitfld.long 0x00 2. " USBHS ,USB host / device controller (peripheral ID 34) sleepwalking activity status" "Not activated,Activated"
|
|
bitfld.long 0x00 1. " ACC ,Analog comparator controller (peripheral ID 33) sleepwalking activity status" "Not activated,Activated"
|
|
bitfld.long 0x00 0. " ICM ,Integrity check monitor (peripheral ID 32) sleepwalking activity status" "Not activated,Activated"
|
|
line.long 0x04 "PMC_SLPWK_AIPR,PMC SleepWalking Activity In Progress Register"
|
|
bitfld.long 0x04 0. " AIP ,Activity in progress" "No activity,Activity"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "PIO (Parallel Input/Output)"
|
|
sif cpuis("ATSAMS70Q*")
|
|
tree "Port A"
|
|
base ad:0x400E0E00
|
|
width 16.
|
|
if ((per.l(ad:0x400E0E00+0xE4)&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PSR_SET/CLR,PIO Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "OSR_SET/CLR,PIO Output Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IFSR_SET/CLR,PIO Input Filter Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PSR,PIO Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "OSR,PIO Output Enable Set/Clear Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "IFSR,PIO Input Filter Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ODSR_SET/CLR,PIO Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 output data status" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 output data status" "Low,High"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 output data status" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 output data status" "Low,High"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 output data status" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 output data status" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output data status" "Low,High"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 output data status" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output data status" "Low,High"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output data status" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 output data status" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 output data status" "Low,High"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 output data status" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 output data status" "Low,High"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 output data status" "Low,High"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 output data status" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output data status" "Low,High"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output data status" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output data status" "Low,High"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PDSR,PIO Data Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 output data status" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 output data status" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 output data status" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 output data status" "Low,High"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 output data status" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 output data status" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output data status" "Low,High"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 output data status" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output data status" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output data status" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 output data status" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 output data status" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 output data status" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 output data status" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 output data status" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 output data status" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output data status" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output data status" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output data status" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "IMR_SET/CLR,PIO Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ISR,PIO Interrupt Status Register"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x400E0E00+0xE4)&0x01)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MDSR_SET/CLR,PIO Multi-Driver Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PUSR_SET/CLR,PIO Pull Up Disable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x08 11. " [11] ,Pin 11 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x08 10. " [10] ,Pin 10 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 31. " P[31] ,Pin 31 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 30. " [30] ,Pin 30 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 29. " [29] ,Pin 29 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 28. " [28] ,Pin 28 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 27. " [27] ,Pin 27 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 26. " [26] ,Pin 26 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,Pin 25 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 24. " [24] ,Pin 24 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 23. " [23] ,Pin 23 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 22. " [22] ,Pin 22 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 21. " [21] ,Pin 21 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 20. " [20] ,Pin 20 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Pin 19 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 18. " [18] ,Pin 18 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 17. " [17] ,Pin 17 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 16. " [16] ,Pin 16 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 15. " [15] ,Pin 15 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 14. " [14] ,Pin 14 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,Pin 13 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 11. " [11] ,Pin 11 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 10. " [10] ,Pin 10 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 6. " [6] ,Pin 6 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "MDSR,PIO Multi-Driver Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "PUSR,PIO Pull Up Disable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 31. " P[31] ,Pin 31 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 30. " [30] ,Pin 30 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 29. " [29] ,Pin 29 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 28. " [28] ,Pin 28 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 27. " [27] ,Pin 27 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 26. " [26] ,Pin 26 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,Pin 25 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 24. " [24] ,Pin 24 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 23. " [23] ,Pin 23 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 22. " [22] ,Pin 22 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 21. " [21] ,Pin 21 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 20. " [20] ,Pin 20 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Pin 19 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 18. " [18] ,Pin 18 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 17. " [17] ,Pin 17 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 16. " [16] ,Pin 16 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 15. " [15] ,Pin 15 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 14. " [14] ,Pin 14 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,Pin 13 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 11. " [11] ,Pin 11 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 10. " [10] ,Pin 10 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 6. " [6] ,Pin 6 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "IFSCSR_SET/CLR,PIO Input Filter Slow Clock Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P[31] ,Pin 31 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " [30] ,Pin 30 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " [29] ,Pin 29 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " [28] ,Pin 28 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " [27] ,Pin 27 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Pin 26 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Pin 25 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " [23] ,Pin 23 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " [19] ,Pin 19 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " [19] ,Pin 19 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " [18] ,Pin 18 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " [17] ,Pin 17 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " [16] ,Pin 16 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " [15] ,Pin 15 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Pin 14 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Pin 13 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow clock divider selection for debouncing"
|
|
if ((per.l(ad:0x400E0E00+0xE4)&0x01)==0x00)
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PPDSR_SET/CLR,PIO Pad Pull Down Disable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "OWSR_SET/CLR,PIO Output Write Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "PPDSR,PIO Pad Pull Down Disable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "OWSR,PIO Output Write Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "AIMMR_SET/CLR,PIO Additional Interrupt Modes Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 peripheral cd status" "Both edge,Registers"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "ELSR_SET/CLR,Edge/level Interrupt Source Selection Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P[31] ,Pin 31 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " [30] ,Pin 30 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " [29] ,Pin 29 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " [28] ,Pin 28 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " [27] ,Pin 27 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Pin 26 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Pin 25 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " [23] ,Pin 23 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " [20] ,Pin 20 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " [19] ,Pin 19 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " [18] ,Pin 18 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " [17] ,Pin 17 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " [16] ,Pin 16 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " [15] ,Pin 15 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Pin 14 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Pin 13 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Edge,Level"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FRLHSR_SET/CLR,PIO Fall/Rise - Low/High Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P[31] ,Pin 31 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " [30] ,Pin 30 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " [29] ,Pin 29 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " [28] ,Pin 28 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " [27] ,Pin 27 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Pin 26 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Pin 25 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " [23] ,Pin 23 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " [20] ,Pin 20 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " [19] ,Pin 19 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " [18] ,Pin 18 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " [17] ,Pin 17 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " [16] ,Pin 16 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " [15] ,Pin 15 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Pin 14 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Pin 13 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 lock status" "Not locked,Locked"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,PIO Write Protect Status Register"
|
|
in
|
|
newline
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SCHMITT,PIO Schmitt Trigger Register"
|
|
bitfld.long 0x00 31. " SCHMITT[31] ,Schmitt trigger 31 disable" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Schmitt trigger 30 disable" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,Schmitt trigger 29 disable" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Schmitt trigger 28 disable" "No,Yes"
|
|
bitfld.long 0x00 27. " [27] ,Schmitt trigger 27 disable" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Schmitt trigger 26 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Schmitt trigger 25 disable" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Schmitt trigger 24 disable" "No,Yes"
|
|
bitfld.long 0x00 23. " [23] ,Schmitt trigger 23 disable" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Schmitt trigger 22 disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Schmitt trigger 21 disable" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Schmitt trigger 20 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Schmitt trigger 19 disable" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Schmitt trigger 18 disable" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Schmitt trigger 17 disable" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Schmitt trigger 16 disable" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Schmitt trigger 15 disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Schmitt trigger 14 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Schmitt trigger 13 disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Schmitt trigger 12 disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Schmitt trigger 11 disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Schmitt trigger 10 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Schmitt trigger 9 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Schmitt trigger 8 disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Schmitt trigger 7 disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Schmitt trigger 6 disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Schmitt trigger 5 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Schmitt trigger 4 disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Schmitt trigger 3 disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Schmitt trigger 2 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Schmitt trigger 1 disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Schmitt trigger 0 disable" "No,Yes"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DRIVER,PIO I/O Drive Register"
|
|
bitfld.long 0x00 31. " LINE[31] ,Drive of PIO line 31" "Low,High"
|
|
bitfld.long 0x00 31. " [30] ,Drive of PIO line 30" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,Drive of PIO line 29" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,Drive of PIO line 28" "Low,High"
|
|
bitfld.long 0x00 27. " [27] ,Drive of PIO line 27" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,Drive of PIO line 26" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Drive of PIO line 25" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Drive of PIO line 24" "Low,High"
|
|
bitfld.long 0x00 23. " [23] ,Drive of PIO line 23" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,Drive of PIO line 22" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Drive of PIO line 21" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Drive of PIO line 20" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Drive of PIO line 19" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Drive of PIO line 18" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,Drive of PIO line 17" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Drive of PIO line 16" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Drive of PIO line 15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Drive of PIO line 14" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Drive of PIO line 13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Drive of PIO line 12" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Drive of PIO line 11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Drive of PIO line 10" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Drive of PIO line 9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Drive of PIO line 8" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Drive of PIO line 7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Drive of PIO line 6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Drive of PIO line 5" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Drive of PIO line 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Drive of PIO line 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Drive of PIO line 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Drive of PIO line 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Drive of PIO line 0" "Low,High"
|
|
width 15.
|
|
newline
|
|
if ((per.l(ad:0x400E0E00+0xE4)&0x01)==0x00)
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "PCIMR_SET/CLR,PIO Parallel Capture Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RXBUFF ,Reception buffer full interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENDRX ,End of reception transfer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " OVRE ,Parallel capture mode overrun error interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DRDY ,Parallel capture mode data ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
in
|
|
newline
|
|
if (per.l(ad:0x400E0E00+0x150)&0x30)==0x00
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RDATA ,Parallel capture mode reception data"
|
|
elif (per.l(ad:0x400E0E00+0x150)&0x30)==0x10
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA ,Parallel capture mode reception data"
|
|
else
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
width 0x0B
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port B"
|
|
base ad:0x400E1000
|
|
width 16.
|
|
if ((per.l(ad:0x400E1000+0xE4)&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PSR_SET/CLR,PIO Enable Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "OSR_SET/CLR,PIO Output Enable Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IFSR_SET/CLR,PIO Input Filter Enable Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PSR,PIO Enable Status Register"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "OSR,PIO Output Enable Set/Clear Register"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "IFSR,PIO Input Filter Enable Status Register"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ODSR_SET/CLR,PIO Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 output data status" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output data status" "Low,High"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PDSR,PIO Data Status Register"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 output data status" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output data status" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "IMR_SET/CLR,PIO Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ISR,PIO Interrupt Status Register"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x400E1000+0xE4)&0x01)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MDSR_SET/CLR,PIO Multi-Driver Enable Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PUSR_SET/CLR,PIO Pull Up Disable Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 13. " P[13] ,Pin 13 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 6. " [6] ,Pin 6 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "MDSR,PIO Multi-Driver Enable Status Register"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "PUSR,PIO Pull Up Disable Status Register"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 13. " P[13] ,Pin 13 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 6. " [6] ,Pin 6 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "IFSCSR_SET/CLR,PIO Input Filter Slow Clock Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P[13] ,Pin 13 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow clock divider selection for debouncing"
|
|
if ((per.l(ad:0x400E1000+0xE4)&0x01)==0x00)
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PPDSR_SET/CLR,PIO Pad Pull Down Disable Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "OWSR_SET/CLR,PIO Output Write Enable Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "PPDSR,PIO Pad Pull Down Disable Status Register"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "OWSR,PIO Output Write Enable Status Register"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "AIMMR_SET/CLR,PIO Additional Interrupt Modes Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 peripheral cd status" "Both edge,Registers"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "ELSR_SET/CLR,Edge/level Interrupt Source Selection Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P[13] ,Pin 13 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Edge,Level"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FRLHSR_SET/CLR,PIO Fall/Rise - Low/High Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P[13] ,Pin 13 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 lock status" "Not locked,Locked"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,PIO Write Protect Status Register"
|
|
in
|
|
newline
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SCHMITT,PIO Schmitt Trigger Register"
|
|
bitfld.long 0x00 13. " SCHMITT[13] ,Schmitt trigger 13 disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Schmitt trigger 12 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Schmitt trigger 9 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Schmitt trigger 8 disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Schmitt trigger 7 disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Schmitt trigger 6 disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Schmitt trigger 5 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Schmitt trigger 4 disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Schmitt trigger 3 disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Schmitt trigger 2 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Schmitt trigger 1 disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Schmitt trigger 0 disable" "No,Yes"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DRIVER,PIO I/O Drive Register"
|
|
bitfld.long 0x00 13. " LINE[13] ,Drive of PIO line 13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Drive of PIO line 12" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Drive of PIO line 9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Drive of PIO line 8" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Drive of PIO line 7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Drive of PIO line 6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Drive of PIO line 5" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Drive of PIO line 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Drive of PIO line 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Drive of PIO line 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Drive of PIO line 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Drive of PIO line 0" "Low,High"
|
|
width 15.
|
|
newline
|
|
if ((per.l(ad:0x400E1000+0xE4)&0x01)==0x00)
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "PCIMR_SET/CLR,PIO Parallel Capture Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RXBUFF ,Reception buffer full interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENDRX ,End of reception transfer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " OVRE ,Parallel capture mode overrun error interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DRDY ,Parallel capture mode data ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
in
|
|
newline
|
|
if (per.l(ad:0x400E1000+0x150)&0x30)==0x00
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RDATA ,Parallel capture mode reception data"
|
|
elif (per.l(ad:0x400E1000+0x150)&0x30)==0x10
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA ,Parallel capture mode reception data"
|
|
else
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
width 0x0B
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port C"
|
|
base ad:0x400E1200
|
|
width 16.
|
|
if ((per.l(ad:0x400E1200+0xE4)&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PSR_SET/CLR,PIO Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "OSR_SET/CLR,PIO Output Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IFSR_SET/CLR,PIO Input Filter Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PSR,PIO Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "OSR,PIO Output Enable Set/Clear Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "IFSR,PIO Input Filter Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ODSR_SET/CLR,PIO Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 output data status" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 output data status" "Low,High"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 output data status" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 output data status" "Low,High"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 output data status" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 output data status" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output data status" "Low,High"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 output data status" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output data status" "Low,High"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output data status" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 output data status" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 output data status" "Low,High"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 output data status" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 output data status" "Low,High"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 output data status" "Low,High"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 output data status" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output data status" "Low,High"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output data status" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output data status" "Low,High"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PDSR,PIO Data Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 output data status" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 output data status" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 output data status" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 output data status" "Low,High"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 output data status" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 output data status" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output data status" "Low,High"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 output data status" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output data status" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output data status" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 output data status" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 output data status" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 output data status" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 output data status" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 output data status" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 output data status" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output data status" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output data status" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output data status" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "IMR_SET/CLR,PIO Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ISR,PIO Interrupt Status Register"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x400E1200+0xE4)&0x01)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MDSR_SET/CLR,PIO Multi-Driver Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PUSR_SET/CLR,PIO Pull Up Disable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x08 11. " [11] ,Pin 11 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x08 10. " [10] ,Pin 10 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 31. " P[31] ,Pin 31 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 30. " [30] ,Pin 30 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 29. " [29] ,Pin 29 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 28. " [28] ,Pin 28 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 27. " [27] ,Pin 27 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 26. " [26] ,Pin 26 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,Pin 25 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 24. " [24] ,Pin 24 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 23. " [23] ,Pin 23 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 22. " [22] ,Pin 22 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 21. " [21] ,Pin 21 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 20. " [20] ,Pin 20 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Pin 19 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 18. " [18] ,Pin 18 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 17. " [17] ,Pin 17 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 16. " [16] ,Pin 16 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 15. " [15] ,Pin 15 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 14. " [14] ,Pin 14 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,Pin 13 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 11. " [11] ,Pin 11 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 10. " [10] ,Pin 10 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 6. " [6] ,Pin 6 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "MDSR,PIO Multi-Driver Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "PUSR,PIO Pull Up Disable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 31. " P[31] ,Pin 31 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 30. " [30] ,Pin 30 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 29. " [29] ,Pin 29 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 28. " [28] ,Pin 28 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 27. " [27] ,Pin 27 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 26. " [26] ,Pin 26 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,Pin 25 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 24. " [24] ,Pin 24 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 23. " [23] ,Pin 23 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 22. " [22] ,Pin 22 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 21. " [21] ,Pin 21 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 20. " [20] ,Pin 20 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Pin 19 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 18. " [18] ,Pin 18 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 17. " [17] ,Pin 17 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 16. " [16] ,Pin 16 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 15. " [15] ,Pin 15 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 14. " [14] ,Pin 14 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,Pin 13 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 11. " [11] ,Pin 11 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 10. " [10] ,Pin 10 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 6. " [6] ,Pin 6 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "IFSCSR_SET/CLR,PIO Input Filter Slow Clock Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P[31] ,Pin 31 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " [30] ,Pin 30 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " [29] ,Pin 29 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " [28] ,Pin 28 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " [27] ,Pin 27 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Pin 26 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Pin 25 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " [23] ,Pin 23 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " [19] ,Pin 19 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " [19] ,Pin 19 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " [18] ,Pin 18 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " [17] ,Pin 17 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " [16] ,Pin 16 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " [15] ,Pin 15 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Pin 14 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Pin 13 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow clock divider selection for debouncing"
|
|
if ((per.l(ad:0x400E1200+0xE4)&0x01)==0x00)
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PPDSR_SET/CLR,PIO Pad Pull Down Disable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "OWSR_SET/CLR,PIO Output Write Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "PPDSR,PIO Pad Pull Down Disable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "OWSR,PIO Output Write Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "AIMMR_SET/CLR,PIO Additional Interrupt Modes Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 peripheral cd status" "Both edge,Registers"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "ELSR_SET/CLR,Edge/level Interrupt Source Selection Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P[31] ,Pin 31 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " [30] ,Pin 30 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " [29] ,Pin 29 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " [28] ,Pin 28 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " [27] ,Pin 27 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Pin 26 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Pin 25 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " [23] ,Pin 23 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " [20] ,Pin 20 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " [19] ,Pin 19 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " [18] ,Pin 18 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " [17] ,Pin 17 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " [16] ,Pin 16 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " [15] ,Pin 15 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Pin 14 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Pin 13 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Edge,Level"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FRLHSR_SET/CLR,PIO Fall/Rise - Low/High Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P[31] ,Pin 31 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " [30] ,Pin 30 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " [29] ,Pin 29 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " [28] ,Pin 28 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " [27] ,Pin 27 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Pin 26 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Pin 25 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " [23] ,Pin 23 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " [20] ,Pin 20 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " [19] ,Pin 19 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " [18] ,Pin 18 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " [17] ,Pin 17 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " [16] ,Pin 16 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " [15] ,Pin 15 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Pin 14 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Pin 13 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 lock status" "Not locked,Locked"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,PIO Write Protect Status Register"
|
|
in
|
|
newline
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SCHMITT,PIO Schmitt Trigger Register"
|
|
bitfld.long 0x00 31. " SCHMITT[31] ,Schmitt trigger 31 disable" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Schmitt trigger 30 disable" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,Schmitt trigger 29 disable" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Schmitt trigger 28 disable" "No,Yes"
|
|
bitfld.long 0x00 27. " [27] ,Schmitt trigger 27 disable" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Schmitt trigger 26 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Schmitt trigger 25 disable" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Schmitt trigger 24 disable" "No,Yes"
|
|
bitfld.long 0x00 23. " [23] ,Schmitt trigger 23 disable" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Schmitt trigger 22 disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Schmitt trigger 21 disable" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Schmitt trigger 20 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Schmitt trigger 19 disable" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Schmitt trigger 18 disable" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Schmitt trigger 17 disable" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Schmitt trigger 16 disable" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Schmitt trigger 15 disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Schmitt trigger 14 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Schmitt trigger 13 disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Schmitt trigger 12 disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Schmitt trigger 11 disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Schmitt trigger 10 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Schmitt trigger 9 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Schmitt trigger 8 disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Schmitt trigger 7 disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Schmitt trigger 6 disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Schmitt trigger 5 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Schmitt trigger 4 disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Schmitt trigger 3 disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Schmitt trigger 2 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Schmitt trigger 1 disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Schmitt trigger 0 disable" "No,Yes"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DRIVER,PIO I/O Drive Register"
|
|
bitfld.long 0x00 31. " LINE[31] ,Drive of PIO line 31" "Low,High"
|
|
bitfld.long 0x00 31. " [30] ,Drive of PIO line 30" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,Drive of PIO line 29" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,Drive of PIO line 28" "Low,High"
|
|
bitfld.long 0x00 27. " [27] ,Drive of PIO line 27" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,Drive of PIO line 26" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Drive of PIO line 25" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Drive of PIO line 24" "Low,High"
|
|
bitfld.long 0x00 23. " [23] ,Drive of PIO line 23" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,Drive of PIO line 22" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Drive of PIO line 21" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Drive of PIO line 20" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Drive of PIO line 19" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Drive of PIO line 18" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,Drive of PIO line 17" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Drive of PIO line 16" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Drive of PIO line 15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Drive of PIO line 14" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Drive of PIO line 13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Drive of PIO line 12" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Drive of PIO line 11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Drive of PIO line 10" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Drive of PIO line 9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Drive of PIO line 8" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Drive of PIO line 7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Drive of PIO line 6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Drive of PIO line 5" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Drive of PIO line 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Drive of PIO line 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Drive of PIO line 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Drive of PIO line 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Drive of PIO line 0" "Low,High"
|
|
width 15.
|
|
newline
|
|
if ((per.l(ad:0x400E1200+0xE4)&0x01)==0x00)
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "PCIMR_SET/CLR,PIO Parallel Capture Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RXBUFF ,Reception buffer full interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENDRX ,End of reception transfer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " OVRE ,Parallel capture mode overrun error interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DRDY ,Parallel capture mode data ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
in
|
|
newline
|
|
if (per.l(ad:0x400E1200+0x150)&0x30)==0x00
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RDATA ,Parallel capture mode reception data"
|
|
elif (per.l(ad:0x400E1200+0x150)&0x30)==0x10
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA ,Parallel capture mode reception data"
|
|
else
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
width 0x0B
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port D"
|
|
base ad:0x400E1400
|
|
width 16.
|
|
if ((per.l(ad:0x400E1400+0xE4)&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PSR_SET/CLR,PIO Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "OSR_SET/CLR,PIO Output Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IFSR_SET/CLR,PIO Input Filter Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PSR,PIO Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "OSR,PIO Output Enable Set/Clear Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "IFSR,PIO Input Filter Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ODSR_SET/CLR,PIO Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 output data status" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 output data status" "Low,High"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 output data status" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 output data status" "Low,High"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 output data status" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 output data status" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output data status" "Low,High"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 output data status" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output data status" "Low,High"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output data status" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 output data status" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 output data status" "Low,High"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 output data status" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 output data status" "Low,High"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 output data status" "Low,High"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 output data status" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output data status" "Low,High"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output data status" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output data status" "Low,High"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PDSR,PIO Data Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 output data status" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 output data status" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 output data status" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 output data status" "Low,High"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 output data status" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 output data status" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output data status" "Low,High"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 output data status" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output data status" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output data status" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 output data status" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 output data status" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 output data status" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 output data status" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 output data status" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 output data status" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output data status" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output data status" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output data status" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "IMR_SET/CLR,PIO Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ISR,PIO Interrupt Status Register"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x400E1400+0xE4)&0x01)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MDSR_SET/CLR,PIO Multi-Driver Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PUSR_SET/CLR,PIO Pull Up Disable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x08 11. " [11] ,Pin 11 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x08 10. " [10] ,Pin 10 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 31. " P[31] ,Pin 31 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 30. " [30] ,Pin 30 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 29. " [29] ,Pin 29 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 28. " [28] ,Pin 28 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 27. " [27] ,Pin 27 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 26. " [26] ,Pin 26 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,Pin 25 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 24. " [24] ,Pin 24 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 23. " [23] ,Pin 23 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 22. " [22] ,Pin 22 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 21. " [21] ,Pin 21 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 20. " [20] ,Pin 20 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Pin 19 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 18. " [18] ,Pin 18 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 17. " [17] ,Pin 17 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 16. " [16] ,Pin 16 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 15. " [15] ,Pin 15 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 14. " [14] ,Pin 14 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,Pin 13 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 11. " [11] ,Pin 11 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 10. " [10] ,Pin 10 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 6. " [6] ,Pin 6 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "MDSR,PIO Multi-Driver Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "PUSR,PIO Pull Up Disable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 31. " P[31] ,Pin 31 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 30. " [30] ,Pin 30 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 29. " [29] ,Pin 29 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 28. " [28] ,Pin 28 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 27. " [27] ,Pin 27 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 26. " [26] ,Pin 26 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 25. " [25] ,Pin 25 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 24. " [24] ,Pin 24 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 23. " [23] ,Pin 23 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 22. " [22] ,Pin 22 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 21. " [21] ,Pin 21 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 20. " [20] ,Pin 20 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,Pin 19 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 18. " [18] ,Pin 18 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 17. " [17] ,Pin 17 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 16. " [16] ,Pin 16 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 15. " [15] ,Pin 15 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 14. " [14] ,Pin 14 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,Pin 13 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 11. " [11] ,Pin 11 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 10. " [10] ,Pin 10 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 6. " [6] ,Pin 6 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "IFSCSR_SET/CLR,PIO Input Filter Slow Clock Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P[31] ,Pin 31 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " [30] ,Pin 30 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " [29] ,Pin 29 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " [28] ,Pin 28 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " [27] ,Pin 27 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Pin 26 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Pin 25 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " [23] ,Pin 23 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " [19] ,Pin 19 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " [19] ,Pin 19 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " [18] ,Pin 18 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " [17] ,Pin 17 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " [16] ,Pin 16 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " [15] ,Pin 15 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Pin 14 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Pin 13 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow clock divider selection for debouncing"
|
|
if ((per.l(ad:0x400E1400+0xE4)&0x01)==0x00)
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PPDSR_SET/CLR,PIO Pad Pull Down Disable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "OWSR_SET/CLR,PIO Output Write Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "PPDSR,PIO Pad Pull Down Disable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "OWSR,PIO Output Write Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "AIMMR_SET/CLR,PIO Additional Interrupt Modes Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " [29] ,Pin 29 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 peripheral cd status" "Both edge,Registers"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "ELSR_SET/CLR,Edge/level Interrupt Source Selection Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P[31] ,Pin 31 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " [30] ,Pin 30 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " [29] ,Pin 29 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " [28] ,Pin 28 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " [27] ,Pin 27 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Pin 26 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Pin 25 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " [23] ,Pin 23 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " [20] ,Pin 20 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " [19] ,Pin 19 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " [18] ,Pin 18 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " [17] ,Pin 17 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " [16] ,Pin 16 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " [15] ,Pin 15 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Pin 14 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Pin 13 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Edge,Level"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FRLHSR_SET/CLR,PIO Fall/Rise - Low/High Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P[31] ,Pin 31 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " [30] ,Pin 30 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 29. -0x04 29. -0x08 29. " [29] ,Pin 29 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " [28] ,Pin 28 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " [27] ,Pin 27 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Pin 26 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Pin 25 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " [23] ,Pin 23 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " [20] ,Pin 20 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " [19] ,Pin 19 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " [18] ,Pin 18 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " [17] ,Pin 17 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " [16] ,Pin 16 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " [15] ,Pin 15 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Pin 14 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Pin 13 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 29. " [29] ,Pin 29 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 lock status" "Not locked,Locked"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,PIO Write Protect Status Register"
|
|
in
|
|
newline
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SCHMITT,PIO Schmitt Trigger Register"
|
|
bitfld.long 0x00 31. " SCHMITT[31] ,Schmitt trigger 31 disable" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Schmitt trigger 30 disable" "No,Yes"
|
|
bitfld.long 0x00 29. " [29] ,Schmitt trigger 29 disable" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Schmitt trigger 28 disable" "No,Yes"
|
|
bitfld.long 0x00 27. " [27] ,Schmitt trigger 27 disable" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Schmitt trigger 26 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Schmitt trigger 25 disable" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Schmitt trigger 24 disable" "No,Yes"
|
|
bitfld.long 0x00 23. " [23] ,Schmitt trigger 23 disable" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Schmitt trigger 22 disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Schmitt trigger 21 disable" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Schmitt trigger 20 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Schmitt trigger 19 disable" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Schmitt trigger 18 disable" "No,Yes"
|
|
bitfld.long 0x00 17. " [17] ,Schmitt trigger 17 disable" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Schmitt trigger 16 disable" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Schmitt trigger 15 disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Schmitt trigger 14 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Schmitt trigger 13 disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Schmitt trigger 12 disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Schmitt trigger 11 disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Schmitt trigger 10 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Schmitt trigger 9 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Schmitt trigger 8 disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Schmitt trigger 7 disable" "No,Yes"
|
|
bitfld.long 0x00 6. " [6] ,Schmitt trigger 6 disable" "No,Yes"
|
|
bitfld.long 0x00 5. " [5] ,Schmitt trigger 5 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Schmitt trigger 4 disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Schmitt trigger 3 disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Schmitt trigger 2 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Schmitt trigger 1 disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Schmitt trigger 0 disable" "No,Yes"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DRIVER,PIO I/O Drive Register"
|
|
bitfld.long 0x00 31. " LINE[31] ,Drive of PIO line 31" "Low,High"
|
|
bitfld.long 0x00 31. " [30] ,Drive of PIO line 30" "Low,High"
|
|
bitfld.long 0x00 29. " [29] ,Drive of PIO line 29" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,Drive of PIO line 28" "Low,High"
|
|
bitfld.long 0x00 27. " [27] ,Drive of PIO line 27" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,Drive of PIO line 26" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 25. " [25] ,Drive of PIO line 25" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Drive of PIO line 24" "Low,High"
|
|
bitfld.long 0x00 23. " [23] ,Drive of PIO line 23" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,Drive of PIO line 22" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Drive of PIO line 21" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Drive of PIO line 20" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Drive of PIO line 19" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Drive of PIO line 18" "Low,High"
|
|
bitfld.long 0x00 17. " [17] ,Drive of PIO line 17" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Drive of PIO line 16" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Drive of PIO line 15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Drive of PIO line 14" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Drive of PIO line 13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Drive of PIO line 12" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Drive of PIO line 11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Drive of PIO line 10" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Drive of PIO line 9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Drive of PIO line 8" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Drive of PIO line 7" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Drive of PIO line 6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Drive of PIO line 5" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Drive of PIO line 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Drive of PIO line 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Drive of PIO line 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Drive of PIO line 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Drive of PIO line 0" "Low,High"
|
|
width 15.
|
|
newline
|
|
if ((per.l(ad:0x400E1400+0xE4)&0x01)==0x00)
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "PCIMR_SET/CLR,PIO Parallel Capture Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RXBUFF ,Reception buffer full interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENDRX ,End of reception transfer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " OVRE ,Parallel capture mode overrun error interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DRDY ,Parallel capture mode data ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
in
|
|
newline
|
|
if (per.l(ad:0x400E1400+0x150)&0x30)==0x00
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RDATA ,Parallel capture mode reception data"
|
|
elif (per.l(ad:0x400E1400+0x150)&0x30)==0x10
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA ,Parallel capture mode reception data"
|
|
else
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
width 0x0B
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port E"
|
|
base ad:0x400E1600
|
|
width 16.
|
|
if ((per.l(ad:0x400E1600+0xE4)&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PSR_SET/CLR,PIO Enable Set/Clear Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P[5] ,Pin 5 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "OSR_SET/CLR,PIO Output Enable Set/Clear Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P[5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IFSR_SET/CLR,PIO Input Filter Enable Set/Clear Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P[5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PSR,PIO Enable Status Register"
|
|
bitfld.long 0x00 5. " P[5] ,Pin 5 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "OSR,PIO Output Enable Set/Clear Register"
|
|
bitfld.long 0x00 5. " P[5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "IFSR,PIO Input Filter Enable Status Register"
|
|
bitfld.long 0x00 5. " P[5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ODSR_SET/CLR,PIO Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P[5] ,Pin 5 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PDSR,PIO Data Status Register"
|
|
bitfld.long 0x00 5. " P[5] ,Pin 5 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "IMR_SET/CLR,PIO Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P[5] ,Pin 5 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ISR,PIO Interrupt Status Register"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x400E1600+0xE4)&0x01)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MDSR_SET/CLR,PIO Multi-Driver Enable Set/Clear Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P[5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PUSR_SET/CLR,PIO Pull Up Disable Set/Clear Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P[5] ,Pin 5 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 5. " P[5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 5. " P[5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "MDSR,PIO Multi-Driver Enable Status Register"
|
|
bitfld.long 0x00 5. " P[5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "PUSR,PIO Pull Up Disable Status Register"
|
|
bitfld.long 0x00 5. " P[5] ,Pin 5 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 5. " P[5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 5. " P[5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "IFSCSR_SET/CLR,PIO Input Filter Slow Clock Set/Clear Register"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P[5] ,Pin 5 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow clock divider selection for debouncing"
|
|
if ((per.l(ad:0x400E1600+0xE4)&0x01)==0x00)
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PPDSR_SET/CLR,PIO Pad Pull Down Disable Set/Clear Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P[5] ,Pin 5 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "OWSR_SET/CLR,PIO Output Write Enable Set/Clear Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P[5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "PPDSR,PIO Pad Pull Down Disable Status Register"
|
|
bitfld.long 0x00 5. " P[5] ,Pin 5 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "OWSR,PIO Output Write Enable Status Register"
|
|
bitfld.long 0x00 5. " P[5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "AIMMR_SET/CLR,PIO Additional Interrupt Modes Set/Clear Register"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " P[5] ,Pin 5 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 peripheral cd status" "Both edge,Registers"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "ELSR_SET/CLR,Edge/level Interrupt Source Selection Set/Clear Register"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P[5] ,Pin 5 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Edge,Level"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FRLHSR_SET/CLR,PIO Fall/Rise - Low/High Set/Clear Register"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " P[5] ,Pin 5 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 5. " P[5] ,Pin 5 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 lock status" "Not locked,Locked"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,PIO Write Protect Status Register"
|
|
in
|
|
newline
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SCHMITT,PIO Schmitt Trigger Register"
|
|
bitfld.long 0x00 5. " SCHMITT[5] ,Schmitt trigger 5 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Schmitt trigger 4 disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Schmitt trigger 3 disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Schmitt trigger 2 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Schmitt trigger 1 disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Schmitt trigger 0 disable" "No,Yes"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DRIVER,PIO I/O Drive Register"
|
|
bitfld.long 0x00 5. " LINE[5] ,Drive of PIO line 5" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Drive of PIO line 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Drive of PIO line 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Drive of PIO line 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Drive of PIO line 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Drive of PIO line 0" "Low,High"
|
|
width 15.
|
|
newline
|
|
if ((per.l(ad:0x400E1600+0xE4)&0x01)==0x00)
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "PCIMR_SET/CLR,PIO Parallel Capture Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RXBUFF ,Reception buffer full interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENDRX ,End of reception transfer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " OVRE ,Parallel capture mode overrun error interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DRDY ,Parallel capture mode data ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
in
|
|
newline
|
|
if (per.l(ad:0x400E1600+0x150)&0x30)==0x00
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RDATA ,Parallel capture mode reception data"
|
|
elif (per.l(ad:0x400E1600+0x150)&0x30)==0x10
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA ,Parallel capture mode reception data"
|
|
else
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
width 0x0B
|
|
width 0x0B
|
|
tree.end
|
|
elif cpuis("ATSAMS70N*")
|
|
tree "Port A"
|
|
base ad:0x400E0E00
|
|
width 16.
|
|
if ((per.l(ad:0x400E0E00+0xE4)&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PSR_SET/CLR,PIO Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "OSR_SET/CLR,PIO Output Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IFSR_SET/CLR,PIO Input Filter Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PSR,PIO Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "OSR,PIO Output Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "IFSR,PIO Input Filter Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ODSR_SET/CLR,PIO Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 output data status" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 output data status" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 output data status" "Low,High"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 output data status" "Low,High"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 output data status" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output data status" "Low,High"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output data status" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 output data status" "Low,High"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 output data status" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 output data status" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 output data status" "Low,High"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 output data status" "Low,High"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 output data status" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output data status" "Low,High"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output data status" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PDSR,PIO Data Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 output data status" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 output data status" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 output data status" "Low,High"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 output data status" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 output data status" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output data status" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output data status" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 output data status" "Low,High"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 output data status" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 output data status" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 output data status" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 output data status" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 output data status" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output data status" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output data status" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "IMR_SET/CLR,PIO Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ISR,PIO Interrupt Status Register"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x400E0E00+0xE4)&0x01)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MDSR_SET/CLR,PIO Multi-Driver Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PUSR_SET/CLR,PIO Pull Up Disable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x08 11. " [11] ,Pin 11 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x08 10. " [10] ,Pin 10 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 31. " P[31] ,Pin 31 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 30. " [30] ,Pin 30 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 28. " [28] ,Pin 28 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 27. " [27] ,Pin 27 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 26. " [26] ,Pin 26 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 25. " [25] ,Pin 25 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 24. " [24] ,Pin 24 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 23. " [23] ,Pin 23 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,Pin 22 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 21. " [21] ,Pin 21 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 20. " [20] ,Pin 20 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 19. " [19] ,Pin 19 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 18. " [18] ,Pin 18 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 17. " [17] ,Pin 17 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 16. " [16] ,Pin 16 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 15. " [15] ,Pin 15 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 14. " [14] ,Pin 14 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,Pin 13 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 11. " [11] ,Pin 11 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 10. " [10] ,Pin 10 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "MDSR,PIO Multi-Driver Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "PUSR,PIO Pull Up Disable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 31. " P[31] ,Pin 31 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 30. " [30] ,Pin 30 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 28. " [28] ,Pin 28 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 27. " [27] ,Pin 27 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 26. " [26] ,Pin 26 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 25. " [25] ,Pin 25 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 24. " [24] ,Pin 24 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 23. " [23] ,Pin 23 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,Pin 22 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 21. " [21] ,Pin 21 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 20. " [20] ,Pin 20 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 19. " [19] ,Pin 19 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 18. " [18] ,Pin 18 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 17. " [17] ,Pin 17 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 16. " [16] ,Pin 16 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 15. " [15] ,Pin 15 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 14. " [14] ,Pin 14 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,Pin 13 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 11. " [11] ,Pin 11 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 10. " [10] ,Pin 10 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "IFSCSR_SET/CLR,PIO Input Filter Slow Clock Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P[31] ,Pin 31 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " [30] ,Pin 30 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " [28] ,Pin 28 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " [27] ,Pin 27 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Pin 26 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Pin 25 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " [23] ,Pin 23 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " [19] ,Pin 19 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " [19] ,Pin 19 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " [18] ,Pin 18 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " [17] ,Pin 17 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " [16] ,Pin 16 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " [15] ,Pin 15 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Pin 14 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Pin 13 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 19 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow clock divider selection for debouncing"
|
|
if ((per.l(ad:0x400E0E00+0xE4)&0x01)==0x00)
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PPDSR_SET/CLR,PIO Pad Pull Down Disable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "OWSR_SET/CLR,PIO Output Write Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "PPDSR,PIO Pad Pull Down Disable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "OWSR,PIO Output Write Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "AIMMR_SET/CLR,PIO Additional Interrupt Modes Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " [23] ,Pin 23 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 peripheral cd status" "Both edge,Registers"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "ELSR_SET/CLR,Edge/Level Interrupt Source Selection Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P[31] ,Pin 31 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " [30] ,Pin 30 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " [28] ,Pin 28 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " [27] ,Pin 27 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Pin 26 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Pin 25 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " [23] ,Pin 23 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " [20] ,Pin 20 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " [19] ,Pin 19 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " [18] ,Pin 18 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " [17] ,Pin 17 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " [16] ,Pin 16 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " [15] ,Pin 15 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Pin 14 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Pin 13 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Edge,Level"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FRLHSR_SET/CLR,PIO Fall/Rise - Low/High Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P[31] ,Pin 31 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " [30] ,Pin 30 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " [28] ,Pin 28 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " [27] ,Pin 27 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Pin 26 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Pin 25 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " [23] ,Pin 23 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " [20] ,Pin 20 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " [19] ,Pin 19 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " [18] ,Pin 18 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " [17] ,Pin 17 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " [16] ,Pin 16 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " [15] ,Pin 15 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Pin 14 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Pin 13 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Pin 23 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 lock status" "Not locked,Locked"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,PIO Write Protect Status Register"
|
|
in
|
|
newline
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SCHMITT,PIO Schmitt Trigger Register"
|
|
bitfld.long 0x00 31. " SCHMITT[31] ,Schmitt trigger 31 disable" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Schmitt trigger 30 disable" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Schmitt trigger 28 disable" "No,Yes"
|
|
bitfld.long 0x00 27. " [27] ,Schmitt trigger 27 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Schmitt trigger 26 disable" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Schmitt trigger 25 disable" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Schmitt trigger 24 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Schmitt trigger 23 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Schmitt trigger 22 disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Schmitt trigger 21 disable" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Schmitt trigger 20 disable" "No,Yes"
|
|
bitfld.long 0x00 19. " [19] ,Schmitt trigger 19 disable" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Schmitt trigger 18 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Schmitt trigger 17 disable" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Schmitt trigger 16 disable" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Schmitt trigger 15 disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Schmitt trigger 14 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Schmitt trigger 13 disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Schmitt trigger 12 disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Schmitt trigger 11 disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Schmitt trigger 10 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Schmitt trigger 9 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Schmitt trigger 8 disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Schmitt trigger 7 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Schmitt trigger 5 disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Schmitt trigger 4 disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Schmitt trigger 3 disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Schmitt trigger 2 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Schmitt trigger 1 disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Schmitt trigger 0 disable" "No,Yes"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DRIVER,PIO I/O Drive Register"
|
|
bitfld.long 0x00 31. " LINE[31] ,Drive of PIO line 31" "Low,High"
|
|
bitfld.long 0x00 31. " [30] ,Drive of PIO line 30" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,Drive of PIO line 28" "Low,High"
|
|
bitfld.long 0x00 27. " [27] ,Drive of PIO line 27" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Drive of PIO line 26" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,Drive of PIO line 25" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Drive of PIO line 24" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Drive of PIO line 23" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Drive of PIO line 22" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Drive of PIO line 21" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Drive of PIO line 20" "Low,High"
|
|
bitfld.long 0x00 19. " [19] ,Drive of PIO line 19" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Drive of PIO line 18" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Drive of PIO line 17" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Drive of PIO line 16" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Drive of PIO line 15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Drive of PIO line 14" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Drive of PIO line 13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Drive of PIO line 12" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Drive of PIO line 11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Drive of PIO line 10" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Drive of PIO line 9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Drive of PIO line 8" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Drive of PIO line 7" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Drive of PIO line 5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Drive of PIO line 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Drive of PIO line 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Drive of PIO line 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Drive of PIO line 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Drive of PIO line 0" "Low,High"
|
|
width 15.
|
|
newline
|
|
if ((per.l(ad:0x400E0E00+0xE4)&0x01)==0x00)
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "PCIMR_SET/CLR,PIO Parallel Capture Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RXBUFF ,Reception buffer full interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENDRX ,End of reception transfer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " OVRE ,Parallel capture mode overrun error interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DRDY ,Parallel capture mode data ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
in
|
|
newline
|
|
if (per.l(ad:0x400E0E00+0x150)&0x30)==0x00
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RDATA ,Parallel capture mode reception data"
|
|
elif (per.l(ad:0x400E0E00+0x150)&0x30)==0x10
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA ,Parallel capture mode reception data"
|
|
else
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
width 0x0B
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port B"
|
|
base ad:0x400E1000
|
|
width 16.
|
|
if ((per.l(ad:0x400E1000+0xE4)&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PSR_SET/CLR,PIO Enable Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "OSR_SET/CLR,PIO Output Enable Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IFSR_SET/CLR,PIO Input Filter Enable Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PSR,PIO Enable Status Register"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "OSR,PIO Output Enable Status Register"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "IFSR,PIO Input Filter Enable Status Register"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ODSR_SET/CLR,PIO Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 output data status" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PDSR,PIO Data Status Register"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 output data status" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "IMR_SET/CLR,PIO Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ISR,PIO Interrupt Status Register"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x400E1000+0xE4)&0x01)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MDSR_SET/CLR,PIO Multi-Driver Enable Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PUSR_SET/CLR,PIO Pull Up Disable Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 13. " P[13] ,Pin 13 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Pin 6 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "MDSR,PIO Multi-Driver Enable Status Register"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "PUSR,PIO Pull Up Disable Status Register"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 13. " P[13] ,Pin 13 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Pin 6 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "IFSCSR_SET/CLR,PIO Input Filter Slow Clock Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P[13] ,Pin 13 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 19 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow clock divider selection for debouncing"
|
|
if ((per.l(ad:0x400E1000+0xE4)&0x01)==0x00)
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PPDSR_SET/CLR,PIO Pad Pull Down Disable Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "OWSR_SET/CLR,PIO Output Write Enable Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "PPDSR,PIO Pad Pull Down Disable Status Register"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "OWSR,PIO Output Write Enable Status Register"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "AIMMR_SET/CLR,PIO Additional Interrupt Modes Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " P[13] ,Pin 13 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 peripheral cd status" "Both edge,Registers"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "ELSR_SET/CLR,Edge/Level Interrupt Source Selection Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P[13] ,Pin 13 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Edge,Level"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FRLHSR_SET/CLR,PIO Fall/Rise - Low/High Set/Clear Register"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " P[13] ,Pin 13 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 13. " P[13] ,Pin 13 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 lock status" "Not locked,Locked"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,PIO Write Protect Status Register"
|
|
in
|
|
newline
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SCHMITT,PIO Schmitt Trigger Register"
|
|
bitfld.long 0x00 13. " SCHMITT[13] ,Schmitt trigger 13 disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Schmitt trigger 12 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Schmitt trigger 9 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Schmitt trigger 8 disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Schmitt trigger 7 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Schmitt trigger 6 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Schmitt trigger 5 disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Schmitt trigger 4 disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Schmitt trigger 3 disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Schmitt trigger 2 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Schmitt trigger 1 disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Schmitt trigger 0 disable" "No,Yes"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DRIVER,PIO I/O Drive Register"
|
|
bitfld.long 0x00 13. " LINE[13] ,Drive of PIO line 13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Drive of PIO line 12" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Drive of PIO line 9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Drive of PIO line 8" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Drive of PIO line 7" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Drive of PIO line 6" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Drive of PIO line 5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Drive of PIO line 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Drive of PIO line 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Drive of PIO line 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Drive of PIO line 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Drive of PIO line 0" "Low,High"
|
|
width 15.
|
|
newline
|
|
if ((per.l(ad:0x400E1000+0xE4)&0x01)==0x00)
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "PCIMR_SET/CLR,PIO Parallel Capture Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RXBUFF ,Reception buffer full interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENDRX ,End of reception transfer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " OVRE ,Parallel capture mode overrun error interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DRDY ,Parallel capture mode data ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
in
|
|
newline
|
|
if (per.l(ad:0x400E1000+0x150)&0x30)==0x00
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RDATA ,Parallel capture mode reception data"
|
|
elif (per.l(ad:0x400E1000+0x150)&0x30)==0x10
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA ,Parallel capture mode reception data"
|
|
else
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
width 0x0B
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port D"
|
|
base ad:0x400E1400
|
|
width 16.
|
|
if ((per.l(ad:0x400E1400+0xE4)&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PSR_SET/CLR,PIO Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "OSR_SET/CLR,PIO Output Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IFSR_SET/CLR,PIO Input Filter Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PSR,PIO Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "OSR,PIO Output Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "IFSR,PIO Input Filter Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ODSR_SET/CLR,PIO Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 output data status" "Low,High"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 output data status" "Low,High"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 output data status" "Low,High"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 output data status" "Low,High"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 output data status" "Low,High"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output data status" "Low,High"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output data status" "Low,High"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 output data status" "Low,High"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 output data status" "Low,High"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 output data status" "Low,High"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 output data status" "Low,High"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 output data status" "Low,High"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 output data status" "Low,High"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output data status" "Low,High"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output data status" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PDSR,PIO Data Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 output data status" "Low,High"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 output data status" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 output data status" "Low,High"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 output data status" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 output data status" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output data status" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output data status" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 output data status" "Low,High"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 output data status" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 output data status" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 output data status" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 output data status" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 output data status" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output data status" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output data status" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "IMR_SET/CLR,PIO Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ISR,PIO Interrupt Status Register"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x400E1400+0xE4)&0x01)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MDSR_SET/CLR,PIO Multi-Driver Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PUSR_SET/CLR,PIO Pull Up Disable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x08 11. " [11] ,Pin 11 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x08 10. " [10] ,Pin 10 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 31. " P[31] ,Pin 31 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 30. " [30] ,Pin 30 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 28. " [28] ,Pin 28 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 27. " [27] ,Pin 27 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 26. " [26] ,Pin 26 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 25. " [25] ,Pin 25 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 24. " [24] ,Pin 24 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,Pin 22 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 21. " [21] ,Pin 21 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 20. " [20] ,Pin 20 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 19. " [19] ,Pin 19 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 18. " [18] ,Pin 18 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 17. " [17] ,Pin 17 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 16. " [16] ,Pin 16 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 15. " [15] ,Pin 15 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 14. " [14] ,Pin 14 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,Pin 13 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 11. " [11] ,Pin 11 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 10. " [10] ,Pin 10 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Pin 6 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "MDSR,PIO Multi-Driver Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "PUSR,PIO Pull Up Disable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 31. " P[31] ,Pin 31 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 30. " [30] ,Pin 30 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 28. " [28] ,Pin 28 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 27. " [27] ,Pin 27 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 26. " [26] ,Pin 26 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 25. " [25] ,Pin 25 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 24. " [24] ,Pin 24 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 22. " [22] ,Pin 22 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 21. " [21] ,Pin 21 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 20. " [20] ,Pin 20 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 19. " [19] ,Pin 19 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 18. " [18] ,Pin 18 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 17. " [17] ,Pin 17 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 16. " [16] ,Pin 16 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 15. " [15] ,Pin 15 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 14. " [14] ,Pin 14 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 13. " [13] ,Pin 13 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 11. " [11] ,Pin 11 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 10. " [10] ,Pin 10 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Pin 6 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "IFSCSR_SET/CLR,PIO Input Filter Slow Clock Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P[31] ,Pin 31 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " [30] ,Pin 30 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " [28] ,Pin 28 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " [27] ,Pin 27 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Pin 26 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Pin 25 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " [19] ,Pin 19 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " [19] ,Pin 19 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " [18] ,Pin 18 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " [17] ,Pin 17 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " [16] ,Pin 16 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " [15] ,Pin 15 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Pin 14 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Pin 13 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 19 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow clock divider selection for debouncing"
|
|
if ((per.l(ad:0x400E1400+0xE4)&0x01)==0x00)
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PPDSR_SET/CLR,PIO Pad Pull Down Disable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "OWSR_SET/CLR,PIO Output Write Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "PPDSR,PIO Pad Pull Down Disable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "OWSR,PIO Output Write Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "AIMMR_SET/CLR,PIO Additional Interrupt Modes Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " [30] ,Pin 30 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " [28] ,Pin 28 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " [27] ,Pin 27 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,Pin 20 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,Pin 19 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,Pin 18 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,Pin 17 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,Pin 16 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,Pin 15 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 peripheral cd status" "Both edge,Registers"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "ELSR_SET/CLR,Edge/Level Interrupt Source Selection Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P[31] ,Pin 31 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " [30] ,Pin 30 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " [28] ,Pin 28 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " [27] ,Pin 27 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Pin 26 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Pin 25 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " [20] ,Pin 20 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " [19] ,Pin 19 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " [18] ,Pin 18 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " [17] ,Pin 17 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " [16] ,Pin 16 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " [15] ,Pin 15 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Pin 14 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Pin 13 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Edge,Level"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FRLHSR_SET/CLR,PIO Fall/Rise - Low/High Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P[31] ,Pin 31 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 30. -0x04 30. -0x08 30. " [30] ,Pin 30 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 28. -0x04 28. -0x08 28. " [28] ,Pin 28 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " [27] ,Pin 27 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Pin 26 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Pin 25 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " [20] ,Pin 20 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " [19] ,Pin 19 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " [18] ,Pin 18 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " [17] ,Pin 17 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " [16] ,Pin 16 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " [15] ,Pin 15 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Pin 14 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Pin 13 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " [30] ,Pin 30 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 28. " [28] ,Pin 28 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 27. " [27] ,Pin 27 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 20. " [20] ,Pin 20 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 19. " [19] ,Pin 19 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 18. " [18] ,Pin 18 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Pin 17 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 16. " [16] ,Pin 16 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 15. " [15] ,Pin 15 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 lock status" "Not locked,Locked"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,PIO Write Protect Status Register"
|
|
in
|
|
newline
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SCHMITT,PIO Schmitt Trigger Register"
|
|
bitfld.long 0x00 31. " SCHMITT[31] ,Schmitt trigger 31 disable" "No,Yes"
|
|
bitfld.long 0x00 30. " [30] ,Schmitt trigger 30 disable" "No,Yes"
|
|
bitfld.long 0x00 28. " [28] ,Schmitt trigger 28 disable" "No,Yes"
|
|
bitfld.long 0x00 27. " [27] ,Schmitt trigger 27 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Schmitt trigger 26 disable" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Schmitt trigger 25 disable" "No,Yes"
|
|
bitfld.long 0x00 24. " [24] ,Schmitt trigger 24 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Schmitt trigger 22 disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Schmitt trigger 21 disable" "No,Yes"
|
|
bitfld.long 0x00 20. " [20] ,Schmitt trigger 20 disable" "No,Yes"
|
|
bitfld.long 0x00 19. " [19] ,Schmitt trigger 19 disable" "No,Yes"
|
|
bitfld.long 0x00 18. " [18] ,Schmitt trigger 18 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Schmitt trigger 17 disable" "No,Yes"
|
|
bitfld.long 0x00 16. " [16] ,Schmitt trigger 16 disable" "No,Yes"
|
|
bitfld.long 0x00 15. " [15] ,Schmitt trigger 15 disable" "No,Yes"
|
|
bitfld.long 0x00 14. " [14] ,Schmitt trigger 14 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Schmitt trigger 13 disable" "No,Yes"
|
|
bitfld.long 0x00 12. " [12] ,Schmitt trigger 12 disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Schmitt trigger 11 disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Schmitt trigger 10 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Schmitt trigger 9 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Schmitt trigger 8 disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Schmitt trigger 7 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Schmitt trigger 6 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Schmitt trigger 5 disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Schmitt trigger 4 disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Schmitt trigger 3 disable" "No,Yes"
|
|
bitfld.long 0x00 2. " [2] ,Schmitt trigger 2 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Schmitt trigger 1 disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Schmitt trigger 0 disable" "No,Yes"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DRIVER,PIO I/O Drive Register"
|
|
bitfld.long 0x00 31. " LINE[31] ,Drive of PIO line 31" "Low,High"
|
|
bitfld.long 0x00 31. " [30] ,Drive of PIO line 30" "Low,High"
|
|
bitfld.long 0x00 28. " [28] ,Drive of PIO line 28" "Low,High"
|
|
bitfld.long 0x00 27. " [27] ,Drive of PIO line 27" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 26. " [26] ,Drive of PIO line 26" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,Drive of PIO line 25" "Low,High"
|
|
bitfld.long 0x00 24. " [24] ,Drive of PIO line 24" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. " [22] ,Drive of PIO line 22" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Drive of PIO line 21" "Low,High"
|
|
bitfld.long 0x00 20. " [20] ,Drive of PIO line 20" "Low,High"
|
|
bitfld.long 0x00 19. " [19] ,Drive of PIO line 19" "Low,High"
|
|
bitfld.long 0x00 18. " [18] ,Drive of PIO line 18" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " [17] ,Drive of PIO line 17" "Low,High"
|
|
bitfld.long 0x00 16. " [16] ,Drive of PIO line 16" "Low,High"
|
|
bitfld.long 0x00 15. " [15] ,Drive of PIO line 15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Drive of PIO line 14" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Drive of PIO line 13" "Low,High"
|
|
bitfld.long 0x00 12. " [12] ,Drive of PIO line 12" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Drive of PIO line 11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Drive of PIO line 10" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Drive of PIO line 9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Drive of PIO line 8" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Drive of PIO line 7" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Drive of PIO line 6" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Drive of PIO line 5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Drive of PIO line 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Drive of PIO line 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Drive of PIO line 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Drive of PIO line 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Drive of PIO line 0" "Low,High"
|
|
width 15.
|
|
newline
|
|
if ((per.l(ad:0x400E1400+0xE4)&0x01)==0x00)
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "PCIMR_SET/CLR,PIO Parallel Capture Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RXBUFF ,Reception buffer full interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENDRX ,End of reception transfer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " OVRE ,Parallel capture mode overrun error interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DRDY ,Parallel capture mode data ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
in
|
|
newline
|
|
if (per.l(ad:0x400E1400+0x150)&0x30)==0x00
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RDATA ,Parallel capture mode reception data"
|
|
elif (per.l(ad:0x400E1400+0x150)&0x30)==0x10
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA ,Parallel capture mode reception data"
|
|
else
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
width 0x0B
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "Port A"
|
|
base ad:0x400E0E00
|
|
width 16.
|
|
if ((per.l(ad:0x400E0E00+0xE4)&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PSR_SET/CLR,PIO Enable Set/Clear Register"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P[27] ,Pin 27 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "OSR_SET/CLR,PIO Output Enable Set/Clear Register"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P[27] ,Pin 27 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IFSR_SET/CLR,PIO Input Filter Enable Set/Clear Register"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P[27] ,Pin 27 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PSR,PIO Enable Status Register"
|
|
bitfld.long 0x00 27. " P[27] ,Pin 27 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "OSR,PIO Output Enable Status Register"
|
|
bitfld.long 0x00 27. " P[27] ,Pin 27 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "IFSR,PIO Input Filter Enable Status Register"
|
|
bitfld.long 0x00 27. " P[27] ,Pin 27 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ODSR_SET/CLR,PIO Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P[27] ,Pin 27 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output data status" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output data status" "Low,High"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 output data status" "Low,High"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output data status" "Low,High"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output data status" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PDSR,PIO Data Status Register"
|
|
bitfld.long 0x00 27. " P[27] ,Pin 27 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output data status" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output data status" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 output data status" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output data status" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output data status" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "IMR_SET/CLR,PIO Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P[27] ,Pin 27 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ISR,PIO Interrupt Status Register"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x400E0E00+0xE4)&0x01)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MDSR_SET/CLR,PIO Multi-Driver Enable Set/Clear Register"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P[27] ,Pin 27 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PUSR_SET/CLR,PIO Pull Up Disable Set/Clear Register"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P[27] ,Pin 27 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x08 11. " [11] ,Pin 11 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x08 10. " [10] ,Pin 10 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 27. " P[27] ,Pin 27 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 27. " P[27] ,Pin 27 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 24. " [24] ,Pin 24 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 22. " [22] ,Pin 22 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 21. " [21] ,Pin 21 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 14. " [14] ,Pin 14 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 13. " [13] ,Pin 13 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 11. " [11] ,Pin 11 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 10. " [10] ,Pin 10 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "MDSR,PIO Multi-Driver Enable Status Register"
|
|
bitfld.long 0x00 27. " P[27] ,Pin 27 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "PUSR,PIO Pull Up Disable Status Register"
|
|
bitfld.long 0x00 27. " P[27] ,Pin 27 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 27. " P[27] ,Pin 27 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 27. " P[27] ,Pin 27 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 24. " [24] ,Pin 24 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 22. " [22] ,Pin 22 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 21. " [21] ,Pin 21 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 14. " [14] ,Pin 14 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 13. " [13] ,Pin 13 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 11. " [11] ,Pin 11 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 10. " [10] ,Pin 10 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "IFSCSR_SET/CLR,PIO Input Filter Slow Clock Set/Clear Register"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " [27] ,Pin 27 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Pin 14 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Pin 13 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 19 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow clock divider selection for debouncing"
|
|
if ((per.l(ad:0x400E0E00+0xE4)&0x01)==0x00)
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PPDSR_SET/CLR,PIO Pad Pull Down Disable Set/Clear Register"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P[27] ,Pin 27 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "OWSR_SET/CLR,PIO Output Write Enable Set/Clear Register"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P[27] ,Pin 27 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "PPDSR,PIO Pad Pull Down Disable Status Register"
|
|
bitfld.long 0x00 27. " P[27] ,Pin 27 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "OWSR,PIO Output Write Enable Status Register"
|
|
bitfld.long 0x00 27. " P[27] ,Pin 27 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "AIMMR_SET/CLR,PIO Additional Interrupt Modes Set/Clear Register"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " P[27] ,Pin 27 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,Pin 14 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,Pin 13 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 peripheral cd status" "Both edge,Registers"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "ELSR_SET/CLR,Edge/level Interrupt Source Selection Set/Clear Register"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P[27] ,Pin 27 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Pin 14 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Pin 13 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Edge,Level"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FRLHSR_SET/CLR,PIO Fall/Rise - Low/High Set/Clear Register"
|
|
setclrfld.long 0x00 27. -0x04 27. -0x08 27. " P[27] ,Pin 27 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [14] ,Pin 14 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [13] ,Pin 13 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 27. " P[27] ,Pin 27 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 14. " [14] ,Pin 14 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " [13] ,Pin 13 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 lock status" "Not locked,Locked"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,PIO Write Protect Status Register"
|
|
in
|
|
newline
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SCHMITT,PIO Schmitt Trigger Register"
|
|
bitfld.long 0x00 27. " SCHMITT[27] ,Schmitt trigger 27 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Schmitt trigger 24 disable" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Schmitt trigger 22 disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Schmitt trigger 21 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 14. " [14] ,Schmitt trigger 14 disable" "No,Yes"
|
|
bitfld.long 0x00 13. " [13] ,Schmitt trigger 13 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Schmitt trigger 12 disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Schmitt trigger 11 disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Schmitt trigger 10 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Schmitt trigger 9 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Schmitt trigger 8 disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Schmitt trigger 7 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Schmitt trigger 5 disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Schmitt trigger 4 disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Schmitt trigger 3 disable" "No,Yes"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DRIVER,PIO I/O Drive Register"
|
|
bitfld.long 0x00 27. " LINE[27] ,Drive of PIO line 27" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Drive of PIO line 24" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,Drive of PIO line 22" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Drive of PIO line 21" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. " [14] ,Drive of PIO line 14" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Drive of PIO line 13" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Drive of PIO line 12" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Drive of PIO line 11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Drive of PIO line 10" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Drive of PIO line 9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Drive of PIO line 8" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Drive of PIO line 7" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Drive of PIO line 5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Drive of PIO line 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Drive of PIO line 3" "Low,High"
|
|
width 15.
|
|
newline
|
|
if ((per.l(ad:0x400E0E00+0xE4)&0x01)==0x00)
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "PCIMR_SET/CLR,PIO Parallel Capture Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RXBUFF ,Reception buffer full interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENDRX ,End of reception transfer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " OVRE ,Parallel capture mode overrun error interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DRDY ,Parallel capture mode data ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
in
|
|
newline
|
|
if (per.l(ad:0x400E0E00+0x150)&0x30)==0x00
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RDATA ,Parallel capture mode reception data"
|
|
elif (per.l(ad:0x400E0E00+0x150)&0x30)==0x10
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA ,Parallel capture mode reception data"
|
|
else
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
width 0x0B
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port B"
|
|
base ad:0x400E1000
|
|
width 16.
|
|
if ((per.l(ad:0x400E1000+0xE4)&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PSR_SET/CLR,PIO Enable Set/Clear Register"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P[12] ,Pin 12 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "OSR_SET/CLR,PIO Output Enable Set/Clear Register"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P[12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IFSR_SET/CLR,PIO Input Filter Enable Set/Clear Register"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P[12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PSR,PIO Enable Status Register"
|
|
bitfld.long 0x00 12. " P[12] ,Pin 12 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "OSR,PIO Output Enable Status Register"
|
|
bitfld.long 0x00 12. " P[12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "IFSR,PIO Input Filter Enable Status Register"
|
|
bitfld.long 0x00 12. " P[12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ODSR_SET/CLR,PIO Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P[12] ,Pin 12 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PDSR,PIO Data Status Register"
|
|
bitfld.long 0x00 12. " P[12] ,Pin 12 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "IMR_SET/CLR,PIO Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P[12] ,Pin 12 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ISR,PIO Interrupt Status Register"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x400E1000+0xE4)&0x01)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MDSR_SET/CLR,PIO Multi-Driver Enable Set/Clear Register"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P[12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PUSR_SET/CLR,PIO Pull Up Disable Set/Clear Register"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P[12] ,Pin 12 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 12. " P[12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 12. " P[12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Pin 6 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "MDSR,PIO Multi-Driver Enable Status Register"
|
|
bitfld.long 0x00 12. " P[12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "PUSR,PIO Pull Up Disable Status Register"
|
|
bitfld.long 0x00 12. " P[12] ,Pin 12 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 12. " P[12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 12. " P[12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Pin 6 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "IFSCSR_SET/CLR,PIO Input Filter Slow Clock Set/Clear Register"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P[12] ,Pin 12 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 19 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow clock divider selection for debouncing"
|
|
if ((per.l(ad:0x400E1000+0xE4)&0x01)==0x00)
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PPDSR_SET/CLR,PIO Pad Pull Down Disable Set/Clear Register"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P[12] ,Pin 12 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "OWSR_SET/CLR,PIO Output Write Enable Set/Clear Register"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P[12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "PPDSR,PIO Pad Pull Down Disable Status Register"
|
|
bitfld.long 0x00 12. " P[12] ,Pin 12 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "OWSR,PIO Output Write Enable Status Register"
|
|
bitfld.long 0x00 12. " P[12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "AIMMR_SET/CLR,PIO Additional Interrupt Modes Set/Clear Register"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " P[12] ,Pin 12 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 peripheral cd status" "Both edge,Registers"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "ELSR_SET/CLR,Edge/level Interrupt Source Selection Set/Clear Register"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P[12] ,Pin 12 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Edge,Level"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FRLHSR_SET/CLR,PIO Fall/Rise - Low/High Set/Clear Register"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " P[12] ,Pin 12 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 12. " P[12] ,Pin 12 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 lock status" "Not locked,Locked"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,PIO Write Protect Status Register"
|
|
in
|
|
newline
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SCHMITT,PIO Schmitt Trigger Register"
|
|
bitfld.long 0x00 12. " SCHMITT[12] ,Schmitt trigger 12 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Schmitt trigger 9 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Schmitt trigger 8 disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Schmitt trigger 7 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Schmitt trigger 6 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Schmitt trigger 5 disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Schmitt trigger 4 disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Schmitt trigger 3 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Schmitt trigger 2 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Schmitt trigger 1 disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Schmitt trigger 0 disable" "No,Yes"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DRIVER,PIO I/O Drive Register"
|
|
bitfld.long 0x00 12. " LINE[12] ,Drive of PIO line 12" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Drive of PIO line 9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Drive of PIO line 8" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Drive of PIO line 7" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Drive of PIO line 6" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Drive of PIO line 5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Drive of PIO line 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Drive of PIO line 3" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Drive of PIO line 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Drive of PIO line 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Drive of PIO line 0" "Low,High"
|
|
width 15.
|
|
newline
|
|
if ((per.l(ad:0x400E1000+0xE4)&0x01)==0x00)
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "PCIMR_SET/CLR,PIO Parallel Capture Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RXBUFF ,Reception buffer full interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENDRX ,End of reception transfer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " OVRE ,Parallel capture mode overrun error interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DRDY ,Parallel capture mode data ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
in
|
|
newline
|
|
if (per.l(ad:0x400E1000+0x150)&0x30)==0x00
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RDATA ,Parallel capture mode reception data"
|
|
elif (per.l(ad:0x400E1000+0x150)&0x30)==0x10
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA ,Parallel capture mode reception data"
|
|
else
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
width 0x0B
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port D"
|
|
base ad:0x400E1400
|
|
width 16.
|
|
if ((per.l(ad:0x400E1400+0xE4)&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PSR_SET/CLR,PIO Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "OSR_SET/CLR,PIO Output Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IFSR_SET/CLR,PIO Input Filter Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "PSR,PIO Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 enable" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "OSR,PIO Output Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output enable" "Disabled,Enabled"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "IFSR,PIO Input Filter Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 input filter enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 input filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 input filter enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ODSR_SET/CLR,PIO Output Data Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 output data status" "Low,High"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 output data status" "Low,High"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output data status" "Low,High"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output data status" "Low,High"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output data status" "Low,High"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output data status" "Low,High"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "PDSR,PIO Data Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 output data status" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 output data status" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output data status" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output data status" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output data status" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output data status" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output data status" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output data status" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output data status" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output data status" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output data status" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output data status" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output data status" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output data status" "Low,High"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "IMR_SET/CLR,PIO Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 input change interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 input change interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "ISR,PIO Interrupt Status Register"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x400E1400+0xE4)&0x01)==0x00)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MDSR_SET/CLR,PIO Multi-Driver Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PUSR_SET/CLR,PIO Pull Up Disable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x08 11. " [11] ,Pin 11 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x08 10. " [10] ,Pin 10 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
group.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 31. " P[31] ,Pin 31 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 26. " [26] ,Pin 26 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 25. " [25] ,Pin 25 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 24. " [24] ,Pin 24 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 22. " [22] ,Pin 22 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 21. " [21] ,Pin 21 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 11. " [11] ,Pin 11 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 10. " [10] ,Pin 10 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Pin 6 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "MDSR,PIO Multi-Driver Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 multi drive enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 multi drive enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 multi drive enable" "Disabled,Enabled"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "PUSR,PIO Pull Up Disable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull up disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull up disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull up disable" "No,Yes"
|
|
rgroup.long 0x70++0x07
|
|
line.long 0x00 "ABCDSR1,PIO Peripheral ABCD Select Register 1"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 peripheral select" "A/C function,B/D function"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 peripheral select" "A/C function,B/D function"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 peripheral select" "A/C function,B/D function"
|
|
line.long 0x04 "ABCDSR2,PIO Peripheral ABCD Select Register 2"
|
|
bitfld.long 0x04 31. " P[31] ,Pin 31 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 26. " [26] ,Pin 26 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 25. " [25] ,Pin 25 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 24. " [24] ,Pin 24 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 22. " [22] ,Pin 22 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 21. " [21] ,Pin 21 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 12. " [12] ,Pin 12 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 11. " [11] ,Pin 11 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 10. " [10] ,Pin 10 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Pin 9 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 8. " [8] ,Pin 8 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 7. " [7] ,Pin 7 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Pin 6 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 5. " [5] ,Pin 5 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 4. " [4] ,Pin 4 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 3. " [3] ,Pin 3 peripheral select" "A/B function,C/D function"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Pin 2 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 1. " [1] ,Pin 1 peripheral select" "A/B function,C/D function"
|
|
bitfld.long 0x04 0. " [0] ,Pin 0 peripheral select" "A/B function,C/D function"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "IFSCSR_SET/CLR,PIO Input Filter Slow Clock Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P[31] ,Pin 31 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Pin 26 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Pin 25 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 19 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 glitch or debouncing filter selection status" "Glitch,Debouncing"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SCDR,PIO Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " DIV ,Slow clock divider selection for debouncing"
|
|
if ((per.l(ad:0x400E1400+0xE4)&0x01)==0x00)
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PPDSR_SET/CLR,PIO Pad Pull Down Disable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "OWSR_SET/CLR,PIO Output Write Enable Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x98++0x03
|
|
line.long 0x00 "PPDSR,PIO Pad Pull Down Disable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 pull down disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 pull down disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 pull down disable" "No,Yes"
|
|
rgroup.long 0xA8++0x03
|
|
line.long 0x00 "OWSR,PIO Output Write Enable Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 output write enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 output write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 output write enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "AIMMR_SET/CLR,PIO Additional Interrupt Modes Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " P[31] ,Pin 31 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " [26] ,Pin 26 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " [25] ,Pin 25 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " [24] ,Pin 24 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,Pin 22 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,Pin 21 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,Pin 12 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,Pin 11 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Pin 10 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Pin 9 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Pin 8 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Pin 7 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Pin 6 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Pin 5 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Pin 4 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Pin 3 peripheral cd status" "Both edge,Registers"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Pin 2 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Pin 1 peripheral cd status" "Both edge,Registers"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Pin 0 peripheral cd status" "Both edge,Registers"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "ELSR_SET/CLR,Edge/level Interrupt Source Selection Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P[31] ,Pin 31 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Pin 26 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Pin 25 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Edge,Level"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Edge,Level"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Edge,Level"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FRLHSR_SET/CLR,PIO Fall/Rise - Low/High Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x04 31. -0x08 31. " P[31] ,Pin 31 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 26. -0x04 26. -0x08 26. " [26] ,Pin 26 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 25. -0x04 25. -0x08 25. " [25] ,Pin 25 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " [24] ,Pin 24 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [22] ,Pin 22 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [21] ,Pin 21 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [12] ,Pin 12 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " [11] ,Pin 11 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [10] ,Pin 10 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [9] ,Pin 9 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [8] ,Pin 8 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " [7] ,Pin 7 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [6] ,Pin 6 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [5] ,Pin 5 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [4] ,Pin 4 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " [3] ,Pin 3 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Pin 2 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Pin 1 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Pin 0 edge/level interrupt source selection" "Falling/Low,Rising/High"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x00 31. " P[31] ,Pin 31 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 26. " [26] ,Pin 26 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 25. " [25] ,Pin 25 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Pin 24 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 22. " [22] ,Pin 22 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 21. " [21] ,Pin 21 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Pin 12 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " [11] ,Pin 11 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " [10] ,Pin 10 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Pin 9 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " [8] ,Pin 8 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 7. " [7] ,Pin 7 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Pin 6 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pin 5 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 4. " [4] ,Pin 4 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " [3] ,Pin 3 lock status" "Not locked,Locked"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Pin 2 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " [1] ,Pin 1 lock status" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " [0] ,Pin 0 lock status" "Not locked,Locked"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,PIO Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,PIO Write Protect Status Register"
|
|
in
|
|
newline
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SCHMITT,PIO Schmitt Trigger Register"
|
|
bitfld.long 0x00 31. " SCHMITT[31] ,Schmitt trigger 31 disable" "No,Yes"
|
|
bitfld.long 0x00 26. " [26] ,Schmitt trigger 26 disable" "No,Yes"
|
|
bitfld.long 0x00 25. " [25] ,Schmitt trigger 25 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Schmitt trigger 24 disable" "No,Yes"
|
|
bitfld.long 0x00 22. " [22] ,Schmitt trigger 22 disable" "No,Yes"
|
|
bitfld.long 0x00 21. " [21] ,Schmitt trigger 21 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Schmitt trigger 12 disable" "No,Yes"
|
|
bitfld.long 0x00 11. " [11] ,Schmitt trigger 11 disable" "No,Yes"
|
|
bitfld.long 0x00 10. " [10] ,Schmitt trigger 10 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Schmitt trigger 9 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " [8] ,Schmitt trigger 8 disable" "No,Yes"
|
|
bitfld.long 0x00 7. " [7] ,Schmitt trigger 7 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Schmitt trigger 6 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Schmitt trigger 5 disable" "No,Yes"
|
|
bitfld.long 0x00 4. " [4] ,Schmitt trigger 4 disable" "No,Yes"
|
|
bitfld.long 0x00 3. " [3] ,Schmitt trigger 3 disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Schmitt trigger 2 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " [1] ,Schmitt trigger 1 disable" "No,Yes"
|
|
bitfld.long 0x00 0. " [0] ,Schmitt trigger 0 disable" "No,Yes"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DRIVER,PIO I/O Drive Register"
|
|
bitfld.long 0x00 31. " LINE[31] ,Drive of PIO line 31" "Low,High"
|
|
bitfld.long 0x00 26. " [26] ,Drive of PIO line 26" "Low,High"
|
|
bitfld.long 0x00 25. " [25] ,Drive of PIO line 25" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 24. " [24] ,Drive of PIO line 24" "Low,High"
|
|
bitfld.long 0x00 22. " [22] ,Drive of PIO line 22" "Low,High"
|
|
bitfld.long 0x00 21. " [21] ,Drive of PIO line 21" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Drive of PIO line 12" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Drive of PIO line 11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Drive of PIO line 10" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Drive of PIO line 9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Drive of PIO line 8" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Drive of PIO line 7" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Drive of PIO line 6" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Drive of PIO line 5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Drive of PIO line 4" "Low,High"
|
|
bitfld.long 0x00 3. " [3] ,Drive of PIO line 3" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. " [2] ,Drive of PIO line 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Drive of PIO line 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Drive of PIO line 0" "Low,High"
|
|
width 15.
|
|
newline
|
|
if ((per.l(ad:0x400E1400+0xE4)&0x01)==0x00)
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "PCMR,PIO Parallel Capture Mode Register"
|
|
bitfld.long 0x00 11. " FRSTS ,Parallel capture mode first sample" "Even index,Odd index"
|
|
bitfld.long 0x00 10. " HALFS ,Parallel capture mode half sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALWYS ,Parallel capture mode always sampling" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " DSIZE ,Parallel capture mode data size" "8 bit,16 bit,32 bit,?..."
|
|
bitfld.long 0x00 0. " PCEN ,Parallel capture mode enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "PCIMR_SET/CLR,PIO Parallel Capture Interrupt Enable Set/Clear Register"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RXBUFF ,Reception buffer full interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENDRX ,End of reception transfer interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " OVRE ,Parallel capture mode overrun error interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DRDY ,Parallel capture mode data ready interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0x160++0x03
|
|
hide.long 0x00 "PCISR,PIO Parallel Capture Interrupt Status Register"
|
|
in
|
|
newline
|
|
if (per.l(ad:0x400E1400+0x150)&0x30)==0x00
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RDATA ,Parallel capture mode reception data"
|
|
elif (per.l(ad:0x400E1400+0x150)&0x30)==0x10
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA ,Parallel capture mode reception data"
|
|
else
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "PCRHR,PIO Parallel Capture Reception Holding Register"
|
|
endif
|
|
width 0x0B
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif cpuis("ATSAMS70Q*")
|
|
tree "SDRAMC (SDRAM Controller)"
|
|
base ad:0x40084000
|
|
width 13.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "MR,SDRAMC Mode Register"
|
|
bitfld.long 0x00 0.--2. " MODE ,SDRAMC command mode" "Normal,NOP,ALLBANKS_PRECHARGE,LOAD_MODEREG,AUTO_REFRESH,EXT_LOAD_MODEREG,DEEP_POWERDOWN,?..."
|
|
line.long 0x04 "TR,SDRAMC Refresh Timer Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " COUNT ,SDRAMC refresh timer count"
|
|
line.long 0x08 "CR,SDRAMC Configuration Register"
|
|
bitfld.long 0x08 28.--31. " TXSR ,Exit self refresh to active delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 24.--27. " TRAS ,Active to precharge delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 20.--23. " TRCD ,Row to column delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 16.--19. " TRP ,Row precharge delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x08 12.--15. " TRC_TRFC ,Row cycle delay and row refresh cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--11. " TWR ,Write recovery delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 7. " DBW ,Data bus width" ",16 bits"
|
|
bitfld.long 0x08 5.--6. " CAS ,CAS latency" "1 cycle,2 cycle,3 cycle,?..."
|
|
newline
|
|
bitfld.long 0x08 4. " NB ,Number of banks" "2 banks,4 banks"
|
|
bitfld.long 0x08 2.--3. " NR ,Number of row bits" "11 row,12 row,13 row,?..."
|
|
bitfld.long 0x08 0.--1. " NC ,Number of column bits" "8 column,9 column,10 column,11 column"
|
|
if (((per.l(ad:0x40084000+0x24))&0x03)==0x01)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "LPR,SDRAMC Low Power Register"
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Enable immediately,64 clock cycles,128 clock cycles,?..."
|
|
bitfld.long 0x00 10.--11. " DS ,Drive strength" "0,1,2,3"
|
|
bitfld.long 0x00 8.--9. " TCSR ,TCSR: temperature compensated self-refresh" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. " PASR ,Partial array self-refresh" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " LPCB ,Low-power configuration bits" "Disabled,Self refresh,Power down,Deep power down"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "LPR,SDRAMC Low Power Register"
|
|
bitfld.long 0x00 12.--13. " TIMEOUT ,Time to define when low-power mode is enabled" "Enable immediately,64 clock cycles,128 clock cycles,?..."
|
|
bitfld.long 0x00 0.--1. " LPCB ,Low-power configuration bits" "Disabled,Self refresh,Power down,Deep power down"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,SDRAMC Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RES ,Refresh error interrupt" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "ISR,SDRAMC Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x24++0x0B
|
|
line.long 0x00 "MDR,SDRAMC Memory Device Register"
|
|
bitfld.long 0x00 0.--1. " MD ,Memory device type" "SDRAM,Low-power,?..."
|
|
line.long 0x04 "CFR1,SDRAMC Configuration 1 Register"
|
|
bitfld.long 0x04 8. " UNAL ,Support unaligned access" "Not supported,Supported"
|
|
bitfld.long 0x04 0.--3. " TMRD ,Load mode register command to active or refresh command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "OCMS,SDRAMC OCMS Register"
|
|
bitfld.long 0x08 0. " SDR_SE ,SDRAM memory controller scrambling enable" "Disabled,Enabled"
|
|
wgroup.long 0x30++0x07
|
|
line.long 0x00 "OCMS_KEY1,SDRAMC OCMS KEY1 Register"
|
|
line.long 0x04 "OCMS_KEY2,SDRAMC OCMS KEY2 Register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "SMC (Static Memory Controller)"
|
|
base ad:0x40080000
|
|
width 8.
|
|
tree "CS0"
|
|
if ((per.l(ad:0x40080000+0xE4)&0x01)==0x00)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SETUP0,SMC Setup Register 0"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS setup length in read access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD setup length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS setup length in write access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE setup length"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PULSE0,SMC Pulse Register 0"
|
|
hexmask.long.byte 0x00 24.--30. 1. " NCS_RD_PULSE ,NCS pulse length in read access"
|
|
hexmask.long.byte 0x00 16.--22. 1. " NRD_PULSE ,NRD pulse length"
|
|
hexmask.long.byte 0x00 8.--14. 1. " NCS_WR_PULSE ,NCS pulse length in write access"
|
|
hexmask.long.byte 0x00 0.--6. 1. " NWE_PULSE ,NWE pulse length"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "CYCLE0,SMC Cycle Register 0"
|
|
hexmask.long.word 0x00 16.--24. 1. " NRD_CYCLE ,Total read cycle length"
|
|
hexmask.long.word 0x00 0.--8. 1. " NWE_CYCLE ,Total write cycle length"
|
|
if (((per.l(ad:0x40080000+0x0))&0x1000)==0x1000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 28.--29. " PS ,Page size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 24. " PMEN ,Page mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data float time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
newline
|
|
bitfld.long 0x00 12. " DBW ,Data bus width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte access type R/W" "BYTE_SELECT,BYTE_WRITE"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write mode" "NCS,NWE"
|
|
newline
|
|
bitfld.long 0x00 0. " READ_MODE ,Read mode" "NCS,NRD"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 28.--29. " PS ,Page size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 24. " PMEN ,Page mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data float time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
newline
|
|
bitfld.long 0x00 12. " DBW ,Data bus width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read mode" "NCS,NRD"
|
|
endif
|
|
else
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "SETUP0,SMC Setup Register 0"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS setup length in read access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD setup length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS setup length in write access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE setup length"
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "PULSE0,SMC Pulse Register 0"
|
|
hexmask.long.byte 0x00 24.--30. 1. " NCS_RD_PULSE ,NCS pulse length in read access"
|
|
hexmask.long.byte 0x00 16.--22. 1. " NRD_PULSE ,NRD pulse length"
|
|
hexmask.long.byte 0x00 8.--14. 1. " NCS_WR_PULSE ,NCS pulse length in write access"
|
|
hexmask.long.byte 0x00 0.--6. 1. " NWE_PULSE ,NWE pulse length"
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "CYCLE0,SMC Cycle Register 0"
|
|
hexmask.long.word 0x00 16.--24. 1. " NRD_CYCLE ,Total read cycle length"
|
|
hexmask.long.word 0x00 0.--8. 1. " NWE_CYCLE ,Total write cycle length"
|
|
if (((per.l(ad:0x40080000+0x0))&0x1000)==0x1000)
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 28.--29. " PS ,Page size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 24. " PMEN ,Page mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data float time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
newline
|
|
bitfld.long 0x00 12. " DBW ,Data bus width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte access type R/W" "BYTE_SELECT,BYTE_WRITE"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write mode" "NCS,NWE"
|
|
newline
|
|
bitfld.long 0x00 0. " READ_MODE ,Read mode" "NCS,NRD"
|
|
else
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "MODE0,SMC Mode Register 0"
|
|
bitfld.long 0x00 28.--29. " PS ,Page size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 24. " PMEN ,Page mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data float time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
newline
|
|
bitfld.long 0x00 12. " DBW ,Data bus width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read mode" "NCS,NRD"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "CS1"
|
|
if ((per.l(ad:0x40080000+0xE4)&0x01)==0x00)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SETUP1,SMC Setup Register 1"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS setup length in read access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD setup length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS setup length in write access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE setup length"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PULSE1,SMC Pulse Register 1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " NCS_RD_PULSE ,NCS pulse length in read access"
|
|
hexmask.long.byte 0x00 16.--22. 1. " NRD_PULSE ,NRD pulse length"
|
|
hexmask.long.byte 0x00 8.--14. 1. " NCS_WR_PULSE ,NCS pulse length in write access"
|
|
hexmask.long.byte 0x00 0.--6. 1. " NWE_PULSE ,NWE pulse length"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "CYCLE1,SMC Cycle Register 1"
|
|
hexmask.long.word 0x00 16.--24. 1. " NRD_CYCLE ,Total read cycle length"
|
|
hexmask.long.word 0x00 0.--8. 1. " NWE_CYCLE ,Total write cycle length"
|
|
if (((per.l(ad:0x40080000+0x0))&0x1000)==0x1000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 28.--29. " PS ,Page size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 24. " PMEN ,Page mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data float time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
newline
|
|
bitfld.long 0x00 12. " DBW ,Data bus width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte access type R/W" "BYTE_SELECT,BYTE_WRITE"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write mode" "NCS,NWE"
|
|
newline
|
|
bitfld.long 0x00 0. " READ_MODE ,Read mode" "NCS,NRD"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 28.--29. " PS ,Page size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 24. " PMEN ,Page mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data float time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
newline
|
|
bitfld.long 0x00 12. " DBW ,Data bus width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read mode" "NCS,NRD"
|
|
endif
|
|
else
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "SETUP1,SMC Setup Register 1"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS setup length in read access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD setup length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS setup length in write access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE setup length"
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "PULSE1,SMC Pulse Register 1"
|
|
hexmask.long.byte 0x00 24.--30. 1. " NCS_RD_PULSE ,NCS pulse length in read access"
|
|
hexmask.long.byte 0x00 16.--22. 1. " NRD_PULSE ,NRD pulse length"
|
|
hexmask.long.byte 0x00 8.--14. 1. " NCS_WR_PULSE ,NCS pulse length in write access"
|
|
hexmask.long.byte 0x00 0.--6. 1. " NWE_PULSE ,NWE pulse length"
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "CYCLE1,SMC Cycle Register 1"
|
|
hexmask.long.word 0x00 16.--24. 1. " NRD_CYCLE ,Total read cycle length"
|
|
hexmask.long.word 0x00 0.--8. 1. " NWE_CYCLE ,Total write cycle length"
|
|
if (((per.l(ad:0x40080000+0x0))&0x1000)==0x1000)
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 28.--29. " PS ,Page size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 24. " PMEN ,Page mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data float time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
newline
|
|
bitfld.long 0x00 12. " DBW ,Data bus width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte access type R/W" "BYTE_SELECT,BYTE_WRITE"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write mode" "NCS,NWE"
|
|
newline
|
|
bitfld.long 0x00 0. " READ_MODE ,Read mode" "NCS,NRD"
|
|
else
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "MODE1,SMC Mode Register 1"
|
|
bitfld.long 0x00 28.--29. " PS ,Page size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 24. " PMEN ,Page mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data float time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
newline
|
|
bitfld.long 0x00 12. " DBW ,Data bus width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read mode" "NCS,NRD"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "CS2"
|
|
if ((per.l(ad:0x40080000+0xE4)&0x01)==0x00)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SETUP2,SMC Setup Register 2"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS setup length in read access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD setup length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS setup length in write access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE setup length"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PULSE2,SMC Pulse Register 2"
|
|
hexmask.long.byte 0x00 24.--30. 1. " NCS_RD_PULSE ,NCS pulse length in read access"
|
|
hexmask.long.byte 0x00 16.--22. 1. " NRD_PULSE ,NRD pulse length"
|
|
hexmask.long.byte 0x00 8.--14. 1. " NCS_WR_PULSE ,NCS pulse length in write access"
|
|
hexmask.long.byte 0x00 0.--6. 1. " NWE_PULSE ,NWE pulse length"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "CYCLE2,SMC Cycle Register 2"
|
|
hexmask.long.word 0x00 16.--24. 1. " NRD_CYCLE ,Total read cycle length"
|
|
hexmask.long.word 0x00 0.--8. 1. " NWE_CYCLE ,Total write cycle length"
|
|
if (((per.l(ad:0x40080000+0x0))&0x1000)==0x1000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 28.--29. " PS ,Page size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 24. " PMEN ,Page mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data float time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
newline
|
|
bitfld.long 0x00 12. " DBW ,Data bus width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte access type R/W" "BYTE_SELECT,BYTE_WRITE"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write mode" "NCS,NWE"
|
|
newline
|
|
bitfld.long 0x00 0. " READ_MODE ,Read mode" "NCS,NRD"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 28.--29. " PS ,Page size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 24. " PMEN ,Page mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data float time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
newline
|
|
bitfld.long 0x00 12. " DBW ,Data bus width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read mode" "NCS,NRD"
|
|
endif
|
|
else
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "SETUP2,SMC Setup Register 2"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS setup length in read access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD setup length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS setup length in write access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE setup length"
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "PULSE2,SMC Pulse Register 2"
|
|
hexmask.long.byte 0x00 24.--30. 1. " NCS_RD_PULSE ,NCS pulse length in read access"
|
|
hexmask.long.byte 0x00 16.--22. 1. " NRD_PULSE ,NRD pulse length"
|
|
hexmask.long.byte 0x00 8.--14. 1. " NCS_WR_PULSE ,NCS pulse length in write access"
|
|
hexmask.long.byte 0x00 0.--6. 1. " NWE_PULSE ,NWE pulse length"
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "CYCLE2,SMC Cycle Register 2"
|
|
hexmask.long.word 0x00 16.--24. 1. " NRD_CYCLE ,Total read cycle length"
|
|
hexmask.long.word 0x00 0.--8. 1. " NWE_CYCLE ,Total write cycle length"
|
|
if (((per.l(ad:0x40080000+0x0))&0x1000)==0x1000)
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 28.--29. " PS ,Page size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 24. " PMEN ,Page mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data float time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
newline
|
|
bitfld.long 0x00 12. " DBW ,Data bus width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte access type R/W" "BYTE_SELECT,BYTE_WRITE"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write mode" "NCS,NWE"
|
|
newline
|
|
bitfld.long 0x00 0. " READ_MODE ,Read mode" "NCS,NRD"
|
|
else
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "MODE2,SMC Mode Register 2"
|
|
bitfld.long 0x00 28.--29. " PS ,Page size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 24. " PMEN ,Page mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data float time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
newline
|
|
bitfld.long 0x00 12. " DBW ,Data bus width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read mode" "NCS,NRD"
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "CS3"
|
|
if ((per.l(ad:0x40080000+0xE4)&0x01)==0x00)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "SETUP3,SMC Setup Register 3"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS setup length in read access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD setup length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS setup length in write access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE setup length"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PULSE3,SMC Pulse Register 3"
|
|
hexmask.long.byte 0x00 24.--30. 1. " NCS_RD_PULSE ,NCS pulse length in read access"
|
|
hexmask.long.byte 0x00 16.--22. 1. " NRD_PULSE ,NRD pulse length"
|
|
hexmask.long.byte 0x00 8.--14. 1. " NCS_WR_PULSE ,NCS pulse length in write access"
|
|
hexmask.long.byte 0x00 0.--6. 1. " NWE_PULSE ,NWE pulse length"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "CYCLE3,SMC Cycle Register 3"
|
|
hexmask.long.word 0x00 16.--24. 1. " NRD_CYCLE ,Total read cycle length"
|
|
hexmask.long.word 0x00 0.--8. 1. " NWE_CYCLE ,Total write cycle length"
|
|
if (((per.l(ad:0x40080000+0x0))&0x1000)==0x1000)
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 28.--29. " PS ,Page size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 24. " PMEN ,Page mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data float time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
newline
|
|
bitfld.long 0x00 12. " DBW ,Data bus width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte access type R/W" "BYTE_SELECT,BYTE_WRITE"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write mode" "NCS,NWE"
|
|
newline
|
|
bitfld.long 0x00 0. " READ_MODE ,Read mode" "NCS,NRD"
|
|
else
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 28.--29. " PS ,Page size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 24. " PMEN ,Page mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data float time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
newline
|
|
bitfld.long 0x00 12. " DBW ,Data bus width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read mode" "NCS,NRD"
|
|
endif
|
|
else
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "SETUP3,SMC Setup Register 3"
|
|
hexmask.long.byte 0x00 24.--29. 1. " NCS_RD_SETUP ,NCS setup length in read access"
|
|
hexmask.long.byte 0x00 16.--21. 1. " NRD_SETUP ,NRD setup length"
|
|
hexmask.long.byte 0x00 8.--13. 1. " NCS_WR_SETUP ,NCS setup length in write access"
|
|
hexmask.long.byte 0x00 0.--5. 1. " NWE_SETUP ,NWE setup length"
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "PULSE3,SMC Pulse Register 3"
|
|
hexmask.long.byte 0x00 24.--30. 1. " NCS_RD_PULSE ,NCS pulse length in read access"
|
|
hexmask.long.byte 0x00 16.--22. 1. " NRD_PULSE ,NRD pulse length"
|
|
hexmask.long.byte 0x00 8.--14. 1. " NCS_WR_PULSE ,NCS pulse length in write access"
|
|
hexmask.long.byte 0x00 0.--6. 1. " NWE_PULSE ,NWE pulse length"
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "CYCLE3,SMC Cycle Register 3"
|
|
hexmask.long.word 0x00 16.--24. 1. " NRD_CYCLE ,Total read cycle length"
|
|
hexmask.long.word 0x00 0.--8. 1. " NWE_CYCLE ,Total write cycle length"
|
|
if (((per.l(ad:0x40080000+0x0))&0x1000)==0x1000)
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 28.--29. " PS ,Page size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 24. " PMEN ,Page mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data float time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
newline
|
|
bitfld.long 0x00 12. " DBW ,Data bus width" "8-bit,16-bit"
|
|
bitfld.long 0x00 8. " BAT ,Byte access type R/W" "BYTE_SELECT,BYTE_WRITE"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write mode" "NCS,NWE"
|
|
newline
|
|
bitfld.long 0x00 0. " READ_MODE ,Read mode" "NCS,NRD"
|
|
else
|
|
rgroup.long 0x0++0x03
|
|
line.long 0x00 "MODE3,SMC Mode Register 3"
|
|
bitfld.long 0x00 28.--29. " PS ,Page size" "4-byte,8-byte,16-byte,32-byte"
|
|
bitfld.long 0x00 24. " PMEN ,Page mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " TDF_MODE ,TDF optimization" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " TDF_CYCLES ,Data float time" "No cycle,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles"
|
|
newline
|
|
bitfld.long 0x00 12. " DBW ,Data bus width" "8-bit,16-bit"
|
|
bitfld.long 0x00 4.--5. " EXNW_MODE ,NWAIT mode" "Disabled,,Frozen,Ready"
|
|
bitfld.long 0x00 1. " WRITE_MODE ,Write mode" "NCS,NWE"
|
|
bitfld.long 0x00 0. " READ_MODE ,Read mode" "NCS,NRD"
|
|
endif
|
|
endif
|
|
tree.end
|
|
width 6.
|
|
newline
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "OCMS,SMC OCMS Mode Register"
|
|
sif !cpuis("ATSAME70*")
|
|
sif cpuis("ATSAMS70*")
|
|
bitfld.long 0x00 11. " CS3SE ,Chip select 3 scrambling enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CS2SE ,Chip select 2 scrambling enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CS1SE ,Chip select 1 scrambling enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CS0SE ,Chip select 0 scrambling enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 19. " CS3SE ,Chip select 3 scrambling enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CS2SE ,Chip select 2 scrambling enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CS1SE ,Chip select 1 scrambling enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CS0SE ,Chip select 0 scrambling enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 0. " SMSE ,Static memory controller scrambling enable" "Disabled,Enabled"
|
|
wgroup.long 0x84++0x07
|
|
line.long 0x00 "KEY1,SMC OCMS Key 1 Register"
|
|
line.long 0x04 "KEY2,SMC OCMS Key 2 Register"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,SMC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protection KEY password"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,SMC Write Protection Status"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "XDMAC (Extensible DMA Controller)"
|
|
base ad:0x40078000
|
|
width 13.
|
|
rgroup.long 0x00++0x07
|
|
line.long 0x00 "GTYPE,Global Type Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " NB_REQ ,Number of peripheral requests minus one"
|
|
hexmask.long.word 0x00 5.--15. 1. " FIFO_SZ ,Number of bytes"
|
|
bitfld.long 0x00 0.--4. " NB_CH ,Number of channels minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "GCFG,Global Configuration Register"
|
|
bitfld.long 0x04 8. " BXKBEN ,Boundary X kilo byte enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " CGDISIF ,Bus interface clock gating disable" "No,Yes"
|
|
bitfld.long 0x04 2. " CGDISFIFO ,FIFO clock gating disable" "No,Yes"
|
|
bitfld.long 0x04 1. " CGDISPIPE ,Pipeline clock gating disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 0. " CGDISREG ,Configuration registers clock gating disable" "No,Yes"
|
|
sif cpuis("ATSAME70*")||cpuis("ATSAMA5D4*")||cpuis("ATSAMA5D2?")
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "GWAC,Global Weighted Arbiter Configuration Register"
|
|
bitfld.long 0x00 12.--15. " PW[3] ,Pool weight 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " [2] ,Pool weight 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " [1] ,Pool weight 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " [0] ,Pool weight 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GWAC,Global Weighted Arbiter Configuration Register"
|
|
bitfld.long 0x00 12.--15. " PW[3] ,Pool weight 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " [2] ,Pool weight 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " [1] ,Pool weight 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " [0] ,Pool weight 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
newline
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GIM_SET/CLR,Global Interrupt Mask Set/Clear Register"
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " IM[23] ,XDMAC channel 23 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,XDMAC channel 22 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,XDMAC channel 21 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,XDMAC channel 20 interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,XDMAC channel 19 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,XDMAC channel 18 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,XDMAC channel 17 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,XDMAC channel 16 interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,XDMAC channel 15 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,XDMAC channel 14 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,XDMAC channel 13 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,XDMAC channel 12 interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,XDMAC channel 11 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,XDMAC channel 10 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,XDMAC channel 9 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,XDMAC channel 8 interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,XDMAC channel 7 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,XDMAC channel 6 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,XDMAC channel 5 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,XDMAC channel 4 interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,XDMAC channel 3 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,XDMAC channel 2 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,XDMAC channel 1 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,XDMAC channel 0 interrupt mask" "Masked,Unmasked"
|
|
else
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " IM[15] ,XDMAC channel 15 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,XDMAC channel 14 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,XDMAC channel 13 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,XDMAC channel 12 interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,XDMAC channel 11 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,XDMAC channel 10 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,XDMAC channel 9 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,XDMAC channel 8 interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,XDMAC channel 7 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,XDMAC channel 6 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,XDMAC channel 5 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,XDMAC channel 4 interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,XDMAC channel 3 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,XDMAC channel 2 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,XDMAC channel 1 interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,XDMAC channel 0 interrupt mask" "Masked,Unmasked"
|
|
endif
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "GIS,Global Interrupt Status Register"
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
bitfld.long 0x00 23. " IS[23] ,XDMAC channel 15 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [22] ,XDMAC channel 14 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [21] ,XDMAC channel 13 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [20] ,XDMAC channel 12 interrupt status bit" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,XDMAC channel 15 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [18] ,XDMAC channel 14 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [17] ,XDMAC channel 13 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [16] ,XDMAC channel 12 interrupt status bit" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,XDMAC channel 15 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [14] ,XDMAC channel 14 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [13] ,XDMAC channel 13 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [12] ,XDMAC channel 12 interrupt status bit" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,XDMAC channel 11 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [10] ,XDMAC channel 10 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [9] ,XDMAC channel 9 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [8] ,XDMAC channel 8 interrupt status bit" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,XDMAC channel 7 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [6] ,XDMAC channel 6 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [5] ,XDMAC channel 5 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [4] ,XDMAC channel 4 interrupt status bit" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,XDMAC channel 3 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [2] ,XDMAC channel 2 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [1] ,XDMAC channel 1 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [0] ,XDMAC channel 0 interrupt status bit" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x00 15. " IS[15] ,XDMAC channel 15 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [14] ,XDMAC channel 14 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [13] ,XDMAC channel 13 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [12] ,XDMAC channel 12 interrupt status bit" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,XDMAC channel 11 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [10] ,XDMAC channel 10 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [9] ,XDMAC channel 9 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [8] ,XDMAC channel 8 interrupt status bit" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,XDMAC channel 7 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [6] ,XDMAC channel 6 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [5] ,XDMAC channel 5 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [4] ,XDMAC channel 4 interrupt status bit" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,XDMAC channel 3 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [2] ,XDMAC channel 2 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [1] ,XDMAC channel 1 interrupt status bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [0] ,XDMAC channel 0 interrupt status bit" "No interrupt,Interrupt"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GS_SET/CLR,Global Channel Status Set/Clear Register"
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " ST[23] ,XDMAC channel 23 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [22] ,XDMAC channel 22 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [21] ,XDMAC channel 21 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [20] ,XDMAC channel 20 status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [19] ,XDMAC channel 19 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [18] ,XDMAC channel 18 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [17] ,XDMAC channel 17 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [16] ,XDMAC channel 16 status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " [15] ,XDMAC channel 15 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,XDMAC channel 14 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,XDMAC channel 13 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,XDMAC channel 12 status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,XDMAC channel 11 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,XDMAC channel 10 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,XDMAC channel 9 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,XDMAC channel 8 status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,XDMAC channel 7 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,XDMAC channel 6 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,XDMAC channel 5 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,XDMAC channel 4 status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,XDMAC channel 3 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,XDMAC channel 2 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,XDMAC channel 1 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,XDMAC channel 0 status" "Disabled,Enabled"
|
|
else
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " ST[15] ,XDMAC channel 15 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [14] ,XDMAC channel 14 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [13] ,XDMAC channel 13 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [12] ,XDMAC channel 12 status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [11] ,XDMAC channel 11 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,XDMAC channel 10 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,XDMAC channel 9 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,XDMAC channel 8 status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,XDMAC channel 7 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,XDMAC channel 6 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,XDMAC channel 5 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,XDMAC channel 4 status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,XDMAC channel 3 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,XDMAC channel 2 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,XDMAC channel 1 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,XDMAC channel 0 status" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "GRS,Global Channel Read Suspend Register"
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
bitfld.long 0x00 23. " RS[23] ,XDMAC channel 23 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 22. " [22] ,XDMAC channel 22 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 21. " [21] ,XDMAC channel 21 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 20. " [20] ,XDMAC channel 20 read suspend" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,XDMAC channel 19 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 18. " [18] ,XDMAC channel 18 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 17. " [17] ,XDMAC channel 17 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 16. " [16] ,XDMAC channel 16 read suspend" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,XDMAC channel 15 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 14. " [14] ,XDMAC channel 14 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 13. " [13] ,XDMAC channel 13 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 12. " [12] ,XDMAC channel 12 read suspend" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,XDMAC channel 11 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 10. " [10] ,XDMAC channel 10 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 9. " [9] ,XDMAC channel 9 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 8. " [8] ,XDMAC channel 8 read suspend" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,XDMAC channel 7 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " [6] ,XDMAC channel 6 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 5. " [5] ,XDMAC channel 5 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 4. " [4] ,XDMAC channel 4 read suspend" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,XDMAC channel 3 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 2. " [2] ,XDMAC channel 2 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 1. " [1] ,XDMAC channel 1 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 0. " [0] ,XDMAC channel 0 read suspend" "Not suspended,Suspended"
|
|
else
|
|
bitfld.long 0x00 15. " RS[15] ,XDMAC channel 15 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 14. " [14] ,XDMAC channel 14 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 13. " [13] ,XDMAC channel 13 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 12. " [12] ,XDMAC channel 12 read suspend" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,XDMAC channel 11 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 10. " [10] ,XDMAC channel 10 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 9. " [9] ,XDMAC channel 9 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 8. " [8] ,XDMAC channel 8 read suspend" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,XDMAC channel 7 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 6. " [6] ,XDMAC channel 6 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 5. " [5] ,XDMAC channel 5 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 4. " [4] ,XDMAC channel 4 read suspend" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,XDMAC channel 3 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 2. " [2] ,XDMAC channel 2 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 1. " [1] ,XDMAC channel 1 read suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 0. " [0] ,XDMAC channel 0 read suspend" "Not suspended,Suspended"
|
|
endif
|
|
line.long 0x04 "GWS,Global Channel Write Suspend Register"
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
bitfld.long 0x04 23. " WS[23] ,XDMAC channel 23 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 22. " [22] ,XDMAC channel 22 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 21. " [21] ,XDMAC channel 21 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 20. " [20] ,XDMAC channel 20 write suspend" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,XDMAC channel 19 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 18. " [18] ,XDMAC channel 18 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 17. " [17] ,XDMAC channel 17 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 16. " [16] ,XDMAC channel 16 write suspend" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x04 15. " [15] ,XDMAC channel 15 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 14. " [14] ,XDMAC channel 14 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 13. " [13] ,XDMAC channel 13 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 12. " [12] ,XDMAC channel 12 write suspend" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,XDMAC channel 11 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 10. " [10] ,XDMAC channel 10 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 9. " [9] ,XDMAC channel 9 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 8. " [8] ,XDMAC channel 8 write suspend" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,XDMAC channel 7 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 6. " [6] ,XDMAC channel 6 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 5. " [5] ,XDMAC channel 5 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 4. " [4] ,XDMAC channel 4 write suspend" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,XDMAC channel 3 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 2. " [2] ,XDMAC channel 2 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 1. " [1] ,XDMAC channel 1 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 0. " [0] ,XDMAC channel 0 write suspend" "Not suspended,Suspended"
|
|
else
|
|
bitfld.long 0x04 15. " WS[15] ,XDMAC channel 15 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 14. " [14] ,XDMAC channel 14 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 13. " [13] ,XDMAC channel 13 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 12. " [12] ,XDMAC channel 12 write suspend" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,XDMAC channel 11 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 10. " [10] ,XDMAC channel 10 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 9. " [9] ,XDMAC channel 9 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 8. " [8] ,XDMAC channel 8 write suspend" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,XDMAC channel 7 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 6. " [6] ,XDMAC channel 6 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 5. " [5] ,XDMAC channel 5 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 4. " [4] ,XDMAC channel 4 write suspend" "Not suspended,Suspended"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,XDMAC channel 3 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 2. " [2] ,XDMAC channel 2 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 1. " [1] ,XDMAC channel 1 write suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x04 0. " [0] ,XDMAC channel 0 write suspend" "Not suspended,Suspended"
|
|
endif
|
|
wgroup.long 0x30++0x0B
|
|
line.long 0x00 "GRWS,Global Channel Read Write Suspend Register"
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
bitfld.long 0x00 23. " RWS[23] ,XDMAC channel 23 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 22. " [22] ,XDMAC channel 22 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 21. " [21] ,XDMAC channel 21 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 20. " [20] ,XDMAC channel 20 read write suspend" "No effect,Suspend"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,XDMAC channel 19 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 18. " [18] ,XDMAC channel 18 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 17. " [17] ,XDMAC channel 17 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 16. " [16] ,XDMAC channel 16 read write suspend" "No effect,Suspend"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,XDMAC channel 15 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 14. " [14] ,XDMAC channel 14 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 13. " [13] ,XDMAC channel 13 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 12. " [12] ,XDMAC channel 12 read write suspend" "No effect,Suspend"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,XDMAC channel 11 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 10. " [10] ,XDMAC channel 10 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 9. " [9] ,XDMAC channel 9 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 8. " [8] ,XDMAC channel 8 read write suspend" "No effect,Suspend"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,XDMAC channel 7 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 6. " [6] ,XDMAC channel 6 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 5. " [5] ,XDMAC channel 5 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 4. " [4] ,XDMAC channel 4 read write suspend" "No effect,Suspend"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,XDMAC channel 3 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 2. " [2] ,XDMAC channel 2 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 1. " [1] ,XDMAC channel 1 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 0. " [0] ,XDMAC channel 0 read write suspend" "No effect,Suspend"
|
|
else
|
|
bitfld.long 0x00 15. " RWS[15] ,XDMAC channel 15 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 14. " [14] ,XDMAC channel 14 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 13. " [13] ,XDMAC channel 13 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 12. " [12] ,XDMAC channel 12 read write suspend" "No effect,Suspend"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,XDMAC channel 11 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 10. " [10] ,XDMAC channel 10 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 9. " [9] ,XDMAC channel 9 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 8. " [8] ,XDMAC channel 8 read write suspend" "No effect,Suspend"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,XDMAC channel 7 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 6. " [6] ,XDMAC channel 6 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 5. " [5] ,XDMAC channel 5 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 4. " [4] ,XDMAC channel 4 read write suspend" "No effect,Suspend"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,XDMAC channel 3 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 2. " [2] ,XDMAC channel 2 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 1. " [1] ,XDMAC channel 1 read write suspend" "No effect,Suspend"
|
|
bitfld.long 0x00 0. " [0] ,XDMAC channel 0 read write suspend" "No effect,Suspend"
|
|
endif
|
|
line.long 0x04 "GRWR,Global Channel Read Write Resume Register"
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
bitfld.long 0x04 23. " RWR[23] ,XDMAC channel 23 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 22. " [22] ,XDMAC channel 22 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 21. " [21] ,XDMAC channel 21 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 20. " [20] ,XDMAC channel 20 read write resume" "No effect,Resume"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,XDMAC channel 19 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 18. " [18] ,XDMAC channel 18 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 17. " [17] ,XDMAC channel 17 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 16. " [16] ,XDMAC channel 16 read write resume" "No effect,Resume"
|
|
newline
|
|
bitfld.long 0x04 15. " [15] ,XDMAC channel 15 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 14. " [14] ,XDMAC channel 14 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 13. " [13] ,XDMAC channel 13 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 12. " [12] ,XDMAC channel 12 read write resume" "No effect,Resume"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,XDMAC channel 11 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 10. " [10] ,XDMAC channel 10 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 9. " [9] ,XDMAC channel 9 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 8. " [8] ,XDMAC channel 8 read write resume" "No effect,Resume"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,XDMAC channel 7 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 6. " [6] ,XDMAC channel 6 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 5. " [5] ,XDMAC channel 5 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 4. " [4] ,XDMAC channel 4 read write resume" "No effect,Resume"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,XDMAC channel 3 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 2. " [2] ,XDMAC channel 2 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 1. " [1] ,XDMAC channel 1 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 0. " [0] ,XDMAC channel 0 read write resume" "No effect,Resume"
|
|
else
|
|
bitfld.long 0x04 15. " RWR[15] ,XDMAC channel 15 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 14. " [14] ,XDMAC channel 14 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 13. " [13] ,XDMAC channel 13 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 12. " [12] ,XDMAC channel 12 read write resume" "No effect,Resume"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,XDMAC channel 11 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 10. " [10] ,XDMAC channel 10 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 9. " [9] ,XDMAC channel 9 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 8. " [8] ,XDMAC channel 8 read write resume" "No effect,Resume"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,XDMAC channel 7 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 6. " [6] ,XDMAC channel 6 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 5. " [5] ,XDMAC channel 5 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 4. " [4] ,XDMAC channel 4 read write resume" "No effect,Resume"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,XDMAC channel 3 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 2. " [2] ,XDMAC channel 2 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 1. " [1] ,XDMAC channel 1 read write resume" "No effect,Resume"
|
|
bitfld.long 0x04 0. " [0] ,XDMAC channel 0 read write resume" "No effect,Resume"
|
|
endif
|
|
line.long 0x08 "GSWR,Global Channel Software Request Register"
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
bitfld.long 0x08 23. " SWREQ[23] ,XDMAC channel 23 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 22. " [22] ,XDMAC channel 22 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 21. " [21] ,XDMAC channel 21 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 20. " [20] ,XDMAC channel 20 software request bit" "No effect,Request"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,XDMAC channel 19 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 18. " [18] ,XDMAC channel 18 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 17. " [17] ,XDMAC channel 17 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 16. " [16] ,XDMAC channel 16 software request bit" "No effect,Request"
|
|
newline
|
|
bitfld.long 0x08 15. " [15] ,XDMAC channel 15 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 14. " [14] ,XDMAC channel 14 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 13. " [13] ,XDMAC channel 13 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 12. " [12] ,XDMAC channel 12 software request bit" "No effect,Request"
|
|
newline
|
|
bitfld.long 0x08 11. " [11] ,XDMAC channel 11 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 10. " [10] ,XDMAC channel 10 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 9. " [9] ,XDMAC channel 9 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 8. " [8] ,XDMAC channel 8 software request bit" "No effect,Request"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,XDMAC channel 7 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 6. " [6] ,XDMAC channel 6 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 5. " [5] ,XDMAC channel 5 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 4. " [4] ,XDMAC channel 4 software request bit" "No effect,Request"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,XDMAC channel 3 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 2. " [2] ,XDMAC channel 2 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 1. " [1] ,XDMAC channel 1 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 0. " [0] ,XDMAC channel 0 software request bit" "No effect,Request"
|
|
else
|
|
bitfld.long 0x08 15. " SWREQ[15] ,XDMAC channel 15 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 14. " [14] ,XDMAC channel 14 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 13. " [13] ,XDMAC channel 13 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 12. " [12] ,XDMAC channel 12 software request bit" "No effect,Request"
|
|
newline
|
|
bitfld.long 0x08 11. " [11] ,XDMAC channel 11 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 10. " [10] ,XDMAC channel 10 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 9. " [9] ,XDMAC channel 9 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 8. " [8] ,XDMAC channel 8 software request bit" "No effect,Request"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,XDMAC channel 7 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 6. " [6] ,XDMAC channel 6 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 5. " [5] ,XDMAC channel 5 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 4. " [4] ,XDMAC channel 4 software request bit" "No effect,Request"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,XDMAC channel 3 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 2. " [2] ,XDMAC channel 2 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 1. " [1] ,XDMAC channel 1 software request bit" "No effect,Request"
|
|
bitfld.long 0x08 0. " [0] ,XDMAC channel 0 software request bit" "No effect,Request"
|
|
endif
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "GSWS,Global Channel Software Request Status Register"
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
bitfld.long 0x00 23. " SWRS[23] ,XDMAC channel 23 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 22. " [22] ,XDMAC channel 22 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 21. " [21] ,XDMAC channel 21 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 20. " [20] ,XDMAC channel 20 software request status" "Serviced,Pending"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,XDMAC channel 19 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 18. " [18] ,XDMAC channel 18 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 17. " [17] ,XDMAC channel 17 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 16. " [16] ,XDMAC channel 16 software request status" "Serviced,Pending"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,XDMAC channel 15 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 14. " [14] ,XDMAC channel 14 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 13. " [13] ,XDMAC channel 13 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 12. " [12] ,XDMAC channel 12 software request status" "Serviced,Pending"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,XDMAC channel 11 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 10. " [10] ,XDMAC channel 10 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 9. " [9] ,XDMAC channel 9 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 8. " [8] ,XDMAC channel 8 software request status" "Serviced,Pending"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,XDMAC channel 7 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 6. " [6] ,XDMAC channel 6 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 5. " [5] ,XDMAC channel 5 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 4. " [4] ,XDMAC channel 4 software request status" "Serviced,Pending"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,XDMAC channel 3 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 2. " [2] ,XDMAC channel 2 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 1. " [1] ,XDMAC channel 1 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 0. " [0] ,XDMAC channel 0 software request status" "Serviced,Pending"
|
|
else
|
|
bitfld.long 0x00 15. " SWRS[15] ,XDMAC channel 15 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 14. " [14] ,XDMAC channel 14 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 13. " [13] ,XDMAC channel 13 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 12. " [12] ,XDMAC channel 12 software request status" "Serviced,Pending"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,XDMAC channel 11 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 10. " [10] ,XDMAC channel 10 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 9. " [9] ,XDMAC channel 9 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 8. " [8] ,XDMAC channel 8 software request status" "Serviced,Pending"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,XDMAC channel 7 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 6. " [6] ,XDMAC channel 6 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 5. " [5] ,XDMAC channel 5 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 4. " [4] ,XDMAC channel 4 software request status" "Serviced,Pending"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,XDMAC channel 3 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 2. " [2] ,XDMAC channel 2 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 1. " [1] ,XDMAC channel 1 software request status" "Serviced,Pending"
|
|
bitfld.long 0x00 0. " [0] ,XDMAC channel 0 software request status" "Serviced,Pending"
|
|
endif
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "GSWF,Global Channel Software Flush Request Register"
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
bitfld.long 0x00 23. " SWF[23] ,XDMAC channel 23 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 22. " [22] ,XDMAC channel 22 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 21. " [21] ,XDMAC channel 21 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 20. " [20] ,XDMAC channel 20 software flush request" "No effect,Request"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,XDMAC channel 19 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 18. " [18] ,XDMAC channel 18 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 17. " [17] ,XDMAC channel 17 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 16. " [16] ,XDMAC channel 16 software flush request" "No effect,Request"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,XDMAC channel 15 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 14. " [14] ,XDMAC channel 14 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 13. " [13] ,XDMAC channel 13 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 12. " [12] ,XDMAC channel 12 software flush request" "No effect,Request"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,XDMAC channel 11 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 10. " [10] ,XDMAC channel 10 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 9. " [9] ,XDMAC channel 9 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 8. " [8] ,XDMAC channel 8 software flush request" "No effect,Request"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,XDMAC channel 7 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 6. " [6] ,XDMAC channel 6 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 5. " [5] ,XDMAC channel 5 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 4. " [4] ,XDMAC channel 4 software flush request" "No effect,Request"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,XDMAC channel 3 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 2. " [2] ,XDMAC channel 2 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 1. " [1] ,XDMAC channel 1 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 0. " [0] ,XDMAC channel 0 software flush request" "No effect,Request"
|
|
else
|
|
bitfld.long 0x00 15. " SWF[15] ,XDMAC channel 15 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 14. " [14] ,XDMAC channel 14 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 13. " [13] ,XDMAC channel 13 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 12. " [12] ,XDMAC channel 12 software flush request" "No effect,Request"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,XDMAC channel 11 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 10. " [10] ,XDMAC channel 10 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 9. " [9] ,XDMAC channel 9 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 8. " [8] ,XDMAC channel 8 software flush request" "No effect,Request"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,XDMAC channel 7 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 6. " [6] ,XDMAC channel 6 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 5. " [5] ,XDMAC channel 5 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 4. " [4] ,XDMAC channel 4 software flush request" "No effect,Request"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,XDMAC channel 3 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 2. " [2] ,XDMAC channel 2 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 1. " [1] ,XDMAC channel 1 software flush request" "No effect,Request"
|
|
bitfld.long 0x00 0. " [0] ,XDMAC channel 0 software flush request" "No effect,Request"
|
|
endif
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
tree "Channel 0 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x0*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM0_SET/CLR,Channel 0 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS0,Channel 0 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA0,Channel 0 Source Address Register"
|
|
line.long 0x04 "CDA0,Channel 0 Destination Address Register"
|
|
line.long 0x08 "CNDA0,Channel 0 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 0 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 0 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC0,Channel 0 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 0 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 0 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 0 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 0 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC0,Channel 0 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 0 microblock length"
|
|
line.long 0x14 "CBC0,Channel 0 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 0 block length"
|
|
line.long 0x18 "CC0,Channel 0 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 0 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 0 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 0 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 0 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 0 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 0 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 0 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 0 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 0 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 0 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 0 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 0 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 0 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 0 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 0 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 0 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 0 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 0 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x0*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP0,Channel 0 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 0 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 0 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP0,Channel 0 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS0,Channel 0 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 0 source microblock stride"
|
|
line.long 0x04 "CDUS0,Channel 0 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 0 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x1*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM1_SET/CLR,Channel 1 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS1,Channel 1 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA1,Channel 1 Source Address Register"
|
|
line.long 0x04 "CDA1,Channel 1 Destination Address Register"
|
|
line.long 0x08 "CNDA1,Channel 1 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 1 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 1 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC1,Channel 1 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 1 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 1 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 1 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 1 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC1,Channel 1 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 1 microblock length"
|
|
line.long 0x14 "CBC1,Channel 1 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 1 block length"
|
|
line.long 0x18 "CC1,Channel 1 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 1 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 1 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 1 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 1 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 1 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 1 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 1 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 1 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 1 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 1 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 1 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 1 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 1 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 1 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 1 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 1 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 1 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 1 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x1*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP1,Channel 1 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 1 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 1 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP1,Channel 1 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS1,Channel 1 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 1 source microblock stride"
|
|
line.long 0x04 "CDUS1,Channel 1 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 1 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 2 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x2*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM2_SET/CLR,Channel 2 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS2,Channel 2 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA2,Channel 2 Source Address Register"
|
|
line.long 0x04 "CDA2,Channel 2 Destination Address Register"
|
|
line.long 0x08 "CNDA2,Channel 2 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 2 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 2 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC2,Channel 2 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 2 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 2 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 2 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 2 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC2,Channel 2 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 2 microblock length"
|
|
line.long 0x14 "CBC2,Channel 2 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 2 block length"
|
|
line.long 0x18 "CC2,Channel 2 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 2 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 2 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 2 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 2 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 2 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 2 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 2 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 2 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 2 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 2 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 2 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 2 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 2 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 2 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 2 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 2 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 2 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 2 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x2*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP2,Channel 2 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 2 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 2 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP2,Channel 2 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS2,Channel 2 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 2 source microblock stride"
|
|
line.long 0x04 "CDUS2,Channel 2 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 2 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 3 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x3*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM3_SET/CLR,Channel 3 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS3,Channel 3 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA3,Channel 3 Source Address Register"
|
|
line.long 0x04 "CDA3,Channel 3 Destination Address Register"
|
|
line.long 0x08 "CNDA3,Channel 3 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 3 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 3 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC3,Channel 3 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 3 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 3 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 3 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 3 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC3,Channel 3 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 3 microblock length"
|
|
line.long 0x14 "CBC3,Channel 3 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 3 block length"
|
|
line.long 0x18 "CC3,Channel 3 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 3 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 3 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 3 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 3 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 3 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 3 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 3 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 3 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 3 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 3 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 3 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 3 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 3 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 3 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 3 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 3 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 3 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 3 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x3*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP3,Channel 3 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 3 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 3 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP3,Channel 3 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS3,Channel 3 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 3 source microblock stride"
|
|
line.long 0x04 "CDUS3,Channel 3 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 3 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 4 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x4*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM4_SET/CLR,Channel 4 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS4,Channel 4 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA4,Channel 4 Source Address Register"
|
|
line.long 0x04 "CDA4,Channel 4 Destination Address Register"
|
|
line.long 0x08 "CNDA4,Channel 4 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 4 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 4 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC4,Channel 4 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 4 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 4 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 4 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 4 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC4,Channel 4 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 4 microblock length"
|
|
line.long 0x14 "CBC4,Channel 4 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 4 block length"
|
|
line.long 0x18 "CC4,Channel 4 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 4 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 4 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 4 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 4 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 4 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 4 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 4 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 4 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 4 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 4 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 4 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 4 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 4 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 4 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 4 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 4 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 4 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 4 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x4*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP4,Channel 4 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 4 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 4 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP4,Channel 4 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS4,Channel 4 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 4 source microblock stride"
|
|
line.long 0x04 "CDUS4,Channel 4 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 4 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 5 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x5*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM5_SET/CLR,Channel 5 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS5,Channel 5 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA5,Channel 5 Source Address Register"
|
|
line.long 0x04 "CDA5,Channel 5 Destination Address Register"
|
|
line.long 0x08 "CNDA5,Channel 5 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 5 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 5 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC5,Channel 5 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 5 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 5 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 5 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 5 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC5,Channel 5 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 5 microblock length"
|
|
line.long 0x14 "CBC5,Channel 5 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 5 block length"
|
|
line.long 0x18 "CC5,Channel 5 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 5 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 5 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 5 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 5 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 5 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 5 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 5 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 5 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 5 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 5 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 5 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 5 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 5 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 5 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 5 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 5 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 5 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 5 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x5*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP5,Channel 5 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 5 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 5 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP5,Channel 5 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS5,Channel 5 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 5 source microblock stride"
|
|
line.long 0x04 "CDUS5,Channel 5 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 5 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 6 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x6*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM6_SET/CLR,Channel 6 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS6,Channel 6 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA6,Channel 6 Source Address Register"
|
|
line.long 0x04 "CDA6,Channel 6 Destination Address Register"
|
|
line.long 0x08 "CNDA6,Channel 6 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 6 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 6 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC6,Channel 6 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 6 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 6 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 6 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 6 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC6,Channel 6 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 6 microblock length"
|
|
line.long 0x14 "CBC6,Channel 6 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 6 block length"
|
|
line.long 0x18 "CC6,Channel 6 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 6 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 6 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 6 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 6 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 6 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 6 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 6 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 6 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 6 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 6 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 6 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 6 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 6 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 6 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 6 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 6 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 6 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 6 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x6*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP6,Channel 6 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 6 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 6 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP6,Channel 6 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS6,Channel 6 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 6 source microblock stride"
|
|
line.long 0x04 "CDUS6,Channel 6 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 6 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 7 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x7*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM7_SET/CLR,Channel 7 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS7,Channel 7 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA7,Channel 7 Source Address Register"
|
|
line.long 0x04 "CDA7,Channel 7 Destination Address Register"
|
|
line.long 0x08 "CNDA7,Channel 7 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 7 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 7 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC7,Channel 7 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 7 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 7 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 7 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 7 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC7,Channel 7 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 7 microblock length"
|
|
line.long 0x14 "CBC7,Channel 7 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 7 block length"
|
|
line.long 0x18 "CC7,Channel 7 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 7 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 7 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 7 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 7 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 7 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 7 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 7 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 7 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 7 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 7 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 7 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 7 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 7 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 7 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 7 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 7 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 7 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 7 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x7*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP7,Channel 7 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 7 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 7 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP7,Channel 7 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS7,Channel 7 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 7 source microblock stride"
|
|
line.long 0x04 "CDUS7,Channel 7 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 7 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 8 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x8*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM8_SET/CLR,Channel 8 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS8,Channel 8 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA8,Channel 8 Source Address Register"
|
|
line.long 0x04 "CDA8,Channel 8 Destination Address Register"
|
|
line.long 0x08 "CNDA8,Channel 8 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 8 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 8 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC8,Channel 8 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 8 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 8 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 8 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 8 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC8,Channel 8 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 8 microblock length"
|
|
line.long 0x14 "CBC8,Channel 8 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 8 block length"
|
|
line.long 0x18 "CC8,Channel 8 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 8 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 8 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 8 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 8 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 8 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 8 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 8 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 8 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 8 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 8 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 8 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 8 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 8 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 8 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 8 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 8 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 8 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 8 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x8*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP8,Channel 8 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 8 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 8 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP8,Channel 8 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS8,Channel 8 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 8 source microblock stride"
|
|
line.long 0x04 "CDUS8,Channel 8 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 8 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 9 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x9*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM9_SET/CLR,Channel 9 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS9,Channel 9 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA9,Channel 9 Source Address Register"
|
|
line.long 0x04 "CDA9,Channel 9 Destination Address Register"
|
|
line.long 0x08 "CNDA9,Channel 9 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 9 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 9 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC9,Channel 9 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 9 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 9 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 9 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 9 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC9,Channel 9 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 9 microblock length"
|
|
line.long 0x14 "CBC9,Channel 9 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 9 block length"
|
|
line.long 0x18 "CC9,Channel 9 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 9 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 9 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 9 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 9 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 9 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 9 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 9 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 9 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 9 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 9 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 9 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 9 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 9 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 9 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 9 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 9 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 9 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 9 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x9*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP9,Channel 9 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 9 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 9 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP9,Channel 9 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS9,Channel 9 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 9 source microblock stride"
|
|
line.long 0x04 "CDUS9,Channel 9 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 9 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 10 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0xA*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM10_SET/CLR,Channel 10 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS10,Channel 10 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA10,Channel 10 Source Address Register"
|
|
line.long 0x04 "CDA10,Channel 10 Destination Address Register"
|
|
line.long 0x08 "CNDA10,Channel 10 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 10 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 10 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC10,Channel 10 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 10 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 10 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 10 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 10 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC10,Channel 10 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 10 microblock length"
|
|
line.long 0x14 "CBC10,Channel 10 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 10 block length"
|
|
line.long 0x18 "CC10,Channel 10 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 10 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 10 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 10 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 10 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 10 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 10 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 10 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 10 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 10 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 10 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 10 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 10 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 10 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 10 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 10 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 10 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 10 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 10 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0xA*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP10,Channel 10 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 10 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 10 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP10,Channel 10 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS10,Channel 10 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 10 source microblock stride"
|
|
line.long 0x04 "CDUS10,Channel 10 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 10 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 11 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0xB*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM11_SET/CLR,Channel 11 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS11,Channel 11 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA11,Channel 11 Source Address Register"
|
|
line.long 0x04 "CDA11,Channel 11 Destination Address Register"
|
|
line.long 0x08 "CNDA11,Channel 11 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 11 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 11 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC11,Channel 11 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 11 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 11 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 11 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 11 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC11,Channel 11 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 11 microblock length"
|
|
line.long 0x14 "CBC11,Channel 11 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 11 block length"
|
|
line.long 0x18 "CC11,Channel 11 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 11 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 11 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 11 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 11 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 11 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 11 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 11 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 11 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 11 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 11 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 11 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 11 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 11 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 11 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 11 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 11 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 11 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 11 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0xB*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP11,Channel 11 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 11 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 11 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP11,Channel 11 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS11,Channel 11 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 11 source microblock stride"
|
|
line.long 0x04 "CDUS11,Channel 11 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 11 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 12 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0xC*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM12_SET/CLR,Channel 12 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS12,Channel 12 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA12,Channel 12 Source Address Register"
|
|
line.long 0x04 "CDA12,Channel 12 Destination Address Register"
|
|
line.long 0x08 "CNDA12,Channel 12 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 12 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 12 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC12,Channel 12 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 12 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 12 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 12 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 12 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC12,Channel 12 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 12 microblock length"
|
|
line.long 0x14 "CBC12,Channel 12 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 12 block length"
|
|
line.long 0x18 "CC12,Channel 12 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 12 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 12 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 12 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 12 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 12 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 12 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 12 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 12 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 12 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 12 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 12 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 12 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 12 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 12 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 12 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 12 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 12 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 12 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0xC*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP12,Channel 12 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 12 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 12 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP12,Channel 12 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS12,Channel 12 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 12 source microblock stride"
|
|
line.long 0x04 "CDUS12,Channel 12 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 12 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 13 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0xD*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM13_SET/CLR,Channel 13 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS13,Channel 13 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA13,Channel 13 Source Address Register"
|
|
line.long 0x04 "CDA13,Channel 13 Destination Address Register"
|
|
line.long 0x08 "CNDA13,Channel 13 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 13 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 13 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC13,Channel 13 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 13 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 13 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 13 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 13 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC13,Channel 13 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 13 microblock length"
|
|
line.long 0x14 "CBC13,Channel 13 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 13 block length"
|
|
line.long 0x18 "CC13,Channel 13 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 13 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 13 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 13 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 13 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 13 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 13 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 13 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 13 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 13 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 13 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 13 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 13 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 13 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 13 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 13 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 13 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 13 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 13 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0xD*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP13,Channel 13 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 13 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 13 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP13,Channel 13 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS13,Channel 13 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 13 source microblock stride"
|
|
line.long 0x04 "CDUS13,Channel 13 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 13 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 14 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0xE*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM14_SET/CLR,Channel 14 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS14,Channel 14 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA14,Channel 14 Source Address Register"
|
|
line.long 0x04 "CDA14,Channel 14 Destination Address Register"
|
|
line.long 0x08 "CNDA14,Channel 14 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 14 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 14 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC14,Channel 14 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 14 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 14 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 14 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 14 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC14,Channel 14 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 14 microblock length"
|
|
line.long 0x14 "CBC14,Channel 14 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 14 block length"
|
|
line.long 0x18 "CC14,Channel 14 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 14 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 14 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 14 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 14 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 14 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 14 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 14 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 14 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 14 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 14 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 14 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 14 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 14 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 14 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 14 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 14 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 14 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 14 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0xE*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP14,Channel 14 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 14 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 14 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP14,Channel 14 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS14,Channel 14 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 14 source microblock stride"
|
|
line.long 0x04 "CDUS14,Channel 14 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 14 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 15 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0xF*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM15_SET/CLR,Channel 15 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS15,Channel 15 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA15,Channel 15 Source Address Register"
|
|
line.long 0x04 "CDA15,Channel 15 Destination Address Register"
|
|
line.long 0x08 "CNDA15,Channel 15 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 15 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 15 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC15,Channel 15 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 15 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 15 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 15 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 15 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC15,Channel 15 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 15 microblock length"
|
|
line.long 0x14 "CBC15,Channel 15 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 15 block length"
|
|
line.long 0x18 "CC15,Channel 15 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 15 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 15 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 15 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 15 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 15 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 15 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 15 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 15 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 15 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 15 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 15 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 15 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 15 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 15 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 15 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 15 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 15 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 15 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0xF*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP15,Channel 15 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 15 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 15 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP15,Channel 15 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS15,Channel 15 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 15 source microblock stride"
|
|
line.long 0x04 "CDUS15,Channel 15 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 15 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 16 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x10*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM16_SET/CLR,Channel 16 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS16,Channel 16 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA16,Channel 16 Source Address Register"
|
|
line.long 0x04 "CDA16,Channel 16 Destination Address Register"
|
|
line.long 0x08 "CNDA16,Channel 16 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 16 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 16 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC16,Channel 16 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 16 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 16 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 16 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 16 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC16,Channel 16 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 16 microblock length"
|
|
line.long 0x14 "CBC16,Channel 16 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 16 block length"
|
|
line.long 0x18 "CC16,Channel 16 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 16 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 16 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 16 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 16 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 16 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 16 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 16 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 16 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 16 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 16 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 16 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 16 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 16 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 16 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 16 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 16 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 16 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 16 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x10*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP16,Channel 16 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 16 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 16 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP16,Channel 16 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS16,Channel 16 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 16 source microblock stride"
|
|
line.long 0x04 "CDUS16,Channel 16 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 16 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 17 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x11*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM17_SET/CLR,Channel 17 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS17,Channel 17 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA17,Channel 17 Source Address Register"
|
|
line.long 0x04 "CDA17,Channel 17 Destination Address Register"
|
|
line.long 0x08 "CNDA17,Channel 17 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 17 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 17 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC17,Channel 17 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 17 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 17 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 17 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 17 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC17,Channel 17 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 17 microblock length"
|
|
line.long 0x14 "CBC17,Channel 17 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 17 block length"
|
|
line.long 0x18 "CC17,Channel 17 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 17 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 17 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 17 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 17 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 17 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 17 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 17 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 17 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 17 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 17 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 17 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 17 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 17 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 17 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 17 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 17 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 17 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 17 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x11*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP17,Channel 17 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 17 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 17 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP17,Channel 17 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS17,Channel 17 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 17 source microblock stride"
|
|
line.long 0x04 "CDUS17,Channel 17 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 17 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 18 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x12*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM18_SET/CLR,Channel 18 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS18,Channel 18 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA18,Channel 18 Source Address Register"
|
|
line.long 0x04 "CDA18,Channel 18 Destination Address Register"
|
|
line.long 0x08 "CNDA18,Channel 18 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 18 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 18 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC18,Channel 18 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 18 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 18 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 18 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 18 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC18,Channel 18 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 18 microblock length"
|
|
line.long 0x14 "CBC18,Channel 18 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 18 block length"
|
|
line.long 0x18 "CC18,Channel 18 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 18 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 18 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 18 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 18 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 18 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 18 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 18 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 18 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 18 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 18 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 18 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 18 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 18 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 18 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 18 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 18 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 18 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 18 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x12*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP18,Channel 18 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 18 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 18 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP18,Channel 18 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS18,Channel 18 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 18 source microblock stride"
|
|
line.long 0x04 "CDUS18,Channel 18 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 18 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 19 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x13*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM19_SET/CLR,Channel 19 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS19,Channel 19 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA19,Channel 19 Source Address Register"
|
|
line.long 0x04 "CDA19,Channel 19 Destination Address Register"
|
|
line.long 0x08 "CNDA19,Channel 19 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 19 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 19 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC19,Channel 19 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 19 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 19 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 19 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 19 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC19,Channel 19 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 19 microblock length"
|
|
line.long 0x14 "CBC19,Channel 19 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 19 block length"
|
|
line.long 0x18 "CC19,Channel 19 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 19 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 19 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 19 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 19 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 19 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 19 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 19 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 19 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 19 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 19 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 19 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 19 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 19 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 19 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 19 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 19 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 19 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 19 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x13*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP19,Channel 19 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 19 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 19 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP19,Channel 19 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS19,Channel 19 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 19 source microblock stride"
|
|
line.long 0x04 "CDUS19,Channel 19 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 19 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 20 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x14*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM20_SET/CLR,Channel 20 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS20,Channel 20 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA20,Channel 20 Source Address Register"
|
|
line.long 0x04 "CDA20,Channel 20 Destination Address Register"
|
|
line.long 0x08 "CNDA20,Channel 20 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 20 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 20 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC20,Channel 20 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 20 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 20 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 20 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 20 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC20,Channel 20 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 20 microblock length"
|
|
line.long 0x14 "CBC20,Channel 20 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 20 block length"
|
|
line.long 0x18 "CC20,Channel 20 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 20 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 20 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 20 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 20 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 20 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 20 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 20 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 20 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 20 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 20 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 20 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 20 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 20 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 20 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 20 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 20 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 20 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 20 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x14*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP20,Channel 20 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 20 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 20 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP20,Channel 20 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS20,Channel 20 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 20 source microblock stride"
|
|
line.long 0x04 "CDUS20,Channel 20 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 20 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 21 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x15*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM21_SET/CLR,Channel 21 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS21,Channel 21 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA21,Channel 21 Source Address Register"
|
|
line.long 0x04 "CDA21,Channel 21 Destination Address Register"
|
|
line.long 0x08 "CNDA21,Channel 21 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 21 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 21 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC21,Channel 21 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 21 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 21 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 21 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 21 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC21,Channel 21 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 21 microblock length"
|
|
line.long 0x14 "CBC21,Channel 21 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 21 block length"
|
|
line.long 0x18 "CC21,Channel 21 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 21 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 21 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 21 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 21 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 21 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 21 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 21 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 21 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 21 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 21 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 21 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 21 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 21 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 21 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 21 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 21 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 21 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 21 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x15*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP21,Channel 21 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 21 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 21 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP21,Channel 21 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS21,Channel 21 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 21 source microblock stride"
|
|
line.long 0x04 "CDUS21,Channel 21 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 21 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 22 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x16*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM22_SET/CLR,Channel 22 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS22,Channel 22 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA22,Channel 22 Source Address Register"
|
|
line.long 0x04 "CDA22,Channel 22 Destination Address Register"
|
|
line.long 0x08 "CNDA22,Channel 22 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 22 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 22 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC22,Channel 22 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 22 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 22 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 22 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 22 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC22,Channel 22 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 22 microblock length"
|
|
line.long 0x14 "CBC22,Channel 22 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 22 block length"
|
|
line.long 0x18 "CC22,Channel 22 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 22 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 22 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 22 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 22 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 22 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 22 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 22 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 22 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 22 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 22 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 22 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 22 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 22 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 22 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 22 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 22 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 22 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 22 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x16*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP22,Channel 22 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 22 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 22 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP22,Channel 22 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS22,Channel 22 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 22 source microblock stride"
|
|
line.long 0x04 "CDUS22,Channel 22 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 22 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 23 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x17*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM23_SET/CLR,Channel 23 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS23,Channel 23 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA23,Channel 23 Source Address Register"
|
|
line.long 0x04 "CDA23,Channel 23 Destination Address Register"
|
|
line.long 0x08 "CNDA23,Channel 23 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 23 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 23 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC23,Channel 23 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 23 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 23 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 23 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 23 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC23,Channel 23 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 23 microblock length"
|
|
line.long 0x14 "CBC23,Channel 23 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 23 block length"
|
|
line.long 0x18 "CC23,Channel 23 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 23 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 23 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 23 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 23 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 23 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 23 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 23 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 23 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 23 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 23 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 23 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 23 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 23 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 23 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 23 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 23 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 23 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 23 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x17*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP23,Channel 23 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 23 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 23 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP23,Channel 23 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS23,Channel 23 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 23 source microblock stride"
|
|
line.long 0x04 "CDUS23,Channel 23 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 23 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "Channel 0 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x0*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM0_SET/CLR,Channel 0 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS0,Channel 0 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA0,Channel 0 Source Address Register"
|
|
line.long 0x04 "CDA0,Channel 0 Destination Address Register"
|
|
line.long 0x08 "CNDA0,Channel 0 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 0 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 0 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC0,Channel 0 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 0 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 0 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 0 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 0 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC0,Channel 0 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 0 microblock length"
|
|
line.long 0x14 "CBC0,Channel 0 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 0 block length"
|
|
line.long 0x18 "CC0,Channel 0 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 0 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 0 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 0 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 0 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 0 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 0 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 0 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 0 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 0 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 0 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 0 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 0 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 0 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 0 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 0 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 0 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 0 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 0 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x0*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP0,Channel 0 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 0 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 0 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP0,Channel 0 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS0,Channel 0 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 0 source microblock stride"
|
|
line.long 0x04 "CDUS0,Channel 0 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 0 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 1 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x1*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM1_SET/CLR,Channel 1 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS1,Channel 1 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA1,Channel 1 Source Address Register"
|
|
line.long 0x04 "CDA1,Channel 1 Destination Address Register"
|
|
line.long 0x08 "CNDA1,Channel 1 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 1 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 1 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC1,Channel 1 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 1 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 1 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 1 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 1 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC1,Channel 1 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 1 microblock length"
|
|
line.long 0x14 "CBC1,Channel 1 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 1 block length"
|
|
line.long 0x18 "CC1,Channel 1 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 1 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 1 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 1 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 1 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 1 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 1 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 1 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 1 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 1 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 1 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 1 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 1 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 1 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 1 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 1 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 1 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 1 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 1 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x1*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP1,Channel 1 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 1 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 1 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP1,Channel 1 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS1,Channel 1 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 1 source microblock stride"
|
|
line.long 0x04 "CDUS1,Channel 1 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 1 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 2 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x2*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM2_SET/CLR,Channel 2 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS2,Channel 2 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA2,Channel 2 Source Address Register"
|
|
line.long 0x04 "CDA2,Channel 2 Destination Address Register"
|
|
line.long 0x08 "CNDA2,Channel 2 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 2 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 2 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC2,Channel 2 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 2 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 2 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 2 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 2 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC2,Channel 2 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 2 microblock length"
|
|
line.long 0x14 "CBC2,Channel 2 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 2 block length"
|
|
line.long 0x18 "CC2,Channel 2 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 2 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 2 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 2 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 2 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 2 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 2 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 2 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 2 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 2 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 2 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 2 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 2 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 2 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 2 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 2 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 2 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 2 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 2 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x2*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP2,Channel 2 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 2 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 2 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP2,Channel 2 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS2,Channel 2 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 2 source microblock stride"
|
|
line.long 0x04 "CDUS2,Channel 2 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 2 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 3 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x3*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM3_SET/CLR,Channel 3 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS3,Channel 3 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA3,Channel 3 Source Address Register"
|
|
line.long 0x04 "CDA3,Channel 3 Destination Address Register"
|
|
line.long 0x08 "CNDA3,Channel 3 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 3 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 3 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC3,Channel 3 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 3 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 3 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 3 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 3 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC3,Channel 3 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 3 microblock length"
|
|
line.long 0x14 "CBC3,Channel 3 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 3 block length"
|
|
line.long 0x18 "CC3,Channel 3 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 3 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 3 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 3 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 3 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 3 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 3 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 3 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 3 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 3 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 3 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 3 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 3 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 3 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 3 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 3 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 3 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 3 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 3 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x3*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP3,Channel 3 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 3 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 3 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP3,Channel 3 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS3,Channel 3 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 3 source microblock stride"
|
|
line.long 0x04 "CDUS3,Channel 3 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 3 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 4 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x4*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM4_SET/CLR,Channel 4 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS4,Channel 4 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA4,Channel 4 Source Address Register"
|
|
line.long 0x04 "CDA4,Channel 4 Destination Address Register"
|
|
line.long 0x08 "CNDA4,Channel 4 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 4 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 4 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC4,Channel 4 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 4 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 4 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 4 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 4 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC4,Channel 4 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 4 microblock length"
|
|
line.long 0x14 "CBC4,Channel 4 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 4 block length"
|
|
line.long 0x18 "CC4,Channel 4 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 4 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 4 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 4 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 4 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 4 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 4 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 4 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 4 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 4 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 4 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 4 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 4 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 4 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 4 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 4 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 4 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 4 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 4 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x4*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP4,Channel 4 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 4 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 4 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP4,Channel 4 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS4,Channel 4 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 4 source microblock stride"
|
|
line.long 0x04 "CDUS4,Channel 4 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 4 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 5 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x5*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM5_SET/CLR,Channel 5 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS5,Channel 5 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA5,Channel 5 Source Address Register"
|
|
line.long 0x04 "CDA5,Channel 5 Destination Address Register"
|
|
line.long 0x08 "CNDA5,Channel 5 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 5 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 5 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC5,Channel 5 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 5 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 5 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 5 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 5 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC5,Channel 5 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 5 microblock length"
|
|
line.long 0x14 "CBC5,Channel 5 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 5 block length"
|
|
line.long 0x18 "CC5,Channel 5 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 5 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 5 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 5 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 5 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 5 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 5 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 5 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 5 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 5 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 5 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 5 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 5 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 5 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 5 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 5 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 5 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 5 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 5 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x5*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP5,Channel 5 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 5 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 5 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP5,Channel 5 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS5,Channel 5 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 5 source microblock stride"
|
|
line.long 0x04 "CDUS5,Channel 5 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 5 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 6 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x6*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM6_SET/CLR,Channel 6 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS6,Channel 6 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA6,Channel 6 Source Address Register"
|
|
line.long 0x04 "CDA6,Channel 6 Destination Address Register"
|
|
line.long 0x08 "CNDA6,Channel 6 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 6 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 6 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC6,Channel 6 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 6 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 6 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 6 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 6 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC6,Channel 6 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 6 microblock length"
|
|
line.long 0x14 "CBC6,Channel 6 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 6 block length"
|
|
line.long 0x18 "CC6,Channel 6 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 6 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 6 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 6 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 6 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 6 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 6 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 6 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 6 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 6 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 6 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 6 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 6 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 6 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 6 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 6 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 6 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 6 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 6 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x6*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP6,Channel 6 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 6 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 6 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP6,Channel 6 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS6,Channel 6 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 6 source microblock stride"
|
|
line.long 0x04 "CDUS6,Channel 6 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 6 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 7 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x7*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM7_SET/CLR,Channel 7 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS7,Channel 7 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA7,Channel 7 Source Address Register"
|
|
line.long 0x04 "CDA7,Channel 7 Destination Address Register"
|
|
line.long 0x08 "CNDA7,Channel 7 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 7 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 7 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC7,Channel 7 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 7 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 7 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 7 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 7 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC7,Channel 7 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 7 microblock length"
|
|
line.long 0x14 "CBC7,Channel 7 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 7 block length"
|
|
line.long 0x18 "CC7,Channel 7 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 7 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 7 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 7 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 7 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 7 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 7 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 7 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 7 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 7 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 7 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 7 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 7 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 7 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 7 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 7 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 7 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 7 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 7 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x7*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP7,Channel 7 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 7 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 7 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP7,Channel 7 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS7,Channel 7 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 7 source microblock stride"
|
|
line.long 0x04 "CDUS7,Channel 7 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 7 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 8 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x8*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM8_SET/CLR,Channel 8 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS8,Channel 8 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA8,Channel 8 Source Address Register"
|
|
line.long 0x04 "CDA8,Channel 8 Destination Address Register"
|
|
line.long 0x08 "CNDA8,Channel 8 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 8 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 8 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC8,Channel 8 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 8 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 8 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 8 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 8 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC8,Channel 8 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 8 microblock length"
|
|
line.long 0x14 "CBC8,Channel 8 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 8 block length"
|
|
line.long 0x18 "CC8,Channel 8 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 8 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 8 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 8 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 8 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 8 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 8 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 8 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 8 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 8 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 8 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 8 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 8 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 8 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 8 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 8 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 8 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 8 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 8 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x8*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP8,Channel 8 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 8 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 8 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP8,Channel 8 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS8,Channel 8 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 8 source microblock stride"
|
|
line.long 0x04 "CDUS8,Channel 8 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 8 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 9 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0x9*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM9_SET/CLR,Channel 9 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS9,Channel 9 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA9,Channel 9 Source Address Register"
|
|
line.long 0x04 "CDA9,Channel 9 Destination Address Register"
|
|
line.long 0x08 "CNDA9,Channel 9 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 9 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 9 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC9,Channel 9 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 9 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 9 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 9 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 9 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC9,Channel 9 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 9 microblock length"
|
|
line.long 0x14 "CBC9,Channel 9 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 9 block length"
|
|
line.long 0x18 "CC9,Channel 9 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 9 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 9 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 9 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 9 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 9 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 9 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 9 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 9 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 9 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 9 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 9 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 9 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 9 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 9 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 9 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 9 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 9 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 9 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0x9*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP9,Channel 9 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 9 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 9 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP9,Channel 9 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS9,Channel 9 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 9 source microblock stride"
|
|
line.long 0x04 "CDUS9,Channel 9 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 9 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 10 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0xA*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM10_SET/CLR,Channel 10 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS10,Channel 10 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA10,Channel 10 Source Address Register"
|
|
line.long 0x04 "CDA10,Channel 10 Destination Address Register"
|
|
line.long 0x08 "CNDA10,Channel 10 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 10 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 10 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC10,Channel 10 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 10 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 10 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 10 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 10 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC10,Channel 10 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 10 microblock length"
|
|
line.long 0x14 "CBC10,Channel 10 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 10 block length"
|
|
line.long 0x18 "CC10,Channel 10 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 10 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 10 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 10 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 10 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 10 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 10 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 10 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 10 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 10 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 10 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 10 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 10 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 10 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 10 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 10 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 10 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 10 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 10 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0xA*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP10,Channel 10 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 10 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 10 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP10,Channel 10 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS10,Channel 10 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 10 source microblock stride"
|
|
line.long 0x04 "CDUS10,Channel 10 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 10 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 11 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0xB*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM11_SET/CLR,Channel 11 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS11,Channel 11 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA11,Channel 11 Source Address Register"
|
|
line.long 0x04 "CDA11,Channel 11 Destination Address Register"
|
|
line.long 0x08 "CNDA11,Channel 11 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 11 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 11 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC11,Channel 11 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 11 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 11 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 11 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 11 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC11,Channel 11 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 11 microblock length"
|
|
line.long 0x14 "CBC11,Channel 11 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 11 block length"
|
|
line.long 0x18 "CC11,Channel 11 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 11 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 11 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 11 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 11 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 11 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 11 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 11 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 11 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 11 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 11 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 11 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 11 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 11 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 11 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 11 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 11 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 11 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 11 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0xB*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP11,Channel 11 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 11 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 11 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP11,Channel 11 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS11,Channel 11 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 11 source microblock stride"
|
|
line.long 0x04 "CDUS11,Channel 11 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 11 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 12 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0xC*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM12_SET/CLR,Channel 12 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS12,Channel 12 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA12,Channel 12 Source Address Register"
|
|
line.long 0x04 "CDA12,Channel 12 Destination Address Register"
|
|
line.long 0x08 "CNDA12,Channel 12 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 12 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 12 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC12,Channel 12 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 12 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 12 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 12 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 12 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC12,Channel 12 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 12 microblock length"
|
|
line.long 0x14 "CBC12,Channel 12 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 12 block length"
|
|
line.long 0x18 "CC12,Channel 12 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 12 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 12 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 12 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 12 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 12 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 12 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 12 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 12 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 12 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 12 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 12 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 12 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 12 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 12 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 12 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 12 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 12 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 12 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0xC*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP12,Channel 12 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 12 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 12 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP12,Channel 12 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS12,Channel 12 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 12 source microblock stride"
|
|
line.long 0x04 "CDUS12,Channel 12 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 12 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 13 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0xD*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM13_SET/CLR,Channel 13 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS13,Channel 13 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA13,Channel 13 Source Address Register"
|
|
line.long 0x04 "CDA13,Channel 13 Destination Address Register"
|
|
line.long 0x08 "CNDA13,Channel 13 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 13 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 13 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC13,Channel 13 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 13 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 13 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 13 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 13 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC13,Channel 13 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 13 microblock length"
|
|
line.long 0x14 "CBC13,Channel 13 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 13 block length"
|
|
line.long 0x18 "CC13,Channel 13 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 13 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 13 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 13 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 13 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 13 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 13 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 13 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 13 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 13 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 13 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 13 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 13 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 13 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 13 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 13 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 13 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 13 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 13 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0xD*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP13,Channel 13 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 13 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 13 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP13,Channel 13 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS13,Channel 13 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 13 source microblock stride"
|
|
line.long 0x04 "CDUS13,Channel 13 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 13 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 14 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0xE*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM14_SET/CLR,Channel 14 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS14,Channel 14 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA14,Channel 14 Source Address Register"
|
|
line.long 0x04 "CDA14,Channel 14 Destination Address Register"
|
|
line.long 0x08 "CNDA14,Channel 14 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 14 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 14 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC14,Channel 14 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 14 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 14 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 14 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 14 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC14,Channel 14 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 14 microblock length"
|
|
line.long 0x14 "CBC14,Channel 14 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 14 block length"
|
|
line.long 0x18 "CC14,Channel 14 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 14 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 14 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 14 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 14 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 14 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 14 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 14 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 14 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 14 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 14 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 14 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 14 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 14 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 14 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 14 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 14 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 14 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 14 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0xE*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP14,Channel 14 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 14 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 14 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP14,Channel 14 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS14,Channel 14 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 14 source microblock stride"
|
|
line.long 0x04 "CDUS14,Channel 14 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 14 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Channel 15 Registers"
|
|
width 15.
|
|
base ad:0x40078000+(0xF*0x40)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CIM15_SET/CLR,Channel 15 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ROIM ,Request overflow error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " WBEIM ,Write bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RBEIM ,Read bus error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " FIM ,End of flush interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " DIM ,End of disable interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LIM ,End of linked list interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " BIM ,End of block interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "CIS15,Channel 15 Interrupt Status Register"
|
|
in
|
|
newline
|
|
group.long 0x60++0x1B
|
|
line.long 0x00 "CSA15,Channel 15 Source Address Register"
|
|
line.long 0x04 "CDA15,Channel 15 Destination Address Register"
|
|
line.long 0x08 "CNDA15,Channel 15 Next Descriptor Address Register"
|
|
hexmask.long 0x08 2.--31. 0x04 " NDA ,Channel 15 next descriptor address"
|
|
bitfld.long 0x08 0. " NDAIF ,Channel 15 next descriptor interface" "0,1"
|
|
line.long 0x0C "CNDC15,Channel 15 Next Descriptor Control Register"
|
|
bitfld.long 0x0C 3.--4. " NDVIEW ,Channel 15 next descriptor view" "NDV0,NDV1,NDV2,NDV3"
|
|
bitfld.long 0x0C 2. " NDDUP ,Channel 15 next descriptor destination update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 1. " NDSUP ,Channel 15 next descriptor source update" "Unchanged,Updated"
|
|
bitfld.long 0x0C 0. " NDE ,Channel 15 next descriptor enable" "Disabled,Enabled"
|
|
line.long 0x10 "CUBC15,Channel 15 Microblock Control Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " UBLEN ,Channel 15 microblock length"
|
|
line.long 0x14 "CBC15,Channel 15 Block Control Register"
|
|
hexmask.long.word 0x14 0.--11. 1. " BLEN ,Channel 15 block length"
|
|
line.long 0x18 "CC15,Channel 15 Configuration Register"
|
|
hexmask.long.byte 0x18 24.--30. 1. " PERID ,Channel 15 peripheral identifier"
|
|
rbitfld.long 0x18 23. " WRIP ,Channel 15 write in progress" "Done,In progress"
|
|
rbitfld.long 0x18 22. " RDIP ,Channel 15 read in progress" "Done,In progress"
|
|
rbitfld.long 0x18 21. " INITD ,Channel 15 channel initialization terminated" "Terminated,In progress"
|
|
newline
|
|
bitfld.long 0x18 18.--19. " DAM ,Channel 15 destination addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 16.--17. " SAM ,Channel 15 source addressing mode" "Fixed,Incremented,UBS,UBS DS"
|
|
bitfld.long 0x18 14. " DIF ,Channel 15 destination interface identifier" "AHB IF0,AHB IF1"
|
|
bitfld.long 0x18 13. " SIF ,Channel 15 source interface identifier" "AHB IF0,AHB IF1"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAME7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 15 data width" "8 bits,16 bits,32 bits,32 bits"
|
|
elif cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 15 data width" "8 bits,16 bits,32 bits,?..."
|
|
else
|
|
bitfld.long 0x18 11.--12. " DWIDTH ,Channel 15 data width" "8 bits,16 bits,32 bits,64 bits"
|
|
endif
|
|
bitfld.long 0x18 8.--10. " CSIZE ,Channel 15 chunk size" "1,2,4,8,16,?..."
|
|
bitfld.long 0x18 7. " MEMSET ,Channel 15 fill block of memory" "Normal mode,HW mode"
|
|
bitfld.long 0x18 6. " SWREQ ,Channel 15 software request trigger" "Hardware,Software"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x18 5. " PROT ,Channel 15 protection" "Secured,Unsecured"
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 4. " DSYNC ,Channel 15 synchronization" "PER2MEM,MEM2PER"
|
|
bitfld.long 0x18 1.--2. " MBSIZE ,Channel 15 memory burst size" "Single,Four,Eight,Sixteen"
|
|
bitfld.long 0x18 0. " TYPE ,Channel 15 transfer type" "Self triggered,Synchronized"
|
|
if ((per.l(ad:0x40078000+(0xF*0x40)+0x78)&0x80)==0x00)
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP15,Channel 15 Data Stride Memory Set Pattern Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DDS ,Channel 15 source data stride"
|
|
hexmask.long.word 0x00 0.--15. 1. " SDS ,Channel 15 destination data stride"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CDS_MSP15,Channel 15 Memory Set Pattern Register"
|
|
endif
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "CSUS15,Channel 15 Source Microblock Stride Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " SUBS ,Channel 15 source microblock stride"
|
|
line.long 0x04 "CDUS15,Channel 15 Destination Microblock Stride Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " DUBS ,Channel 15 destination microblock stride"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "ISI (Image Sensor Interface)"
|
|
base ad:0x4004C000
|
|
width 18.
|
|
group.long 0x00++0x23
|
|
line.long 0x00 "CFG1,Configuration 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " SFD ,Start of frame delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SLD ,Start of line delay"
|
|
bitfld.long 0x00 13.--14. " THMASK ,Threshold mask" "BEATS_4,BEATS_8,BEATS_16,?..."
|
|
bitfld.long 0x00 12. " FULL ,Full mode is allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 11. " DISCR ,Disable codec request" "No,Yes"
|
|
bitfld.long 0x00 8.--10. " FRATE ,Frame rate" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. " CRC_SYNC ,Embedded synchronization correction" "Not performed,Performed"
|
|
bitfld.long 0x00 6. " EMB_SYNC ,Embedded synchronization" "HSYNC/VSYNC,SAV/EAV"
|
|
newline
|
|
sif cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 5. " GRAYLE ,Grayscale little endian" "Big,Little"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 4. " PIXCLK_POL ,Pixel clock polarity" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 3. " VSYNC_POL ,Vertical synchronization polarity" "Active high,Active low"
|
|
bitfld.long 0x00 2. " HSYNC_POL ,Horizontal synchronization polarity" "Active high,Active low"
|
|
line.long 0x04 "CFG2,Configuration 2 Register"
|
|
bitfld.long 0x04 30.--31. " RGB_CFG ,Defines RGB pattern when RGB_MODE is set to 1" "Default,Mode1,Mode2,Mode3"
|
|
bitfld.long 0x04 28.--29. " YCC_SWAP ,Defines the YCC image data" "Default,Mode1,Mode2,Mode3"
|
|
hexmask.long.word 0x04 16.--26. 1. " IM_HSIZE ,Horizontal size of the image sensor"
|
|
bitfld.long 0x04 15. " COL_SPACE ,Color space for the image data" "YCbCr,RGB"
|
|
newline
|
|
bitfld.long 0x04 14. " RGB_SWAP ,RGB swap" "D7->R7,D0->R7"
|
|
bitfld.long 0x04 13. " GRAYSCALE ,Grayscale mode format enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RGB_MODE ,RGB input mode" "8:8:8/24 bits,5:6:5/16 bits"
|
|
bitfld.long 0x04 11. " GS_MODE ,Grayscale pixel format mode" "2 px per word,1 px per word"
|
|
newline
|
|
hexmask.long.word 0x04 0.--10. 1. " IM_VSIZE ,Vertical size of the image sensor"
|
|
line.long 0x08 "PSIZE,Preview Size Register"
|
|
hexmask.long.word 0x08 16.--25. 1. " PREV_HSIZE ,Horizontal size for the preview path"
|
|
hexmask.long.word 0x08 0.--9. 1. " PREV_VSIZE ,Vertical size for the preview path"
|
|
line.long 0x0C "PDECF,Preview Decimation Factor Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " DEC_FACTOR ,Decimation factor"
|
|
line.long 0x10 "Y2R_SET0,Color Space Conversion YCrCb To RGB Set 0 Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " C3 ,Color space conversion matrix coefficient C3"
|
|
hexmask.long.byte 0x10 16.--23. 1. " C2 ,Color space conversion matrix coefficient C2"
|
|
hexmask.long.byte 0x10 8.--15. 1. " C1 ,Color space conversion matrix coefficient C1"
|
|
hexmask.long.byte 0x10 0.--7. 1. " C0 ,Color space conversion matrix coefficient C0"
|
|
line.long 0x14 "Y2R_SET1,Color Space Conversion YCrCb To RGB Set 1 Register"
|
|
bitfld.long 0x14 14. " CBOFF ,Color space conversion blue chrominance default offset" "No offset,Offset = 16"
|
|
bitfld.long 0x14 13. " CROFF ,Color space conversion red chrominance default offset" "No offset,Offset = 16"
|
|
bitfld.long 0x14 12. " YOFF ,Color space conversion luminance default offset" "No offset,Offset = 128"
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D3*")||cpuis("ATSAMA5D4*")
|
|
hexmask.long.word 0x14 0.--8. 1. " C4 ,Color space conversion matrix coefficient C4"
|
|
else
|
|
hexmask.long.byte 0x14 0.--7. 1. " C4 ,Color space conversion matrix coefficient C4"
|
|
endif
|
|
line.long 0x18 "R2Y_SET0,Color Space Conversion RGB To YCrCb Set 0 Register"
|
|
bitfld.long 0x18 24. " ROFF ,Color space conversion red component offset" "No offset,Offset = 16"
|
|
hexmask.long.byte 0x18 16.--22. 1. " C2 ,Color space conversion matrix coefficient C2"
|
|
hexmask.long.byte 0x18 8.--14. 1. " C1 ,Color space conversion matrix coefficient C1"
|
|
hexmask.long.byte 0x18 0.--6. 1. " C0 ,Color space conversion matrix coefficient C0"
|
|
line.long 0x1C "R2Y_SET1,Color Space Conversion RGB To YCrCb Set 1 Register"
|
|
bitfld.long 0x1C 24. " GOFF ,Color space conversion green component offset" "No offset,Offset = 128"
|
|
hexmask.long.byte 0x1C 16.--22. 1. " C5 ,Color space conversion matrix coefficient C5"
|
|
hexmask.long.byte 0x1C 8.--14. 1. " C4 ,Color space conversion matrix coefficient C4"
|
|
hexmask.long.byte 0x1C 0.--6. 1. " C3 ,Color space conversion matrix coefficient C3"
|
|
line.long 0x20 "R2Y_SET2,Color Space Conversion RGB To YCrCb Set 2 Register"
|
|
bitfld.long 0x20 24. " BOFF ,Color space conversion blue component offset" "No offset,Offset = 128"
|
|
hexmask.long.byte 0x20 16.--22. 1. " C8 ,Color space conversion matrix coefficient C8"
|
|
hexmask.long.byte 0x20 8.--14. 1. " C7 ,Color space conversion matrix coefficient C7"
|
|
hexmask.long.byte 0x20 0.--6. 1. " C6 ,Color space conversion matrix coefficient C6"
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " CDC ,Codec request" "No request,Request"
|
|
bitfld.long 0x00 2. " SRST ,Software reset request" "No request,Request"
|
|
bitfld.long 0x00 1. " DIS ,Module disable request" "No request,Request"
|
|
bitfld.long 0x00 0. " EN ,Module enable request" "No request,Request"
|
|
newline
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "SR,Status Register"
|
|
in
|
|
newline
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " FR_OVR ,Frame rate overrun" "Masked,Unmasked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " CRC_ERR ,CRC synchronization error" "Masked,Unmasked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " C_OVR ,FIFO codec overflow" "Masked,Unmasked"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " P_OVR ,FIFO preview overflow" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " CXFR_DONE ,Codec DMA transfer interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " PXFR_DONE ,Preview DMA transfer interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " VSYNC ,Vertical synchronization" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " SRST ,Software reset completed" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DIS_DONE ,Module disable operation completed" "Masked,Unmasked"
|
|
group.long 0x40++0x1B
|
|
line.long 0x00 "DMA_CHSR_SET/CLR,Channel Status Set/Clear Register"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " C_CH_S ,Codec DMA channel status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " P_CH_S ,Preview DMA channel status" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_P_ADDR,DMA Preview Base Address Register"
|
|
hexmask.long 0x04 2.--31. 0x04 " P_ADDR ,Preview image base address"
|
|
line.long 0x08 "DMA_P_CTRL,DMA Preview Control Register"
|
|
bitfld.long 0x08 3. " P_DONE ,Preview transfer done" "Not completed,Completed"
|
|
bitfld.long 0x08 2. " P_IEN ,Transfer done flag control" "Enabled,Disabled"
|
|
bitfld.long 0x08 1. " P_WB ,Descriptor writeback control bit" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " P_FETCH ,Descriptor fetch control bit" "Disabled,Enabled"
|
|
line.long 0x0C "DMA_P_DSCR,DMA Preview Descriptor Address Register"
|
|
hexmask.long 0x0C 2.--31. 0x04 " P_DSCR ,Preview descriptor base address"
|
|
line.long 0x10 "DMA_C_ADDR,DMA Codec Base Address Register"
|
|
hexmask.long 0x10 2.--31. 0x04 " C_ADDR ,Codec image base address"
|
|
line.long 0x14 "DMA_C_CTRL,DMA Codec Control Register"
|
|
bitfld.long 0x14 3. " C_DONE ,Codec transfer done" "Not completed,Completed"
|
|
bitfld.long 0x14 2. " C_IEN ,Transfer done flag control disable" "No,Yes"
|
|
bitfld.long 0x14 1. " C_WB ,Descriptor writeback control bit" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " C_FETCH ,Descriptor fetch control bit" "Disabled,Enabled"
|
|
line.long 0x18 "DMA_C_DSCR,DMA Codec Descriptor Address Register"
|
|
hexmask.long 0x18 2.--31. 0x04 " C_DSCR ,Codec descriptor base address"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPCR,Write Protection Control"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protection KEY password"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,Write Protection Status"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "USBHS (USB High-Speed Interface)"
|
|
base ad:0x40038000
|
|
width 6.
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "CTRL,General Control Register"
|
|
bitfld.long 0x00 25. " UIMOD ,USBHS mode" "Host,Device"
|
|
bitfld.long 0x00 15. " USBE ,USBHS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FRZCLK ,Freeze USB clock" "Not frozen,Frozen"
|
|
bitfld.long 0x00 8. " VBUSHWC ,VBUS hardware control disable" "No,Yes"
|
|
bitfld.long 0x00 4. " RDERRE ,Remote device connection error interrupt enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40038000+0x800))&0x2000000)==0x2000000)
|
|
rgroup.long 0x804++0x03
|
|
line.long 0x00 "SR,General Status Register"
|
|
bitfld.long 0x00 14. " CLKUSABLE ,UTMI clock usable" "Not usable,Usable"
|
|
bitfld.long 0x00 12.--13. " SPEED ,Speed status" "FULL_SPEED,HIGH_SPEED,LOW_SPEED,?..."
|
|
else
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "SR,General Status Register"
|
|
rbitfld.long 0x00 14. " CLKUSABLE ,UTMI clock usable" "Not usable,Usable"
|
|
rbitfld.long 0x00 4. " RDERRI ,Remote device connection error interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
wgroup.long 0x808++0x03
|
|
line.long 0x00 "SCR,General Status Clear Register"
|
|
bitfld.long 0x00 4. " RDERRIC ,Remote device connection error interrupt clear" "No effect,Clear"
|
|
wgroup.long 0x80C++0x03
|
|
line.long 0x00 "SFR,General Status Set Register"
|
|
bitfld.long 0x00 9. " VBUSRQS ,VBUS request set" "No effect,Set"
|
|
bitfld.long 0x00 4. " RDERRIS ,Remote device connection error interrupt set" "No effect,Set"
|
|
width 16.
|
|
tree "USB High Speed Device Port"
|
|
if (((per.l(ad:0x40038000))&0x80)==0x80)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DEVCTRL,Device General Control Register"
|
|
bitfld.long 0x00 16. " OPMODE2 ,Specific operational mode" "Normal,Opmode"
|
|
bitfld.long 0x00 15. " TSTPCKT ,Test packet mode" "Normal,Test"
|
|
bitfld.long 0x00 14. " TSTK ,Test mode K" "Normal,Test"
|
|
bitfld.long 0x00 13. " TSTJ ,Test mode J" "Normal,Test"
|
|
newline
|
|
bitfld.long 0x00 12. " LS ,Low-speed mode force" "Full-speed,Low-speed"
|
|
bitfld.long 0x00 10.--11. " SPDCONF ,Mode configuration" "Normal,LOW_POWER,HIGH_SPEED,FORCED_FS"
|
|
bitfld.long 0x00 9. " RMWKUP ,Remote wake-up" "No effect,Wake-up"
|
|
bitfld.long 0x00 8. " DETACH ,Detach" "Reconnected,Disconnected"
|
|
newline
|
|
bitfld.long 0x00 7. " ADDEN ,Address enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " UADD ,USB address"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DEVCTRL,Device General Control Register"
|
|
bitfld.long 0x00 16. " OPMODE2 ,Specific operational mode" "Normal,Opmode"
|
|
bitfld.long 0x00 15. " TSTPCKT ,Test packet mode" "Normal,Test"
|
|
bitfld.long 0x00 14. " TSTK ,Test mode K" "Normal,Test"
|
|
bitfld.long 0x00 13. " TSTJ ,Test mode J" "Normal,Test"
|
|
newline
|
|
bitfld.long 0x00 12. " LS ,Low-speed mode force" "Full-speed,Low-speed"
|
|
bitfld.long 0x00 10.--11. " SPDCONF ,Mode configuration" "Normal,LOW_POWER,HIGH_SPEED,FORCED_FS"
|
|
bitfld.long 0x00 9. " RMWKUP ,Remote wake-up" "No effect,Wake-up"
|
|
bitfld.long 0x00 8. " DETACH ,Detach" "Reconnected,Disconnected"
|
|
newline
|
|
bitfld.long 0x00 7. " ADDEN ,Address enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DEVISR,Device Global Interrupt Status Register"
|
|
rbitfld.long 0x00 31. " DMA_6 ,DMA channel 6 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 30. " DMA_5 ,DMA channel 5 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " DMA_4 ,DMA channel 4 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 28. " DMA_3 ,DMA channel 3 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 27. " DMA_2 ,DMA channel 2 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 26. " DMA_1 ,DMA channel 1 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 25. " DMA_0 ,DMA channel 0 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 21. " PEP_9 ,Endpoint 9 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 20. " PEP_8 ,Endpoint 8 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 19. " PEP_7 ,Endpoint 7 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 18. " PEP_6 ,Endpoint 6 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 17. " PEP_5 ,Endpoint 5 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 16. " PEP_4 ,Endpoint 4 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 15. " PEP_3 ,Endpoint 3 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 14. " PEP_2 ,Endpoint 2 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 13. " PEP_1 ,Endpoint 1 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 12. " PEP_0 ,Endpoint 0 interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " UPRSM_SET/CLR ,Upstream resume interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " EORSM_SET/CLR ,End of resume interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " WAKEUP_SET/CLR ,Wake-up interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " EORST_SET/CLR ,End of reset interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " SOF_SET/CLR ,Start of frame interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " MSOF_SET/CLR ,Micro start of frame interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " SUSP_SET/CLR ,Suspend interrupt" "No interrupt,Interrupt"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "DEVIFR,Device Global Interrupt Set Register"
|
|
bitfld.long 0x00 31. " DMA_6 ,DMA channel 6 interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 30. " DMA_5 ,DMA channel 5 interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 29. " DMA_4 ,DMA channel 4 interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 28. " DMA_3 ,DMA channel 3 interrupt set" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 27. " DMA_2 ,DMA channel 2 interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 26. " DMA_1 ,DMA channel 1 interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 25. " DMA_0 ,DMA channel 0 interrupt set" "No effect,Set"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DEVIMR_SET/CLR,Device Global Interrupt Set/Clear Register"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x04 31. " DMA_6 ,DMA channel 6 interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x04 30. " DMA_5 ,DMA channel 5 interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x04 29. " DMA_4 ,DMA channel 4 interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 28. 0x08 28. 0x04 28. " DMA_3 ,DMA channel 3 interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x08 27. 0x04 27. " DMA_2 ,DMA channel 2 interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x04 26. " DMA_1 ,DMA channel 1 interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. 0x08 25. 0x04 25. " DMA_0 ,DMA channel 0 interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 22. 0x08 21. 0x04 21. " PEP_9 ,Endpoint 9 interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 21. 0x08 20. 0x04 20. " PEP_8 ,Endpoint 8 interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. 0x08 19. 0x04 19. " PEP_7 ,Endpoint 7 interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x04 18. " PEP_6 ,Endpoint 6 interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " PEP_5 ,Endpoint 5 interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " PEP_4 ,Endpoint 4 interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 15. 0x08 15. 0x04 15. " PEP_3 ,Endpoint 3 interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " PEP_2 ,Endpoint 2 interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " PEP_1 ,Endpoint 1 interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " PEP_0 ,Endpoint 0 interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " UPRSME ,Upstream resume interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " EORSME ,End of resume interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " WAKEUPE ,Wake-up interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " EORSTE ,End of reset interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " SOFE ,Start of frame interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " MSOFE ,Micro start of frame interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " SUSPE ,Suspend interrupt mask" "Masked,Not masked"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DEVEPT,Device Endpoint Register"
|
|
bitfld.long 0x00 25. " EPRST[9] ,Endpoint 9 reset" "No reset,Reset"
|
|
bitfld.long 0x00 24. " [8] ,Endpoint 8 reset" "No reset,Reset"
|
|
bitfld.long 0x00 23. " [7] ,Endpoint 7 reset" "No reset,Reset"
|
|
bitfld.long 0x00 22. " [6] ,Endpoint 6 reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 21. " [5] ,Endpoint 5 reset" "No reset,Reset"
|
|
bitfld.long 0x00 20. " [4] ,Endpoint 4 reset" "No reset,Reset"
|
|
bitfld.long 0x00 19. " [3] ,Endpoint 3 reset" "No reset,Reset"
|
|
bitfld.long 0x00 18. " [2] ,Endpoint 2 reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 17. " [1] ,Endpoint 1 reset" "No reset,Reset"
|
|
bitfld.long 0x00 16. " [0] ,Endpoint 0 reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 9. " EPEN[9] ,Endpoint 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Endpoint 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Endpoint 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Endpoint 6 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Endpoint 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Endpoint 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Endpoint 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Endpoint 2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Endpoint 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Endpoint 0 enable" "Disabled,Enabled"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "DEVFNUM,Device Frame Number Register"
|
|
bitfld.long 0x00 15. " FNCERR ,Frame number CRC error" "No error,Error"
|
|
hexmask.long.word 0x00 3.--13. 1. " FNUM ,Frame number"
|
|
bitfld.long 0x00 0.--2. " MFNUM ,Micro frame number" "0,1,2,3,4,5,6,7"
|
|
width 12.
|
|
tree "Endpoint 0"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DEVEPTCFG0,Device Endpoint 0 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transactions per microframe for isochronous endpoint" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint type" "Control,?..."
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint size" "8 bytes,16 bytes,32 bytes,64 bytes,?..."
|
|
bitfld.long 0x00 2.--3. " EPBK ,Endpoint banks" "Single-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Endpoint memory allocate" "Free memory,Allocate memory"
|
|
if (((per.l(ad:0x40038000+0x100))&0x1800)==0x800)
|
|
if (((per.l(ad:0x40038000+0x100))&0x100)==0x00)
|
|
group.long (0x100+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR0,Device Endpoint 0 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x100+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR0,Device Endpoint 0 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
elif (((per.l(ad:0x40038000+0x100))&0x1800)==0x00)
|
|
group.long (0x100+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR0,Device Endpoint 0 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI_SET/CLR ,Received SETUP interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
if (((per.l(ad:0x40038000+0x100))&0x100)==0x00)
|
|
group.long (0x100+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR0,Device Endpoint 0 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 7. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x100+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR0,Device Endpoint 0 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
endif
|
|
wgroup.long (0x100+0x90)++0x03
|
|
line.long 0x00 "DEVEPTIFR0,Device Endpoint 0 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
if (((per.l(ad:0x40038000+0x100))&0x1800)!=0x800)
|
|
group.long (0x100+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR0,Device Endpoint 0 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_SET/CLR ,STALL request" "Masked,Unmasked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_SET/CLR ,NYET token disable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Masked,Unmasked"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE_SET/CLR ,STALLed interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE_SET/CLR ,NAKed IN interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE_SET/CLR ,NAKed OUT interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE_SET/CLR ,Received SETUP interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Masked,Unmasked"
|
|
newline
|
|
wgroup.long (0x100+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER0,Device Endpoint 0 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
else
|
|
group.long (0x100+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR0,Device Endpoint 0 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_SET/CLR ,Transaction error interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_SET/CLR ,DataX interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_SET/CLR ,MData interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,STALLed interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " HBISOFLUSHE_SET/CLR ,High bandwidth isochronous IN flush interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " HBISOINERRE_SET/CLR ,High bandwidth isochronous IN error interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFE_SET/CLR ,Received SETUP interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Disabled,Enabled"
|
|
wgroup.long (0x100+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER0,Device Endpoint 0 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 1"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DEVEPTCFG1,Device Endpoint 1 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transactions per microframe for isochronous endpoint" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " EPBK ,Endpoint banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Endpoint memory allocate" "Free memory,Allocate memory"
|
|
if (((per.l(ad:0x40038000+0x104))&0x1800)==0x800)
|
|
if (((per.l(ad:0x40038000+0x104))&0x100)==0x00)
|
|
group.long (0x104+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR1,Device Endpoint 1 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x104+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR1,Device Endpoint 1 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
elif (((per.l(ad:0x40038000+0x104))&0x1800)==0x00)
|
|
group.long (0x104+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR1,Device Endpoint 1 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI_SET/CLR ,Received SETUP interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
if (((per.l(ad:0x40038000+0x104))&0x100)==0x00)
|
|
group.long (0x104+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR1,Device Endpoint 1 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 7. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x104+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR1,Device Endpoint 1 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
endif
|
|
wgroup.long (0x104+0x90)++0x03
|
|
line.long 0x00 "DEVEPTIFR1,Device Endpoint 1 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
if (((per.l(ad:0x40038000+0x104))&0x1800)!=0x800)
|
|
group.long (0x104+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR1,Device Endpoint 1 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_SET/CLR ,STALL request" "Masked,Unmasked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_SET/CLR ,NYET token disable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Masked,Unmasked"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE_SET/CLR ,STALLed interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE_SET/CLR ,NAKed IN interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE_SET/CLR ,NAKed OUT interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE_SET/CLR ,Received SETUP interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Masked,Unmasked"
|
|
newline
|
|
wgroup.long (0x104+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER1,Device Endpoint 1 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
else
|
|
group.long (0x104+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR1,Device Endpoint 1 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_SET/CLR ,Transaction error interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_SET/CLR ,DataX interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_SET/CLR ,MData interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,STALLed interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " HBISOFLUSHE_SET/CLR ,High bandwidth isochronous IN flush interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " HBISOINERRE_SET/CLR ,High bandwidth isochronous IN error interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFE_SET/CLR ,Received SETUP interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Disabled,Enabled"
|
|
wgroup.long (0x104+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER1,Device Endpoint 1 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 2"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DEVEPTCFG2,Device Endpoint 2 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transactions per microframe for isochronous endpoint" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " EPBK ,Endpoint banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Endpoint memory allocate" "Free memory,Allocate memory"
|
|
if (((per.l(ad:0x40038000+0x108))&0x1800)==0x800)
|
|
if (((per.l(ad:0x40038000+0x108))&0x100)==0x00)
|
|
group.long (0x108+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR2,Device Endpoint 2 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x108+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR2,Device Endpoint 2 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
elif (((per.l(ad:0x40038000+0x108))&0x1800)==0x00)
|
|
group.long (0x108+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR2,Device Endpoint 2 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI_SET/CLR ,Received SETUP interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
if (((per.l(ad:0x40038000+0x108))&0x100)==0x00)
|
|
group.long (0x108+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR2,Device Endpoint 2 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 7. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x108+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR2,Device Endpoint 2 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
endif
|
|
wgroup.long (0x108+0x90)++0x03
|
|
line.long 0x00 "DEVEPTIFR2,Device Endpoint 2 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
if (((per.l(ad:0x40038000+0x108))&0x1800)!=0x800)
|
|
group.long (0x108+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR2,Device Endpoint 2 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_SET/CLR ,STALL request" "Masked,Unmasked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_SET/CLR ,NYET token disable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Masked,Unmasked"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE_SET/CLR ,STALLed interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE_SET/CLR ,NAKed IN interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE_SET/CLR ,NAKed OUT interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE_SET/CLR ,Received SETUP interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Masked,Unmasked"
|
|
newline
|
|
wgroup.long (0x108+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER2,Device Endpoint 2 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
else
|
|
group.long (0x108+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR2,Device Endpoint 2 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_SET/CLR ,Transaction error interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_SET/CLR ,DataX interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_SET/CLR ,MData interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,STALLed interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " HBISOFLUSHE_SET/CLR ,High bandwidth isochronous IN flush interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " HBISOINERRE_SET/CLR ,High bandwidth isochronous IN error interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFE_SET/CLR ,Received SETUP interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Disabled,Enabled"
|
|
wgroup.long (0x108+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER2,Device Endpoint 2 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 3"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DEVEPTCFG3,Device Endpoint 3 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transactions per microframe for isochronous endpoint" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " EPBK ,Endpoint banks" "Single-bank,Double-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Endpoint memory allocate" "Free memory,Allocate memory"
|
|
if (((per.l(ad:0x40038000+0x10C))&0x1800)==0x800)
|
|
if (((per.l(ad:0x40038000+0x10C))&0x100)==0x00)
|
|
group.long (0x10C+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR3,Device Endpoint 3 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x10C+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR3,Device Endpoint 3 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
elif (((per.l(ad:0x40038000+0x10C))&0x1800)==0x00)
|
|
group.long (0x10C+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR3,Device Endpoint 3 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI_SET/CLR ,Received SETUP interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
if (((per.l(ad:0x40038000+0x10C))&0x100)==0x00)
|
|
group.long (0x10C+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR3,Device Endpoint 3 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 7. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x10C+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR3,Device Endpoint 3 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
endif
|
|
wgroup.long (0x10C+0x90)++0x03
|
|
line.long 0x00 "DEVEPTIFR3,Device Endpoint 3 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
if (((per.l(ad:0x40038000+0x10C))&0x1800)!=0x800)
|
|
group.long (0x10C+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR3,Device Endpoint 3 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_SET/CLR ,STALL request" "Masked,Unmasked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_SET/CLR ,NYET token disable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Masked,Unmasked"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE_SET/CLR ,STALLed interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE_SET/CLR ,NAKed IN interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE_SET/CLR ,NAKed OUT interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE_SET/CLR ,Received SETUP interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Masked,Unmasked"
|
|
newline
|
|
wgroup.long (0x10C+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER3,Device Endpoint 3 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
else
|
|
group.long (0x10C+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR3,Device Endpoint 3 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_SET/CLR ,Transaction error interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_SET/CLR ,DataX interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_SET/CLR ,MData interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,STALLed interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " HBISOFLUSHE_SET/CLR ,High bandwidth isochronous IN flush interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " HBISOINERRE_SET/CLR ,High bandwidth isochronous IN error interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFE_SET/CLR ,Received SETUP interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Disabled,Enabled"
|
|
wgroup.long (0x10C+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER3,Device Endpoint 3 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 4"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DEVEPTCFG4,Device Endpoint 4 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transactions per microframe for isochronous endpoint" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " EPBK ,Endpoint banks" "Single-bank,Double-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Endpoint memory allocate" "Free memory,Allocate memory"
|
|
if (((per.l(ad:0x40038000+0x110))&0x1800)==0x800)
|
|
if (((per.l(ad:0x40038000+0x110))&0x100)==0x00)
|
|
group.long (0x110+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR4,Device Endpoint 4 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x110+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR4,Device Endpoint 4 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
elif (((per.l(ad:0x40038000+0x110))&0x1800)==0x00)
|
|
group.long (0x110+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR4,Device Endpoint 4 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI_SET/CLR ,Received SETUP interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
if (((per.l(ad:0x40038000+0x110))&0x100)==0x00)
|
|
group.long (0x110+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR4,Device Endpoint 4 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 7. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x110+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR4,Device Endpoint 4 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
endif
|
|
wgroup.long (0x110+0x90)++0x03
|
|
line.long 0x00 "DEVEPTIFR4,Device Endpoint 4 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
if (((per.l(ad:0x40038000+0x110))&0x1800)!=0x800)
|
|
group.long (0x110+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR4,Device Endpoint 4 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_SET/CLR ,STALL request" "Masked,Unmasked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_SET/CLR ,NYET token disable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Masked,Unmasked"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE_SET/CLR ,STALLed interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE_SET/CLR ,NAKed IN interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE_SET/CLR ,NAKed OUT interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE_SET/CLR ,Received SETUP interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Masked,Unmasked"
|
|
newline
|
|
wgroup.long (0x110+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER4,Device Endpoint 4 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
else
|
|
group.long (0x110+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR4,Device Endpoint 4 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_SET/CLR ,Transaction error interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_SET/CLR ,DataX interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_SET/CLR ,MData interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,STALLed interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " HBISOFLUSHE_SET/CLR ,High bandwidth isochronous IN flush interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " HBISOINERRE_SET/CLR ,High bandwidth isochronous IN error interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFE_SET/CLR ,Received SETUP interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Disabled,Enabled"
|
|
wgroup.long (0x110+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER4,Device Endpoint 4 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 5"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DEVEPTCFG5,Device Endpoint 5 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transactions per microframe for isochronous endpoint" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " EPBK ,Endpoint banks" "Single-bank,Double-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Endpoint memory allocate" "Free memory,Allocate memory"
|
|
if (((per.l(ad:0x40038000+0x114))&0x1800)==0x800)
|
|
if (((per.l(ad:0x40038000+0x114))&0x100)==0x00)
|
|
group.long (0x114+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR5,Device Endpoint 5 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x114+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR5,Device Endpoint 5 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
elif (((per.l(ad:0x40038000+0x114))&0x1800)==0x00)
|
|
group.long (0x114+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR5,Device Endpoint 5 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI_SET/CLR ,Received SETUP interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
if (((per.l(ad:0x40038000+0x114))&0x100)==0x00)
|
|
group.long (0x114+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR5,Device Endpoint 5 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 7. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x114+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR5,Device Endpoint 5 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
endif
|
|
wgroup.long (0x114+0x90)++0x03
|
|
line.long 0x00 "DEVEPTIFR5,Device Endpoint 5 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
if (((per.l(ad:0x40038000+0x114))&0x1800)!=0x800)
|
|
group.long (0x114+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR5,Device Endpoint 5 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_SET/CLR ,STALL request" "Masked,Unmasked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_SET/CLR ,NYET token disable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Masked,Unmasked"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE_SET/CLR ,STALLed interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE_SET/CLR ,NAKed IN interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE_SET/CLR ,NAKed OUT interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE_SET/CLR ,Received SETUP interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Masked,Unmasked"
|
|
newline
|
|
wgroup.long (0x114+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER5,Device Endpoint 5 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
else
|
|
group.long (0x114+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR5,Device Endpoint 5 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_SET/CLR ,Transaction error interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_SET/CLR ,DataX interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_SET/CLR ,MData interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,STALLed interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " HBISOFLUSHE_SET/CLR ,High bandwidth isochronous IN flush interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " HBISOINERRE_SET/CLR ,High bandwidth isochronous IN error interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFE_SET/CLR ,Received SETUP interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Disabled,Enabled"
|
|
wgroup.long (0x114+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER5,Device Endpoint 5 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 6"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DEVEPTCFG6,Device Endpoint 6 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transactions per microframe for isochronous endpoint" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " EPBK ,Endpoint banks" "Single-bank,Double-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Endpoint memory allocate" "Free memory,Allocate memory"
|
|
if (((per.l(ad:0x40038000+0x118))&0x1800)==0x800)
|
|
if (((per.l(ad:0x40038000+0x118))&0x100)==0x00)
|
|
group.long (0x118+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR6,Device Endpoint 6 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x118+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR6,Device Endpoint 6 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
elif (((per.l(ad:0x40038000+0x118))&0x1800)==0x00)
|
|
group.long (0x118+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR6,Device Endpoint 6 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI_SET/CLR ,Received SETUP interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
if (((per.l(ad:0x40038000+0x118))&0x100)==0x00)
|
|
group.long (0x118+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR6,Device Endpoint 6 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 7. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x118+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR6,Device Endpoint 6 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
endif
|
|
wgroup.long (0x118+0x90)++0x03
|
|
line.long 0x00 "DEVEPTIFR6,Device Endpoint 6 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
if (((per.l(ad:0x40038000+0x118))&0x1800)!=0x800)
|
|
group.long (0x118+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR6,Device Endpoint 6 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_SET/CLR ,STALL request" "Masked,Unmasked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_SET/CLR ,NYET token disable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Masked,Unmasked"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE_SET/CLR ,STALLed interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE_SET/CLR ,NAKed IN interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE_SET/CLR ,NAKed OUT interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE_SET/CLR ,Received SETUP interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Masked,Unmasked"
|
|
newline
|
|
wgroup.long (0x118+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER6,Device Endpoint 6 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
else
|
|
group.long (0x118+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR6,Device Endpoint 6 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_SET/CLR ,Transaction error interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_SET/CLR ,DataX interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_SET/CLR ,MData interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,STALLed interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " HBISOFLUSHE_SET/CLR ,High bandwidth isochronous IN flush interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " HBISOINERRE_SET/CLR ,High bandwidth isochronous IN error interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFE_SET/CLR ,Received SETUP interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Disabled,Enabled"
|
|
wgroup.long (0x118+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER6,Device Endpoint 6 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 7"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "DEVEPTCFG7,Device Endpoint 7 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transactions per microframe for isochronous endpoint" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " EPBK ,Endpoint banks" "Single-bank,Double-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Endpoint memory allocate" "Free memory,Allocate memory"
|
|
if (((per.l(ad:0x40038000+0x11C))&0x1800)==0x800)
|
|
if (((per.l(ad:0x40038000+0x11C))&0x100)==0x00)
|
|
group.long (0x11C+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR7,Device Endpoint 7 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x11C+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR7,Device Endpoint 7 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
elif (((per.l(ad:0x40038000+0x11C))&0x1800)==0x00)
|
|
group.long (0x11C+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR7,Device Endpoint 7 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI_SET/CLR ,Received SETUP interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
if (((per.l(ad:0x40038000+0x11C))&0x100)==0x00)
|
|
group.long (0x11C+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR7,Device Endpoint 7 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 7. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x11C+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR7,Device Endpoint 7 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
endif
|
|
wgroup.long (0x11C+0x90)++0x03
|
|
line.long 0x00 "DEVEPTIFR7,Device Endpoint 7 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
if (((per.l(ad:0x40038000+0x11C))&0x1800)!=0x800)
|
|
group.long (0x11C+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR7,Device Endpoint 7 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_SET/CLR ,STALL request" "Masked,Unmasked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_SET/CLR ,NYET token disable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Masked,Unmasked"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE_SET/CLR ,STALLed interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE_SET/CLR ,NAKed IN interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE_SET/CLR ,NAKed OUT interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE_SET/CLR ,Received SETUP interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Masked,Unmasked"
|
|
newline
|
|
wgroup.long (0x11C+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER7,Device Endpoint 7 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
else
|
|
group.long (0x11C+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR7,Device Endpoint 7 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_SET/CLR ,Transaction error interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_SET/CLR ,DataX interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_SET/CLR ,MData interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,STALLed interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " HBISOFLUSHE_SET/CLR ,High bandwidth isochronous IN flush interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " HBISOINERRE_SET/CLR ,High bandwidth isochronous IN error interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFE_SET/CLR ,Received SETUP interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Disabled,Enabled"
|
|
wgroup.long (0x11C+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER7,Device Endpoint 7 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 8"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "DEVEPTCFG8,Device Endpoint 8 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transactions per microframe for isochronous endpoint" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " EPBK ,Endpoint banks" "Single-bank,Double-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Endpoint memory allocate" "Free memory,Allocate memory"
|
|
if (((per.l(ad:0x40038000+0x120))&0x1800)==0x800)
|
|
if (((per.l(ad:0x40038000+0x120))&0x100)==0x00)
|
|
group.long (0x120+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR8,Device Endpoint 8 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x120+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR8,Device Endpoint 8 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
elif (((per.l(ad:0x40038000+0x120))&0x1800)==0x00)
|
|
group.long (0x120+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR8,Device Endpoint 8 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI_SET/CLR ,Received SETUP interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
if (((per.l(ad:0x40038000+0x120))&0x100)==0x00)
|
|
group.long (0x120+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR8,Device Endpoint 8 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 7. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x120+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR8,Device Endpoint 8 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
endif
|
|
wgroup.long (0x120+0x90)++0x03
|
|
line.long 0x00 "DEVEPTIFR8,Device Endpoint 8 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
if (((per.l(ad:0x40038000+0x120))&0x1800)!=0x800)
|
|
group.long (0x120+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR8,Device Endpoint 8 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_SET/CLR ,STALL request" "Masked,Unmasked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_SET/CLR ,NYET token disable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Masked,Unmasked"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE_SET/CLR ,STALLed interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE_SET/CLR ,NAKed IN interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE_SET/CLR ,NAKed OUT interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE_SET/CLR ,Received SETUP interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Masked,Unmasked"
|
|
newline
|
|
wgroup.long (0x120+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER8,Device Endpoint 8 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
else
|
|
group.long (0x120+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR8,Device Endpoint 8 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_SET/CLR ,Transaction error interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_SET/CLR ,DataX interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_SET/CLR ,MData interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,STALLed interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " HBISOFLUSHE_SET/CLR ,High bandwidth isochronous IN flush interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " HBISOINERRE_SET/CLR ,High bandwidth isochronous IN error interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFE_SET/CLR ,Received SETUP interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Disabled,Enabled"
|
|
wgroup.long (0x120+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER8,Device Endpoint 8 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint 9"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DEVEPTCFG9,Device Endpoint 9 Configuration Register"
|
|
bitfld.long 0x00 13.--14. " NBTRANS ,Number of transactions per microframe for isochronous endpoint" ",1 transaction,2 transactions,3 transactions"
|
|
bitfld.long 0x00 11.--12. " EPTYPE ,Endpoint type" "Control,Isochronous,Bulk,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 9. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EPDIR ,Endpoint direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " EPSIZE ,Endpoint size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " EPBK ,Endpoint banks" "Single-bank,Double-bank,?..."
|
|
newline
|
|
bitfld.long 0x00 1. " ALLOC ,Endpoint memory allocate" "Free memory,Allocate memory"
|
|
if (((per.l(ad:0x40038000+0x124))&0x1800)==0x800)
|
|
if (((per.l(ad:0x40038000+0x124))&0x100)==0x00)
|
|
group.long (0x124+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR9,Device Endpoint 9 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x124+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR9,Device Endpoint 9 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 10. " ERRORTRANS ,High-bandwidth isochronous OUT endpoint transaction error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,DATA2,MDATA"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HBISOFLUSHI_SET/CLR ,High bandwidth isochronous IN flush interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " HBISOINERRI_SET/CLR ,High bandwidth isochronous IN underflow error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " UNDERFI_SET/CLR ,Received underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
elif (((per.l(ad:0x40038000+0x124))&0x1800)==0x00)
|
|
group.long (0x124+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR9,Device Endpoint 9 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXSTPI_SET/CLR ,Received SETUP interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
if (((per.l(ad:0x40038000+0x124))&0x100)==0x00)
|
|
group.long (0x124+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR9,Device Endpoint 9 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 7. 0x04 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXOUTI_SET/CLR ,Received OUT data interrupt" "No interrupt,Interrupt"
|
|
else
|
|
group.long (0x124+0x30)++0x03
|
|
line.long 0x00 "DEVEPTISR9,Device Endpoint 9 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " BYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 17. " CTRLDIR ,Control direction" "OUT,IN"
|
|
newline
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " SHORTPACKET_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " STALLEDI_SET/CLR ,STALLed interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " NAKINI_SET/CLR ,NAKed IN interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " NAKOUTI_SET/CLR ,NAKed OUT interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " TXINI_SET/CLR ,Transmitted IN data interrupt" "No interrupt,Interrupt"
|
|
endif
|
|
endif
|
|
wgroup.long (0x124+0x90)++0x03
|
|
line.long 0x00 "DEVEPTIFR9,Device Endpoint 9 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
if (((per.l(ad:0x40038000+0x124))&0x1800)!=0x800)
|
|
group.long (0x124+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR9,Device Endpoint 9 Mask Register"
|
|
setclrfld.long 0x00 19. 0x30 19. 0x60 19. " STALLRQ_SET/CLR ,STALL request" "Masked,Unmasked"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " NYETDIS_SET/CLR ,NYET token disable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Masked,Unmasked"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " STALLEDE_SET/CLR ,STALLed interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKINE_SET/CLR ,NAKed IN interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " NAKOUTE_SET/CLR ,NAKed OUT interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " RXSTPE_SET/CLR ,Received SETUP interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Masked,Unmasked"
|
|
newline
|
|
wgroup.long (0x124+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER9,Device Endpoint 9 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
else
|
|
group.long (0x124+0xC0)++0x03
|
|
line.long 0x00 "DEVEPTIMR9,Device Endpoint 9 Mask Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " EPDISHDMA_SET/CLR ,Endpoint interrupts disable HDMA request" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x30 10. 0x60 10. " ERRORTRANSE_SET/CLR ,Transaction error interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x30 9. 0x60 9. " DATAXE_SET/CLR ,DataX interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x30 8. 0x60 8. " MDATAE_SET/CLR ,MData interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETE_SET/CLR ,Short packet interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,STALLed interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFE_SET/CLR ,Overflow interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " HBISOFLUSHE_SET/CLR ,High bandwidth isochronous IN flush interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " HBISOINERRE_SET/CLR ,High bandwidth isochronous IN error interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFE_SET/CLR ,Received SETUP interrupt" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " RXOUTE_SET/CLR ,Received OUT data interrupt" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " TXINE_SET/CLR ,Transmitted IN data interrupt" "Disabled,Enabled"
|
|
wgroup.long (0x124+0x120)++0x03
|
|
line.long 0x00 "DEVEPTIER9,Device Endpoint 9 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " KILLBK ,Kill IN bank" "No effect,Enabled"
|
|
endif
|
|
tree.end
|
|
width 16.
|
|
tree "DMA channel 1"
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "DEVDMANXTDSC1,Device DMA Channel 1 Next Descriptor Address Register"
|
|
line.long 0x04 "DEVDMAADDRESS1,Device DMA Channel 1 Address Register"
|
|
if (((per.l(ad:0x40038000+0x300+0x08))&0x03)!=0x00)
|
|
group.long (0x300+0x08)++0x03
|
|
line.long 0x00 "DEVDMACONTROL1,Device DMA Channel 1 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
bitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
else
|
|
group.long (0x300+0x08)++0x03
|
|
line.long 0x00 "DEVDMACONTROL1,Device DMA Channel 1 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
rbitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
endif
|
|
hgroup.long (0x300+0x0C)++0x03
|
|
hide.long 0x00 "DEVDMASTATUS1,Device DMA Channel 1 Status Register"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 2"
|
|
group.long 0x310++0x07
|
|
line.long 0x00 "DEVDMANXTDSC2,Device DMA Channel 2 Next Descriptor Address Register"
|
|
line.long 0x04 "DEVDMAADDRESS2,Device DMA Channel 2 Address Register"
|
|
if (((per.l(ad:0x40038000+0x310+0x08))&0x03)!=0x00)
|
|
group.long (0x310+0x08)++0x03
|
|
line.long 0x00 "DEVDMACONTROL2,Device DMA Channel 2 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
bitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
else
|
|
group.long (0x310+0x08)++0x03
|
|
line.long 0x00 "DEVDMACONTROL2,Device DMA Channel 2 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
rbitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
endif
|
|
hgroup.long (0x310+0x0C)++0x03
|
|
hide.long 0x00 "DEVDMASTATUS2,Device DMA Channel 2 Status Register"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 3"
|
|
group.long 0x320++0x07
|
|
line.long 0x00 "DEVDMANXTDSC3,Device DMA Channel 3 Next Descriptor Address Register"
|
|
line.long 0x04 "DEVDMAADDRESS3,Device DMA Channel 3 Address Register"
|
|
if (((per.l(ad:0x40038000+0x320+0x08))&0x03)!=0x00)
|
|
group.long (0x320+0x08)++0x03
|
|
line.long 0x00 "DEVDMACONTROL3,Device DMA Channel 3 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
bitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
else
|
|
group.long (0x320+0x08)++0x03
|
|
line.long 0x00 "DEVDMACONTROL3,Device DMA Channel 3 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
rbitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
endif
|
|
hgroup.long (0x320+0x0C)++0x03
|
|
hide.long 0x00 "DEVDMASTATUS3,Device DMA Channel 3 Status Register"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 4"
|
|
group.long 0x330++0x07
|
|
line.long 0x00 "DEVDMANXTDSC4,Device DMA Channel 4 Next Descriptor Address Register"
|
|
line.long 0x04 "DEVDMAADDRESS4,Device DMA Channel 4 Address Register"
|
|
if (((per.l(ad:0x40038000+0x330+0x08))&0x03)!=0x00)
|
|
group.long (0x330+0x08)++0x03
|
|
line.long 0x00 "DEVDMACONTROL4,Device DMA Channel 4 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
bitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
else
|
|
group.long (0x330+0x08)++0x03
|
|
line.long 0x00 "DEVDMACONTROL4,Device DMA Channel 4 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
rbitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
endif
|
|
hgroup.long (0x330+0x0C)++0x03
|
|
hide.long 0x00 "DEVDMASTATUS4,Device DMA Channel 4 Status Register"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 5"
|
|
group.long 0x340++0x07
|
|
line.long 0x00 "DEVDMANXTDSC5,Device DMA Channel 5 Next Descriptor Address Register"
|
|
line.long 0x04 "DEVDMAADDRESS5,Device DMA Channel 5 Address Register"
|
|
if (((per.l(ad:0x40038000+0x340+0x08))&0x03)!=0x00)
|
|
group.long (0x340+0x08)++0x03
|
|
line.long 0x00 "DEVDMACONTROL5,Device DMA Channel 5 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
bitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
else
|
|
group.long (0x340+0x08)++0x03
|
|
line.long 0x00 "DEVDMACONTROL5,Device DMA Channel 5 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
rbitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
endif
|
|
hgroup.long (0x340+0x0C)++0x03
|
|
hide.long 0x00 "DEVDMASTATUS5,Device DMA Channel 5 Status Register"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 6"
|
|
group.long 0x350++0x07
|
|
line.long 0x00 "DEVDMANXTDSC6,Device DMA Channel 6 Next Descriptor Address Register"
|
|
line.long 0x04 "DEVDMAADDRESS6,Device DMA Channel 6 Address Register"
|
|
if (((per.l(ad:0x40038000+0x350+0x08))&0x03)!=0x00)
|
|
group.long (0x350+0x08)++0x03
|
|
line.long 0x00 "DEVDMACONTROL6,Device DMA Channel 6 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
bitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
else
|
|
group.long (0x350+0x08)++0x03
|
|
line.long 0x00 "DEVDMACONTROL6,Device DMA Channel 6 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
rbitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
endif
|
|
hgroup.long (0x350+0x0C)++0x03
|
|
hide.long 0x00 "DEVDMASTATUS6,Device DMA Channel 6 Status Register"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 7"
|
|
group.long 0x360++0x07
|
|
line.long 0x00 "DEVDMANXTDSC7,Device DMA Channel 7 Next Descriptor Address Register"
|
|
line.long 0x04 "DEVDMAADDRESS7,Device DMA Channel 7 Address Register"
|
|
if (((per.l(ad:0x40038000+0x360+0x08))&0x03)!=0x00)
|
|
group.long (0x360+0x08)++0x03
|
|
line.long 0x00 "DEVDMACONTROL7,Device DMA Channel 7 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
bitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
else
|
|
group.long (0x360+0x08)++0x03
|
|
line.long 0x00 "DEVDMACONTROL7,Device DMA Channel 7 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
rbitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
endif
|
|
hgroup.long (0x360+0x0C)++0x03
|
|
hide.long 0x00 "DEVDMASTATUS7,Device DMA Channel 7 Status Register"
|
|
in
|
|
tree.end
|
|
tree.end
|
|
tree "USB Host High Speed Port"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "HSTCTRL,Host General Control Register"
|
|
bitfld.long 0x00 12.--13. " SPDCONF ,Mode configuration" "NORMAL,LOW_POWER,HIGH_SPEED,FORCED_FS"
|
|
bitfld.long 0x00 10. " RESUME ,Send USB resume" "No effect,Resume"
|
|
bitfld.long 0x00 9. " RESET ,Send USB reset" "No effect,Reset"
|
|
bitfld.long 0x00 8. " SOFE ,Start of frame generation enable" "Disabled,Enabled"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "HSTISR,Host Global Interrupt Status Register"
|
|
rbitfld.long 0x00 31. " DMA_6 ,DMA channel 6 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 30. " DMA_5 ,DMA channel 5 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 29. " DMA_4 ,DMA channel 4 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 28. " DMA_3 ,DMA channel 3 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 27. " DMA_2 ,DMA channel 2 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 26. " DMA_1 ,DMA channel 1 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 25. " DMA_0 ,DMA channel 0 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 17. " PEP_9 ,Pipe 9 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 16. " PEP_8 ,Pipe 8 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 15. " PEP_7 ,Pipe 7 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 14. " PEP_6 ,Pipe 6 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 13. " PEP_5 ,Pipe 5 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 12. " PEP_4 ,Pipe 4 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 11. " PEP_3 ,Pipe 3 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 10. " PEP_2 ,Pipe 2 interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 9. " PEP_1 ,Pipe 1 interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 8. " PEP_0 ,Pipe 0 interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " HWUPI_SET/CLR ,Host wake-up interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " HSOFI_SET/CLR ,Host start of frame interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " RXRSMI_SET/CLR ,Upstream resume received interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " RSMEDI_SET/CLR ,Downstream resume sent interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RSTI_SET/CLR ,USB reset sent interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " DDISCI_SET/CLR ,Device disconnection interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " DCONNI_SET/CLR ,Device connection interrupt" "No interrupt,Interrupt"
|
|
wgroup.long 0x40C++0x03
|
|
line.long 0x00 "HSTIFR,Host Global Interrupt Set Register"
|
|
bitfld.long 0x00 31. " DMA_6 ,DMA channel 6 interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 30. " DMA_5 ,DMA channel 5 interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 29. " DMA_4 ,DMA channel 4 interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 28. " DMA_3 ,DMA channel 3 interrupt set" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 27. " DMA_2 ,DMA channel 2 interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 26. " DMA_1 ,DMA channel 1 interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 25. " DMA_0 ,DMA channel 0 interrupt set" "No effect,Set"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "HSTIMR_SET/CLR,Host Global Interrupt Mask Register"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x04 31. " DMA_6 ,DMA channel 7 interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x04 30. " DMA_5 ,DMA channel 6 interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x04 29. " DMA_4 ,DMA channel 5 interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 28. 0x08 28. 0x04 28. " DMA_3 ,DMA channel 4 interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x08 27. 0x04 27. " DMA_2 ,DMA channel 3 interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x04 26. " DMA_1 ,DMA channel 2 interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 25. 0x08 25. 0x04 25. " DMA_0 ,DMA channel 1 interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " PEP_9 ,Pipe 9 interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " PEP_8 ,Pipe 8 interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 15. 0x08 15. 0x04 15. " PEP_7 ,Pipe 7 interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " PEP_6 ,Pipe 6 interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " PEP_5 ,Pipe 5 interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " PEP_4 ,Pipe 4 interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " PEP_3 ,Pipe 3 interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " PEP_2 ,Pipe 2 interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " PEP_1 ,Pipe 1 interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " PEP_0 ,Pipe 0 interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " HWUPIE ,Host wake-up interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " HSOFIE ,Host start of frame interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " RXRSMIE ,Upstream resume received interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " RSMEDIE ,Downstream resume sent interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RSTIE ,USB reset sent interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " DDISCIE ,Device disconnection interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " DCONNIE ,Device connection interrupt enable" "Masked,Unmasked"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "DEVFNUM,Device Frame Number Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " FLENHIGH ,Frame length"
|
|
hexmask.long.word 0x00 3.--13. 1. " FNUM ,Frame number"
|
|
bitfld.long 0x00 0.--2. " MFNUM ,Micro frame number" "0,1,2,3,4,5,6,7"
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "HSTADDR1,Host Address 1 Register"
|
|
hexmask.long.byte 0x00 24.--30. 0x01 " HSTADDRP3 ,USB host address"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " HSTADDRP2 ,USB host address"
|
|
hexmask.long.byte 0x00 8.--14. 0x01 " HSTADDRP1 ,USB host address"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " HSTADDRP0 ,USB host address"
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "HSTADDR2,Host Address 2 Register"
|
|
hexmask.long.byte 0x00 24.--30. 0x01 " HSTADDRP7 ,USB host address"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " HSTADDRP6 ,USB host address"
|
|
hexmask.long.byte 0x00 8.--14. 0x01 " HSTADDRP5 ,USB host address"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " HSTADDRP4 ,USB host address"
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "HSTADDR3,Host Address 3 Register"
|
|
hexmask.long.byte 0x00 8.--14. 0x01 " HSTADDRP9 ,USB host address"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " HSTADDRP8 ,USB host address"
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "HSTPIP,Host Pipe Register"
|
|
bitfld.long 0x00 24. " PRST[8] ,Pipe 8 reset" "No reset,Reset"
|
|
bitfld.long 0x00 23. " [7] ,Pipe 7 reset" "No reset,Reset"
|
|
bitfld.long 0x00 22. " [6] ,Pipe 6 reset" "No reset,Reset"
|
|
bitfld.long 0x00 21. " [5] ,Pipe 5 reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 20. " [4] ,Pipe 4 reset" "No reset,Reset"
|
|
bitfld.long 0x00 19. " [3] ,Pipe 3 reset" "No reset,Reset"
|
|
bitfld.long 0x00 18. " [2] ,Pipe 2 reset" "No reset,Reset"
|
|
bitfld.long 0x00 17. " [1] ,Pipe 1 reset" "No reset,Reset"
|
|
newline
|
|
bitfld.long 0x00 16. " [0] ,Pipe 0 reset" "No reset,Reset"
|
|
bitfld.long 0x00 8. " PEN[8] ,Pipe 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " [7] ,Pipe 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Pipe 6 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " [5] ,Pipe 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Pipe 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " [3] ,Pipe 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Pipe 2 enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Pipe 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Pipe 0 enable" "Disabled,Enabled"
|
|
width 13.
|
|
tree "Pipe 0"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "HSTPIPCFG0,Host Pipe 0 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BINTERVAL ,Binterval parameter for the bulk-out/ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe endpoint number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe type" "Control,?..."
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe token" "SETUP,IN,OUT,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe size" "8 bytes,16 bytes,32 bytes,64 bytes,?..."
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe banks" "Single-bank,?..."
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe memory allocate" "Freed,Allocated"
|
|
if (((per.l(ad:0x40038000+0x500))&0x3000)==(0x00||0x2000))
|
|
group.long (0x500+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR0,Host Pipe 0 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " TXSTPI_SET/CLR ,Transmitted SETUP interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x500+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR0,Host Pipe 0 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
elif (((per.l(ad:0x40038000+0x500))&0x3000)==0x1000)
|
|
group.long (0x500+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR0,Host Pipe 0 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x500+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR0,Host Pipe 0 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
else
|
|
group.long (0x500+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR0,Host Pipe 0 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,?..."
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x500+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR0,Host Pipe 0 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x500))&0x3000)==(0x00||0x2000))
|
|
group.long (0x500+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR0,Host Pipe 0 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " TXSTPE_SET/CLR ,Transmitted SETUP interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x500+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER0,Host Pipe 0 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
elif (((per.l(ad:0x40038000+0x500))&0x3000)==0x1000)
|
|
group.long (0x500+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR0,Host Pipe 0 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,CRC error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x500+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER0,Host Pipe 0 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
else
|
|
group.long (0x500+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR0,Host Pipe 0 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x500+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER0,Host Pipe 0 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
endif
|
|
group.long (0x500+0x150)++0x03
|
|
line.long 0x00 "HSTPIPINRQ0,Host Pipe 0 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN request mode" "INRQ_IN,INFINITE_IN"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN request number before freeze"
|
|
group.long (0x500+0x180)++0x03
|
|
line.long 0x00 "HSTPIPERR0,Host Pipe 0 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 error" "No error,Error"
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-out error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " PID ,PID error" "No error,Error"
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID error" "No error,Error"
|
|
bitfld.long 0x00 0. " DATATGL ,Data toggle error" "No error,Error"
|
|
tree.end
|
|
tree "Pipe 1"
|
|
if (((per.l(ad:0x40038000+0x504))&0x3000)==(0x00||0x2000))
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "HSTPIPCFG1,Host Pipe 1 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BINTERVAL ,Binterval parameter for the bulk-out/ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe endpoint number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe type" "Control,,Bulk,?..."
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe token" "SETUP,IN,OUT,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe memory allocate" "Freed,Allocated"
|
|
else
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "HSTPIPCFG1,Host Pipe 1 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTFRQ ,Pipe interrupt request frequency"
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe endpoint number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe token" "SETUP,IN,OUT,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe memory allocate" "Freed,Allocated"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x504))&0x3000)==(0x00||0x2000))
|
|
group.long (0x504+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR1,Host Pipe 1 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " TXSTPI_SET/CLR ,Transmitted SETUP interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x504+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR1,Host Pipe 1 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
elif (((per.l(ad:0x40038000+0x504))&0x3000)==0x1000)
|
|
group.long (0x504+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR1,Host Pipe 1 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x504+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR1,Host Pipe 1 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
else
|
|
group.long (0x504+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR1,Host Pipe 1 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x504+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR1,Host Pipe 1 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x504))&0x3000)==(0x00||0x2000))
|
|
group.long (0x504+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR1,Host Pipe 1 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " TXSTPE_SET/CLR ,Transmitted SETUP interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x504+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER1,Host Pipe 1 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
elif (((per.l(ad:0x40038000+0x504))&0x3000)==0x1000)
|
|
group.long (0x504+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR1,Host Pipe 1 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,CRC error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x504+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER1,Host Pipe 1 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
else
|
|
group.long (0x504+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR1,Host Pipe 1 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x504+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER1,Host Pipe 1 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
endif
|
|
group.long (0x504+0x150)++0x03
|
|
line.long 0x00 "HSTPIPINRQ1,Host Pipe 1 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN request mode" "INRQ_IN,INFINITE_IN"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN request number before freeze"
|
|
group.long (0x504+0x180)++0x03
|
|
line.long 0x00 "HSTPIPERR1,Host Pipe 1 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 error" "No error,Error"
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-out error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " PID ,PID error" "No error,Error"
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID error" "No error,Error"
|
|
bitfld.long 0x00 0. " DATATGL ,Data toggle error" "No error,Error"
|
|
tree.end
|
|
tree "Pipe 2"
|
|
if (((per.l(ad:0x40038000+0x508))&0x3000)==(0x00||0x2000))
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "HSTPIPCFG2,Host Pipe 2 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BINTERVAL ,Binterval parameter for the bulk-out/ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe endpoint number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe type" "Control,,Bulk,?..."
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe token" "SETUP,IN,OUT,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe memory allocate" "Freed,Allocated"
|
|
else
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "HSTPIPCFG2,Host Pipe 2 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTFRQ ,Pipe interrupt request frequency"
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe endpoint number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe token" "SETUP,IN,OUT,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe banks" "Single-bank,Double-bank,Triple-bank,?..."
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe memory allocate" "Freed,Allocated"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x508))&0x3000)==(0x00||0x2000))
|
|
group.long (0x508+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR2,Host Pipe 2 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " TXSTPI_SET/CLR ,Transmitted SETUP interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x508+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR2,Host Pipe 2 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
elif (((per.l(ad:0x40038000+0x508))&0x3000)==0x1000)
|
|
group.long (0x508+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR2,Host Pipe 2 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x508+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR2,Host Pipe 2 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
else
|
|
group.long (0x508+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR2,Host Pipe 2 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,BANK2,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,3_BUSY"
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x508+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR2,Host Pipe 2 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x508))&0x3000)==(0x00||0x2000))
|
|
group.long (0x508+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR2,Host Pipe 2 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " TXSTPE_SET/CLR ,Transmitted SETUP interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x508+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER2,Host Pipe 2 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
elif (((per.l(ad:0x40038000+0x508))&0x3000)==0x1000)
|
|
group.long (0x508+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR2,Host Pipe 2 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,CRC error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x508+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER2,Host Pipe 2 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
else
|
|
group.long (0x508+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR2,Host Pipe 2 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x508+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER2,Host Pipe 2 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
endif
|
|
group.long (0x508+0x150)++0x03
|
|
line.long 0x00 "HSTPIPINRQ2,Host Pipe 2 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN request mode" "INRQ_IN,INFINITE_IN"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN request number before freeze"
|
|
group.long (0x508+0x180)++0x03
|
|
line.long 0x00 "HSTPIPERR2,Host Pipe 2 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 error" "No error,Error"
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-out error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " PID ,PID error" "No error,Error"
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID error" "No error,Error"
|
|
bitfld.long 0x00 0. " DATATGL ,Data toggle error" "No error,Error"
|
|
tree.end
|
|
tree "Pipe 3"
|
|
if (((per.l(ad:0x40038000+0x50C))&0x3000)==(0x00||0x2000))
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "HSTPIPCFG3,Host Pipe 3 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BINTERVAL ,Binterval parameter for the bulk-out/ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe endpoint number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe type" "Control,,Bulk,?..."
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe token" "SETUP,IN,OUT,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe banks" "Single-bank,Double-bank,?..."
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe memory allocate" "Freed,Allocated"
|
|
else
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "HSTPIPCFG3,Host Pipe 3 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTFRQ ,Pipe interrupt request frequency"
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe endpoint number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe token" "SETUP,IN,OUT,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe banks" "Single-bank,Double-bank,?..."
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe memory allocate" "Freed,Allocated"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x50C))&0x3000)==(0x00||0x2000))
|
|
group.long (0x50C+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR3,Host Pipe 3 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " TXSTPI_SET/CLR ,Transmitted SETUP interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x50C+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR3,Host Pipe 3 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
elif (((per.l(ad:0x40038000+0x50C))&0x3000)==0x1000)
|
|
group.long (0x50C+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR3,Host Pipe 3 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x50C+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR3,Host Pipe 3 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
else
|
|
group.long (0x50C+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR3,Host Pipe 3 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x50C+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR3,Host Pipe 3 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x50C))&0x3000)==(0x00||0x2000))
|
|
group.long (0x50C+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR3,Host Pipe 3 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " TXSTPE_SET/CLR ,Transmitted SETUP interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x50C+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER3,Host Pipe 3 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
elif (((per.l(ad:0x40038000+0x50C))&0x3000)==0x1000)
|
|
group.long (0x50C+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR3,Host Pipe 3 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,CRC error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x50C+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER3,Host Pipe 3 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
else
|
|
group.long (0x50C+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR3,Host Pipe 3 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x50C+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER3,Host Pipe 3 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
endif
|
|
group.long (0x50C+0x150)++0x03
|
|
line.long 0x00 "HSTPIPINRQ3,Host Pipe 3 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN request mode" "INRQ_IN,INFINITE_IN"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN request number before freeze"
|
|
group.long (0x50C+0x180)++0x03
|
|
line.long 0x00 "HSTPIPERR3,Host Pipe 3 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 error" "No error,Error"
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-out error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " PID ,PID error" "No error,Error"
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID error" "No error,Error"
|
|
bitfld.long 0x00 0. " DATATGL ,Data toggle error" "No error,Error"
|
|
tree.end
|
|
tree "Pipe 4"
|
|
if (((per.l(ad:0x40038000+0x510))&0x3000)==(0x00||0x2000))
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "HSTPIPCFG4,Host Pipe 4 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BINTERVAL ,Binterval parameter for the bulk-out/ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe endpoint number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe type" "Control,,Bulk,?..."
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe token" "SETUP,IN,OUT,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe banks" "Single-bank,Double-bank,?..."
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe memory allocate" "Freed,Allocated"
|
|
else
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "HSTPIPCFG4,Host Pipe 4 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTFRQ ,Pipe interrupt request frequency"
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe endpoint number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe token" "SETUP,IN,OUT,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe banks" "Single-bank,Double-bank,?..."
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe memory allocate" "Freed,Allocated"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x510))&0x3000)==(0x00||0x2000))
|
|
group.long (0x510+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR4,Host Pipe 4 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " TXSTPI_SET/CLR ,Transmitted SETUP interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x510+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR4,Host Pipe 4 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
elif (((per.l(ad:0x40038000+0x510))&0x3000)==0x1000)
|
|
group.long (0x510+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR4,Host Pipe 4 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x510+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR4,Host Pipe 4 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
else
|
|
group.long (0x510+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR4,Host Pipe 4 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x510+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR4,Host Pipe 4 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x510))&0x3000)==(0x00||0x2000))
|
|
group.long (0x510+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR4,Host Pipe 4 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " TXSTPE_SET/CLR ,Transmitted SETUP interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x510+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER4,Host Pipe 4 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
elif (((per.l(ad:0x40038000+0x510))&0x3000)==0x1000)
|
|
group.long (0x510+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR4,Host Pipe 4 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,CRC error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x510+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER4,Host Pipe 4 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
else
|
|
group.long (0x510+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR4,Host Pipe 4 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x510+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER4,Host Pipe 4 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
endif
|
|
group.long (0x510+0x150)++0x03
|
|
line.long 0x00 "HSTPIPINRQ4,Host Pipe 4 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN request mode" "INRQ_IN,INFINITE_IN"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN request number before freeze"
|
|
group.long (0x510+0x180)++0x03
|
|
line.long 0x00 "HSTPIPERR4,Host Pipe 4 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 error" "No error,Error"
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-out error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " PID ,PID error" "No error,Error"
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID error" "No error,Error"
|
|
bitfld.long 0x00 0. " DATATGL ,Data toggle error" "No error,Error"
|
|
tree.end
|
|
tree "Pipe 5"
|
|
if (((per.l(ad:0x40038000+0x514))&0x3000)==(0x00||0x2000))
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "HSTPIPCFG5,Host Pipe 5 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BINTERVAL ,Binterval parameter for the bulk-out/ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe endpoint number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe type" "Control,,Bulk,?..."
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe token" "SETUP,IN,OUT,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe banks" "Single-bank,Double-bank,?..."
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe memory allocate" "Freed,Allocated"
|
|
else
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "HSTPIPCFG5,Host Pipe 5 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTFRQ ,Pipe interrupt request frequency"
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe endpoint number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe token" "SETUP,IN,OUT,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe banks" "Single-bank,Double-bank,?..."
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe memory allocate" "Freed,Allocated"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x514))&0x3000)==(0x00||0x2000))
|
|
group.long (0x514+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR5,Host Pipe 5 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " TXSTPI_SET/CLR ,Transmitted SETUP interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x514+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR5,Host Pipe 5 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
elif (((per.l(ad:0x40038000+0x514))&0x3000)==0x1000)
|
|
group.long (0x514+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR5,Host Pipe 5 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x514+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR5,Host Pipe 5 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
else
|
|
group.long (0x514+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR5,Host Pipe 5 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x514+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR5,Host Pipe 5 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x514))&0x3000)==(0x00||0x2000))
|
|
group.long (0x514+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR5,Host Pipe 5 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " TXSTPE_SET/CLR ,Transmitted SETUP interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x514+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER5,Host Pipe 5 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
elif (((per.l(ad:0x40038000+0x514))&0x3000)==0x1000)
|
|
group.long (0x514+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR5,Host Pipe 5 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,CRC error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x514+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER5,Host Pipe 5 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
else
|
|
group.long (0x514+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR5,Host Pipe 5 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x514+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER5,Host Pipe 5 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
endif
|
|
group.long (0x514+0x150)++0x03
|
|
line.long 0x00 "HSTPIPINRQ5,Host Pipe 5 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN request mode" "INRQ_IN,INFINITE_IN"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN request number before freeze"
|
|
group.long (0x514+0x180)++0x03
|
|
line.long 0x00 "HSTPIPERR5,Host Pipe 5 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 error" "No error,Error"
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-out error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " PID ,PID error" "No error,Error"
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID error" "No error,Error"
|
|
bitfld.long 0x00 0. " DATATGL ,Data toggle error" "No error,Error"
|
|
tree.end
|
|
tree "Pipe 6"
|
|
if (((per.l(ad:0x40038000+0x518))&0x3000)==(0x00||0x2000))
|
|
group.long 0x518++0x03
|
|
line.long 0x00 "HSTPIPCFG6,Host Pipe 6 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BINTERVAL ,Binterval parameter for the bulk-out/ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe endpoint number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe type" "Control,,Bulk,?..."
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe token" "SETUP,IN,OUT,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe banks" "Single-bank,Double-bank,?..."
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe memory allocate" "Freed,Allocated"
|
|
else
|
|
group.long 0x518++0x03
|
|
line.long 0x00 "HSTPIPCFG6,Host Pipe 6 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTFRQ ,Pipe interrupt request frequency"
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe endpoint number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe token" "SETUP,IN,OUT,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe banks" "Single-bank,Double-bank,?..."
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe memory allocate" "Freed,Allocated"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x518))&0x3000)==(0x00||0x2000))
|
|
group.long (0x518+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR6,Host Pipe 6 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " TXSTPI_SET/CLR ,Transmitted SETUP interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x518+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR6,Host Pipe 6 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
elif (((per.l(ad:0x40038000+0x518))&0x3000)==0x1000)
|
|
group.long (0x518+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR6,Host Pipe 6 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x518+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR6,Host Pipe 6 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
else
|
|
group.long (0x518+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR6,Host Pipe 6 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x518+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR6,Host Pipe 6 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x518))&0x3000)==(0x00||0x2000))
|
|
group.long (0x518+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR6,Host Pipe 6 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " TXSTPE_SET/CLR ,Transmitted SETUP interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x518+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER6,Host Pipe 6 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
elif (((per.l(ad:0x40038000+0x518))&0x3000)==0x1000)
|
|
group.long (0x518+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR6,Host Pipe 6 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,CRC error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x518+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER6,Host Pipe 6 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
else
|
|
group.long (0x518+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR6,Host Pipe 6 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x518+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER6,Host Pipe 6 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
endif
|
|
group.long (0x518+0x150)++0x03
|
|
line.long 0x00 "HSTPIPINRQ6,Host Pipe 6 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN request mode" "INRQ_IN,INFINITE_IN"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN request number before freeze"
|
|
group.long (0x518+0x180)++0x03
|
|
line.long 0x00 "HSTPIPERR6,Host Pipe 6 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 error" "No error,Error"
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-out error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " PID ,PID error" "No error,Error"
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID error" "No error,Error"
|
|
bitfld.long 0x00 0. " DATATGL ,Data toggle error" "No error,Error"
|
|
tree.end
|
|
tree "Pipe 7"
|
|
if (((per.l(ad:0x40038000+0x51C))&0x3000)==(0x00||0x2000))
|
|
group.long 0x51C++0x03
|
|
line.long 0x00 "HSTPIPCFG7,Host Pipe 7 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BINTERVAL ,Binterval parameter for the bulk-out/ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe endpoint number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe type" "Control,,Bulk,?..."
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe token" "SETUP,IN,OUT,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe banks" "Single-bank,Double-bank,?..."
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe memory allocate" "Freed,Allocated"
|
|
else
|
|
group.long 0x51C++0x03
|
|
line.long 0x00 "HSTPIPCFG7,Host Pipe 7 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTFRQ ,Pipe interrupt request frequency"
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe endpoint number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe token" "SETUP,IN,OUT,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe banks" "Single-bank,Double-bank,?..."
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe memory allocate" "Freed,Allocated"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x51C))&0x3000)==(0x00||0x2000))
|
|
group.long (0x51C+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR7,Host Pipe 7 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " TXSTPI_SET/CLR ,Transmitted SETUP interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x51C+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR7,Host Pipe 7 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
elif (((per.l(ad:0x40038000+0x51C))&0x3000)==0x1000)
|
|
group.long (0x51C+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR7,Host Pipe 7 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x51C+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR7,Host Pipe 7 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
else
|
|
group.long (0x51C+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR7,Host Pipe 7 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x51C+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR7,Host Pipe 7 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x51C))&0x3000)==(0x00||0x2000))
|
|
group.long (0x51C+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR7,Host Pipe 7 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " TXSTPE_SET/CLR ,Transmitted SETUP interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x51C+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER7,Host Pipe 7 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
elif (((per.l(ad:0x40038000+0x51C))&0x3000)==0x1000)
|
|
group.long (0x51C+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR7,Host Pipe 7 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,CRC error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x51C+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER7,Host Pipe 7 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
else
|
|
group.long (0x51C+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR7,Host Pipe 7 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x51C+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER7,Host Pipe 7 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
endif
|
|
group.long (0x51C+0x150)++0x03
|
|
line.long 0x00 "HSTPIPINRQ7,Host Pipe 7 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN request mode" "INRQ_IN,INFINITE_IN"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN request number before freeze"
|
|
group.long (0x51C+0x180)++0x03
|
|
line.long 0x00 "HSTPIPERR7,Host Pipe 7 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 error" "No error,Error"
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-out error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " PID ,PID error" "No error,Error"
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID error" "No error,Error"
|
|
bitfld.long 0x00 0. " DATATGL ,Data toggle error" "No error,Error"
|
|
tree.end
|
|
tree "Pipe 8"
|
|
if (((per.l(ad:0x40038000+0x520))&0x3000)==(0x00||0x2000))
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "HSTPIPCFG8,Host Pipe 8 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BINTERVAL ,Binterval parameter for the bulk-out/ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe endpoint number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe type" "Control,,Bulk,?..."
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe token" "SETUP,IN,OUT,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe banks" "Single-bank,Double-bank,?..."
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe memory allocate" "Freed,Allocated"
|
|
else
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "HSTPIPCFG8,Host Pipe 8 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTFRQ ,Pipe interrupt request frequency"
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe endpoint number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe token" "SETUP,IN,OUT,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe banks" "Single-bank,Double-bank,?..."
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe memory allocate" "Freed,Allocated"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x520))&0x3000)==(0x00||0x2000))
|
|
group.long (0x520+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR8,Host Pipe 8 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " TXSTPI_SET/CLR ,Transmitted SETUP interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x520+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR8,Host Pipe 8 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
elif (((per.l(ad:0x40038000+0x520))&0x3000)==0x1000)
|
|
group.long (0x520+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR8,Host Pipe 8 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x520+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR8,Host Pipe 8 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
else
|
|
group.long (0x520+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR8,Host Pipe 8 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x520+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR8,Host Pipe 8 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x520))&0x3000)==(0x00||0x2000))
|
|
group.long (0x520+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR8,Host Pipe 8 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " TXSTPE_SET/CLR ,Transmitted SETUP interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x520+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER8,Host Pipe 8 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
elif (((per.l(ad:0x40038000+0x520))&0x3000)==0x1000)
|
|
group.long (0x520+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR8,Host Pipe 8 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,CRC error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x520+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER8,Host Pipe 8 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
else
|
|
group.long (0x520+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR8,Host Pipe 8 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x520+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER8,Host Pipe 8 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
endif
|
|
group.long (0x520+0x150)++0x03
|
|
line.long 0x00 "HSTPIPINRQ8,Host Pipe 8 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN request mode" "INRQ_IN,INFINITE_IN"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN request number before freeze"
|
|
group.long (0x520+0x180)++0x03
|
|
line.long 0x00 "HSTPIPERR8,Host Pipe 8 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 error" "No error,Error"
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-out error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " PID ,PID error" "No error,Error"
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID error" "No error,Error"
|
|
bitfld.long 0x00 0. " DATATGL ,Data toggle error" "No error,Error"
|
|
tree.end
|
|
tree "Pipe 9"
|
|
if (((per.l(ad:0x40038000+0x524))&0x3000)==(0x00||0x2000))
|
|
group.long 0x524++0x03
|
|
line.long 0x00 "HSTPIPCFG9,Host Pipe 9 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BINTERVAL ,Binterval parameter for the bulk-out/ping transaction"
|
|
bitfld.long 0x00 20. " PINGEN ,Ping enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe endpoint number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe type" "Control,,Bulk,?..."
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe token" "SETUP,IN,OUT,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe banks" "Single-bank,Double-bank,?..."
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe memory allocate" "Freed,Allocated"
|
|
else
|
|
group.long 0x524++0x03
|
|
line.long 0x00 "HSTPIPCFG9,Host Pipe 9 Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " INTFRQ ,Pipe interrupt request frequency"
|
|
bitfld.long 0x00 16.--19. " PEPNUM ,Pipe endpoint number" "0,1,2,3,4,5,6,7,8,9,10,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PTYPE ,Pipe type" "Control,Isochronous,Bulk,Interrupt"
|
|
bitfld.long 0x00 10. " AUTOSW ,Automatic switch" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " PTOKEN ,Pipe token" "SETUP,IN,OUT,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. " PSIZE ,Pipe size" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1024 bytes"
|
|
bitfld.long 0x00 2.--3. " PBK ,Pipe banks" "Single-bank,Double-bank,?..."
|
|
bitfld.long 0x00 1. " ALLOC ,Pipe memory allocate" "Freed,Allocated"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x524))&0x3000)==(0x00||0x2000))
|
|
group.long (0x524+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR9,Host Pipe 9 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " TXSTPI_SET/CLR ,Transmitted SETUP interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x524+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR9,Host Pipe 9 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
elif (((per.l(ad:0x40038000+0x524))&0x3000)==0x1000)
|
|
group.long (0x524+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR9,Host Pipe 9 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " CRCERRI_SET/CLR ,CRC error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x524+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR9,Host Pipe 9 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
newline
|
|
else
|
|
group.long (0x524+0x30)++0x03
|
|
line.long 0x00 "HSTPIPISR9,Host Pipe 9 Status Register"
|
|
hexmask.long.word 0x00 20.--30. 1. " PBYCT ,Byte count"
|
|
bitfld.long 0x00 18. " CFGOK ,Configuration OK status" "No,Yes"
|
|
bitfld.long 0x00 16. " RWALL ,Read/write allowed" "Not allowed,Allowed"
|
|
newline
|
|
bitfld.long 0x00 14.--15. " CURRBK ,Current bank" "BANK0,BANK1,?..."
|
|
bitfld.long 0x00 12.--13. " NBUSYBK ,Number of busy banks" "0_BUSY,1_BUSY,2_BUSY,?..."
|
|
newline
|
|
rbitfld.long 0x00 8.--9. " DTSEQ ,Data toggle sequence" "DATA0,DATA1,?..."
|
|
setclrfld.long 0x00 7. 0x60 7. 0x30 7. " SHORTPACKETI_SET/CLR ,Short packet interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 6. 0x60 6. 0x30 6. " RXSTALLDI_SET/CLR ,Received STALLed interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x60 5. 0x30 5. " OVERFI_SET/CLR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 4. 0x60 4. 0x30 4. " NAKEDI_SET/CLR ,NAKed interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PERRI ,Pipe error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x60 2. 0x30 2. " UNDERFI_SET/CLR ,Underflow interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 1. 0x60 1. 0x30 1. " TXOUTI_SET/CLR ,Transmitted OUT data interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x00 0. 0x60 0. 0x30 0. " RXINI_SET/CLR ,Received IN data interrupt" "No interrupt,Interrupt"
|
|
wgroup.long (0x524+0x90)++0x03
|
|
line.long 0x00 "HSTPIPIFR9,Host Pipe 9 Set Register"
|
|
bitfld.long 0x00 12. " NBUSYBKS ,Number of busy banks interrupt set" "No effect,Set"
|
|
bitfld.long 0x00 3. " PERRIS ,Pipe error interrupt set" "No effect,Set"
|
|
endif
|
|
if (((per.l(ad:0x40038000+0x524))&0x3000)==(0x00||0x2000))
|
|
group.long (0x524+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR9,Host Pipe 9 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " TXSTPE_SET/CLR ,Transmitted SETUP interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x524+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER9,Host Pipe 9 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
elif (((per.l(ad:0x40038000+0x524))&0x3000)==0x1000)
|
|
group.long (0x524+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR9,Host Pipe 9 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " CRCERRE_SET/CLR ,CRC error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x524+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER9,Host Pipe 9 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
else
|
|
group.long (0x524+0xC0)++0x03
|
|
line.long 0x00 "HSTPIPIMR9,Host Pipe 9 Mask Register"
|
|
rbitfld.long 0x00 18. " RSTDT ,Reset data toggle" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. 0x30 17. 0x60 17. " PFREEZE_SET/CLR ,Pipe freeze" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. 0x30 16. 0x60 16. " PDISHDMA_SET/CLR ,Pipe interrupts disable HDMA request enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x30 14. 0x60 14. " FIFOCON_SET/CLR ,FIFO control" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. 0x30 12. 0x60 12. " NBUSYBKE_SET/CLR ,Number of busy banks interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 7. 0x30 7. 0x60 7. " SHORTPACKETIE_SET/CLR ,Short packet interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x30 6. 0x60 6. " RXSTALLDE_SET/CLR ,Received STALLed interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. 0x30 5. 0x60 5. " OVERFIE_SET/CLR ,Overflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. 0x30 4. 0x60 4. " NAKEDE_SET/CLR ,NAKed interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x30 3. 0x60 3. " PERRE_SET/CLR ,Pipe error interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. 0x30 2. 0x60 2. " UNDERFIE_SET/CLR ,Underflow interrupt enable" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. 0x30 1. 0x60 1. " TXOUTE_SET/CLR ,Transmitted OUT data interrupt enable" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x30 0. 0x60 0. " RXINE_SET/CLR ,Received IN data interrupt enable" "Masked,Unmasked"
|
|
wgroup.long (0x524+0xF0)++0x03
|
|
line.long 0x00 "HSTPIPIER9,Host Pipe 9 Enable Register"
|
|
bitfld.long 0x00 18. " RSTDT ,Reset data toggle" "No effect,Enabled"
|
|
endif
|
|
group.long (0x524+0x150)++0x03
|
|
line.long 0x00 "HSTPIPINRQ9,Host Pipe 9 IN Request Register"
|
|
bitfld.long 0x00 8. " INMODE ,IN request mode" "INRQ_IN,INFINITE_IN"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INRQ ,IN request number before freeze"
|
|
group.long (0x524+0x180)++0x03
|
|
line.long 0x00 "HSTPIPERR9,Host Pipe 9 Error Register"
|
|
bitfld.long 0x00 5.--6. " COUNTER ,Error counter" "0,1,2,3"
|
|
bitfld.long 0x00 4. " CRC16 ,CRC16 error" "No error,Error"
|
|
bitfld.long 0x00 3. " TIMEOUT ,Time-out error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 2. " PID ,PID error" "No error,Error"
|
|
bitfld.long 0x00 1. " DATAPID ,Data PID error" "No error,Error"
|
|
bitfld.long 0x00 0. " DATATGL ,Data toggle error" "No error,Error"
|
|
tree.end
|
|
width 16.
|
|
tree "DMA channel 1"
|
|
group.long 0x700++0x07
|
|
line.long 0x00 "HSTDMANXTDSC1,Host DMA Channel 1 Next Descriptor Address Register"
|
|
line.long 0x04 "HSTDMAADDRESS1,Host DMA Channel 1 Address Register"
|
|
if (((per.l(ad:0x40038000+0x700+0x08))&0x03)!=0x00)
|
|
group.long (0x700+0x08)++0x03
|
|
line.long 0x00 "HSTDMACONTROL1,Host DMA Channel 1 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
bitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
else
|
|
group.long (0x700+0x08)++0x03
|
|
line.long 0x00 "HSTDMACONTROL1,Host DMA Channel 1 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
rbitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
endif
|
|
hgroup.long (0x700+0x0C)++0x03
|
|
hide.long 0x00 "HSTDMASTATUS1,Host DMA Channel 1 Status Register"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 2"
|
|
group.long 0x710++0x07
|
|
line.long 0x00 "HSTDMANXTDSC2,Host DMA Channel 2 Next Descriptor Address Register"
|
|
line.long 0x04 "HSTDMAADDRESS2,Host DMA Channel 2 Address Register"
|
|
if (((per.l(ad:0x40038000+0x710+0x08))&0x03)!=0x00)
|
|
group.long (0x710+0x08)++0x03
|
|
line.long 0x00 "HSTDMACONTROL2,Host DMA Channel 2 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
bitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
else
|
|
group.long (0x710+0x08)++0x03
|
|
line.long 0x00 "HSTDMACONTROL2,Host DMA Channel 2 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
rbitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
endif
|
|
hgroup.long (0x710+0x0C)++0x03
|
|
hide.long 0x00 "HSTDMASTATUS2,Host DMA Channel 2 Status Register"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 3"
|
|
group.long 0x720++0x07
|
|
line.long 0x00 "HSTDMANXTDSC3,Host DMA Channel 3 Next Descriptor Address Register"
|
|
line.long 0x04 "HSTDMAADDRESS3,Host DMA Channel 3 Address Register"
|
|
if (((per.l(ad:0x40038000+0x720+0x08))&0x03)!=0x00)
|
|
group.long (0x720+0x08)++0x03
|
|
line.long 0x00 "HSTDMACONTROL3,Host DMA Channel 3 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
bitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
else
|
|
group.long (0x720+0x08)++0x03
|
|
line.long 0x00 "HSTDMACONTROL3,Host DMA Channel 3 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
rbitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
endif
|
|
hgroup.long (0x720+0x0C)++0x03
|
|
hide.long 0x00 "HSTDMASTATUS3,Host DMA Channel 3 Status Register"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 4"
|
|
group.long 0x730++0x07
|
|
line.long 0x00 "HSTDMANXTDSC4,Host DMA Channel 4 Next Descriptor Address Register"
|
|
line.long 0x04 "HSTDMAADDRESS4,Host DMA Channel 4 Address Register"
|
|
if (((per.l(ad:0x40038000+0x730+0x08))&0x03)!=0x00)
|
|
group.long (0x730+0x08)++0x03
|
|
line.long 0x00 "HSTDMACONTROL4,Host DMA Channel 4 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
bitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
else
|
|
group.long (0x730+0x08)++0x03
|
|
line.long 0x00 "HSTDMACONTROL4,Host DMA Channel 4 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
rbitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
endif
|
|
hgroup.long (0x730+0x0C)++0x03
|
|
hide.long 0x00 "HSTDMASTATUS4,Host DMA Channel 4 Status Register"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 5"
|
|
group.long 0x740++0x07
|
|
line.long 0x00 "HSTDMANXTDSC5,Host DMA Channel 5 Next Descriptor Address Register"
|
|
line.long 0x04 "HSTDMAADDRESS5,Host DMA Channel 5 Address Register"
|
|
if (((per.l(ad:0x40038000+0x740+0x08))&0x03)!=0x00)
|
|
group.long (0x740+0x08)++0x03
|
|
line.long 0x00 "HSTDMACONTROL5,Host DMA Channel 5 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
bitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
else
|
|
group.long (0x740+0x08)++0x03
|
|
line.long 0x00 "HSTDMACONTROL5,Host DMA Channel 5 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
rbitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
endif
|
|
hgroup.long (0x740+0x0C)++0x03
|
|
hide.long 0x00 "HSTDMASTATUS5,Host DMA Channel 5 Status Register"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 6"
|
|
group.long 0x750++0x07
|
|
line.long 0x00 "HSTDMANXTDSC6,Host DMA Channel 6 Next Descriptor Address Register"
|
|
line.long 0x04 "HSTDMAADDRESS6,Host DMA Channel 6 Address Register"
|
|
if (((per.l(ad:0x40038000+0x750+0x08))&0x03)!=0x00)
|
|
group.long (0x750+0x08)++0x03
|
|
line.long 0x00 "HSTDMACONTROL6,Host DMA Channel 6 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
bitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
else
|
|
group.long (0x750+0x08)++0x03
|
|
line.long 0x00 "HSTDMACONTROL6,Host DMA Channel 6 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
rbitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
endif
|
|
hgroup.long (0x750+0x0C)++0x03
|
|
hide.long 0x00 "HSTDMASTATUS6,Host DMA Channel 6 Status Register"
|
|
in
|
|
tree.end
|
|
tree "DMA channel 7"
|
|
group.long 0x760++0x07
|
|
line.long 0x00 "HSTDMANXTDSC7,Host DMA Channel 7 Next Descriptor Address Register"
|
|
line.long 0x04 "HSTDMAADDRESS7,Host DMA Channel 7 Address Register"
|
|
if (((per.l(ad:0x40038000+0x760+0x08))&0x03)!=0x00)
|
|
group.long (0x760+0x08)++0x03
|
|
line.long 0x00 "HSTDMACONTROL7,Host DMA Channel 7 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
bitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
else
|
|
group.long (0x760+0x08)++0x03
|
|
line.long 0x00 "HSTDMACONTROL7,Host DMA Channel 7 Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BUFF_LENGTH ,Buffer byte length"
|
|
rbitfld.long 0x00 7. " BURST_LCK ,Burst lock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " DESC_LD_IT ,Descriptor loaded interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " END_BUFFIT ,End of buffer interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4. " END_TR_IT ,End of transfer interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " END_B_EN ,End of buffer enable control" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " END_TR_EN ,End of transfer enable control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CHANN_ENB/LDNXT_DSC ,DMA channel control command (channel enable command/load next channel transfer descriptor enable)" "STOP_NOW,RUN_AND_STOP,LOAD_NEXT_DESC,RUN_AND_LINK"
|
|
newline
|
|
endif
|
|
hgroup.long (0x760+0x0C)++0x03
|
|
hide.long 0x00 "HSTDMASTATUS7,Host DMA Channel 7 Status Register"
|
|
in
|
|
tree.end
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("ATSAMS70J*")
|
|
tree "HSMCI (High Speed MultiMedia Card Interface)"
|
|
base ad:0x40000000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,MCI Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 3. " PWSDIS ,Power save mode disable" "No effect,Yes"
|
|
bitfld.long 0x00 2. " PWSEN ,Power save mode enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " MCIDIS ,Multi-media interface disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 0. " MCIEN ,Multi-media interface enable" "No effect,Enable"
|
|
if ((per.l(ad:0x40000000+0xE4)&0x01)==0x00)
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "MR,MCI Mode Register"
|
|
sif cpuis("ATSAM4S*")
|
|
bitfld.long 0x00 15. " PDCMODE ,PDC-oriented mode" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 16. " CLKODD ,Clock divider is odd" "Even,Odd"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " PADV ,Padding value" "0x00,0xFF"
|
|
bitfld.long 0x00 13. " FBYTE ,Force byte transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WRPROOF ,Write proof enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDPROOF ,Read proof enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " PWSDIV ,Power saving divider" "Clock/2,Clock/3,Clock/5,Clock/9,Clock/17,Clock/33,Clock/65,Clock/129"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKDIV ,Clock divider"
|
|
line.long 0x04 "DTOR,MCI Data Timeout Register"
|
|
bitfld.long 0x04 4.--6. " DTOMUL ,Data timeout multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x04 0.--3. " DTOCYC ,Data timeout cycle number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "SDCR,MCI SDCard Register"
|
|
bitfld.long 0x08 6.--7. " SDCBUS ,SDCard bus width" "1-bit,,4-bit,8-bit"
|
|
sif cpuis("ATSAMA5D4*")
|
|
bitfld.long 0x08 0.--1. " SDCSEL ,SDCard slot" "A,B,?..."
|
|
else
|
|
bitfld.long 0x08 0.--1. " SDCSEL ,SDCard slot" "A,?..."
|
|
endif
|
|
else
|
|
rgroup.long 0x04++0x0B
|
|
line.long 0x00 "MR,MCI Mode Register"
|
|
sif cpuis("ATSAM4S*")
|
|
bitfld.long 0x00 15. " PDCMODE ,PDC-oriented mode" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 16. " CLKODD ,Clock divider is odd" "Even,Odd"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 14. " PADV ,Padding value" "0x00,0xFF"
|
|
bitfld.long 0x00 13. " FBYTE ,Force byte transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WRPROOF ,Write proof enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " RDPROOF ,Read proof enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " PWSDIV ,Power saving divider" "Clock/2,Clock/3,Clock/5,Clock/9,Clock/17,Clock/33,Clock/65,Clock/129"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKDIV ,Clock divider"
|
|
line.long 0x04 "DTOR,MCI Data Timeout Register"
|
|
bitfld.long 0x04 4.--6. " DTOMUL ,Data timeout multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x04 0.--3. " DTOCYC ,Data timeout cycle number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "SDCR,MCI SDCard Register"
|
|
bitfld.long 0x08 6.--7. " SDCBUS ,SDCard bus width" "1-bit,,4-bit,8-bit"
|
|
sif cpuis("ATSAMA5D4*")
|
|
bitfld.long 0x08 0.--1. " SDCSEL ,SDCard slot" "A,B,?..."
|
|
else
|
|
bitfld.long 0x08 0.--1. " SDCSEL ,SDCard slot" "A,?..."
|
|
endif
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ARGR,MCI Argument Register"
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "CMDR,MCI Command Register"
|
|
bitfld.long 0x00 27. " BOOT_ACK ,Boot operation acknowledge" "Not expected,Expected"
|
|
bitfld.long 0x00 26. " ATACS ,ATA with command completion signal" "Normal,With completion"
|
|
bitfld.long 0x00 24.--25. " IOSPCMD ,SDIO special command" "Not Special,SDIO suspend,SDIO resume,?..."
|
|
bitfld.long 0x00 19.--21. " TRTYP ,Transfer type" "Single block,Multiple block,Stream,,SDIO byte,SDIO block,?..."
|
|
newline
|
|
bitfld.long 0x00 18. " TRDIR ,Transfer direction" "Write,Read"
|
|
bitfld.long 0x00 16.--17. " TRCMD ,Transfer command" "No transfer,Start,Stop,?..."
|
|
bitfld.long 0x00 12. " MAXLAT ,Max latency for command to response" "5-cycle,64-cycle"
|
|
bitfld.long 0x00 11. " OPDCMD ,Open drain command" "Push pull,Open drain"
|
|
newline
|
|
bitfld.long 0x00 8.--10. " SPCMD ,Special command" "STD,INIT,SYNC,CE-ATA,IT_CMD,INT_RESP,BOR,EBO"
|
|
bitfld.long 0x00 6.--7. " RSPTYP ,Response type" "No response,48-bit,136-bit,R1b"
|
|
bitfld.long 0x00 0.--5. " CMDNB ,Command number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "BLKR,Block Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " BLKLEN ,Data block length"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCNT ,MMC/SDIO block count - SDIO byte count"
|
|
if ((per.l(ad:0x40000000+0xE4)&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CSTOR,HSMCI Completion Signal Timeout Register"
|
|
bitfld.long 0x00 4.--6. " CSTOMUL ,Completion signal timeout multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x00 0.--3. " CSTOCYC ,Completion signal timeout cycle number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "CSTOR,HSMCI Completion Signal Timeout Register"
|
|
bitfld.long 0x00 4.--6. " CSTOMUL ,Completion signal timeout multiplier" "1,16,128,256,1024,4096,65536,1048576"
|
|
bitfld.long 0x00 0.--3. " CSTOCYC ,Completion signal timeout cycle number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RSPR0,HSMCI Response Register 0"
|
|
in
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "RSPR1,HSMCI Response Register 1"
|
|
in
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "RSPR2,HSMCI Response Register 2"
|
|
in
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "RSPR3,HSMCI Response Register 3"
|
|
in
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "RDR,HSMCI Receive Data Register"
|
|
in
|
|
newline
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "TDR,HSMCI Transmit Data Register"
|
|
newline
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SR,HSMCI Status Register"
|
|
in
|
|
newline
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,MCI Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " UNRE ,UnderRun interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " OVRE ,Overrun interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " ACKRCVE ,Boot operation acknowledge error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " ACKRCV ,Boot operation acknowledge received interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " XFRDONE ,Transfer done interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " FIFOEMPTY ,FIFO empty interrupt mask" "Masked,Not masked"
|
|
newline
|
|
sif cpuis("ATSAMA5D31")||cpuis("ATSAMA5D34")||cpuis("ATSAMA5D35")||cpuis("ATSAMA5D36")
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " DMADONE ,DMA transfer completed interrupt mask" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
sif !cpuis("ATSAM4S*")
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " BLKOVRE ,DMA block overrun error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " CSTOE ,Completion signal time-out error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " DTOE ,Data time-out error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " DCRCE ,Data CRC error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " RTOE ,Response time-out error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " RENDE ,Response end bit error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " RCRCE ,Response CRC error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " RDIRE ,Response direction error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " RINDE ,Response index error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
sif (cpuis("ATSAM4S*")||cpuis("ATSAM4E*"))
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " TXBUFE ,Transmit buffer empty interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " RXBUFF ,Receive buffer full interrupt mask" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " CSRCV ,Completion signal received interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " SDIOWAIT ,SDIO read wait operation status interrupt mask" "Masked,Not masked"
|
|
newline
|
|
sif cpuis("ATSAMA5D4*")
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " SDIOIRQB ,SDIO interrupt for slot B interrupt mask" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
sif cpuis("ATSAM4S*")
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " SDIOIRQA ,SDIO interrupt for slot A interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ENDTX ,End of transmit buffer interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ENDRX ,End of receive buffer interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " NOTBUSY ,Data not busy interrupt mask" "Masked,Not masked"
|
|
newline
|
|
else
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " SDIOIRQA ,SDIO interrupt for slot A interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " NOTBUSY ,Data not busy interrupt mask" "Masked,Not masked"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " DTIP ,Data transfer in progress interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " BLKE ,Data block ended interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXRDY ,Transmit ready interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY ,Receiver ready interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CMDRDY ,Command ready interrupt mask" "Masked,Not masked"
|
|
newline
|
|
if ((per.l(ad:0x40000000+0xE4)&0x01)==0x00)
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS70*")||cpuis("ATSAME70*")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DMA,HSMCI DMA Configuration Register"
|
|
bitfld.long 0x00 8. " DMAEN ,DMA hardware handshaking enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " CHKSIZE ,DMA channel read and write chunk size" "1,2,4,8,16,?..."
|
|
elif cpuis("ATSAMA5D3*")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DMA,HSMCI DMA Configuration Register"
|
|
bitfld.long 0x00 12. " ROPT ,Read optimization with padding" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DMAEN ,DMA hardware handshaking enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CHKSIZE ,DMA channel read and write chunk size" "1,4,8,16,32,?..."
|
|
bitfld.long 0x00 0.--1. " OFFSET ,DMA write buffer offset" "0,1,2,3"
|
|
endif
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CFG,HSMCI Configuration Register"
|
|
bitfld.long 0x00 12. " LSYNC ,Synchronize on the last block" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " HSMODE ,High speed mode" "Normal,High"
|
|
newline
|
|
bitfld.long 0x00 4. " FERRCTRL ,Flow error flag reset control mode" "Write/read command,Read status"
|
|
bitfld.long 0x00 0. " FIFOMODE ,HSMCI internal FIFO control mode" "Sufficient level,One data written"
|
|
else
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS70*")||cpuis("ATSAME70*")
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "DMA,HSMCI DMA Configuration Register"
|
|
bitfld.long 0x00 8. " DMAEN ,DMA hardware handshaking enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " CHKSIZE ,DMA channel read and write chunk size" "1,2,4,8,16,?..."
|
|
elif cpuis("ATSAMA5D3*")
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "DMA,HSMCI DMA Configuration Register"
|
|
bitfld.long 0x00 12. " ROPT ,Read optimization with padding" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DMAEN ,DMA hardware handshaking enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. " CHKSIZE ,DMA channel read and write chunk size" "1,4,8,16,32,?..."
|
|
bitfld.long 0x00 0.--1. " OFFSET ,DMA write buffer offset" "0,1,2,3"
|
|
endif
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "CFG,HSMCI Configuration Register"
|
|
bitfld.long 0x00 12. " LSYNC ,Synchronize on the last block" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " HSMODE ,High speed mode" "Normal,High"
|
|
newline
|
|
bitfld.long 0x00 4. " FERRCTRL ,Flow error flag reset control mode" "Write/read command,Read status"
|
|
bitfld.long 0x00 0. " FIFOMODE ,HSMCI internal FIFO control mode" "Sufficient level,One data written"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,HSMCI Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect key"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,HSMCI Write Protect Status Register"
|
|
in
|
|
newline
|
|
width 9.
|
|
tree "HSMCI FIFO Memory Aperture"
|
|
hgroup.long 0x200++0x03
|
|
hide.long 0x00 "FIFO0,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x204++0x03
|
|
hide.long 0x00 "FIFO1,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x208++0x03
|
|
hide.long 0x00 "FIFO2,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x20C++0x03
|
|
hide.long 0x00 "FIFO3,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "FIFO4,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x214++0x03
|
|
hide.long 0x00 "FIFO5,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x218++0x03
|
|
hide.long 0x00 "FIFO6,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "FIFO7,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x220++0x03
|
|
hide.long 0x00 "FIFO8,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x224++0x03
|
|
hide.long 0x00 "FIFO9,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x228++0x03
|
|
hide.long 0x00 "FIFO10,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x22C++0x03
|
|
hide.long 0x00 "FIFO11,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x230++0x03
|
|
hide.long 0x00 "FIFO12,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x234++0x03
|
|
hide.long 0x00 "FIFO13,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x238++0x03
|
|
hide.long 0x00 "FIFO14,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x23C++0x03
|
|
hide.long 0x00 "FIFO15,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x240++0x03
|
|
hide.long 0x00 "FIFO16,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x244++0x03
|
|
hide.long 0x00 "FIFO17,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x248++0x03
|
|
hide.long 0x00 "FIFO18,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x24C++0x03
|
|
hide.long 0x00 "FIFO19,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x250++0x03
|
|
hide.long 0x00 "FIFO20,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x254++0x03
|
|
hide.long 0x00 "FIFO21,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x258++0x03
|
|
hide.long 0x00 "FIFO22,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x25C++0x03
|
|
hide.long 0x00 "FIFO23,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x260++0x03
|
|
hide.long 0x00 "FIFO24,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x264++0x03
|
|
hide.long 0x00 "FIFO25,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x268++0x03
|
|
hide.long 0x00 "FIFO26,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x26C++0x03
|
|
hide.long 0x00 "FIFO27,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x270++0x03
|
|
hide.long 0x00 "FIFO28,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x274++0x03
|
|
hide.long 0x00 "FIFO29,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x278++0x03
|
|
hide.long 0x00 "FIFO30,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x27C++0x03
|
|
hide.long 0x00 "FIFO31,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x280++0x03
|
|
hide.long 0x00 "FIFO32,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x284++0x03
|
|
hide.long 0x00 "FIFO33,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x288++0x03
|
|
hide.long 0x00 "FIFO34,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x28C++0x03
|
|
hide.long 0x00 "FIFO35,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x290++0x03
|
|
hide.long 0x00 "FIFO36,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x294++0x03
|
|
hide.long 0x00 "FIFO37,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x298++0x03
|
|
hide.long 0x00 "FIFO38,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x29C++0x03
|
|
hide.long 0x00 "FIFO39,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2A0++0x03
|
|
hide.long 0x00 "FIFO40,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2A4++0x03
|
|
hide.long 0x00 "FIFO41,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2A8++0x03
|
|
hide.long 0x00 "FIFO42,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2AC++0x03
|
|
hide.long 0x00 "FIFO43,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2B0++0x03
|
|
hide.long 0x00 "FIFO44,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2B4++0x03
|
|
hide.long 0x00 "FIFO45,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2B8++0x03
|
|
hide.long 0x00 "FIFO46,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2BC++0x03
|
|
hide.long 0x00 "FIFO47,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2C0++0x03
|
|
hide.long 0x00 "FIFO48,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2C4++0x03
|
|
hide.long 0x00 "FIFO49,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2C8++0x03
|
|
hide.long 0x00 "FIFO50,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2CC++0x03
|
|
hide.long 0x00 "FIFO51,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2D0++0x03
|
|
hide.long 0x00 "FIFO52,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2D4++0x03
|
|
hide.long 0x00 "FIFO53,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2D8++0x03
|
|
hide.long 0x00 "FIFO54,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2DC++0x03
|
|
hide.long 0x00 "FIFO55,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2E0++0x03
|
|
hide.long 0x00 "FIFO56,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2E4++0x03
|
|
hide.long 0x00 "FIFO57,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2E8++0x03
|
|
hide.long 0x00 "FIFO58,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2EC++0x03
|
|
hide.long 0x00 "FIFO59,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2F0++0x03
|
|
hide.long 0x00 "FIFO60,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2F4++0x03
|
|
hide.long 0x00 "FIFO61,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2F8++0x03
|
|
hide.long 0x00 "FIFO62,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x2FC++0x03
|
|
hide.long 0x00 "FIFO63,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x300++0x03
|
|
hide.long 0x00 "FIFO64,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "FIFO65,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x308++0x03
|
|
hide.long 0x00 "FIFO66,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x30C++0x03
|
|
hide.long 0x00 "FIFO67,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "FIFO68,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x314++0x03
|
|
hide.long 0x00 "FIFO69,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x318++0x03
|
|
hide.long 0x00 "FIFO70,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x31C++0x03
|
|
hide.long 0x00 "FIFO71,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x320++0x03
|
|
hide.long 0x00 "FIFO72,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x324++0x03
|
|
hide.long 0x00 "FIFO73,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x328++0x03
|
|
hide.long 0x00 "FIFO74,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x32C++0x03
|
|
hide.long 0x00 "FIFO75,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x330++0x03
|
|
hide.long 0x00 "FIFO76,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x334++0x03
|
|
hide.long 0x00 "FIFO77,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x338++0x03
|
|
hide.long 0x00 "FIFO78,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x33C++0x03
|
|
hide.long 0x00 "FIFO79,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x340++0x03
|
|
hide.long 0x00 "FIFO80,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x344++0x03
|
|
hide.long 0x00 "FIFO81,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x348++0x03
|
|
hide.long 0x00 "FIFO82,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x34C++0x03
|
|
hide.long 0x00 "FIFO83,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x350++0x03
|
|
hide.long 0x00 "FIFO84,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x354++0x03
|
|
hide.long 0x00 "FIFO85,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x358++0x03
|
|
hide.long 0x00 "FIFO86,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x35C++0x03
|
|
hide.long 0x00 "FIFO87,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x360++0x03
|
|
hide.long 0x00 "FIFO88,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x364++0x03
|
|
hide.long 0x00 "FIFO89,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x368++0x03
|
|
hide.long 0x00 "FIFO90,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x36C++0x03
|
|
hide.long 0x00 "FIFO91,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x370++0x03
|
|
hide.long 0x00 "FIFO92,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x374++0x03
|
|
hide.long 0x00 "FIFO93,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x378++0x03
|
|
hide.long 0x00 "FIFO94,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x37C++0x03
|
|
hide.long 0x00 "FIFO95,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x380++0x03
|
|
hide.long 0x00 "FIFO96,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x384++0x03
|
|
hide.long 0x00 "FIFO97,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x388++0x03
|
|
hide.long 0x00 "FIFO98,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x38C++0x03
|
|
hide.long 0x00 "FIFO99,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "FIFO100,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x394++0x03
|
|
hide.long 0x00 "FIFO101,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x398++0x03
|
|
hide.long 0x00 "FIFO102,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x39C++0x03
|
|
hide.long 0x00 "FIFO103,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3A0++0x03
|
|
hide.long 0x00 "FIFO104,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3A4++0x03
|
|
hide.long 0x00 "FIFO105,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3A8++0x03
|
|
hide.long 0x00 "FIFO106,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3AC++0x03
|
|
hide.long 0x00 "FIFO107,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3B0++0x03
|
|
hide.long 0x00 "FIFO108,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3B4++0x03
|
|
hide.long 0x00 "FIFO109,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3B8++0x03
|
|
hide.long 0x00 "FIFO110,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3BC++0x03
|
|
hide.long 0x00 "FIFO111,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3C0++0x03
|
|
hide.long 0x00 "FIFO112,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3C4++0x03
|
|
hide.long 0x00 "FIFO113,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3C8++0x03
|
|
hide.long 0x00 "FIFO114,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3CC++0x03
|
|
hide.long 0x00 "FIFO115,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3D0++0x03
|
|
hide.long 0x00 "FIFO116,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3D4++0x03
|
|
hide.long 0x00 "FIFO117,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3D8++0x03
|
|
hide.long 0x00 "FIFO118,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3DC++0x03
|
|
hide.long 0x00 "FIFO119,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3E0++0x03
|
|
hide.long 0x00 "FIFO120,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3E4++0x03
|
|
hide.long 0x00 "FIFO121,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3E8++0x03
|
|
hide.long 0x00 "FIFO122,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3EC++0x03
|
|
hide.long 0x00 "FIFO123,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3F0++0x03
|
|
hide.long 0x00 "FIFO124,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3F4++0x03
|
|
hide.long 0x00 "FIFO125,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3F8++0x03
|
|
hide.long 0x00 "FIFO126,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x3FC++0x03
|
|
hide.long 0x00 "FIFO127,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x400++0x03
|
|
hide.long 0x00 "FIFO128,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x404++0x03
|
|
hide.long 0x00 "FIFO129,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x408++0x03
|
|
hide.long 0x00 "FIFO130,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x40C++0x03
|
|
hide.long 0x00 "FIFO131,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x410++0x03
|
|
hide.long 0x00 "FIFO132,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x414++0x03
|
|
hide.long 0x00 "FIFO133,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x418++0x03
|
|
hide.long 0x00 "FIFO134,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x41C++0x03
|
|
hide.long 0x00 "FIFO135,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x420++0x03
|
|
hide.long 0x00 "FIFO136,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x424++0x03
|
|
hide.long 0x00 "FIFO137,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x428++0x03
|
|
hide.long 0x00 "FIFO138,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x42C++0x03
|
|
hide.long 0x00 "FIFO139,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x430++0x03
|
|
hide.long 0x00 "FIFO140,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x434++0x03
|
|
hide.long 0x00 "FIFO141,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x438++0x03
|
|
hide.long 0x00 "FIFO142,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x43C++0x03
|
|
hide.long 0x00 "FIFO143,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x440++0x03
|
|
hide.long 0x00 "FIFO144,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x444++0x03
|
|
hide.long 0x00 "FIFO145,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x448++0x03
|
|
hide.long 0x00 "FIFO146,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x44C++0x03
|
|
hide.long 0x00 "FIFO147,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x450++0x03
|
|
hide.long 0x00 "FIFO148,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x454++0x03
|
|
hide.long 0x00 "FIFO149,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x458++0x03
|
|
hide.long 0x00 "FIFO150,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x45C++0x03
|
|
hide.long 0x00 "FIFO151,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x460++0x03
|
|
hide.long 0x00 "FIFO152,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x464++0x03
|
|
hide.long 0x00 "FIFO153,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x468++0x03
|
|
hide.long 0x00 "FIFO154,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x46C++0x03
|
|
hide.long 0x00 "FIFO155,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x470++0x03
|
|
hide.long 0x00 "FIFO156,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x474++0x03
|
|
hide.long 0x00 "FIFO157,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x478++0x03
|
|
hide.long 0x00 "FIFO158,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x47C++0x03
|
|
hide.long 0x00 "FIFO159,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x480++0x03
|
|
hide.long 0x00 "FIFO160,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x484++0x03
|
|
hide.long 0x00 "FIFO161,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x488++0x03
|
|
hide.long 0x00 "FIFO162,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x48C++0x03
|
|
hide.long 0x00 "FIFO163,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x490++0x03
|
|
hide.long 0x00 "FIFO164,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x494++0x03
|
|
hide.long 0x00 "FIFO165,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x498++0x03
|
|
hide.long 0x00 "FIFO166,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x49C++0x03
|
|
hide.long 0x00 "FIFO167,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4A0++0x03
|
|
hide.long 0x00 "FIFO168,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4A4++0x03
|
|
hide.long 0x00 "FIFO169,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4A8++0x03
|
|
hide.long 0x00 "FIFO170,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4AC++0x03
|
|
hide.long 0x00 "FIFO171,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4B0++0x03
|
|
hide.long 0x00 "FIFO172,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4B4++0x03
|
|
hide.long 0x00 "FIFO173,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4B8++0x03
|
|
hide.long 0x00 "FIFO174,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4BC++0x03
|
|
hide.long 0x00 "FIFO175,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4C0++0x03
|
|
hide.long 0x00 "FIFO176,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4C4++0x03
|
|
hide.long 0x00 "FIFO177,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4C8++0x03
|
|
hide.long 0x00 "FIFO178,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4CC++0x03
|
|
hide.long 0x00 "FIFO179,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4D0++0x03
|
|
hide.long 0x00 "FIFO180,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4D4++0x03
|
|
hide.long 0x00 "FIFO181,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4D8++0x03
|
|
hide.long 0x00 "FIFO182,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4DC++0x03
|
|
hide.long 0x00 "FIFO183,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4E0++0x03
|
|
hide.long 0x00 "FIFO184,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4E4++0x03
|
|
hide.long 0x00 "FIFO185,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4E8++0x03
|
|
hide.long 0x00 "FIFO186,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4EC++0x03
|
|
hide.long 0x00 "FIFO187,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4F0++0x03
|
|
hide.long 0x00 "FIFO188,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4F4++0x03
|
|
hide.long 0x00 "FIFO189,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4F8++0x03
|
|
hide.long 0x00 "FIFO190,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x4FC++0x03
|
|
hide.long 0x00 "FIFO191,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x500++0x03
|
|
hide.long 0x00 "FIFO192,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x504++0x03
|
|
hide.long 0x00 "FIFO193,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x508++0x03
|
|
hide.long 0x00 "FIFO194,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x50C++0x03
|
|
hide.long 0x00 "FIFO195,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x510++0x03
|
|
hide.long 0x00 "FIFO196,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x514++0x03
|
|
hide.long 0x00 "FIFO197,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x518++0x03
|
|
hide.long 0x00 "FIFO198,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x51C++0x03
|
|
hide.long 0x00 "FIFO199,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x520++0x03
|
|
hide.long 0x00 "FIFO200,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x524++0x03
|
|
hide.long 0x00 "FIFO201,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x528++0x03
|
|
hide.long 0x00 "FIFO202,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x52C++0x03
|
|
hide.long 0x00 "FIFO203,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x530++0x03
|
|
hide.long 0x00 "FIFO204,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x534++0x03
|
|
hide.long 0x00 "FIFO205,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x538++0x03
|
|
hide.long 0x00 "FIFO206,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x53C++0x03
|
|
hide.long 0x00 "FIFO207,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x540++0x03
|
|
hide.long 0x00 "FIFO208,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x544++0x03
|
|
hide.long 0x00 "FIFO209,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x548++0x03
|
|
hide.long 0x00 "FIFO210,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x54C++0x03
|
|
hide.long 0x00 "FIFO211,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x550++0x03
|
|
hide.long 0x00 "FIFO212,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x554++0x03
|
|
hide.long 0x00 "FIFO213,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x558++0x03
|
|
hide.long 0x00 "FIFO214,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x55C++0x03
|
|
hide.long 0x00 "FIFO215,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x560++0x03
|
|
hide.long 0x00 "FIFO216,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x564++0x03
|
|
hide.long 0x00 "FIFO217,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x568++0x03
|
|
hide.long 0x00 "FIFO218,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x56C++0x03
|
|
hide.long 0x00 "FIFO219,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x570++0x03
|
|
hide.long 0x00 "FIFO220,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x574++0x03
|
|
hide.long 0x00 "FIFO221,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x578++0x03
|
|
hide.long 0x00 "FIFO222,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x57C++0x03
|
|
hide.long 0x00 "FIFO223,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x580++0x03
|
|
hide.long 0x00 "FIFO224,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x584++0x03
|
|
hide.long 0x00 "FIFO225,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x588++0x03
|
|
hide.long 0x00 "FIFO226,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x58C++0x03
|
|
hide.long 0x00 "FIFO227,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x590++0x03
|
|
hide.long 0x00 "FIFO228,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x594++0x03
|
|
hide.long 0x00 "FIFO229,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x598++0x03
|
|
hide.long 0x00 "FIFO230,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x59C++0x03
|
|
hide.long 0x00 "FIFO231,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5A0++0x03
|
|
hide.long 0x00 "FIFO232,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5A4++0x03
|
|
hide.long 0x00 "FIFO233,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5A8++0x03
|
|
hide.long 0x00 "FIFO234,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5AC++0x03
|
|
hide.long 0x00 "FIFO235,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5B0++0x03
|
|
hide.long 0x00 "FIFO236,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5B4++0x03
|
|
hide.long 0x00 "FIFO237,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5B8++0x03
|
|
hide.long 0x00 "FIFO238,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5BC++0x03
|
|
hide.long 0x00 "FIFO239,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5C0++0x03
|
|
hide.long 0x00 "FIFO240,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5C4++0x03
|
|
hide.long 0x00 "FIFO241,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5C8++0x03
|
|
hide.long 0x00 "FIFO242,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5CC++0x03
|
|
hide.long 0x00 "FIFO243,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5D0++0x03
|
|
hide.long 0x00 "FIFO244,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5D4++0x03
|
|
hide.long 0x00 "FIFO245,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5D8++0x03
|
|
hide.long 0x00 "FIFO246,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5DC++0x03
|
|
hide.long 0x00 "FIFO247,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5E0++0x03
|
|
hide.long 0x00 "FIFO248,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5E4++0x03
|
|
hide.long 0x00 "FIFO249,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5E8++0x03
|
|
hide.long 0x00 "FIFO250,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5EC++0x03
|
|
hide.long 0x00 "FIFO251,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5F0++0x03
|
|
hide.long 0x00 "FIFO252,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5F4++0x03
|
|
hide.long 0x00 "FIFO253,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5F8++0x03
|
|
hide.long 0x00 "FIFO254,HSMCI FIFO Memory Aperture"
|
|
in
|
|
hgroup.long 0x5FC++0x03
|
|
hide.long 0x00 "FIFO255,HSMCI FIFO Memory Aperture"
|
|
in
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif !cpuis("ATSAMS70J*")
|
|
sif cpuis("ATSAMS70Q*")
|
|
tree.open "SPI (Serial Peripheral Interface)"
|
|
tree "SPI 0"
|
|
base ad:0x40008000
|
|
width 13.
|
|
if ((per.l(ad:0x40008000+0xE4)&0x04)==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 12. " REQCLR ,Request to clear the comparison trigger" "No request,Request"
|
|
bitfld.long 0x00 7. " SWRST ,SPI software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI disable" "No effect,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " SPIEN ,SPI enable" "No effect,Enable"
|
|
else
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "CR,SPI Control Register"
|
|
endif
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
if (((per.l((ad:0x40008000+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects belay"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40008000+0x04)))&0x07)==0x01)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x05)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==(0x03||0x07))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x04)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "RDR,SPI Receive Data Register"
|
|
in
|
|
newline
|
|
if (((per.l((ad:0x40008000+0x04)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deasserted"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deasserted"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
endif
|
|
newline
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SR,SPI Status Register"
|
|
in
|
|
newline
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,SPI Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES ,Underrun error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,Transmission registers empty mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR ,NSS rising interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES ,Overrun error interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF ,Mode fault error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE ,SPI transmit data register empty interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF ,Receive data register full interrupt mask" "Masked,Unmasked"
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
endif
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
endif
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
endif
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,SPI write protection key password"
|
|
bitfld.long 0x00 2. " WPCREN ,Write protection control register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WPITEN ,Write protection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WPEN ,SPI write protection enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,SPI Write Protection Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI 1"
|
|
base ad:0x40058000
|
|
width 13.
|
|
if ((per.l(ad:0x40058000+0xE4)&0x04)==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 12. " REQCLR ,Request to clear the comparison trigger" "No request,Request"
|
|
bitfld.long 0x00 7. " SWRST ,SPI software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI disable" "No effect,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " SPIEN ,SPI enable" "No effect,Enable"
|
|
else
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "CR,SPI Control Register"
|
|
endif
|
|
if ((per.l(ad:0x40058000+0xE4)&0x01)==0x00)
|
|
if (((per.l((ad:0x40058000+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40058000+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40058000+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40058000+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40058000+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects belay"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40058000+0x04)))&0x07)==0x01)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40058000+0x04)))&0x07)==0x05)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40058000+0x04)))&0x07)==(0x03||0x07))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40058000+0x04)))&0x07)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40058000+0x04)))&0x07)==0x04)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "RDR,SPI Receive Data Register"
|
|
in
|
|
newline
|
|
if (((per.l((ad:0x40058000+0x04)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deasserted"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
elif (((per.l((ad:0x40058000+0x04)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deasserted"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
endif
|
|
newline
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SR,SPI Status Register"
|
|
in
|
|
newline
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,SPI Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES ,Underrun error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,Transmission registers empty mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR ,NSS rising interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES ,Overrun error interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF ,Mode fault error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE ,SPI transmit data register empty interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF ,Receive data register full interrupt mask" "Masked,Unmasked"
|
|
if ((per.l(ad:0x40058000+0xE4)&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
endif
|
|
if ((per.l(ad:0x40058000+0xE4)&0x01)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
endif
|
|
if ((per.l(ad:0x40058000+0xE4)&0x01)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
endif
|
|
if ((per.l(ad:0x40058000+0xE4)&0x01)==0x00)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,SPI write protection key password"
|
|
bitfld.long 0x00 2. " WPCREN ,Write protection control register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WPITEN ,Write protection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WPEN ,SPI write protection enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,SPI Write Protection Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x40008000
|
|
width 13.
|
|
if ((per.l(ad:0x40008000+0xE4)&0x04)==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,SPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 12. " REQCLR ,Request to clear the comparison trigger" "No request,Request"
|
|
bitfld.long 0x00 7. " SWRST ,SPI software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " SPIDIS ,SPI disable" "No effect,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. " SPIEN ,SPI enable" "No effect,Enable"
|
|
else
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "CR,SPI Control Register"
|
|
endif
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
if (((per.l((ad:0x40008000+0x04)))&0x07)==0x01)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x05)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==(0x03||0x07))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects belay"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
endif
|
|
else
|
|
if (((per.l((ad:0x40008000+0x04)))&0x07)==0x01)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x05)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==(0x03||0x07))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 7. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x07)==0x04)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,SPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCS ,Chip selects delay"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 5. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MODFDIS ,Mode fault detection disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PCSDEC ,Chip select decode" "Directly,Decoder"
|
|
bitfld.long 0x00 1. " PS ,Peripheral selection" "Fixed,Variable"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTR ,Master mode" "Slave,Master"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "RDR,SPI Receive Data Register"
|
|
in
|
|
newline
|
|
if (((per.l((ad:0x40008000+0x04)))&0x06)==0x02)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deasserted"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 0111,NPCS = 1110,NPCS = 1101,NPCS = 1110,NPCS = 1011,NPCS = 1110,NPCS = 1101,NPCS = 1110,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
elif (((per.l((ad:0x40008000+0x04)))&0x06)==0x06)
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deasserted"
|
|
bitfld.long 0x00 16.--19. " PCS ,Peripheral chip select" "NPCS = 0000,NPCS = 0001,NPCS = 0010,NPCS = 0011,NPCS = 0100,NPCS = 0101,NPCS = 0110,NPCS = 0111,NPCS = 1000,NPCS = 1001,NPCS = 1010,NPCS = 1011,NPCS = 1100,NPCS = 1101,NPCS = 1110,NPCS = 1111"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
else
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,SPI Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
endif
|
|
newline
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SR,SPI Status Register"
|
|
in
|
|
newline
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,SPI Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNDES ,Underrun error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,Transmission registers empty mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NSSR ,NSS rising interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES ,Overrun error interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MODF ,Mode fault error interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE ,SPI transmit data register empty interrupt mask" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF ,Receive data register full interrupt mask" "Masked,Unmasked"
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
else
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "CSR0,SPI Chip Select Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
endif
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
else
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "CSR1,SPI Chip Select Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
endif
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CSR2,SPI Chip Select Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
endif
|
|
if ((per.l(ad:0x40008000+0xE4)&0x01)==0x00)
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock bit rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
else
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "CSR3,SPI Chip Select Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYBCT ,Consecutive transfers delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before SPCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 4.--7. " BITS ,Bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " CSAAT ,Chip select active after transfer" "Risen,Not risen"
|
|
bitfld.long 0x00 2. " CSNAAT ,Chip select not active after transfer" "Not risen,Risen"
|
|
bitfld.long 0x00 1. " NCPHA ,Clock phase (leading/following edge)" "Changed/captured,Captured/changed"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,SPI write protection key password"
|
|
bitfld.long 0x00 2. " WPCREN ,Write protection control register enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " WPITEN ,Write protection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " WPEN ,SPI write protection enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,SPI Write Protection Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree "QSPI (Quad SPI Interface)"
|
|
base ad:0x4007C000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,QSPI Control Register"
|
|
bitfld.long 0x00 24. " LASTXFER ,Last transfer" "No effect,Deassert"
|
|
bitfld.long 0x00 7. " SWRST ,SPI software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " QSPIDIS ,QSPI disable" "No effect,Yes"
|
|
bitfld.long 0x00 0. " QSPIEN ,QSPI enable" "No effect,Enable"
|
|
if ((per.l(ad:0x4007C000+0xE4)&0x01)==0x00)
|
|
sif cpuis("ATSAMA5D2?")
|
|
if (((per.l(ad:0x4007C000+0x04))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,QSPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYCS ,Delay between consecutive transfers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBCT ,Minimum inactive QCS delay"
|
|
bitfld.long 0x00 8.--11. " NBBITS ,Number of bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x00 4.--5. " CSMODE ,Chip select mode" "Not reloaded,Lastxfer,Systematically,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " SMRM ,Serial memory register mode" "AHB,APB"
|
|
bitfld.long 0x00 2. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SMM ,Serial memory mode" "SPI,Memory"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,QSPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYCS ,Delay between consecutive transfers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBCT ,Minimum inactive QCS delay"
|
|
bitfld.long 0x00 8.--11. " NBBITS ,Number of bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x00 4.--5. " CSMODE ,Chip select mode" "Not reloaded,Lastxfer,Systematically,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " SMRM ,Serial memory register mode" "AHB,APB"
|
|
bitfld.long 0x00 2. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SMM ,Serial memory mode" "SPI,Memory"
|
|
endif
|
|
elif !cpuis("ATSAMV70J*")&&!cpuis("ATSAMV71J*")&&!cpuis("ATSAMS70J*")&&!cpuis("ATSAME70J*")
|
|
if (((per.l(ad:0x4007C000+0x04))&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,QSPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYCS ,Delay between consecutive transfers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBCT ,Minimum inactive QCS delay"
|
|
bitfld.long 0x00 8.--11. " NBBITS ,Number of bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x00 4.--5. " CSMODE ,Chip select mode" "Not reloaded,Lastxfer,Systematically,?..."
|
|
newline
|
|
bitfld.long 0x00 2. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SMM ,Serial memory mode" "SPI,Memory"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,QSPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYCS ,Delay between consecutive transfers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBCT ,Minimum inactive QCS delay"
|
|
bitfld.long 0x00 8.--11. " NBBITS ,Number of bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x00 4.--5. " CSMODE ,Chip select mode" "Not reloaded,Lastxfer,Systematically,?..."
|
|
newline
|
|
bitfld.long 0x00 2. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SMM ,Serial memory mode" "SPI,Memory"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,QSPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYCS ,Delay between consecutive transfers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBCT ,Minimum inactive QCS delay"
|
|
bitfld.long 0x00 8.--11. " NBBITS ,Number of bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x00 4.--5. " CSMODE ,Chip select mode" "Not reloaded,Lastxfer,Systematically,?..."
|
|
newline
|
|
bitfld.long 0x00 2. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SMM ,Serial memory mode" "SPI,?..."
|
|
endif
|
|
else
|
|
sif cpuis("ATSAMA5D2?")
|
|
if (((per.l(ad:0x4007C000+0x04))&0x01)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,QSPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYCS ,Delay between consecutive transfers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBCT ,Minimum inactive QCS delay"
|
|
bitfld.long 0x00 8.--11. " NBBITS ,Number of bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x00 4.--5. " CSMODE ,Chip select mode" "Not reloaded,Lastxfer,Systematically,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " SMRM ,Serial memory register mode" "AHB,APB"
|
|
bitfld.long 0x00 2. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SMM ,Serial memory mode" "SPI,Memory"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,QSPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYCS ,Delay between consecutive transfers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBCT ,Minimum inactive QCS delay"
|
|
bitfld.long 0x00 8.--11. " NBBITS ,Number of bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x00 4.--5. " CSMODE ,Chip select mode" "Not reloaded,Lastxfer,Systematically,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " SMRM ,Serial memory register mode" "AHB,APB"
|
|
bitfld.long 0x00 2. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SMM ,Serial memory mode" "SPI,Memory"
|
|
endif
|
|
elif !cpuis("ATSAMV70J*")&&!cpuis("ATSAMV71J*")&&!cpuis("ATSAMS70J*")&&!cpuis("ATSAME70J*")
|
|
if (((per.l(ad:0x4007C000+0x04))&0x01)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,QSPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYCS ,Delay between consecutive transfers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBCT ,Minimum inactive QCS delay"
|
|
bitfld.long 0x00 8.--11. " NBBITS ,Number of bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x00 4.--5. " CSMODE ,Chip select mode" "Not reloaded,Lastxfer,Systematically,?..."
|
|
newline
|
|
bitfld.long 0x00 2. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SMM ,Serial memory mode" "SPI,Memory"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,QSPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYCS ,Delay between consecutive transfers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBCT ,Minimum inactive QCS delay"
|
|
bitfld.long 0x00 8.--11. " NBBITS ,Number of bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x00 4.--5. " CSMODE ,Chip select mode" "Not reloaded,Lastxfer,Systematically,?..."
|
|
newline
|
|
bitfld.long 0x00 2. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SMM ,Serial memory mode" "SPI,Memory"
|
|
endif
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,QSPI Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DLYCS ,Delay between consecutive transfers"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBCT ,Minimum inactive QCS delay"
|
|
bitfld.long 0x00 8.--11. " NBBITS ,Number of bits per transfer" "8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,?..."
|
|
bitfld.long 0x00 4.--5. " CSMODE ,Chip select mode" "Not reloaded,Lastxfer,Systematically,?..."
|
|
newline
|
|
bitfld.long 0x00 2. " WDRBT ,Wait data read before transfer" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LLB ,Local loopback enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SMM ,Serial memory mode" "SPI,?..."
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "RDR,QSPI Receive Data Register"
|
|
in
|
|
newline
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "TDR,QSPI Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TD ,Transmit data"
|
|
newline
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SR,SPI Status Register"
|
|
in
|
|
newline
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,QSPI Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " INSTRE ,Instruction end interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " CSS ,Chip select status interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " CSR ,Chip select rise interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " OVRES ,Overrun error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXEMPTY ,Transmission registers empty mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TDRE ,SPI transmit data register empty interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RDRF ,Receive data register full interrupt mask" "Masked,Not masked"
|
|
if ((per.l(ad:0x4007C000+0xE4)&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SCR,QSPI Serial Clock Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before QSCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 1. " CPHA ,Clock phase (leading edge/following edge)" "Captured/changed,Changed/captured"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "SCR,QSPI Serial Clock Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DLYBS ,Delay before QSCK"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCBR ,Serial clock baud rate"
|
|
bitfld.long 0x00 1. " CPHA ,Clock phase (leading edge/following edge)" "Captured/Changed,Changed/Captured"
|
|
bitfld.long 0x00 0. " CPOL ,Clock polarity" "Inactive-low,Inactive-high"
|
|
endif
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "IAR,QSPI Instruction Address Register"
|
|
line.long 0x04 "ICR,QSPI Instruction Code Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " OPT ,Option code"
|
|
hexmask.long.byte 0x04 0.--7. 1. " INST ,Instruction code"
|
|
line.long 0x08 "IFR,QSPI Instruction Frame Register"
|
|
sif cpuis("ATSAMS7*")
|
|
bitfld.long 0x08 26. " DDRCMDEN ,DDR mode command enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " APBTFRTYP ,APB transfer type" "Write,Read"
|
|
newline
|
|
endif
|
|
bitfld.long 0x08 16.--20. " NBDUM ,Number of dummy cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
sif cpuis("ATSAMS7*")
|
|
bitfld.long 0x08 15. " DDREN ,DDR mode enable" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x08 14. " CRM ,Continuous read mode" "Disabled,Enabled"
|
|
bitfld.long 0x08 12.--13. " TFRTYP ,Data transfer type" "TRSFR_READ,TRSFR_READ_MEMORY,TRSFR_WRITE,TRSFR_WRITE_MEMORY"
|
|
newline
|
|
bitfld.long 0x08 10. " ADDRL ,Address length" "24 bits,32 bits"
|
|
sif cpuis("ATSAMA5D2*")||cpuis("ATSAMS7*")
|
|
bitfld.long 0x08 8.--9. " OPTL ,Option code length" "1 bit,2 bits,4 bits,8 bits"
|
|
else
|
|
bitfld.long 0x08 8.--9. " OPTL ,Option code length" "1 bit,2 bits,3 bits,4 bits"
|
|
endif
|
|
bitfld.long 0x08 7. " DATAEN ,Data enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " OPTEN ,Option enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 5. " ADDREN ,Address enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " INSTEN ,Instruction enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0.--2. " WIDTH ,Width of instruction code/address/option code/data" "SINGLE_BIT_SPI,DUAL_OUTPUT,QUAD_OUTPUT,DUAL_IO,QUAD_IO,DUAL_CMD,QUAD_CMD,?..."
|
|
if ((per.l(ad:0x4007C000+0xE4)&0x01)==0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SMR,QSPI Scrambling Mode Register"
|
|
bitfld.long 0x00 1. " RVDIS ,Scrambling/unscrambling random value disable" "No,Yes"
|
|
bitfld.long 0x00 0. " SCREN ,Scrambling/unscrambling enable" "Disabled,Enabled"
|
|
wgroup.long 0x44++0x03
|
|
line.long 0x00 "SKR,QSPI Scrambling Key Register"
|
|
else
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "SMR,QSPI Scrambling Mode Register"
|
|
bitfld.long 0x00 1. " RVDIS ,Scrambling/unscrambling random value disable" "No,Yes"
|
|
bitfld.long 0x00 0. " SCREN ,Scrambling/unscrambling enable" "Disabled,Enabled"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "SKR,QSPI Scrambling Key Register"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,QSPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protection key password"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,QSPI Write Protection Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "TWIHS (Two-wire Interface)"
|
|
tree "TWIHS 0"
|
|
base ad:0x40018000
|
|
width 13.
|
|
sif cpuis("ATSAMA5D4*")
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " SVDIS ,Slave mode disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,Slave mode enabled" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. " MSDIS ,Master transfer disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,Master transfer enabled" "No effect,Enable"
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP condition" "No effect,Send"
|
|
bitfld.long 0x00 0. " START ,Send a START condition" "No effect,Send"
|
|
elif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
sif cpuis("ATSAMA5D2?")||cpuis("ATSAME7*")||cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 29. " FIFODIS ,FIFO disable" "No effect,Disable"
|
|
bitfld.long 0x00 28. " FIFOEN ,FIFO enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 26. " LOCKCLR ,Lock clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " THRCLR ,Transmit holding register clear" "No effect,Clear"
|
|
bitfld.long 0x00 17. " ACMDIS ,Alternative command mode disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " ACMEN ,Alternative command mode enable" "No effect,Enable"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " CLEAR ,Bus CLEAR command" "No effect,Send"
|
|
bitfld.long 0x00 14. " PECRQ ,PEC request" "No effect,Requested"
|
|
bitfld.long 0x00 13. " PECDIS ,Packet error checking disable" "No effect,Disabled"
|
|
bitfld.long 0x00 12. " PECEN ,Packet error checking enable" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " SMBDIS ,SMBus mode disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " SMBEN ,SMBus mode enabled" "No effect,Enabled"
|
|
bitfld.long 0x00 9. " HSDIS ,TWIHS high-speed mode disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " HSEN ,TWIHS high-speed mode enabled" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS quick command" "No effect,Send"
|
|
bitfld.long 0x00 5. " SVDIS ,Slave mode disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " SVEN ,Slave mode enabled" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " MSDIS ,Master transfer disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " MSEN ,Master transfer enabled" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP condition" "No effect,Send"
|
|
bitfld.long 0x00 0. " START ,Send a START condition" "No effect,Send"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS quick command" "No effect,Send"
|
|
bitfld.long 0x00 5. " SVDIS ,Slave mode disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,Slave mode enabled" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. " MSDIS ,Master transfer disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,Master transfer enabled" "No effect,Enable"
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP condition" "No effect,Send"
|
|
bitfld.long 0x00 0. " START ,Send a START condition" "No effect,Send"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MMR,Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " DADR ,Device address"
|
|
bitfld.long 0x00 12. " MREAD ,Master read direction" "Write,Read"
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal device address size" "No address,One-byte,Two-byte,Three-byte"
|
|
sif cpuis("ATSAME70*")||cpuis("ATSAMS7*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMR,Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data matching enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave address 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave address 1 enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave address"
|
|
bitfld.long 0x00 14. " MASK ,Slave address mask bit 6" "0,1"
|
|
bitfld.long 0x00 13. ",Slave address mask bit 5" "0,1"
|
|
bitfld.long 0x00 12. ",Slave address mask bit 4" "0,1"
|
|
bitfld.long 0x00 11. ",Slave address mask bit 3" "0,1"
|
|
bitfld.long 0x00 10. ",Slave address mask bit 2" "0,1"
|
|
bitfld.long 0x00 9. ",Slave address mask bit 1" "0,1"
|
|
bitfld.long 0x00 8. ",Slave address mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock wait state disable" "No effect,Disabled"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus host header" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SMDA ,SMBus default address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave receiver data phase NACK enable" "Disabled,Enabled"
|
|
else
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMA5D2?")
|
|
if ((per.l(ad:0x40018000+0xE4)&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMR,Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data matching enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave address 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave address 1 enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave address"
|
|
bitfld.long 0x00 14. " MASK ,Slave address mask bit 6" "0,1"
|
|
bitfld.long 0x00 13. ",Slave address mask bit 5" "0,1"
|
|
bitfld.long 0x00 12. ",Slave address mask bit 4" "0,1"
|
|
bitfld.long 0x00 11. ",Slave address mask bit 3" "0,1"
|
|
bitfld.long 0x00 10. ",Slave address mask bit 2" "0,1"
|
|
bitfld.long 0x00 9. ",Slave address mask bit 1" "0,1"
|
|
bitfld.long 0x00 8. ",Slave address mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock wait state disable" "No effect,Disabled"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus host header" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SMDA ,SMBus default address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave receiver data phase NACK enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SMR,Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data matching enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave address 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave address 1 enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave address"
|
|
bitfld.long 0x00 14. " MASK ,Slave address mask bit 6" "0,1"
|
|
bitfld.long 0x00 13. ",Slave address mask bit 5" "0,1"
|
|
bitfld.long 0x00 12. ",Slave address mask bit 4" "0,1"
|
|
bitfld.long 0x00 11. ",Slave address mask bit 3" "0,1"
|
|
bitfld.long 0x00 10. ",Slave address mask bit 2" "0,1"
|
|
bitfld.long 0x00 9. ",Slave address mask bit 1" "0,1"
|
|
bitfld.long 0x00 8. ",Slave address mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock wait state disable" "No effect,Disabled"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus host header" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SMDA ,SMBus default address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave receiver data phase NACK enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40018000+0xE4)&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMR,Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave address"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SMR,Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave address"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40018000+0x04)&0x300)==0x300)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IADR,Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 0x01 " IADR ,Internal address"
|
|
elif ((per.l(ad:0x40018000+0x04)&0x300)==0x200)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IADR,Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " IADR ,Internal address"
|
|
elif ((per.l(ad:0x40018000+0x04)&0x300)==0x100)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IADR,Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " IADR ,Internal address"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "IADR,Internal Address Register"
|
|
endif
|
|
if ((per.l(ad:0x40018000+0xE4)&0x01)==0x00)
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
sif cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 24.--29. " HOLD ,TWD hold time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD hold time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock high divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock low divider"
|
|
elif cpuis("ATSAMA5D2?")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD hold time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " CKSRC ,Transfer rate clock source" "Peripheral clock,PMC PCK"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock high divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock low divider"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock high divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock low divider"
|
|
endif
|
|
else
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
sif cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 24.--29. " HOLD ,TWD hold time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD hold time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock high divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock low divider"
|
|
elif cpuis("ATSAMA5D2?")
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD hold time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " CKSRC ,Transfer rate clock source" "Peripheral clock,PMC PCK"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock high divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock low divider"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock high divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock low divider"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "SR,Status Register"
|
|
in
|
|
newline
|
|
sif cpuis("ATSAME70*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SMBTR,TWIHS SMBus Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THMAX ,Clock high maximum cycles"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOWM ,Master clock stretch maximum cycles"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOWS ,Slave clock stretch maximum cycles"
|
|
bitfld.long 0x00 0.--3. " PRESC ,SMBus clock prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "FILTR,TWIHS Filter Register"
|
|
bitfld.long 0x00 8.--10. " THRES ,Digital filter threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PADFCFG ,PAD filter config" "0,1"
|
|
bitfld.long 0x00 1. " PADFEN ,PAD filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FILT ,RX digital filter" "Not active,Active"
|
|
else
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAMA5D2?")
|
|
if ((per.l(ad:0x40018000+0xE4)&0x01)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SMBTR,TWIHS SMBus Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THMAX ,Clock high maximum cycles"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOWM ,Master clock stretch maximum cycles"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOWS ,Slave clock stretch maximum cycles"
|
|
bitfld.long 0x00 0.--3. " PRESC ,SMBus clock prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "SMBTR,TWIHS SMBus Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THMAX ,Clock high maximum cycles"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOWM ,Master clock stretch maximum cycles"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOWS ,Slave clock stretch maximum cycles"
|
|
bitfld.long 0x00 0.--3. " PRESC ,SMBus clock prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("ATSAMA5D2?")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ACR,TWIHS Alternative Command Register"
|
|
bitfld.long 0x00 25. " NPEC ,Next PEC request" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " NDIR ,Next transfer direction" "Write,Read"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NDATAL ,Next data length"
|
|
bitfld.long 0x00 9. " PEC ,PEC request" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " DIR ,Transfer direction" "Write,Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATAL ,Data length"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "FILTR,TWIHS Filter Register"
|
|
bitfld.long 0x00 8.--10. " THRES ,Digital filter threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PADFCFG ,PAD filter config" "0,1"
|
|
bitfld.long 0x00 1. " PADFEN ,PAD filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FILT ,RX digital filter" "Not active,Active"
|
|
endif
|
|
endif
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " SMBHHM ,SMBus host header address match interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " SMBDAM ,SMBus default address match interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " PECERR ,PEC error interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " TOUT ,Timeout error interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " MCACK ,Master code acknowledge interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOSACC ,End of slave access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SCL_WS ,Clock wait state interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ABRLST ,Arbitration lost interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NACK ,Not acknowledge interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " UNRE ,Underrun error interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVRE ,Overrun error interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GACC ,General call access interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " SVACC ,Slave access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXRDY ,Transmit holding register ready interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY ,Receive holding register ready interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXCOMP ,Transmission completed interrupt" "Masked,Not masked"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
sif cpuis("ATSAMA5D3*")
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOSACC ,End of slave access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SCL_WS ,Clock wait state interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ABRLST ,Arbitration lost interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NACK ,Not acknowledge" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVRE ,Overrun error" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GACC ,General call access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " SVACC ,Slave access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXRDY ,Transmit holding register ready interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY ,Receive holding register ready interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXCOMP ,Transmission completed interrupt" "Masked,Not masked"
|
|
else
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " EOSACC ,End of slave access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " SCL_WS ,Clock wait state interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " ABRLST ,Arbitration lost interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " NACK ,Not acknowledge" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " OVRE ,Overrun error" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " GACC ,General call access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " SVACC ,Slave access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXRDY ,Transmit holding register ready interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXRDY ,Receive holding register ready interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXCOMP ,Transmission completed interrupt" "Masked,Not masked"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "RHR,Receive Holding Register"
|
|
in
|
|
newline
|
|
sif cpuis("ATSAME7*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SWMR,TWIHS Sleep Walking Matching Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATAM ,Data match"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR3 ,Slave address 3"
|
|
hexmask.long.byte 0x00 8.--14. 0x01 " SADR2 ,Slave address 2"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " SADR1 ,Slave address 1"
|
|
else
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAMA5D2?")
|
|
if ((per.l(ad:0x40018000+0xE4)&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SWMR,TWIHS SleepWalking Matching Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATAM ,Data match"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR3 ,Slave address 3"
|
|
hexmask.long.byte 0x00 8.--14. 0x01 " SADR2 ,Slave address 2"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " SADR1 ,Slave address 1"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "SWMR,TWIHS SleepWalking Matching Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATAM ,Data match"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR3 ,Slave address 3"
|
|
hexmask.long.byte 0x00 8.--14. 0x01 " SADR2 ,Slave address 2"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " SADR1 ,Slave address 1"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("ATSAMA5D2?")
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "THR,Transmit Holding Register"
|
|
else
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "THR,Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or slave transmit holding data"
|
|
endif
|
|
sif cpuis("ATSAMA5D2?")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FMR,TWIHS FIFO Mode Register"
|
|
bitfld.long 0x00 24.--29. " RXFTHRES ,Receive FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 16.--21. " TXFTHRES ,Transmit FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 4.--5. " RXRDYM ,Receiver ready mode" "ONE_DATA,TWO_DATA,FOUR_DATA,?..."
|
|
bitfld.long 0x00 0.--1. " TXRDYM ,Transmitter ready mode" "ONE_DATA,TWO_DATA,FOUR_DATA,?..."
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "FLR,TWIHS FIFO Level Register"
|
|
bitfld.long 0x00 16.--21. " RXFL ,Receive FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0.--5. " TXFL ,Transmit FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
newline
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "FSR,TWIHS FIFO Status Register"
|
|
in
|
|
newline
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "FIMR_SET/CLR,TWIHS FIFO Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " RXFPTEF ,RXFPTEF interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " TXFPTEF ,TXFPTEF interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " RXFTHF ,RXFTHF interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RXFFF ,RXFFF interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RXFEF ,RXFEF interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXFTHF ,TXFTHF interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXFFF ,TXFFF interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXFEF ,TXFEF interrupt mask" "Masked,Not masked"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protection mode security code"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection bit" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "TWIHS 1"
|
|
base ad:0x4001C000
|
|
width 13.
|
|
sif cpuis("ATSAMA5D4*")
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " SVDIS ,Slave mode disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,Slave mode enabled" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. " MSDIS ,Master transfer disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,Master transfer enabled" "No effect,Enable"
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP condition" "No effect,Send"
|
|
bitfld.long 0x00 0. " START ,Send a START condition" "No effect,Send"
|
|
elif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
sif cpuis("ATSAMA5D2?")||cpuis("ATSAME7*")||cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 29. " FIFODIS ,FIFO disable" "No effect,Disable"
|
|
bitfld.long 0x00 28. " FIFOEN ,FIFO enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 26. " LOCKCLR ,Lock clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " THRCLR ,Transmit holding register clear" "No effect,Clear"
|
|
bitfld.long 0x00 17. " ACMDIS ,Alternative command mode disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " ACMEN ,Alternative command mode enable" "No effect,Enable"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " CLEAR ,Bus CLEAR command" "No effect,Send"
|
|
bitfld.long 0x00 14. " PECRQ ,PEC request" "No effect,Requested"
|
|
bitfld.long 0x00 13. " PECDIS ,Packet error checking disable" "No effect,Disabled"
|
|
bitfld.long 0x00 12. " PECEN ,Packet error checking enable" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " SMBDIS ,SMBus mode disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " SMBEN ,SMBus mode enabled" "No effect,Enabled"
|
|
bitfld.long 0x00 9. " HSDIS ,TWIHS high-speed mode disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " HSEN ,TWIHS high-speed mode enabled" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS quick command" "No effect,Send"
|
|
bitfld.long 0x00 5. " SVDIS ,Slave mode disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " SVEN ,Slave mode enabled" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " MSDIS ,Master transfer disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " MSEN ,Master transfer enabled" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP condition" "No effect,Send"
|
|
bitfld.long 0x00 0. " START ,Send a START condition" "No effect,Send"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS quick command" "No effect,Send"
|
|
bitfld.long 0x00 5. " SVDIS ,Slave mode disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,Slave mode enabled" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. " MSDIS ,Master transfer disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,Master transfer enabled" "No effect,Enable"
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP condition" "No effect,Send"
|
|
bitfld.long 0x00 0. " START ,Send a START condition" "No effect,Send"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MMR,Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " DADR ,Device address"
|
|
bitfld.long 0x00 12. " MREAD ,Master read direction" "Write,Read"
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal device address size" "No address,One-byte,Two-byte,Three-byte"
|
|
sif cpuis("ATSAME70*")||cpuis("ATSAMS7*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMR,Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data matching enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave address 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave address 1 enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave address"
|
|
bitfld.long 0x00 14. " MASK ,Slave address mask bit 6" "0,1"
|
|
bitfld.long 0x00 13. ",Slave address mask bit 5" "0,1"
|
|
bitfld.long 0x00 12. ",Slave address mask bit 4" "0,1"
|
|
bitfld.long 0x00 11. ",Slave address mask bit 3" "0,1"
|
|
bitfld.long 0x00 10. ",Slave address mask bit 2" "0,1"
|
|
bitfld.long 0x00 9. ",Slave address mask bit 1" "0,1"
|
|
bitfld.long 0x00 8. ",Slave address mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock wait state disable" "No effect,Disabled"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus host header" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SMDA ,SMBus default address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave receiver data phase NACK enable" "Disabled,Enabled"
|
|
else
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMA5D2?")
|
|
if ((per.l(ad:0x4001C000+0xE4)&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMR,Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data matching enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave address 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave address 1 enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave address"
|
|
bitfld.long 0x00 14. " MASK ,Slave address mask bit 6" "0,1"
|
|
bitfld.long 0x00 13. ",Slave address mask bit 5" "0,1"
|
|
bitfld.long 0x00 12. ",Slave address mask bit 4" "0,1"
|
|
bitfld.long 0x00 11. ",Slave address mask bit 3" "0,1"
|
|
bitfld.long 0x00 10. ",Slave address mask bit 2" "0,1"
|
|
bitfld.long 0x00 9. ",Slave address mask bit 1" "0,1"
|
|
bitfld.long 0x00 8. ",Slave address mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock wait state disable" "No effect,Disabled"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus host header" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SMDA ,SMBus default address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave receiver data phase NACK enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SMR,Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data matching enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave address 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave address 1 enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave address"
|
|
bitfld.long 0x00 14. " MASK ,Slave address mask bit 6" "0,1"
|
|
bitfld.long 0x00 13. ",Slave address mask bit 5" "0,1"
|
|
bitfld.long 0x00 12. ",Slave address mask bit 4" "0,1"
|
|
bitfld.long 0x00 11. ",Slave address mask bit 3" "0,1"
|
|
bitfld.long 0x00 10. ",Slave address mask bit 2" "0,1"
|
|
bitfld.long 0x00 9. ",Slave address mask bit 1" "0,1"
|
|
bitfld.long 0x00 8. ",Slave address mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock wait state disable" "No effect,Disabled"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus host header" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SMDA ,SMBus default address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave receiver data phase NACK enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4001C000+0xE4)&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMR,Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave address"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SMR,Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave address"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x4001C000+0x04)&0x300)==0x300)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IADR,Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 0x01 " IADR ,Internal address"
|
|
elif ((per.l(ad:0x4001C000+0x04)&0x300)==0x200)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IADR,Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " IADR ,Internal address"
|
|
elif ((per.l(ad:0x4001C000+0x04)&0x300)==0x100)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IADR,Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " IADR ,Internal address"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "IADR,Internal Address Register"
|
|
endif
|
|
if ((per.l(ad:0x4001C000+0xE4)&0x01)==0x00)
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
sif cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 24.--29. " HOLD ,TWD hold time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD hold time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock high divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock low divider"
|
|
elif cpuis("ATSAMA5D2?")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD hold time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " CKSRC ,Transfer rate clock source" "Peripheral clock,PMC PCK"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock high divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock low divider"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock high divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock low divider"
|
|
endif
|
|
else
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
sif cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 24.--29. " HOLD ,TWD hold time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD hold time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock high divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock low divider"
|
|
elif cpuis("ATSAMA5D2?")
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD hold time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " CKSRC ,Transfer rate clock source" "Peripheral clock,PMC PCK"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock high divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock low divider"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock high divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock low divider"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "SR,Status Register"
|
|
in
|
|
newline
|
|
sif cpuis("ATSAME70*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SMBTR,TWIHS SMBus Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THMAX ,Clock high maximum cycles"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOWM ,Master clock stretch maximum cycles"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOWS ,Slave clock stretch maximum cycles"
|
|
bitfld.long 0x00 0.--3. " PRESC ,SMBus clock prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "FILTR,TWIHS Filter Register"
|
|
bitfld.long 0x00 8.--10. " THRES ,Digital filter threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PADFCFG ,PAD filter config" "0,1"
|
|
bitfld.long 0x00 1. " PADFEN ,PAD filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FILT ,RX digital filter" "Not active,Active"
|
|
else
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAMA5D2?")
|
|
if ((per.l(ad:0x4001C000+0xE4)&0x01)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SMBTR,TWIHS SMBus Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THMAX ,Clock high maximum cycles"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOWM ,Master clock stretch maximum cycles"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOWS ,Slave clock stretch maximum cycles"
|
|
bitfld.long 0x00 0.--3. " PRESC ,SMBus clock prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "SMBTR,TWIHS SMBus Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THMAX ,Clock high maximum cycles"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOWM ,Master clock stretch maximum cycles"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOWS ,Slave clock stretch maximum cycles"
|
|
bitfld.long 0x00 0.--3. " PRESC ,SMBus clock prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("ATSAMA5D2?")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ACR,TWIHS Alternative Command Register"
|
|
bitfld.long 0x00 25. " NPEC ,Next PEC request" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " NDIR ,Next transfer direction" "Write,Read"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NDATAL ,Next data length"
|
|
bitfld.long 0x00 9. " PEC ,PEC request" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " DIR ,Transfer direction" "Write,Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATAL ,Data length"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "FILTR,TWIHS Filter Register"
|
|
bitfld.long 0x00 8.--10. " THRES ,Digital filter threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PADFCFG ,PAD filter config" "0,1"
|
|
bitfld.long 0x00 1. " PADFEN ,PAD filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FILT ,RX digital filter" "Not active,Active"
|
|
endif
|
|
endif
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " SMBHHM ,SMBus host header address match interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " SMBDAM ,SMBus default address match interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " PECERR ,PEC error interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " TOUT ,Timeout error interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " MCACK ,Master code acknowledge interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOSACC ,End of slave access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SCL_WS ,Clock wait state interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ABRLST ,Arbitration lost interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NACK ,Not acknowledge interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " UNRE ,Underrun error interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVRE ,Overrun error interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GACC ,General call access interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " SVACC ,Slave access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXRDY ,Transmit holding register ready interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY ,Receive holding register ready interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXCOMP ,Transmission completed interrupt" "Masked,Not masked"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
sif cpuis("ATSAMA5D3*")
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOSACC ,End of slave access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SCL_WS ,Clock wait state interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ABRLST ,Arbitration lost interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NACK ,Not acknowledge" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVRE ,Overrun error" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GACC ,General call access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " SVACC ,Slave access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXRDY ,Transmit holding register ready interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY ,Receive holding register ready interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXCOMP ,Transmission completed interrupt" "Masked,Not masked"
|
|
else
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " EOSACC ,End of slave access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " SCL_WS ,Clock wait state interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " ABRLST ,Arbitration lost interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " NACK ,Not acknowledge" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " OVRE ,Overrun error" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " GACC ,General call access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " SVACC ,Slave access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXRDY ,Transmit holding register ready interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXRDY ,Receive holding register ready interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXCOMP ,Transmission completed interrupt" "Masked,Not masked"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "RHR,Receive Holding Register"
|
|
in
|
|
newline
|
|
sif cpuis("ATSAME7*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SWMR,TWIHS Sleep Walking Matching Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATAM ,Data match"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR3 ,Slave address 3"
|
|
hexmask.long.byte 0x00 8.--14. 0x01 " SADR2 ,Slave address 2"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " SADR1 ,Slave address 1"
|
|
else
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAMA5D2?")
|
|
if ((per.l(ad:0x4001C000+0xE4)&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SWMR,TWIHS SleepWalking Matching Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATAM ,Data match"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR3 ,Slave address 3"
|
|
hexmask.long.byte 0x00 8.--14. 0x01 " SADR2 ,Slave address 2"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " SADR1 ,Slave address 1"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "SWMR,TWIHS SleepWalking Matching Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATAM ,Data match"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR3 ,Slave address 3"
|
|
hexmask.long.byte 0x00 8.--14. 0x01 " SADR2 ,Slave address 2"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " SADR1 ,Slave address 1"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("ATSAMA5D2?")
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "THR,Transmit Holding Register"
|
|
else
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "THR,Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or slave transmit holding data"
|
|
endif
|
|
sif cpuis("ATSAMA5D2?")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FMR,TWIHS FIFO Mode Register"
|
|
bitfld.long 0x00 24.--29. " RXFTHRES ,Receive FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 16.--21. " TXFTHRES ,Transmit FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 4.--5. " RXRDYM ,Receiver ready mode" "ONE_DATA,TWO_DATA,FOUR_DATA,?..."
|
|
bitfld.long 0x00 0.--1. " TXRDYM ,Transmitter ready mode" "ONE_DATA,TWO_DATA,FOUR_DATA,?..."
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "FLR,TWIHS FIFO Level Register"
|
|
bitfld.long 0x00 16.--21. " RXFL ,Receive FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0.--5. " TXFL ,Transmit FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
newline
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "FSR,TWIHS FIFO Status Register"
|
|
in
|
|
newline
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "FIMR_SET/CLR,TWIHS FIFO Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " RXFPTEF ,RXFPTEF interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " TXFPTEF ,TXFPTEF interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " RXFTHF ,RXFTHF interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RXFFF ,RXFFF interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RXFEF ,RXFEF interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXFTHF ,TXFTHF interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXFFF ,TXFFF interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXFEF ,TXFEF interrupt mask" "Masked,Not masked"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protection mode security code"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection bit" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("ATSAMS70J*")
|
|
tree "TWIHS 2"
|
|
base ad:0x40060000
|
|
width 13.
|
|
sif cpuis("ATSAMA5D4*")
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " SVDIS ,Slave mode disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,Slave mode enabled" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. " MSDIS ,Master transfer disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,Master transfer enabled" "No effect,Enable"
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP condition" "No effect,Send"
|
|
bitfld.long 0x00 0. " START ,Send a START condition" "No effect,Send"
|
|
elif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
sif cpuis("ATSAMA5D2?")||cpuis("ATSAME7*")||cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 29. " FIFODIS ,FIFO disable" "No effect,Disable"
|
|
bitfld.long 0x00 28. " FIFOEN ,FIFO enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 26. " LOCKCLR ,Lock clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " THRCLR ,Transmit holding register clear" "No effect,Clear"
|
|
bitfld.long 0x00 17. " ACMDIS ,Alternative command mode disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " ACMEN ,Alternative command mode enable" "No effect,Enable"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 15. " CLEAR ,Bus CLEAR command" "No effect,Send"
|
|
bitfld.long 0x00 14. " PECRQ ,PEC request" "No effect,Requested"
|
|
bitfld.long 0x00 13. " PECDIS ,Packet error checking disable" "No effect,Disabled"
|
|
bitfld.long 0x00 12. " PECEN ,Packet error checking enable" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " SMBDIS ,SMBus mode disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " SMBEN ,SMBus mode enabled" "No effect,Enabled"
|
|
bitfld.long 0x00 9. " HSDIS ,TWIHS high-speed mode disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " HSEN ,TWIHS high-speed mode enabled" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS quick command" "No effect,Send"
|
|
bitfld.long 0x00 5. " SVDIS ,Slave mode disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " SVEN ,Slave mode enabled" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " MSDIS ,Master transfer disabled" "No effect,Disabled"
|
|
bitfld.long 0x00 2. " MSEN ,Master transfer enabled" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP condition" "No effect,Send"
|
|
bitfld.long 0x00 0. " START ,Send a START condition" "No effect,Send"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 6. " QUICK ,SMBUS quick command" "No effect,Send"
|
|
bitfld.long 0x00 5. " SVDIS ,Slave mode disabled" "No effect,Disable"
|
|
bitfld.long 0x00 4. " SVEN ,Slave mode enabled" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. " MSDIS ,Master transfer disabled" "No effect,Disable"
|
|
bitfld.long 0x00 2. " MSEN ,Master transfer enabled" "No effect,Enable"
|
|
bitfld.long 0x00 1. " STOP ,Send a STOP condition" "No effect,Send"
|
|
bitfld.long 0x00 0. " START ,Send a START condition" "No effect,Send"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MMR,Master Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " DADR ,Device address"
|
|
bitfld.long 0x00 12. " MREAD ,Master read direction" "Write,Read"
|
|
bitfld.long 0x00 8.--9. " IADRSZ ,Internal device address size" "No address,One-byte,Two-byte,Three-byte"
|
|
sif cpuis("ATSAME70*")||cpuis("ATSAMS7*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMR,Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data matching enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave address 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave address 1 enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave address"
|
|
bitfld.long 0x00 14. " MASK ,Slave address mask bit 6" "0,1"
|
|
bitfld.long 0x00 13. ",Slave address mask bit 5" "0,1"
|
|
bitfld.long 0x00 12. ",Slave address mask bit 4" "0,1"
|
|
bitfld.long 0x00 11. ",Slave address mask bit 3" "0,1"
|
|
bitfld.long 0x00 10. ",Slave address mask bit 2" "0,1"
|
|
bitfld.long 0x00 9. ",Slave address mask bit 1" "0,1"
|
|
bitfld.long 0x00 8. ",Slave address mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock wait state disable" "No effect,Disabled"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus host header" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SMDA ,SMBus default address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave receiver data phase NACK enable" "Disabled,Enabled"
|
|
else
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMA5D2?")
|
|
if ((per.l(ad:0x40060000+0xE4)&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMR,Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data matching enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave address 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave address 1 enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave address"
|
|
bitfld.long 0x00 14. " MASK ,Slave address mask bit 6" "0,1"
|
|
bitfld.long 0x00 13. ",Slave address mask bit 5" "0,1"
|
|
bitfld.long 0x00 12. ",Slave address mask bit 4" "0,1"
|
|
bitfld.long 0x00 11. ",Slave address mask bit 3" "0,1"
|
|
bitfld.long 0x00 10. ",Slave address mask bit 2" "0,1"
|
|
bitfld.long 0x00 9. ",Slave address mask bit 1" "0,1"
|
|
bitfld.long 0x00 8. ",Slave address mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock wait state disable" "No effect,Disabled"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus host header" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SMDA ,SMBus default address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave receiver data phase NACK enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SMR,Slave Mode Register"
|
|
bitfld.long 0x00 31. " DATAMEN ,Data matching enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SADR3EN ,Slave address 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SADR2EN ,Slave address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SADR1EN ,Slave address 1 enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave address"
|
|
bitfld.long 0x00 14. " MASK ,Slave address mask bit 6" "0,1"
|
|
bitfld.long 0x00 13. ",Slave address mask bit 5" "0,1"
|
|
bitfld.long 0x00 12. ",Slave address mask bit 4" "0,1"
|
|
bitfld.long 0x00 11. ",Slave address mask bit 3" "0,1"
|
|
bitfld.long 0x00 10. ",Slave address mask bit 2" "0,1"
|
|
bitfld.long 0x00 9. ",Slave address mask bit 1" "0,1"
|
|
bitfld.long 0x00 8. ",Slave address mask bit 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. " SCLWSDIS ,Clock wait state disable" "No effect,Disabled"
|
|
bitfld.long 0x00 3. " SMHH ,SMBus host header" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SMDA ,SMBus default address" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " NACKEN ,Slave receiver data phase NACK enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40060000+0xE4)&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SMR,Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave address"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SMR,Slave Mode Register"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR ,Slave address"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40060000+0x04)&0x300)==0x300)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IADR,Internal Address Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 0x01 " IADR ,Internal address"
|
|
elif ((per.l(ad:0x40060000+0x04)&0x300)==0x200)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IADR,Internal Address Register"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " IADR ,Internal address"
|
|
elif ((per.l(ad:0x40060000+0x04)&0x300)==0x100)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IADR,Internal Address Register"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " IADR ,Internal address"
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "IADR,Internal Address Register"
|
|
endif
|
|
if ((per.l(ad:0x40060000+0xE4)&0x01)==0x00)
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
sif cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 24.--29. " HOLD ,TWD hold time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD hold time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock high divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock low divider"
|
|
elif cpuis("ATSAMA5D2?")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD hold time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " CKSRC ,Transfer rate clock source" "Peripheral clock,PMC PCK"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock high divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock low divider"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock high divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock low divider"
|
|
endif
|
|
else
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
sif cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 24.--29. " HOLD ,TWD hold time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD hold time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock high divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock low divider"
|
|
elif cpuis("ATSAMA5D2?")
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
bitfld.long 0x00 24.--28. " HOLD ,TWD hold time versus TWCK falling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 20. " CKSRC ,Transfer rate clock source" "Peripheral clock,PMC PCK"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock high divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock low divider"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CWGR,Clock Waveform Generator Register"
|
|
bitfld.long 0x00 16.--18. " CKDIV ,Clock divider" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CHDIV ,Clock high divider"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLDIV ,Clock low divider"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "SR,Status Register"
|
|
in
|
|
newline
|
|
sif cpuis("ATSAME70*")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SMBTR,TWIHS SMBus Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THMAX ,Clock high maximum cycles"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOWM ,Master clock stretch maximum cycles"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOWS ,Slave clock stretch maximum cycles"
|
|
bitfld.long 0x00 0.--3. " PRESC ,SMBus clock prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "FILTR,TWIHS Filter Register"
|
|
bitfld.long 0x00 8.--10. " THRES ,Digital filter threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PADFCFG ,PAD filter config" "0,1"
|
|
bitfld.long 0x00 1. " PADFEN ,PAD filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FILT ,RX digital filter" "Not active,Active"
|
|
else
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAMA5D2?")
|
|
if ((per.l(ad:0x40060000+0xE4)&0x01)==0x00)
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SMBTR,TWIHS SMBus Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THMAX ,Clock high maximum cycles"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOWM ,Master clock stretch maximum cycles"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOWS ,Slave clock stretch maximum cycles"
|
|
bitfld.long 0x00 0.--3. " PRESC ,SMBus clock prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "SMBTR,TWIHS SMBus Timing Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THMAX ,Clock high maximum cycles"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TLOWM ,Master clock stretch maximum cycles"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TLOWS ,Slave clock stretch maximum cycles"
|
|
bitfld.long 0x00 0.--3. " PRESC ,SMBus clock prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("ATSAMA5D2?")
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ACR,TWIHS Alternative Command Register"
|
|
bitfld.long 0x00 25. " NPEC ,Next PEC request" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " NDIR ,Next transfer direction" "Write,Read"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NDATAL ,Next data length"
|
|
bitfld.long 0x00 9. " PEC ,PEC request" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " DIR ,Transfer direction" "Write,Read"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATAL ,Data length"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "FILTR,TWIHS Filter Register"
|
|
bitfld.long 0x00 8.--10. " THRES ,Digital filter threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. " PADFCFG ,PAD filter config" "0,1"
|
|
bitfld.long 0x00 1. " PADFEN ,PAD filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FILT ,RX digital filter" "Not active,Active"
|
|
endif
|
|
endif
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " SMBHHM ,SMBus host header address match interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " SMBDAM ,SMBus default address match interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " PECERR ,PEC error interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " TOUT ,Timeout error interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " MCACK ,Master code acknowledge interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOSACC ,End of slave access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SCL_WS ,Clock wait state interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ABRLST ,Arbitration lost interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NACK ,Not acknowledge interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " UNRE ,Underrun error interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVRE ,Overrun error interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GACC ,General call access interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " SVACC ,Slave access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXRDY ,Transmit holding register ready interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY ,Receive holding register ready interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXCOMP ,Transmission completed interrupt" "Masked,Not masked"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
sif cpuis("ATSAMA5D3*")
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOSACC ,End of slave access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " SCL_WS ,Clock wait state interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ABRLST ,Arbitration lost interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " NACK ,Not acknowledge" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " OVRE ,Overrun error" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " GACC ,General call access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " SVACC ,Slave access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXRDY ,Transmit holding register ready interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXRDY ,Receive holding register ready interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXCOMP ,Transmission completed interrupt" "Masked,Not masked"
|
|
else
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " EOSACC ,End of slave access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " SCL_WS ,Clock wait state interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " ABRLST ,Arbitration lost interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " NACK ,Not acknowledge" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " OVRE ,Overrun error" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " GACC ,General call access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " SVACC ,Slave access interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " TXRDY ,Transmit holding register ready interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " RXRDY ,Receive holding register ready interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " TXCOMP ,Transmission completed interrupt" "Masked,Not masked"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "RHR,Receive Holding Register"
|
|
in
|
|
newline
|
|
sif cpuis("ATSAME7*")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SWMR,TWIHS Sleep Walking Matching Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATAM ,Data match"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR3 ,Slave address 3"
|
|
hexmask.long.byte 0x00 8.--14. 0x01 " SADR2 ,Slave address 2"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " SADR1 ,Slave address 1"
|
|
else
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAMA5D2?")
|
|
if ((per.l(ad:0x40060000+0xE4)&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SWMR,TWIHS SleepWalking Matching Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATAM ,Data match"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR3 ,Slave address 3"
|
|
hexmask.long.byte 0x00 8.--14. 0x01 " SADR2 ,Slave address 2"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " SADR1 ,Slave address 1"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "SWMR,TWIHS SleepWalking Matching Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATAM ,Data match"
|
|
hexmask.long.byte 0x00 16.--22. 0x01 " SADR3 ,Slave address 3"
|
|
hexmask.long.byte 0x00 8.--14. 0x01 " SADR2 ,Slave address 2"
|
|
hexmask.long.byte 0x00 0.--6. 0x01 " SADR1 ,Slave address 1"
|
|
endif
|
|
endif
|
|
endif
|
|
sif cpuis("ATSAMA5D2?")
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "THR,Transmit Holding Register"
|
|
else
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "THR,Transmit Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,Master or slave transmit holding data"
|
|
endif
|
|
sif cpuis("ATSAMA5D2?")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "FMR,TWIHS FIFO Mode Register"
|
|
bitfld.long 0x00 24.--29. " RXFTHRES ,Receive FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 16.--21. " TXFTHRES ,Transmit FIFO threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 4.--5. " RXRDYM ,Receiver ready mode" "ONE_DATA,TWO_DATA,FOUR_DATA,?..."
|
|
bitfld.long 0x00 0.--1. " TXRDYM ,Transmitter ready mode" "ONE_DATA,TWO_DATA,FOUR_DATA,?..."
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "FLR,TWIHS FIFO Level Register"
|
|
bitfld.long 0x00 16.--21. " RXFL ,Receive FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0.--5. " TXFL ,Transmit FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
newline
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "FSR,TWIHS FIFO Status Register"
|
|
in
|
|
newline
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "FIMR_SET/CLR,TWIHS FIFO Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " RXFPTEF ,RXFPTEF interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " TXFPTEF ,TXFPTEF interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " RXFTHF ,RXFTHF interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RXFFF ,RXFFF interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RXFEF ,RXFEF interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXFTHF ,TXFTHF interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXFFF ,TXFFF interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXFEF ,TXFEF interrupt mask" "Masked,Not masked"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protection mode security code"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection bit" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "SSC (Synchronous Serial Controller)"
|
|
base ad:0x40004000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,SSC Control Register"
|
|
bitfld.long 0x00 15. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 9. " TXDIS ,Transmit disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " TXEN ,Transmit enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXDIS ,Receive disable" "No effect,Disabled"
|
|
newline
|
|
bitfld.long 0x00 0. " RXEN ,Receive enable" "No effect,Enabled"
|
|
sif cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
if ((per.l(ad:0x40004000+0xE4)&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CMR,SSC Clock Mode Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIV ,Clock divider"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "RCMR,SSC Receive Clock Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PERIOD ,Receive period divider selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STTDLY ,Receive start delay"
|
|
bitfld.long 0x00 12. " STOP ,Receive stop selection" "Completed,Compare 1"
|
|
bitfld.long 0x00 8.--11. " START ,Receive start selection" "Continuous,Transmit start,Low,High,Falling,Rising,Level change,Any edge,Compare 0,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. " CKG ,Receive clock gating selection" "No gating,Low,High,?..."
|
|
bitfld.long 0x00 5. " CKI ,Receive clock inversion (data inputs/frame sync)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 2.--4. " CKO ,Receive clock output mode selection" "No clock,Continuous,During transfers,?..."
|
|
bitfld.long 0x00 0.--1. " CKS ,Receive clock selection" "Divided,TK,RK,?..."
|
|
line.long 0x04 "RFMR,SSC Receive Frame Mode Register"
|
|
bitfld.long 0x04 28.--31. " FSLEN_EXT ,FSLEN field extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24. " FSEDGE ,Frame sync edge detection" "Positive,Negative"
|
|
bitfld.long 0x04 20.--22. " FSOS ,Receive frame sync output selection" "No signal,Negative,Positive,Low,High,Toggled,?..."
|
|
bitfld.long 0x04 16.--19. " FSLEN ,Receive frame sync length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 8.--11. " DATNB ,Data number per frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x04 7. " MSBF ,Most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x04 5. " LOOP ,Loop mode" "Normal,Loop"
|
|
bitfld.long 0x04 0.--4. " DATLEN ,Data length" ",2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
line.long 0x08 "TCMR,SSC Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PERIOD ,Transmit period divider selection"
|
|
hexmask.long.byte 0x08 16.--23. 1. " STTDLY ,Transmit start delay"
|
|
bitfld.long 0x08 8.--11. " START ,Transmit start selection" "Continuous,Receive start,Low,High,Falling,Rising,Level change,Any edge,?..."
|
|
bitfld.long 0x08 6.--7. " CKG ,Transmit clock gating selection" "No gating,Low,High,?..."
|
|
newline
|
|
bitfld.long 0x08 5. " CKI ,Transmit clock inversion (shifted out/sampled)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x08 2.--4. " CKO ,Transmit clock output mode selection" "No clock,Continuous,During transfers,?..."
|
|
bitfld.long 0x08 0.--1. " CKS ,Transmit clock selection" "Divided,RK,TK,?..."
|
|
line.long 0x0C "TFMR,SSC Transmit Frame Mode Register"
|
|
bitfld.long 0x0C 28.--31. " FSLEN_EXT ,FSLEN field extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 24. " FSEDGE ,Frame sync edge detection" "Positive,Negative"
|
|
bitfld.long 0x0C 23. " FSDEN ,Frame sync data enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20.--22. " FSOS ,Transmit frame sync output selection" "No signal,Negative,Positive,Low,High,Toggled,?..."
|
|
newline
|
|
bitfld.long 0x0C 16.--19. " FSLEN ,Transmit frame sync length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 8.--11. " DATNB ,Data number per frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x0C 7. " MSBF ,Most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x0C 5. " DATDEF ,Data default value" "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " DATLEN ,Data length" ",2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CMR,SSC Clock Mode Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIV ,Clock divider"
|
|
rgroup.long 0x10++0x0F
|
|
line.long 0x00 "RCMR,SSC Receive Clock Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PERIOD ,Receive period divider selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STTDLY ,Receive start delay"
|
|
bitfld.long 0x00 12. " STOP ,Receive stop selection" "Completed,Compare 1"
|
|
bitfld.long 0x00 8.--11. " START ,Receive start selection" "Continuous,Transmit start,Low,High,Falling,Rising,Level change,Any edge,Compare 0,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. " CKG ,Receive clock gating selection" "No gating,Low,High,?..."
|
|
bitfld.long 0x00 5. " CKI ,Receive clock inversion (data inputs/frame sync)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 2.--4. " CKO ,Receive clock output mode selection" "No clock,Continuous,During transfers,?..."
|
|
bitfld.long 0x00 0.--1. " CKS ,Receive clock selection" "Divided,TK,RK,?..."
|
|
line.long 0x04 "RFMR,SSC Receive Frame Mode Register"
|
|
bitfld.long 0x04 28.--31. " FSLEN_EXT ,FSLEN field extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24. " FSEDGE ,Frame sync edge detection" "Positive,Negative"
|
|
bitfld.long 0x04 20.--22. " FSOS ,Receive frame sync output selection" "No signal,Negative,Positive,Low,High,Toggled,?..."
|
|
bitfld.long 0x04 16.--19. " FSLEN ,Receive frame sync length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 8.--11. " DATNB ,Data number per frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x04 7. " MSBF ,Most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x04 5. " LOOP ,Loop mode" "Normal,Loop"
|
|
bitfld.long 0x04 0.--4. " DATLEN ,Data length" ",2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
line.long 0x08 "TCMR,SSC Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PERIOD ,Transmit period divider selection"
|
|
hexmask.long.byte 0x08 16.--23. 1. " STTDLY ,Transmit start delay"
|
|
bitfld.long 0x08 8.--11. " START ,Transmit start selection" "Continuous,Receive start,Low,High,Falling,Rising,Level change,Any edge,?..."
|
|
bitfld.long 0x08 6.--7. " CKG ,Transmit clock gating selection" "No gating,Low,High,?..."
|
|
newline
|
|
bitfld.long 0x08 5. " CKI ,Transmit clock inversion (shifted out/sampled)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x08 2.--4. " CKO ,Transmit clock output mode selection" "No clock,Continuous,During transfers,?..."
|
|
bitfld.long 0x08 0.--1. " CKS ,Transmit clock selection" "Divided,RK,TK,?..."
|
|
line.long 0x0C "TFMR,SSC Transmit Frame Mode Register"
|
|
bitfld.long 0x0C 28.--31. " FSLEN_EXT ,FSLEN field extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 24. " FSEDGE ,Frame sync edge detection" "Positive,Negative"
|
|
bitfld.long 0x0C 23. " FSDEN ,Frame sync data enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20.--22. " FSOS ,Transmit frame sync output selection" "No signal,Negative,Positive,Low,High,Toggled,?..."
|
|
newline
|
|
bitfld.long 0x0C 16.--19. " FSLEN ,Transmit frame sync length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 8.--11. " DATNB ,Data number per frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x0C 7. " MSBF ,Most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x0C 5. " DATDEF ,Data default value" "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " DATLEN ,Data length" ",2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CMR,SSC Clock Mode Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DIV ,Clock divider"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "RCMR,SSC Receive Clock Mode Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " PERIOD ,Receive period divider selection"
|
|
hexmask.long.byte 0x00 16.--23. 1. " STTDLY ,Receive start delay"
|
|
bitfld.long 0x00 12. " STOP ,Receive stop selection" "Completed,Compare 1"
|
|
bitfld.long 0x00 8.--11. " START ,Receive start selection" "Continuous,Transmit start,Low,High,Falling,Rising,Level change,Any edge,Compare 0,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. " CKG ,Receive clock gating selection" "No gating,RF Low,RF High,?..."
|
|
bitfld.long 0x00 5. " CKI ,Receive clock inversion (data inputs/frame sync)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x00 2.--4. " CKO ,Receive clock output mode selection" "No clock,Continuous,During transfers,?..."
|
|
bitfld.long 0x00 0.--1. " CKS ,Receive clock selection" "Divided,TK,RK,?..."
|
|
line.long 0x04 "RFMR,SSC Receive Frame Mode Register"
|
|
bitfld.long 0x04 28.--31. " FSLEN_EXT ,FSLEN field extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24. " FSEDGE ,Frame sync edge detection" "Positive,Negative"
|
|
bitfld.long 0x04 20.--22. " FSOS ,Receive frame sync output selection" "No signal,Negative,Positive,Low,High,Toggled,?..."
|
|
bitfld.long 0x04 16.--19. " FSLEN ,Receive frame sync length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x04 8.--11. " DATNB ,Data number per frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x04 7. " MSBF ,Most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x04 5. " LOOP ,Loop mode" "Normal,Loop"
|
|
bitfld.long 0x04 0.--4. " DATLEN ,Data length" ",2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
line.long 0x08 "TCMR,SSC Transmit Clock Mode Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " PERIOD ,Transmit period divider selection"
|
|
hexmask.long.byte 0x08 16.--23. 1. " STTDLY ,Transmit start delay"
|
|
bitfld.long 0x08 8.--11. " START ,Transmit start selection" "Continuous,Receive start,Low,High,Falling,Rising,Level change,Any edge,?..."
|
|
bitfld.long 0x08 6.--7. " CKG ,Transmit clock gating selection" "No gating,Low,High,?..."
|
|
newline
|
|
bitfld.long 0x08 5. " CKI ,Transmit clock inversion (shifted out/sampled)" "Falling/rising,Rising/falling"
|
|
bitfld.long 0x08 2.--4. " CKO ,Transmit clock output mode selection" "No clock,Continuous,During transfers,?..."
|
|
bitfld.long 0x08 0.--1. " CKS ,Transmit clock selection" "Divided,RK,TK,?..."
|
|
line.long 0x0C "TFMR,SSC Transmit Frame Mode Register"
|
|
bitfld.long 0x0C 28.--31. " FSLEN_EXT ,FSLEN field extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 24. " FSEDGE ,Frame sync edge detection" "Positive,Negative"
|
|
bitfld.long 0x0C 23. " FSDEN ,Frame sync data enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20.--22. " FSOS ,Transmit frame sync output selection" "No signal,Negative,Positive,Low,High,Toggled,?..."
|
|
newline
|
|
bitfld.long 0x0C 16.--19. " FSLEN ,Transmit frame sync length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 8.--11. " DATNB ,Data number per frame" "1 word,2 words,3 words,4 words,5 words,6 words,7 words,8 words,9 words,10 words,11 words,12 words,13 words,14 words,15 words,16 words"
|
|
bitfld.long 0x0C 7. " MSBF ,Most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x0C 5. " DATDEF ,Data default value" "Low,High"
|
|
newline
|
|
bitfld.long 0x0C 0.--4. " DATLEN ,Data length" ",2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
endif
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RHR,SSC Receive Holding Register"
|
|
in
|
|
newline
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "THR,SSC Transmit Holding Register"
|
|
newline
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "RSHR,SSC Receive Synchronization Holding Register"
|
|
in
|
|
newline
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TSHR,SSC Transmit Synchronization Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " TSDAT ,Transmit synchronization data"
|
|
sif cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
if ((per.l(ad:0x40004000+0xE4)&0x01)==0x00)
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "RC0R,SSC Receive Compare 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CP0 ,Receive compare data 0"
|
|
line.long 0x04 "RC1R,SSC Receive Compare 1 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CP1 ,Receive compare data 1"
|
|
else
|
|
rgroup.long 0x38++0x07
|
|
line.long 0x00 "RC0R,SSC Receive Compare 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CP0 ,Receive compare data 0"
|
|
line.long 0x04 "RC1R,SSC Receive Compare 1 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CP1 ,Receive compare data 1"
|
|
endif
|
|
else
|
|
group.long 0x38++0x07
|
|
line.long 0x00 "RC0R,SSC Receive Compare 0 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CP0 ,Receive compare data 0"
|
|
line.long 0x04 "RC1R,SSC Receive Compare 1 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CP1 ,Receive compare data 1"
|
|
endif
|
|
newline
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "SR,SSC Status Register"
|
|
in
|
|
newline
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,SSC Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " RXSYN ,Rx sync interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " TXSYN ,Tx sync interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " CP1 ,Compare 1 interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " CP0 ,Compare 0 interrupt" "Masked,Unmasked"
|
|
newline
|
|
sif !cpuis("AT91SAM3A*")&&!cpuis("AT91SAM3X4C")&&!cpuis("AT91SAM3X4E")&&!cpuis("AT91SAM3X8C")&&!cpuis("AT91SAM3X8E")&&!cpuis("ATSAMV7*")&&!cpuis("ATSAMS7*")&&!cpuis("ATSAME70*")
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " RXBUFF ,Receive buffer full interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " ENDRX ,Reception end interrupt" "Masked,Unmasked"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRUN ,Receive overrun interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " RXRDY ,Receive ready interrupt" "Masked,Unmasked"
|
|
newline
|
|
sif !cpuis("AT91SAM3A*")&&!cpuis("AT91SAM3X4C")&&!cpuis("AT91SAM3X4E")&&!cpuis("AT91SAM3X8C")&&!cpuis("AT91SAM3X8E")&&!cpuis("ATSAMV7*")&&!cpuis("ATSAMS7*")&&!cpuis("ATSAME70*")
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " TXBUFE ,Transmit buffer empty interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " ENDTX ,Transmission end interrupt" "Masked,Unmasked"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXEMPTY ,Transmit empty interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXRDY ,Transmit ready interrupt" "Masked,Unmasked"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,SSC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,SSC Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("ATSAMS70J*")
|
|
sif !cpuis("ATSAMS70N*")
|
|
tree.open "I2SC (Inter-IC Sound Controller)"
|
|
tree "I2SC0"
|
|
base ad:0x4008C000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Inter-IC Sound Controller Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " TXDIS ,Transmitter disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " TXEN ,Transmitter enable" "No effect,Enabled"
|
|
bitfld.long 0x00 3. " CKDIS ,Clocks disable" "No effect,Disabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CKEN ,Clocks enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXDIS ,Receiver disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXEN ,Receiver enable" "No effect,Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Inter-IC Mode Register"
|
|
bitfld.long 0x00 31. " IWS ,I2SWS slot width" "32bit,24bit"
|
|
bitfld.long 0x00 30. " IMCKMODE ,Master clock mode" "Not generated,Generated"
|
|
bitfld.long 0x00 24.--29. " IMCKFS ,Master clock to fs ratio" "M2SF32,M2SF64,M2SF96,M2SF128,,M2SF192,,M2SF256,,,,M2SF384,,,,M2SF512,,,,,,,,M2SF768,,,,,,,,M2SF31024,,,,,,,,,,,,,,,,M2SF1536,,,,,,,,,,,,,,,,M2SF2048"
|
|
bitfld.long 0x00 16.--21. " IMCKDIV ,Clock to I2SC master clock ratio" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14. " TXSAME ,Transmit data when underrun" "Zero,Previous"
|
|
bitfld.long 0x00 13. " TXDMA ,Single or multiple DMA controller channels for transmitter" "Single,Multiple"
|
|
bitfld.long 0x00 12. " TXMONO ,Transmit mono" "Stereo,Mono"
|
|
bitfld.long 0x00 10. " RXLOOP ,Loop-back test mode" "Normal,Internal"
|
|
newline
|
|
bitfld.long 0x00 9. " RXDMA ,Single or multiple DMA controller channels for receiver" "Single,Multiple"
|
|
bitfld.long 0x00 8. " RXMONO ,Receive mono" "Stereo,Mono"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 6.--7. " FORMAT ,Data format" "I2S,LJ,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2.--4. " DATALENGTH ,Data word length" "32_BITS,24_BITS,20_BITS,18_BITS,16_BITS,16_BITS_COMPACT,8_BITS,8_BITS_COMPACT"
|
|
bitfld.long 0x00 0. " MODE ,Inter-IC sound controller mode" "Slave,Master"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR,Inter-IC Sound Controller Status Register"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x04 21. " TXURCH[1]_SET/CLR ,Transmit underrun channel 1" "No underrun,Underrun"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x04 20. " TXURCH[0]_SET/CLR ,Transmit underrun channel 0" "No underrun,Underrun"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " RXORCH[1]_SET/CLR ,Receive overrun channel 1" "No overrun,Overrun"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " RXORCH[0]_SET/CLR ,Receive overrun channel 0" "No overrun,Overrun"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " TXUR_SET/CLR ,Transmit underrun" "No underrun,Underrun"
|
|
rbitfld.long 0x00 5. " TXRDY ,Transmit ready" "Not ready,Ready"
|
|
rbitfld.long 0x00 4. " TXEN ,Transmitter enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXOR_SET/CLR ,Receive overrun" "No overrun,Overrun"
|
|
newline
|
|
rbitfld.long 0x00 1. " RXRDY ,Receive ready" "Not ready,Ready"
|
|
rbitfld.long 0x00 0. " RXEN ,Receiver enabled" "Disabled,Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Inter-IC Sound Controller Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " TXUR ,Transmit underflow interrupt disable" "No,Yes"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " TXRDY ,Transmit ready interrupt disable" "No,Yes"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " RXOR ,Receiver overrun interrupt disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " RXRDY ,Receiver ready interrupt disable" "No,Yes"
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RHR,Inter-IC Sound Controller Receiver Holding Register"
|
|
in
|
|
newline
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "THR,Inter-IC Transmitter Holding Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2SC0"
|
|
base ad:0x40090000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Inter-IC Sound Controller Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " TXDIS ,Transmitter disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " TXEN ,Transmitter enable" "No effect,Enabled"
|
|
bitfld.long 0x00 3. " CKDIS ,Clocks disable" "No effect,Disabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CKEN ,Clocks enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXDIS ,Receiver disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXEN ,Receiver enable" "No effect,Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Inter-IC Mode Register"
|
|
bitfld.long 0x00 31. " IWS ,I2SWS slot width" "32bit,24bit"
|
|
bitfld.long 0x00 30. " IMCKMODE ,Master clock mode" "Not generated,Generated"
|
|
bitfld.long 0x00 24.--29. " IMCKFS ,Master clock to fs ratio" "M2SF32,M2SF64,M2SF96,M2SF128,,M2SF192,,M2SF256,,,,M2SF384,,,,M2SF512,,,,,,,,M2SF768,,,,,,,,M2SF31024,,,,,,,,,,,,,,,,M2SF1536,,,,,,,,,,,,,,,,M2SF2048"
|
|
bitfld.long 0x00 16.--21. " IMCKDIV ,Clock to I2SC master clock ratio" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14. " TXSAME ,Transmit data when underrun" "Zero,Previous"
|
|
bitfld.long 0x00 13. " TXDMA ,Single or multiple DMA controller channels for transmitter" "Single,Multiple"
|
|
bitfld.long 0x00 12. " TXMONO ,Transmit mono" "Stereo,Mono"
|
|
bitfld.long 0x00 10. " RXLOOP ,Loop-back test mode" "Normal,Internal"
|
|
newline
|
|
bitfld.long 0x00 9. " RXDMA ,Single or multiple DMA controller channels for receiver" "Single,Multiple"
|
|
bitfld.long 0x00 8. " RXMONO ,Receive mono" "Stereo,Mono"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 6.--7. " FORMAT ,Data format" "I2S,LJ,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2.--4. " DATALENGTH ,Data word length" "32_BITS,24_BITS,20_BITS,18_BITS,16_BITS,16_BITS_COMPACT,8_BITS,8_BITS_COMPACT"
|
|
bitfld.long 0x00 0. " MODE ,Inter-IC sound controller mode" "Slave,Master"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR,Inter-IC Sound Controller Status Register"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x04 21. " TXURCH[1]_SET/CLR ,Transmit underrun channel 1" "No underrun,Underrun"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x04 20. " TXURCH[0]_SET/CLR ,Transmit underrun channel 0" "No underrun,Underrun"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " RXORCH[1]_SET/CLR ,Receive overrun channel 1" "No overrun,Overrun"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " RXORCH[0]_SET/CLR ,Receive overrun channel 0" "No overrun,Overrun"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " TXUR_SET/CLR ,Transmit underrun" "No underrun,Underrun"
|
|
rbitfld.long 0x00 5. " TXRDY ,Transmit ready" "Not ready,Ready"
|
|
rbitfld.long 0x00 4. " TXEN ,Transmitter enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXOR_SET/CLR ,Receive overrun" "No overrun,Overrun"
|
|
newline
|
|
rbitfld.long 0x00 1. " RXRDY ,Receive ready" "Not ready,Ready"
|
|
rbitfld.long 0x00 0. " RXEN ,Receiver enabled" "Disabled,Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Inter-IC Sound Controller Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " TXUR ,Transmit underflow interrupt disable" "No,Yes"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " TXRDY ,Transmit ready interrupt disable" "No,Yes"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " RXOR ,Receiver overrun interrupt disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " RXRDY ,Receiver ready interrupt disable" "No,Yes"
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RHR,Inter-IC Sound Controller Receiver Holding Register"
|
|
in
|
|
newline
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "THR,Inter-IC Transmitter Holding Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
else
|
|
tree "I2SC (Inter-IC Sound Controller)"
|
|
base ad:0x4008C000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Inter-IC Sound Controller Control Register"
|
|
bitfld.long 0x00 7. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 5. " TXDIS ,Transmitter disable" "No effect,Disabled"
|
|
bitfld.long 0x00 4. " TXEN ,Transmitter enable" "No effect,Enabled"
|
|
bitfld.long 0x00 3. " CKDIS ,Clocks disable" "No effect,Disabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CKEN ,Clocks enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " RXDIS ,Receiver disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " RXEN ,Receiver enable" "No effect,Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Inter-IC Mode Register"
|
|
bitfld.long 0x00 31. " IWS ,I2SWS slot width" "32bit,24bit"
|
|
bitfld.long 0x00 30. " IMCKMODE ,Master clock mode" "Not generated,Generated"
|
|
bitfld.long 0x00 24.--29. " IMCKFS ,Master clock to fs ratio" "M2SF32,M2SF64,M2SF96,M2SF128,,M2SF192,,M2SF256,,,,M2SF384,,,,M2SF512,,,,,,,,M2SF768,,,,,,,,M2SF31024,,,,,,,,,,,,,,,,M2SF1536,,,,,,,,,,,,,,,,M2SF2048"
|
|
bitfld.long 0x00 16.--21. " IMCKDIV ,Clock to I2SC master clock ratio" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 14. " TXSAME ,Transmit data when underrun" "Zero,Previous"
|
|
bitfld.long 0x00 13. " TXDMA ,Single or multiple DMA controller channels for transmitter" "Single,Multiple"
|
|
bitfld.long 0x00 12. " TXMONO ,Transmit mono" "Stereo,Mono"
|
|
bitfld.long 0x00 10. " RXLOOP ,Loop-back test mode" "Normal,Internal"
|
|
newline
|
|
bitfld.long 0x00 9. " RXDMA ,Single or multiple DMA controller channels for receiver" "Single,Multiple"
|
|
bitfld.long 0x00 8. " RXMONO ,Receive mono" "Stereo,Mono"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 6.--7. " FORMAT ,Data format" "I2S,LJ,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 2.--4. " DATALENGTH ,Data word length" "32_BITS,24_BITS,20_BITS,18_BITS,16_BITS,16_BITS_COMPACT,8_BITS,8_BITS_COMPACT"
|
|
bitfld.long 0x00 0. " MODE ,Inter-IC sound controller mode" "Slave,Master"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR,Inter-IC Sound Controller Status Register"
|
|
setclrfld.long 0x00 21. 0x08 21. 0x04 21. " TXURCH[1]_SET/CLR ,Transmit underrun channel 1" "No underrun,Underrun"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x04 20. " TXURCH[0]_SET/CLR ,Transmit underrun channel 0" "No underrun,Underrun"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " RXORCH[1]_SET/CLR ,Receive overrun channel 1" "No overrun,Overrun"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " RXORCH[0]_SET/CLR ,Receive overrun channel 0" "No overrun,Overrun"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " TXUR_SET/CLR ,Transmit underrun" "No underrun,Underrun"
|
|
rbitfld.long 0x00 5. " TXRDY ,Transmit ready" "Not ready,Ready"
|
|
rbitfld.long 0x00 4. " TXEN ,Transmitter enabled" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " RXOR_SET/CLR ,Receive overrun" "No overrun,Overrun"
|
|
newline
|
|
rbitfld.long 0x00 1. " RXRDY ,Receive ready" "Not ready,Ready"
|
|
rbitfld.long 0x00 0. " RXEN ,Receiver enabled" "Disabled,Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Inter-IC Sound Controller Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " TXUR ,Transmit underflow interrupt disable" "No,Yes"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " TXRDY ,Transmit ready interrupt disable" "No,Yes"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " RXOR ,Receiver overrun interrupt disable" "No,Yes"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " RXRDY ,Receiver ready interrupt disable" "No,Yes"
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "RHR,Inter-IC Sound Controller Receiver Holding Register"
|
|
in
|
|
newline
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "THR,Inter-IC Transmitter Holding Register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
endif
|
|
sif !cpuis("ATSAMS70J*")
|
|
tree.open "USART (Universal Synchronous Asynchronous Receiver Transmitter)"
|
|
tree "USART 0"
|
|
base ad:0x40024000
|
|
width 13.
|
|
if ((per.l(ad:0x40024000+0x04)&0x0F)==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN wakeup signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to send pin control" "No effect,Drive RTS to 1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to send pin control" "No effect,Drive RTS to 0"
|
|
newline
|
|
bitfld.long 0x00 17. " DTRDIS ,Data terminal ready disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " DTREN ,Data terminal ready enable" "No effect,Enable"
|
|
bitfld.long 0x00 15. " RETTO ,Start time-out immediately" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset non acknowledge" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 12. " SENDA ,Send address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT flag and start time-out after next character received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop break" "No effect,Stop"
|
|
bitfld.long 0x00 9. " STTBRK ,Start break" "No effect,Start"
|
|
newline
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
elif ((per.l(ad:0x40024000+0x04)&0x0F)==0x02)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN wakeup signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to send pin control" "No effect,Drive RTS to 0"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to send pin control" "No effect,Drive RTS to 1"
|
|
newline
|
|
bitfld.long 0x00 17. " DTRDIS ,Data terminal ready disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " DTREN ,Data terminal ready enable" "No effect,Enable"
|
|
bitfld.long 0x00 15. " RETTO ,Start time-out immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send address" "No effect,Send"
|
|
newline
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT flag and start time-out after next character received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop break" "No effect,Stop"
|
|
bitfld.long 0x00 9. " STTBRK ,Start break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
elif (((per.l(ad:0x40024000+0x04)&0x0F)==0x04)||((per.l(ad:0x40024000+0x04)&0x0F)==0x06))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN wakeup signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN transmission" "No effect,Abort transmission"
|
|
newline
|
|
bitfld.long 0x00 17. " DTRDIS ,Data terminal ready disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " DTREN ,Data terminal ready enable" "No effect,Enable"
|
|
bitfld.long 0x00 15. " RETTO ,Start time-out immediately" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset non acknowledge" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 13. " RSTIT ,Reset iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT flag and start time-out after next character received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop break" "No effect,Stop"
|
|
newline
|
|
bitfld.long 0x00 9. " STTBRK ,Start break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
elif ((per.l((ad:0x40024000)+0x04)&0x0F)==0x0E)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 19. " RCS ,Release SPI chip select (release slave select line NSS)" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI chip select (force slave select line NSS to 0)" "No effect,Force"
|
|
newline
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
elif ((per.l((ad:0x40024000)+0x04)&0x0F)==0x0F)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN wakeup signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN transmission" "No effect,Abort transmission"
|
|
newline
|
|
bitfld.long 0x00 17. " DTRDIS ,Data terminal ready disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " DTREN ,Data terminal ready enable" "No effect,Enable"
|
|
bitfld.long 0x00 15. " RETTO ,Start time-out immediately" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset non acknowledge" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 12. " SENDA ,Send address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT flag and start time-out after next character received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop break" "No effect,Stop"
|
|
bitfld.long 0x00 9. " STTBRK ,Start break" "No effect,Start"
|
|
newline
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
endif
|
|
if ((per.l(ad:0x40024000+0xE4)&0x01)==0x00)
|
|
if ((per.l(ad:0x40024000+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 20. " WRDBT ,Wait read data before transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock output select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI clock polarity" "Inactive-low,Inactive-high"
|
|
newline
|
|
bitfld.long 0x00 8. " CPHA ,SPI clock phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/captured,Captured/changed"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock selection" "MCK,MCK/8,,SCK"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN master,LIN slave,,,SPI master,SPI slave"
|
|
newline
|
|
else
|
|
if (((per.l(ad:0x40024000+0x04))&0x100)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start frame delimiter selector" "DATA SYNC,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester synchronization mode" "0 to 1,1 to 0"
|
|
bitfld.long 0x00 29. " MAN ,Manchester encoder/decoder enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Receive line filter" "Not filtered,Filtered"
|
|
newline
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum number of automatic iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted data" "Not inverted,Inverted"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable synchronization of command/data sync" "User defined,THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable successive NACK" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 20. " INACK ,Inhibit non acknowledge" "Generated,Not generated"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock output select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit character length" "Def by CHRL,9-bit"
|
|
newline
|
|
bitfld.long 0x00 16. " MSBF ,Bit order" "LSB,MSB"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of stop bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
newline
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous mode select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock selection" "MCK,MCK/8,PCK,SCK"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN master,LIN slave,,,SPI master,SPI slave"
|
|
newline
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start frame delimiter selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester synchronization mode" "0 to 1,1 to 0"
|
|
bitfld.long 0x00 29. " MAN ,Manchester encoder/decoder enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Receive line filter" "Not filtered,Filtered"
|
|
newline
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum number of automatic iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted data" "Not inverted,Inverted"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable synchronization of command/data sync" "User defined,THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable successive NACK" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 20. " INACK ,Inhibit non acknowledge" "Generated,Not generated"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock output select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit character length" "Def by CHRL,9-bit"
|
|
newline
|
|
bitfld.long 0x00 16. " MSBF ,Bit order" "LSB,MSB"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of stop bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
newline
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous mode select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock selection" "MCK,MCK/8,PCK,SCK"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN master,LIN slave,,,SPI master,SPI slave"
|
|
newline
|
|
endif
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40024000+0x04)&0x0F)==(0x0E||0x0F))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 20. " WRDBT ,Wait read data before transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock output select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI clock polarity" "Inactive-low,Inactive-high"
|
|
newline
|
|
bitfld.long 0x00 8. " CPHA ,SPI clock phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/captured,Captured/changed"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock selection" "MCK,MCK/8,,SCK"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN master,LIN slave,,,SPI master,SPI slave"
|
|
newline
|
|
else
|
|
if (((per.l(ad:0x40024000+0x04))&0x100)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start frame delimiter selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester synchronization mode" "0 to 1,1 to 0"
|
|
bitfld.long 0x00 29. " MAN ,Manchester encoder/decoder enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Receive line filter" "Not filtered,Filtered"
|
|
newline
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum number of automatic iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted data" "Not inverted,Inverted"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable synchronization of command/data sync" "User defined,THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable successive NACK" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 20. " INACK ,Inhibit non acknowledge" "Generated,Not generated"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock output select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit character length" "Def by CHRL,9-bit"
|
|
newline
|
|
bitfld.long 0x00 16. " MSBF ,Bit order" "LSB,MSB"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of stop bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
newline
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous mode select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock selection" "MCK,MCK/8,PCK,SCK"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN master,LIN slave,,,SPI master,SPI slave"
|
|
newline
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start frame delimiter selector" "DATA SYNC,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester synchronization mode" "0 to 1,1 to 0"
|
|
bitfld.long 0x00 29. " MAN ,Manchester encoder/decoder enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Receive line filter" "Not filtered,Filtered"
|
|
newline
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum number of automatic iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted data" "Not inverted,Inverted"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable synchronization of command/data sync" "User defined,THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable successive NACK" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 20. " INACK ,Inhibit non acknowledge" "Generated,Not generated"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock output select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit character length" "Def by CHRL,9-bit"
|
|
newline
|
|
bitfld.long 0x00 16. " MSBF ,Bit order" "LSB,MSB"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of stop bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
newline
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous mode select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock selection" "MCK,MCK/8,PCK,SCK"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN master,LIN slave,,,SPI master,SPI slave"
|
|
newline
|
|
endif
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40024000+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " NSSE ,NSS line rising or falling edge event interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNRE ,SPI underrun error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,TXEMPTY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE ,Overrun error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY ,TXRDY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY ,RXRDY interrupt mask" "Masked,Not masked"
|
|
elif ((per.l(ad:0x40024000+0x04)&0x0F)==(0x0A||0x0B))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " LINHTE ,LIN header timeout error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " LINSTE ,LIN synch tolerance error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " LINSNRE ,LIN slave not responding error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " LINCE ,LIN checksum error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " LINIPE ,LIN identifier parity interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " LINISFE ,LIN inconsistent synch field error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " LINBE ,LIN bus error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " LINTC ,LIN transfer completed interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " LINID ,LIN identifier sent or LIN identifier received interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " LINBK ,LIN break sent or LIN break received interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,TXEMPTY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT ,Time-out interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE ,Parity error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME ,Framing error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE ,Overrun error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY ,TXRDY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY ,RXRDY interrupt mask" "Masked,Not masked"
|
|
elif ((per.l(ad:0x40024000+0x04)&0x0F)==0x09)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " LBLOVFE ,LON backlog overflow error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " LRXD ,LON reception done interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " LFET ,LON frame early termination interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " LCOL ,LON collision interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " LTXD ,LON transmission done interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNRE ,Underrun error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,TXEMPTY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " LCRCE ,LON CRC error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LSFE ,LON short frame error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE ,Overrun error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY ,TXRDY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY ,RXRDY interrupt mask" "Masked,Not masked"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " MANE ,Manchester error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC ,Clear to send input change interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " DCDIC ,Data carrier detect input change interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " DSRIC ,Data set ready input change mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " RIIC ,Ring indicator input change mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " NACK ,Non acknowledge interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " ITER ,Max number of repetitions reached interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,TXEMPTY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT ,Time-out interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE ,Parity error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME ,Framing error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE ,Overrun error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXBRK ,Receiver break interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY ,TXRDY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY ,RXRDY interrupt mask" "Masked,Not masked"
|
|
endif
|
|
newline
|
|
if ((per.l(ad:0x40024000+0x04)&0x0F)==(0x0E||0x0F))
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CSR,Channel Status Register"
|
|
in
|
|
elif ((per.l(ad:0x40024000+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((per.l(ad:0x40024000+0x04)&0x0F)==0x0A)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN header timeout error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN synch tolerance error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN slave not responding error" "No error,Error"
|
|
bitfld.long 0x00 28. " LINCE ,LIN checksum error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " LINIPE ,LIN identifier parity error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN inconsistent synch field error" "No error,Error"
|
|
bitfld.long 0x00 25. " LINBE ,LIN bit error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN bus line status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " LINTC ,LIN transfer completed" "Idle,Completed"
|
|
bitfld.long 0x00 14. " LINID ,LIN identifier sent" "Not sent,Sent"
|
|
bitfld.long 0x00 13. " LINBK ,LIN break sent" "Not sent,Sent"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver time-out" "No time-out,Time-out"
|
|
bitfld.long 0x00 7. " PARE ,Parity error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver ready" "Not ready,Ready"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN header timeout error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN synch tolerance error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN slave not responding error" "No error,Error"
|
|
bitfld.long 0x00 28. " LINCE ,LIN checksum error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " LINIPE ,LIN identifier parity error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN inconsistent synch field error" "No error,Error"
|
|
bitfld.long 0x00 25. " LINBE ,LIN bit error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN bus line status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " LINTC ,LIN transfer completed" "Idle,Completed"
|
|
bitfld.long 0x00 14. " LINID ,LIN identifier received" "Not received,Received"
|
|
bitfld.long 0x00 13. " LINBK ,LIN break received" "Not received,Received"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver time-out" "No time-out,Time-out"
|
|
bitfld.long 0x00 7. " PARE ,Parity error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver ready" "Not ready,Ready"
|
|
endif
|
|
elif ((per.l(ad:0x40024000+0x04)&0x0F)==0x09)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CSR,Channel Status Register"
|
|
bitfld.long 0x00 28. " LBLOVFE ,LON backlog overflow error" "No error,Error"
|
|
bitfld.long 0x00 27. " LRXD ,LON reception end flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 26. " LFET ,LON frame early termination" "No terminated,Terminated"
|
|
bitfld.long 0x00 25. " LCOL ,LON collision detected flag" "No occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 24. " LTXD ,LON transmission end flag" "No occurred,Performed"
|
|
bitfld.long 0x00 10. " UNRE ,Underrun error" "No error,Error"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter empty" "Not empty,Empty"
|
|
bitfld.long 0x00 7. " LCRCE ,LON CRC error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 6. " LSFE ,LON short frame error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver ready" "Not ready,Ready"
|
|
else
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CSR,Channel Status Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be transmitted"
|
|
if ((per.l(ad:0x40024000+0xE4)&0x01)==0x00)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out value"
|
|
if ((per.l(ad:0x40024000+0x04)&0x0F)==0x09)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PCYCLE ,LON PCYCLE length"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FIDI,FI DI Ratio Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BETA2 ,LON BETA2 length"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FIDI,FI DI Ratio Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI over DI ratio value"
|
|
endif
|
|
else
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out value"
|
|
if ((per.l(ad:0x40024000+0x04)&0x0F)==0x09)
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PCYCLE ,LON PCYCLE length"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "FIDI,FI DI Ratio Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BETA2 ,LON BETA2 length"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard value"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "FIDI,FI DI Ratio Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI over DI ratio value"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40024000+0x04)&0x0F)==0x04)||((per.l(ad:0x40024000+0x04)&0x0F)==0x06))
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "NER,Number Of Errors Register"
|
|
in
|
|
endif
|
|
if ((per.l(ad:0x40024000+0x04)&0x0F)==0x08)
|
|
if ((per.l(ad:0x40024000+0xE4)&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "IF,IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA filter"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "IF,IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA filter"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40024000+0xE4)&0x01)==0x00)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver idle value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver manchester polarity" "0-to-1,1-to-0"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver preamble pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver preamble length" "Disabled,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter manchester polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter preamble pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter preamble length" "Disabled,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver idle value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver manchester polarity" "0-to-1,1-to-0"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver preamble pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver preamble length" "Disabled,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter manchester polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter preamble pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter preamble length" "Disabled,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits"
|
|
endif
|
|
if ((per.l(ad:0x40024000+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((per.l(ad:0x40024000+0xE4)&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data length control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup signal type" "LIN 2.0,LIN 1.3"
|
|
newline
|
|
bitfld.long 0x00 6. " FSDIS ,Frame slot mode disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data length mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PARDIS ,Parity disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN mode action" "Publish,Subscribe,Ignore,?..."
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data length control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup signal type" "LIN 2.0,LIN 1.3"
|
|
newline
|
|
bitfld.long 0x00 6. " FSDIS ,Frame slot mode disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data length mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PARDIS ,Parity disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN node action" "Publish,Subscribe,Ignore,?..."
|
|
endif
|
|
if ((per.l(ad:0x40024000+0x04)&0x0F)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,Fractional part after synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,Clock divider after synchronization"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,USART Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART 1"
|
|
base ad:0x40028000
|
|
width 13.
|
|
if ((per.l(ad:0x40028000+0x04)&0x0F)==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN wakeup signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to send pin control" "No effect,Drive RTS to 1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to send pin control" "No effect,Drive RTS to 0"
|
|
newline
|
|
bitfld.long 0x00 17. " DTRDIS ,Data terminal ready disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " DTREN ,Data terminal ready enable" "No effect,Enable"
|
|
bitfld.long 0x00 15. " RETTO ,Start time-out immediately" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset non acknowledge" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 12. " SENDA ,Send address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT flag and start time-out after next character received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop break" "No effect,Stop"
|
|
bitfld.long 0x00 9. " STTBRK ,Start break" "No effect,Start"
|
|
newline
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
elif ((per.l(ad:0x40028000+0x04)&0x0F)==0x02)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN wakeup signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to send pin control" "No effect,Drive RTS to 0"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to send pin control" "No effect,Drive RTS to 1"
|
|
newline
|
|
bitfld.long 0x00 17. " DTRDIS ,Data terminal ready disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " DTREN ,Data terminal ready enable" "No effect,Enable"
|
|
bitfld.long 0x00 15. " RETTO ,Start time-out immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send address" "No effect,Send"
|
|
newline
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT flag and start time-out after next character received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop break" "No effect,Stop"
|
|
bitfld.long 0x00 9. " STTBRK ,Start break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
elif (((per.l(ad:0x40028000+0x04)&0x0F)==0x04)||((per.l(ad:0x40028000+0x04)&0x0F)==0x06))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN wakeup signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN transmission" "No effect,Abort transmission"
|
|
newline
|
|
bitfld.long 0x00 17. " DTRDIS ,Data terminal ready disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " DTREN ,Data terminal ready enable" "No effect,Enable"
|
|
bitfld.long 0x00 15. " RETTO ,Start time-out immediately" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset non acknowledge" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 13. " RSTIT ,Reset iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT flag and start time-out after next character received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop break" "No effect,Stop"
|
|
newline
|
|
bitfld.long 0x00 9. " STTBRK ,Start break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
elif ((per.l((ad:0x40028000)+0x04)&0x0F)==0x0E)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 19. " RCS ,Release SPI chip select (release slave select line NSS)" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI chip select (force slave select line NSS to 0)" "No effect,Force"
|
|
newline
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
elif ((per.l((ad:0x40028000)+0x04)&0x0F)==0x0F)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN wakeup signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN transmission" "No effect,Abort transmission"
|
|
newline
|
|
bitfld.long 0x00 17. " DTRDIS ,Data terminal ready disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " DTREN ,Data terminal ready enable" "No effect,Enable"
|
|
bitfld.long 0x00 15. " RETTO ,Start time-out immediately" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset non acknowledge" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 12. " SENDA ,Send address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT flag and start time-out after next character received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop break" "No effect,Stop"
|
|
bitfld.long 0x00 9. " STTBRK ,Start break" "No effect,Start"
|
|
newline
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
endif
|
|
if ((per.l(ad:0x40028000+0xE4)&0x01)==0x00)
|
|
if ((per.l(ad:0x40028000+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 20. " WRDBT ,Wait read data before transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock output select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI clock polarity" "Inactive-low,Inactive-high"
|
|
newline
|
|
bitfld.long 0x00 8. " CPHA ,SPI clock phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/captured,Captured/changed"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock selection" "MCK,MCK/8,,SCK"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,LON,LIN master,LIN slave,,,SPI master,SPI slave"
|
|
newline
|
|
else
|
|
if (((per.l(ad:0x40028000+0x04))&0x100)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start frame delimiter selector" "DATA SYNC,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester synchronization mode" "0 to 1,1 to 0"
|
|
bitfld.long 0x00 29. " MAN ,Manchester encoder/decoder enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Receive line filter" "Not filtered,Filtered"
|
|
newline
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum number of automatic iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted data" "Not inverted,Inverted"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable synchronization of command/data sync" "User defined,THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable successive NACK" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 20. " INACK ,Inhibit non acknowledge" "Generated,Not generated"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock output select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit character length" "Def by CHRL,9-bit"
|
|
newline
|
|
bitfld.long 0x00 16. " MSBF ,Bit order" "LSB,MSB"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of stop bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
newline
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous mode select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock selection" "MCK,MCK/8,PCK,SCK"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,LON,LIN master,LIN slave,,,SPI master,SPI slave"
|
|
newline
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start frame delimiter selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester synchronization mode" "0 to 1,1 to 0"
|
|
bitfld.long 0x00 29. " MAN ,Manchester encoder/decoder enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Receive line filter" "Not filtered,Filtered"
|
|
newline
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum number of automatic iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted data" "Not inverted,Inverted"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable synchronization of command/data sync" "User defined,THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable successive NACK" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 20. " INACK ,Inhibit non acknowledge" "Generated,Not generated"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock output select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit character length" "Def by CHRL,9-bit"
|
|
newline
|
|
bitfld.long 0x00 16. " MSBF ,Bit order" "LSB,MSB"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of stop bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
newline
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous mode select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock selection" "MCK,MCK/8,PCK,SCK"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,LON,LIN master,LIN slave,,,SPI master,SPI slave"
|
|
newline
|
|
endif
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x40028000+0x04)&0x0F)==(0x0E||0x0F))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 20. " WRDBT ,Wait read data before transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock output select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI clock polarity" "Inactive-low,Inactive-high"
|
|
newline
|
|
bitfld.long 0x00 8. " CPHA ,SPI clock phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/captured,Captured/changed"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock selection" "MCK,MCK/8,,SCK"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,LON,LIN master,LIN slave,,,SPI master,SPI slave"
|
|
newline
|
|
else
|
|
if (((per.l(ad:0x40028000+0x04))&0x100)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start frame delimiter selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester synchronization mode" "0 to 1,1 to 0"
|
|
bitfld.long 0x00 29. " MAN ,Manchester encoder/decoder enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Receive line filter" "Not filtered,Filtered"
|
|
newline
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum number of automatic iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted data" "Not inverted,Inverted"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable synchronization of command/data sync" "User defined,THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable successive NACK" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 20. " INACK ,Inhibit non acknowledge" "Generated,Not generated"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock output select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit character length" "Def by CHRL,9-bit"
|
|
newline
|
|
bitfld.long 0x00 16. " MSBF ,Bit order" "LSB,MSB"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of stop bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
newline
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous mode select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock selection" "MCK,MCK/8,PCK,SCK"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,LON,LIN master,LIN slave,,,SPI master,SPI slave"
|
|
newline
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start frame delimiter selector" "DATA SYNC,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester synchronization mode" "0 to 1,1 to 0"
|
|
bitfld.long 0x00 29. " MAN ,Manchester encoder/decoder enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Receive line filter" "Not filtered,Filtered"
|
|
newline
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum number of automatic iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted data" "Not inverted,Inverted"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable synchronization of command/data sync" "User defined,THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable successive NACK" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 20. " INACK ,Inhibit non acknowledge" "Generated,Not generated"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock output select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit character length" "Def by CHRL,9-bit"
|
|
newline
|
|
bitfld.long 0x00 16. " MSBF ,Bit order" "LSB,MSB"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of stop bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
newline
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous mode select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock selection" "MCK,MCK/8,PCK,SCK"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,LON,LIN master,LIN slave,,,SPI master,SPI slave"
|
|
newline
|
|
endif
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40028000+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " NSSE ,NSS line rising or falling edge event interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNRE ,SPI underrun error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,TXEMPTY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE ,Overrun error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY ,TXRDY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY ,RXRDY interrupt mask" "Masked,Not masked"
|
|
elif ((per.l(ad:0x40028000+0x04)&0x0F)==(0x0A||0x0B))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " LINHTE ,LIN header timeout error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " LINSTE ,LIN synch tolerance error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " LINSNRE ,LIN slave not responding error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " LINCE ,LIN checksum error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " LINIPE ,LIN identifier parity interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " LINISFE ,LIN inconsistent synch field error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " LINBE ,LIN bus error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " LINTC ,LIN transfer completed interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " LINID ,LIN identifier sent or LIN identifier received interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " LINBK ,LIN break sent or LIN break received interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,TXEMPTY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT ,Time-out interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE ,Parity error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME ,Framing error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE ,Overrun error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY ,TXRDY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY ,RXRDY interrupt mask" "Masked,Not masked"
|
|
elif ((per.l(ad:0x40028000+0x04)&0x0F)==0x09)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " LBLOVFE ,LON backlog overflow error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " LRXD ,LON reception done interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " LFET ,LON frame early termination interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " LCOL ,LON collision interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " LTXD ,LON transmission done interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNRE ,Underrun error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,TXEMPTY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " LCRCE ,LON CRC error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LSFE ,LON short frame error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE ,Overrun error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY ,TXRDY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY ,RXRDY interrupt mask" "Masked,Not masked"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " MANE ,Manchester error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC ,Clear to send input change interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " DCDIC ,Data carrier detect input change interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " DSRIC ,Data set ready input change mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " RIIC ,Ring indicator input change mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " NACK ,Non acknowledge interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " ITER ,Max number of repetitions reached interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,TXEMPTY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT ,Time-out interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE ,Parity error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME ,Framing error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE ,Overrun error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXBRK ,Receiver break interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY ,TXRDY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY ,RXRDY interrupt mask" "Masked,Not masked"
|
|
endif
|
|
newline
|
|
if ((per.l(ad:0x40028000+0x04)&0x0F)==(0x0E||0x0F))
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CSR,Channel Status Register"
|
|
in
|
|
elif ((per.l(ad:0x40028000+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((per.l(ad:0x40028000+0x04)&0x0F)==0x0A)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN header timeout error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN synch tolerance error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN slave not responding error" "No error,Error"
|
|
bitfld.long 0x00 28. " LINCE ,LIN checksum error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " LINIPE ,LIN identifier parity error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN inconsistent synch field error" "No error,Error"
|
|
bitfld.long 0x00 25. " LINBE ,LIN bit error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN bus line status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " LINTC ,LIN transfer completed" "Idle,Completed"
|
|
bitfld.long 0x00 14. " LINID ,LIN identifier sent" "Not sent,Sent"
|
|
bitfld.long 0x00 13. " LINBK ,LIN break sent" "Not sent,Sent"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver time-out" "No time-out,Time-out"
|
|
bitfld.long 0x00 7. " PARE ,Parity error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver ready" "Not ready,Ready"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN header timeout error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN synch tolerance error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN slave not responding error" "No error,Error"
|
|
bitfld.long 0x00 28. " LINCE ,LIN checksum error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " LINIPE ,LIN identifier parity error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN inconsistent synch field error" "No error,Error"
|
|
bitfld.long 0x00 25. " LINBE ,LIN bit error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN bus line status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " LINTC ,LIN transfer completed" "Idle,Completed"
|
|
bitfld.long 0x00 14. " LINID ,LIN identifier received" "Not received,Received"
|
|
bitfld.long 0x00 13. " LINBK ,LIN break received" "Not received,Received"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver time-out" "No time-out,Time-out"
|
|
bitfld.long 0x00 7. " PARE ,Parity error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver ready" "Not ready,Ready"
|
|
endif
|
|
elif ((per.l(ad:0x40028000+0x04)&0x0F)==0x09)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CSR,Channel Status Register"
|
|
bitfld.long 0x00 28. " LBLOVFE ,LON backlog overflow error" "No error,Error"
|
|
bitfld.long 0x00 27. " LRXD ,LON reception end flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 26. " LFET ,LON frame early termination" "No terminated,Terminated"
|
|
bitfld.long 0x00 25. " LCOL ,LON collision detected flag" "No occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 24. " LTXD ,LON transmission end flag" "No occurred,Performed"
|
|
bitfld.long 0x00 10. " UNRE ,Underrun error" "No error,Error"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter empty" "Not empty,Empty"
|
|
bitfld.long 0x00 7. " LCRCE ,LON CRC error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 6. " LSFE ,LON short frame error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver ready" "Not ready,Ready"
|
|
else
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CSR,Channel Status Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be transmitted"
|
|
if ((per.l(ad:0x40028000+0xE4)&0x01)==0x00)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out value"
|
|
if ((per.l(ad:0x40028000+0x04)&0x0F)==0x09)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PCYCLE ,LON PCYCLE length"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FIDI,FI DI Ratio Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BETA2 ,LON BETA2 length"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FIDI,FI DI Ratio Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI over DI ratio value"
|
|
endif
|
|
else
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out value"
|
|
if ((per.l(ad:0x40028000+0x04)&0x0F)==0x09)
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PCYCLE ,LON PCYCLE length"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "FIDI,FI DI Ratio Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BETA2 ,LON BETA2 length"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard value"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "FIDI,FI DI Ratio Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI over DI ratio value"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40028000+0x04)&0x0F)==0x04)||((per.l(ad:0x40028000+0x04)&0x0F)==0x06))
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "NER,Number Of Errors Register"
|
|
in
|
|
endif
|
|
if ((per.l(ad:0x40028000+0x04)&0x0F)==0x08)
|
|
if ((per.l(ad:0x40028000+0xE4)&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "IF,IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA filter"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "IF,IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA filter"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40028000+0xE4)&0x01)==0x00)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver idle value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver manchester polarity" "0-to-1,1-to-0"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver preamble pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver preamble length" "Disabled,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter manchester polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter preamble pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter preamble length" "Disabled,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver idle value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver manchester polarity" "0-to-1,1-to-0"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver preamble pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver preamble length" "Disabled,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter manchester polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter preamble pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter preamble length" "Disabled,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits"
|
|
endif
|
|
if ((per.l(ad:0x40028000+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((per.l(ad:0x40028000+0xE4)&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data length control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup signal type" "LIN 2.0,LIN 1.3"
|
|
newline
|
|
bitfld.long 0x00 6. " FSDIS ,Frame slot mode disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data length mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PARDIS ,Parity disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN mode action" "Publish,Subscribe,Ignore,?..."
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data length control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup signal type" "LIN 2.0,LIN 1.3"
|
|
newline
|
|
bitfld.long 0x00 6. " FSDIS ,Frame slot mode disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data length mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PARDIS ,Parity disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN node action" "Publish,Subscribe,Ignore,?..."
|
|
endif
|
|
if ((per.l(ad:0x40028000+0x04)&0x0F)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,Fractional part after synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,Clock divider after synchronization"
|
|
endif
|
|
if ((per.l(ad:0x40028000+0x04)&0x0F)==0x09)
|
|
if ((per.l(ad:0x40028000+0xE4)&0x01)==0x00)
|
|
if (((per.l(ad:0x40028000+0x60))&0x01)==0x00)
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "LONMR,USART LON Mode Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " EOFS ,End of frame condition size"
|
|
bitfld.long 0x00 5. " LCDS ,LON collision detection source" "External,Internal"
|
|
bitfld.long 0x00 4. " DMAM ,LON DMA mode" "Not written,Written"
|
|
bitfld.long 0x00 3. " CDTAIL ,LON collision detection on frame tail" "Detected,Ignored"
|
|
newline
|
|
bitfld.long 0x00 2. " TCOL ,Terminate frame upon collision notification" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COLDET ,LON collision detection feature" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " COMMT ,LON comm_type parameter value" "1,2"
|
|
line.long 0x04 "LONPR,USART LON Preamble Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " LONPL ,LON preamble length"
|
|
else
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "LONMR,USART LON Mode Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " EOFS ,End of frame condition size"
|
|
bitfld.long 0x00 5. " LCDS ,LON collision detection source" "External,Internal"
|
|
bitfld.long 0x00 4. " DMAM ,LON DMA mode" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x00 1. " COLDET ,LON collision detection feature" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " COMMT ,LON comm_type parameter value" "1,2"
|
|
line.long 0x04 "LONPR,USART LON Preamble Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " LONPL ,LON preamble length"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40028000+0x60))&0x01)==0x00)
|
|
rgroup.long 0x60++0x07
|
|
line.long 0x00 "LONMR,USART LON Mode Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " EOFS ,End of frame condition size"
|
|
bitfld.long 0x00 5. " LCDS ,LON collision detection source" "External,Internal"
|
|
bitfld.long 0x00 4. " DMAM ,LON DMA mode" "Not written,Written"
|
|
bitfld.long 0x00 3. " CDTAIL ,LON collision detection on frame tail" "Detected,Ignored"
|
|
newline
|
|
bitfld.long 0x00 2. " TCOL ,Terminate frame upon collision notification" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COLDET ,LON collision detection feature" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " COMMT ,LON comm_type parameter value" "1,2"
|
|
line.long 0x04 "LONPR,USART LON Preamble Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " LONPL ,LON preamble length"
|
|
else
|
|
rgroup.long 0x60++0x07
|
|
line.long 0x00 "LONMR,USART LON Mode Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " EOFS ,End of frame condition size"
|
|
bitfld.long 0x00 5. " LCDS ,LON collision detection source" "External,Internal"
|
|
bitfld.long 0x00 4. " DMAM ,LON DMA mode" "Not written,Written"
|
|
newline
|
|
bitfld.long 0x00 1. " COLDET ,LON collision detection feature" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " COMMT ,LON comm_type parameter value" "1,2"
|
|
line.long 0x04 "LONPR,USART LON Preamble Register"
|
|
hexmask.long.word 0x04 0.--13. 1. " LONPL ,LON preamble length"
|
|
endif
|
|
endif
|
|
group.long 0x68++0x07
|
|
line.long 0x00 "LONDL,USART LON Data Length Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LONDL ,LON data length"
|
|
line.long 0x04 "LONL2HDR,USART LON L2HDR Register"
|
|
bitfld.long 0x04 7. " PB ,LON priority bit" "Reset,Set"
|
|
bitfld.long 0x04 6. " ALTP ,LON alternate path bit" "Reset,Set"
|
|
bitfld.long 0x04 0.--5. " BLI ,LON backlog increment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "LONBL,USART LON Backlog Register"
|
|
bitfld.long 0x00 0.--5. " LONBL ,LON node backlog value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
if ((per.l(ad:0x40028000+0xE4)&0x01)==0x00)
|
|
group.long 0x74++0x0B
|
|
line.long 0x00 "LONB1TX,USART LON Beta1 Tx Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BETA1TX ,LON beta1 length after transmission"
|
|
line.long 0x04 "LONB1RX,USART LON Beta1 Rx Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " BETA1RX ,LON beta1 length after reception"
|
|
line.long 0x08 "LONPRIO,USART LON Priority Register"
|
|
hexmask.long.byte 0x08 8.--14. 1. " NPS ,LON node priority slot"
|
|
hexmask.long.byte 0x08 0.--6. 1. " PSNB ,LON priority slot number"
|
|
if (((per.l(ad:0x40028000+0x60))&0x01)==0x00)
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "IDTTX,USART LON Priority Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IDTTX ,LON indeterminate time after transmission"
|
|
line.long 0x04 "IDTRX,USART LON IDT Rx Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " IDTRX ,LON indeterminate time after reception"
|
|
else
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "IDTTX,USART LON Priority Register"
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "IDTRX,USART LON IDT Rx Register"
|
|
endif
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "ICDIFF,USART IC DIFF Register"
|
|
bitfld.long 0x00 0.--3. " ICDIFF ,IC differentiator number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x74++0x0B
|
|
line.long 0x00 "LONB1TX,USART LON Beta1 Tx Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BETA1TX ,LON beta1 length after transmission"
|
|
line.long 0x04 "LONB1RX,USART LON Beta1 Rx Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " BETA1RX ,LON beta1 length after reception"
|
|
line.long 0x08 "LONPRIO,USART LON Priority Register"
|
|
hexmask.long.byte 0x08 8.--14. 1. " NPS ,LON node priority slot"
|
|
hexmask.long.byte 0x08 0.--6. 1. " PSNB ,LON priority slot number"
|
|
if (((per.l(ad:0x40028000+0x60))&0x01)==0x00)
|
|
rgroup.long 0x80++0x07
|
|
line.long 0x00 "IDTTX,USART LON Priority Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " IDTTX ,LON indeterminate time after transmission"
|
|
line.long 0x04 "IDTRX,USART LON IDT Rx Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " IDTRX ,LON indeterminate time after reception"
|
|
else
|
|
hgroup.long 0x80++0x03
|
|
hide.long 0x00 "IDTTX,USART LON Priority Register"
|
|
hgroup.long 0x84++0x03
|
|
hide.long 0x00 "IDTRX,USART LON IDT Rx Register"
|
|
endif
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "ICDIFF,USART IC DIFF Register"
|
|
bitfld.long 0x00 0.--3. " ICDIFF ,IC differentiator number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,USART Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART 2"
|
|
base ad:0x4002C000
|
|
width 13.
|
|
if ((per.l(ad:0x4002C000+0x04)&0x0F)==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN wakeup signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to send pin control" "No effect,Drive RTS to 1"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to send pin control" "No effect,Drive RTS to 0"
|
|
newline
|
|
bitfld.long 0x00 17. " DTRDIS ,Data terminal ready disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " DTREN ,Data terminal ready enable" "No effect,Enable"
|
|
bitfld.long 0x00 15. " RETTO ,Start time-out immediately" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset non acknowledge" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 12. " SENDA ,Send address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT flag and start time-out after next character received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop break" "No effect,Stop"
|
|
bitfld.long 0x00 9. " STTBRK ,Start break" "No effect,Start"
|
|
newline
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
elif ((per.l(ad:0x4002C000+0x04)&0x0F)==0x02)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN wakeup signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN transmission" "No effect,Abort transmission"
|
|
bitfld.long 0x00 19. " RTSDIS ,Request to send pin control" "No effect,Drive RTS to 0"
|
|
bitfld.long 0x00 18. " RTSEN ,Request to send pin control" "No effect,Drive RTS to 1"
|
|
newline
|
|
bitfld.long 0x00 17. " DTRDIS ,Data terminal ready disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " DTREN ,Data terminal ready enable" "No effect,Enable"
|
|
bitfld.long 0x00 15. " RETTO ,Start time-out immediately" "No effect,Restart"
|
|
bitfld.long 0x00 12. " SENDA ,Send address" "No effect,Send"
|
|
newline
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT flag and start time-out after next character received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop break" "No effect,Stop"
|
|
bitfld.long 0x00 9. " STTBRK ,Start break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
elif (((per.l(ad:0x4002C000+0x04)&0x0F)==0x04)||((per.l(ad:0x4002C000+0x04)&0x0F)==0x06))
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN wakeup signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN transmission" "No effect,Abort transmission"
|
|
newline
|
|
bitfld.long 0x00 17. " DTRDIS ,Data terminal ready disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " DTREN ,Data terminal ready enable" "No effect,Enable"
|
|
bitfld.long 0x00 15. " RETTO ,Start time-out immediately" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset non acknowledge" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 13. " RSTIT ,Reset iterations" "No effect,Reset"
|
|
bitfld.long 0x00 12. " SENDA ,Send address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT flag and start time-out after next character received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop break" "No effect,Stop"
|
|
newline
|
|
bitfld.long 0x00 9. " STTBRK ,Start break" "No effect,Start"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
elif ((per.l((ad:0x4002C000)+0x04)&0x0F)==0x0E)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 19. " RCS ,Release SPI chip select (release slave select line NSS)" "No effect,Release"
|
|
bitfld.long 0x00 18. " FCS ,Force SPI chip select (force slave select line NSS to 0)" "No effect,Force"
|
|
newline
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
elif ((per.l((ad:0x4002C000)+0x04)&0x0F)==0x0F)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 21. " LINWKUP ,Send LIN wakeup signal" "No effect,Send"
|
|
bitfld.long 0x00 20. " LINABT ,Abort LIN transmission" "No effect,Abort transmission"
|
|
newline
|
|
bitfld.long 0x00 17. " DTRDIS ,Data terminal ready disable" "No effect,Disable"
|
|
bitfld.long 0x00 16. " DTREN ,Data terminal ready enable" "No effect,Enable"
|
|
bitfld.long 0x00 15. " RETTO ,Start time-out immediately" "No effect,Restart"
|
|
bitfld.long 0x00 14. " RSTNACK ,Reset non acknowledge" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x00 12. " SENDA ,Send address" "No effect,Send"
|
|
bitfld.long 0x00 11. " STTTO ,Clear TIMEOUT flag and start time-out after next character received" "No effect,Start"
|
|
bitfld.long 0x00 10. " STPBRK ,Stop break" "No effect,Stop"
|
|
bitfld.long 0x00 9. " STTBRK ,Start break" "No effect,Start"
|
|
newline
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
endif
|
|
if ((per.l(ad:0x4002C000+0xE4)&0x01)==0x00)
|
|
if ((per.l(ad:0x4002C000+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 20. " WRDBT ,Wait read data before transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock output select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI clock polarity" "Inactive-low,Inactive-high"
|
|
newline
|
|
bitfld.long 0x00 8. " CPHA ,SPI clock phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/captured,Captured/changed"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock selection" "MCK,MCK/8,,SCK"
|
|
newline
|
|
newline
|
|
newline
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN master,LIN slave,,,SPI master,SPI slave"
|
|
newline
|
|
else
|
|
if (((per.l(ad:0x4002C000+0x04))&0x100)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start frame delimiter selector" "DATA SYNC,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester synchronization mode" "0 to 1,1 to 0"
|
|
bitfld.long 0x00 29. " MAN ,Manchester encoder/decoder enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Receive line filter" "Not filtered,Filtered"
|
|
newline
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum number of automatic iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted data" "Not inverted,Inverted"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable synchronization of command/data sync" "User defined,THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable successive NACK" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 20. " INACK ,Inhibit non acknowledge" "Generated,Not generated"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock output select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit character length" "Def by CHRL,9-bit"
|
|
newline
|
|
bitfld.long 0x00 16. " MSBF ,Bit order" "LSB,MSB"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of stop bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
newline
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous mode select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock selection" "MCK,MCK/8,PCK,SCK"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN master,LIN slave,,,SPI master,SPI slave"
|
|
newline
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start frame delimiter selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester synchronization mode" "0 to 1,1 to 0"
|
|
bitfld.long 0x00 29. " MAN ,Manchester encoder/decoder enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Receive line filter" "Not filtered,Filtered"
|
|
newline
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum number of automatic iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted data" "Not inverted,Inverted"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable synchronization of command/data sync" "User defined,THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable successive NACK" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 20. " INACK ,Inhibit non acknowledge" "Generated,Not generated"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock output select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit character length" "Def by CHRL,9-bit"
|
|
newline
|
|
bitfld.long 0x00 16. " MSBF ,Bit order" "LSB,MSB"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of stop bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
newline
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous mode select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock selection" "MCK,MCK/8,PCK,SCK"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN master,LIN slave,,,SPI master,SPI slave"
|
|
newline
|
|
endif
|
|
endif
|
|
else
|
|
if ((per.l(ad:0x4002C000+0x04)&0x0F)==(0x0E||0x0F))
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 20. " WRDBT ,Wait read data before transfer" "No,Yes"
|
|
bitfld.long 0x00 18. " CKLO ,Clock output select" "No SCK,SCK"
|
|
bitfld.long 0x00 16. " CPOL ,SPI clock polarity" "Inactive-low,Inactive-high"
|
|
newline
|
|
bitfld.long 0x00 8. " CPHA ,SPI clock phase (on the leading edge of SPCK/on the following edge of SPCK)" "Changed/captured,Captured/changed"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character length" ",,,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock selection" "MCK,MCK/8,,SCK"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN master,LIN slave,,,SPI master,SPI slave"
|
|
newline
|
|
else
|
|
if (((per.l(ad:0x4002C000+0x04))&0x100)==0x00)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start frame delimiter selector" "DATA SYNC,One Bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester synchronization mode" "0 to 1,1 to 0"
|
|
bitfld.long 0x00 29. " MAN ,Manchester encoder/decoder enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Receive line filter" "Not filtered,Filtered"
|
|
newline
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum number of automatic iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted data" "Not inverted,Inverted"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable synchronization of command/data sync" "User defined,THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable successive NACK" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 20. " INACK ,Inhibit non acknowledge" "Generated,Not generated"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock output select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit character length" "Def by CHRL,9-bit"
|
|
newline
|
|
bitfld.long 0x00 16. " MSBF ,Bit order" "LSB,MSB"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of stop bits" "1,1.5,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
newline
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous mode select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock selection" "MCK,MCK/8,PCK,SCK"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN master,LIN slave,,,SPI master,SPI slave"
|
|
newline
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
bitfld.long 0x00 31. " ONEBIT ,Start frame delimiter selector" "DATA SYNC,One bit"
|
|
bitfld.long 0x00 30. " MODSYNC ,Manchester synchronization mode" "0 to 1,1 to 0"
|
|
bitfld.long 0x00 29. " MAN ,Manchester encoder/decoder enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " FILTER ,Receive line filter" "Not filtered,Filtered"
|
|
newline
|
|
bitfld.long 0x00 24.--26. " MAX_ITERATION ,Maximum number of automatic iteration" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 23. " INVDATA ,Inverted data" "Not inverted,Inverted"
|
|
bitfld.long 0x00 22. " VAR_SYNC ,Variable synchronization of command/data sync" "User defined,THR register"
|
|
bitfld.long 0x00 21. " DSNACK ,Disable successive NACK" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 20. " INACK ,Inhibit non acknowledge" "Generated,Not generated"
|
|
bitfld.long 0x00 19. " OVER ,Oversampling mode" "16x,8x"
|
|
bitfld.long 0x00 18. " CKLO ,Clock output select" "No SCK,SCK"
|
|
bitfld.long 0x00 17. " MODE9 ,9-bit character length" "Def by CHRL,9-bit"
|
|
newline
|
|
bitfld.long 0x00 16. " MSBF ,Bit order" "LSB,MSB"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12.--13. " NBSTOP ,Number of stop bits" "1,,2,?..."
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,,Multidrop,?..."
|
|
newline
|
|
bitfld.long 0x00 8. " SYNC ,Synchronous mode select" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 6.--7. " CHRL ,Character length" "5 bits,6 bits,7 bits,8 bits"
|
|
bitfld.long 0x00 4.--5. " USCLKS ,Clock selection" "MCK,MCK/8,PCK,SCK"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " USART_MODE ,Mode of the USART" "Normal,RS485,Hardware handshaking,Modem,IS07816 T = 0,,IS07816 T = 1,,IrDA,,LIN master,LIN slave,,,SPI master,SPI slave"
|
|
newline
|
|
endif
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x4002C000+0x04)&0x0F)==(0x0E||0x0F))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " NSSE ,NSS line rising or falling edge event interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNRE ,SPI underrun error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,TXEMPTY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE ,Overrun error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY ,TXRDY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY ,RXRDY interrupt mask" "Masked,Not masked"
|
|
elif ((per.l(ad:0x4002C000+0x04)&0x0F)==(0x0A||0x0B))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 31. -0x08 31. -0x04 31. " LINHTE ,LIN header timeout error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " LINSTE ,LIN synch tolerance error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 29. -0x08 29. -0x04 29. " LINSNRE ,LIN slave not responding error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " LINCE ,LIN checksum error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " LINIPE ,LIN identifier parity interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " LINISFE ,LIN inconsistent synch field error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " LINBE ,LIN bus error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " LINTC ,LIN transfer completed interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " LINID ,LIN identifier sent or LIN identifier received interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " LINBK ,LIN break sent or LIN break received interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,TXEMPTY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT ,Time-out interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE ,Parity error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME ,Framing error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE ,Overrun error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY ,TXRDY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY ,RXRDY interrupt mask" "Masked,Not masked"
|
|
elif ((per.l(ad:0x4002C000+0x04)&0x0F)==0x09)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 28. -0x08 28. -0x04 28. " LBLOVFE ,LON backlog overflow error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 27. -0x08 27. -0x04 27. " LRXD ,LON reception done interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " LFET ,LON frame early termination interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " LCOL ,LON collision interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " LTXD ,LON transmission done interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " UNRE ,Underrun error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,TXEMPTY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " LCRCE ,LON CRC error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LSFE ,LON short frame error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE ,Overrun error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY ,TXRDY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY ,RXRDY interrupt mask" "Masked,Not masked"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " MANE ,Manchester error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " CTSIC ,Clear to send input change interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " DCDIC ,Data carrier detect input change interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " DSRIC ,Data set ready input change mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " RIIC ,Ring indicator input change mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " NACK ,Non acknowledge interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " ITER ,Max number of repetitions reached interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,TXEMPTY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " TIMEOUT ,Time-out interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE ,Parity error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME ,Framing error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE ,Overrun error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " RXBRK ,Receiver break interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY ,TXRDY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY ,RXRDY interrupt mask" "Masked,Not masked"
|
|
endif
|
|
newline
|
|
if ((per.l(ad:0x4002C000+0x04)&0x0F)==(0x0E||0x0F))
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CSR,Channel Status Register"
|
|
in
|
|
elif ((per.l(ad:0x4002C000+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((per.l(ad:0x4002C000+0x04)&0x0F)==0x0A)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN header timeout error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN synch tolerance error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN slave not responding error" "No error,Error"
|
|
bitfld.long 0x00 28. " LINCE ,LIN checksum error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " LINIPE ,LIN identifier parity error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN inconsistent synch field error" "No error,Error"
|
|
bitfld.long 0x00 25. " LINBE ,LIN bit error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN bus line status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " LINTC ,LIN transfer completed" "Idle,Completed"
|
|
bitfld.long 0x00 14. " LINID ,LIN identifier sent" "Not sent,Sent"
|
|
bitfld.long 0x00 13. " LINBK ,LIN break sent" "Not sent,Sent"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver time-out" "No time-out,Time-out"
|
|
bitfld.long 0x00 7. " PARE ,Parity error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver ready" "Not ready,Ready"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CSR,Channel Status Register"
|
|
bitfld.long 0x00 31. " LINHTE ,LIN header timeout error" "No error,Error"
|
|
bitfld.long 0x00 30. " LINSTE ,LIN synch tolerance error" "No error,Error"
|
|
bitfld.long 0x00 29. " LINSNRE ,LIN slave not responding error" "No error,Error"
|
|
bitfld.long 0x00 28. " LINCE ,LIN checksum error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 27. " LINIPE ,LIN identifier parity error" "No error,Error"
|
|
bitfld.long 0x00 26. " LINISFE ,LIN inconsistent synch field error" "No error,Error"
|
|
bitfld.long 0x00 25. " LINBE ,LIN bit error" "No error,Error"
|
|
bitfld.long 0x00 23. " LINBLS ,LIN bus line status" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " LINTC ,LIN transfer completed" "Idle,Completed"
|
|
bitfld.long 0x00 14. " LINID ,LIN identifier received" "Not received,Received"
|
|
bitfld.long 0x00 13. " LINBK ,LIN break received" "Not received,Received"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter empty" "Not empty,Empty"
|
|
newline
|
|
bitfld.long 0x00 8. " TIMEOUT ,Receiver time-out" "No time-out,Time-out"
|
|
bitfld.long 0x00 7. " PARE ,Parity error" "No error,Error"
|
|
bitfld.long 0x00 6. " FRAME ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver ready" "Not ready,Ready"
|
|
endif
|
|
elif ((per.l(ad:0x4002C000+0x04)&0x0F)==0x09)
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CSR,Channel Status Register"
|
|
bitfld.long 0x00 28. " LBLOVFE ,LON backlog overflow error" "No error,Error"
|
|
bitfld.long 0x00 27. " LRXD ,LON reception end flag" "No occurred,Occurred"
|
|
bitfld.long 0x00 26. " LFET ,LON frame early termination" "No terminated,Terminated"
|
|
bitfld.long 0x00 25. " LCOL ,LON collision detected flag" "No occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 24. " LTXD ,LON transmission end flag" "No occurred,Performed"
|
|
bitfld.long 0x00 10. " UNRE ,Underrun error" "No error,Error"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter empty" "Not empty,Empty"
|
|
bitfld.long 0x00 7. " LCRCE ,LON CRC error" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 6. " LSFE ,LON short frame error" "No error,Error"
|
|
bitfld.long 0x00 5. " OVRE ,Overrun error" "No error,Error"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver ready" "Not ready,Ready"
|
|
else
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "CSR,Channel Status Register"
|
|
in
|
|
endif
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,Receiver Holding Register"
|
|
in
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "THR,Transmitter Holding Register"
|
|
bitfld.long 0x00 15. " TXSYNH ,Sync field to be transmitted" "Data,Command"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXCHR ,Character to be transmitted"
|
|
if ((per.l(ad:0x4002C000+0xE4)&0x01)==0x00)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out value"
|
|
if ((per.l(ad:0x4002C000+0x04)&0x0F)==0x09)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PCYCLE ,LON PCYCLE length"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FIDI,FI DI Ratio Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BETA2 ,LON BETA2 length"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FIDI,FI DI Ratio Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI over DI ratio value"
|
|
endif
|
|
else
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "BRGR,Baud Rate Generator Register"
|
|
bitfld.long 0x00 16.--18. " FP ,Fractional part" "Disabled,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock divider"
|
|
line.long 0x04 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TO ,Time-out value"
|
|
if ((per.l(ad:0x4002C000+0x04)&0x0F)==0x09)
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PCYCLE ,LON PCYCLE length"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "FIDI,FI DI Ratio Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " BETA2 ,LON BETA2 length"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TTGR,Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TG ,Timeguard value"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "FIDI,FI DI Ratio Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " FI_DI_RATIO ,FI over DI ratio value"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x4002C000+0x04)&0x0F)==0x04)||((per.l(ad:0x4002C000+0x04)&0x0F)==0x06))
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "NER,Number Of Errors Register"
|
|
in
|
|
endif
|
|
if ((per.l(ad:0x4002C000+0x04)&0x0F)==0x08)
|
|
if ((per.l(ad:0x4002C000+0xE4)&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "IF,IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA filter"
|
|
else
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "IF,IrDA Filter Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IRDA_FILTER ,IrDA filter"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x4002C000+0xE4)&0x01)==0x00)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver idle value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver manchester polarity" "0-to-1,1-to-0"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver preamble pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver preamble length" "Disabled,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter manchester polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter preamble pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter preamble length" "Disabled,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x00 31. " RXIDLEV ,Receiver idle value" "0,1"
|
|
bitfld.long 0x00 30. " DRIFT ,Drift compensation" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ONE ,Must be set to 1" ",1"
|
|
bitfld.long 0x00 28. " RX_MPOL ,Receiver manchester polarity" "0-to-1,1-to-0"
|
|
newline
|
|
bitfld.long 0x00 24.--25. " RX_PP ,Receiver preamble pattern detected" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
bitfld.long 0x00 16.--19. " RX_PL ,Receiver preamble length" "Disabled,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits"
|
|
bitfld.long 0x00 12. " TX_MPOL ,Transmitter manchester polarity" "0-to-1,1-to-0"
|
|
bitfld.long 0x00 8.--9. " TX_PP ,Transmitter preamble pattern" "ALL_ONE,ALL_ZERO,ZERO_ONE,ONE_ZERO"
|
|
newline
|
|
bitfld.long 0x00 0.--3. " TX_PL ,Transmitter preamble length" "Disabled,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits"
|
|
endif
|
|
if ((per.l(ad:0x4002C000+0x04)&0x0F)==(0x0A||0x0B))
|
|
if ((per.l(ad:0x4002C000+0xE4)&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data length control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup signal type" "LIN 2.0,LIN 1.3"
|
|
newline
|
|
bitfld.long 0x00 6. " FSDIS ,Frame slot mode disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data length mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PARDIS ,Parity disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN mode action" "Publish,Subscribe,Ignore,?..."
|
|
else
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x00 17. " SYNCDIS ,Synchronization disable" "No,Yes"
|
|
bitfld.long 0x00 16. " PDCM ,DMAC mode" "Not written,Written"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLC ,Data length control"
|
|
bitfld.long 0x00 7. " WKUPTYP ,Wakeup signal type" "LIN 2.0,LIN 1.3"
|
|
newline
|
|
bitfld.long 0x00 6. " FSDIS ,Frame slot mode disable" "No,Yes"
|
|
bitfld.long 0x00 5. " DLM ,Data length mode" "DLC,Bits 5 and 6 of LINIR"
|
|
bitfld.long 0x00 4. " CHKTYP ,Checksum type" "Enhanced,Classic"
|
|
bitfld.long 0x00 3. " CHKDIS ,Checksum disable" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 2. " PARDIS ,Parity disable" "No,Yes"
|
|
bitfld.long 0x00 0.--1. " NACT ,LIN node action" "Publish,Subscribe,Ignore,?..."
|
|
endif
|
|
if ((per.l(ad:0x4002C000+0x04)&0x0F)==0x0A)
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier character"
|
|
else
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IDCHR ,Identifier character"
|
|
endif
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x00 16.--18. " LINFP ,Fractional part after synchronization" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x00 0.--15. 1. " LINCD ,Clock divider after synchronization"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,USART Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,USART Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree.open "UART (Universal Asynchronous Receiver Transmitter)"
|
|
tree "UART 0"
|
|
base ad:0x400E0800
|
|
width 13.
|
|
if (((per.l(ad:0x400E071C))&(0x80))==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,UART Control Register"
|
|
bitfld.long 0x00 12. " REQCLR ,Request clear" "No effect,Restart"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,UART Control Register"
|
|
bitfld.long 0x00 12. " REQCLR ,Request clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
endif
|
|
if ((per.l(ad:0x400E0800+0xE4)&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12. " BRSRCCK ,Baud rate source clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,?..."
|
|
bitfld.long 0x00 4. " FILTER ,Receiver digital filter" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12. " BRSRCCK ,Baud rate source clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,?..."
|
|
bitfld.long 0x00 4. " FILTER ,Receiver digital filter" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR_SET/CLR,UART Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " CMP ,Comparison interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,TXEMPTY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE ,Parity error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME ,Framing error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE ,Overrun error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY ,TXRDY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY ,RXRDY interrupt mask" "Masked,Not masked"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "SR,UART Status Register"
|
|
in
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SR,UART Status Register"
|
|
bitfld.long 0x00 15. " CMP ,Comparison match" "Not matched,Matched"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter empty" "Not empty,Empty"
|
|
bitfld.long 0x00 7. " PARE ,Parity error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " FRAME ,Framing error" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 5. " OVRE ,Overrun error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver ready" "Not ready,Ready"
|
|
newline
|
|
endif
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,UART Receiver Holding Register"
|
|
in
|
|
newline
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "THR,Transmitter Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCHR ,Character to be transmitted"
|
|
if ((per.l(ad:0x400E0800+0xE4)&0x01)==0x00)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock divider"
|
|
line.long 0x04 "CMPR,UART Comparison Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " VAL2 ,Second comparison value for received character"
|
|
bitfld.long 0x04 14. " CMPPAR ,Compare parity" "Not checked,Checked"
|
|
bitfld.long 0x04 12. " CMPMODE ,Comparison mode" "Flag only,Start condition"
|
|
hexmask.long.byte 0x04 0.--7. 1. " VAL1 ,First comparison value for received character"
|
|
else
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock divider"
|
|
line.long 0x04 "CMPR,UART Comparison Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " VAL2 ,Second comparison value for received character"
|
|
bitfld.long 0x04 14. " CMPPAR ,Compare parity" "Not checked,Checked"
|
|
bitfld.long 0x04 12. " CMPMODE ,Comparison mode" "Flag only,Start condition"
|
|
hexmask.long.byte 0x04 0.--7. 1. " VAL1 ,First comparison value for received character"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect mode register"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 1"
|
|
base ad:0x400E0A00
|
|
width 13.
|
|
if (((per.l(ad:0x400E071C))&(0x100))==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,UART Control Register"
|
|
bitfld.long 0x00 12. " REQCLR ,Request clear" "No effect,Restart"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,UART Control Register"
|
|
bitfld.long 0x00 12. " REQCLR ,Request clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
endif
|
|
if ((per.l(ad:0x400E0A00+0xE4)&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12. " BRSRCCK ,Baud rate source clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,?..."
|
|
bitfld.long 0x00 4. " FILTER ,Receiver digital filter" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12. " BRSRCCK ,Baud rate source clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,?..."
|
|
bitfld.long 0x00 4. " FILTER ,Receiver digital filter" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR_SET/CLR,UART Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " CMP ,Comparison interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,TXEMPTY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE ,Parity error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME ,Framing error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE ,Overrun error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY ,TXRDY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY ,RXRDY interrupt mask" "Masked,Not masked"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "SR,UART Status Register"
|
|
in
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SR,UART Status Register"
|
|
bitfld.long 0x00 15. " CMP ,Comparison match" "Not matched,Matched"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter empty" "Not empty,Empty"
|
|
bitfld.long 0x00 7. " PARE ,Parity error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " FRAME ,Framing error" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 5. " OVRE ,Overrun error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver ready" "Not ready,Ready"
|
|
newline
|
|
endif
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,UART Receiver Holding Register"
|
|
in
|
|
newline
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "THR,Transmitter Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCHR ,Character to be transmitted"
|
|
if ((per.l(ad:0x400E0A00+0xE4)&0x01)==0x00)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock divider"
|
|
line.long 0x04 "CMPR,UART Comparison Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " VAL2 ,Second comparison value for received character"
|
|
bitfld.long 0x04 14. " CMPPAR ,Compare parity" "Not checked,Checked"
|
|
bitfld.long 0x04 12. " CMPMODE ,Comparison mode" "Flag only,Start condition"
|
|
hexmask.long.byte 0x04 0.--7. 1. " VAL1 ,First comparison value for received character"
|
|
else
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock divider"
|
|
line.long 0x04 "CMPR,UART Comparison Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " VAL2 ,Second comparison value for received character"
|
|
bitfld.long 0x04 14. " CMPPAR ,Compare parity" "Not checked,Checked"
|
|
bitfld.long 0x04 12. " CMPMODE ,Comparison mode" "Flag only,Start condition"
|
|
hexmask.long.byte 0x04 0.--7. 1. " VAL1 ,First comparison value for received character"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect mode register"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 2"
|
|
base ad:0x400E1A00
|
|
width 13.
|
|
if (((per.l(ad:0x400E073C))&(0x1000))==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,UART Control Register"
|
|
bitfld.long 0x00 12. " REQCLR ,Request clear" "No effect,Restart"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,UART Control Register"
|
|
bitfld.long 0x00 12. " REQCLR ,Request clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
endif
|
|
if ((per.l(ad:0x400E1A00+0xE4)&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12. " BRSRCCK ,Baud rate source clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,?..."
|
|
bitfld.long 0x00 4. " FILTER ,Receiver digital filter" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12. " BRSRCCK ,Baud rate source clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,?..."
|
|
bitfld.long 0x00 4. " FILTER ,Receiver digital filter" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR_SET/CLR,UART Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " CMP ,Comparison interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,TXEMPTY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE ,Parity error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME ,Framing error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE ,Overrun error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY ,TXRDY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY ,RXRDY interrupt mask" "Masked,Not masked"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "SR,UART Status Register"
|
|
in
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SR,UART Status Register"
|
|
bitfld.long 0x00 15. " CMP ,Comparison match" "Not matched,Matched"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter empty" "Not empty,Empty"
|
|
bitfld.long 0x00 7. " PARE ,Parity error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " FRAME ,Framing error" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 5. " OVRE ,Overrun error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver ready" "Not ready,Ready"
|
|
newline
|
|
endif
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,UART Receiver Holding Register"
|
|
in
|
|
newline
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "THR,Transmitter Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCHR ,Character to be transmitted"
|
|
if ((per.l(ad:0x400E1A00+0xE4)&0x01)==0x00)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock divider"
|
|
line.long 0x04 "CMPR,UART Comparison Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " VAL2 ,Second comparison value for received character"
|
|
bitfld.long 0x04 14. " CMPPAR ,Compare parity" "Not checked,Checked"
|
|
bitfld.long 0x04 12. " CMPMODE ,Comparison mode" "Flag only,Start condition"
|
|
hexmask.long.byte 0x04 0.--7. 1. " VAL1 ,First comparison value for received character"
|
|
else
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock divider"
|
|
line.long 0x04 "CMPR,UART Comparison Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " VAL2 ,Second comparison value for received character"
|
|
bitfld.long 0x04 14. " CMPPAR ,Compare parity" "Not checked,Checked"
|
|
bitfld.long 0x04 12. " CMPMODE ,Comparison mode" "Flag only,Start condition"
|
|
hexmask.long.byte 0x04 0.--7. 1. " VAL1 ,First comparison value for received character"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect mode register"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 3"
|
|
base ad:0x400E1C00
|
|
width 13.
|
|
if (((per.l(ad:0x400E073C))&(0x2000))==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,UART Control Register"
|
|
bitfld.long 0x00 12. " REQCLR ,Request clear" "No effect,Restart"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,UART Control Register"
|
|
bitfld.long 0x00 12. " REQCLR ,Request clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
endif
|
|
if ((per.l(ad:0x400E1C00+0xE4)&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12. " BRSRCCK ,Baud rate source clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,?..."
|
|
bitfld.long 0x00 4. " FILTER ,Receiver digital filter" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12. " BRSRCCK ,Baud rate source clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,?..."
|
|
bitfld.long 0x00 4. " FILTER ,Receiver digital filter" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR_SET/CLR,UART Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " CMP ,Comparison interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,TXEMPTY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE ,Parity error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME ,Framing error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE ,Overrun error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY ,TXRDY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY ,RXRDY interrupt mask" "Masked,Not masked"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "SR,UART Status Register"
|
|
in
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SR,UART Status Register"
|
|
bitfld.long 0x00 15. " CMP ,Comparison match" "Not matched,Matched"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter empty" "Not empty,Empty"
|
|
bitfld.long 0x00 7. " PARE ,Parity error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " FRAME ,Framing error" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 5. " OVRE ,Overrun error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver ready" "Not ready,Ready"
|
|
newline
|
|
endif
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,UART Receiver Holding Register"
|
|
in
|
|
newline
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "THR,Transmitter Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCHR ,Character to be transmitted"
|
|
if ((per.l(ad:0x400E1C00+0xE4)&0x01)==0x00)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock divider"
|
|
line.long 0x04 "CMPR,UART Comparison Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " VAL2 ,Second comparison value for received character"
|
|
bitfld.long 0x04 14. " CMPPAR ,Compare parity" "Not checked,Checked"
|
|
bitfld.long 0x04 12. " CMPMODE ,Comparison mode" "Flag only,Start condition"
|
|
hexmask.long.byte 0x04 0.--7. 1. " VAL1 ,First comparison value for received character"
|
|
else
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock divider"
|
|
line.long 0x04 "CMPR,UART Comparison Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " VAL2 ,Second comparison value for received character"
|
|
bitfld.long 0x04 14. " CMPPAR ,Compare parity" "Not checked,Checked"
|
|
bitfld.long 0x04 12. " CMPMODE ,Comparison mode" "Flag only,Start condition"
|
|
hexmask.long.byte 0x04 0.--7. 1. " VAL1 ,First comparison value for received character"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect mode register"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 4"
|
|
base ad:0x400E1E00
|
|
width 13.
|
|
if (((per.l(ad:0x400E073C))&(0x4000))==0x00)
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,UART Control Register"
|
|
bitfld.long 0x00 12. " REQCLR ,Request clear" "No effect,Restart"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
else
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,UART Control Register"
|
|
bitfld.long 0x00 12. " REQCLR ,Request clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " RSTSTA ,Reset status bits" "No effect,Reset"
|
|
bitfld.long 0x00 7. " TXDIS ,Transmitter disable" "No effect,Disable"
|
|
bitfld.long 0x00 6. " TXEN ,Transmitter enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 5. " RXDIS ,Receiver disable" "No effect,Disable"
|
|
bitfld.long 0x00 4. " RXEN ,Receiver enable" "No effect,Enable"
|
|
bitfld.long 0x00 3. " RSTTX ,Reset transmitter" "No effect,Reset"
|
|
bitfld.long 0x00 2. " RSTRX ,Reset receiver" "No effect,Reset"
|
|
endif
|
|
if ((per.l(ad:0x400E1E00+0xE4)&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12. " BRSRCCK ,Baud rate source clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,?..."
|
|
bitfld.long 0x00 4. " FILTER ,Receiver digital filter" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,UART Mode Register"
|
|
bitfld.long 0x00 14.--15. " CHMODE ,Channel mode" "Normal,Automatic echo,Local loopback,Remote loopback"
|
|
bitfld.long 0x00 12. " BRSRCCK ,Baud rate source clock" "PERIPH_CLK,PMC_PCK"
|
|
bitfld.long 0x00 9.--11. " PAR ,Parity type" "Even,Odd,Forced to 0,Forced to 1,No parity,?..."
|
|
bitfld.long 0x00 4. " FILTER ,Receiver digital filter" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IMR_SET/CLR,UART Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " CMP ,Comparison interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " TXEMPTY ,TXEMPTY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " PARE ,Parity error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " FRAME ,Framing error interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " OVRE ,Overrun error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY ,TXRDY interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " RXRDY ,RXRDY interrupt mask" "Masked,Not masked"
|
|
newline
|
|
sif !cpuis("ATSAMS7*")
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "SR,UART Status Register"
|
|
in
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "SR,UART Status Register"
|
|
bitfld.long 0x00 15. " CMP ,Comparison match" "Not matched,Matched"
|
|
bitfld.long 0x00 9. " TXEMPTY ,Transmitter empty" "Not empty,Empty"
|
|
bitfld.long 0x00 7. " PARE ,Parity error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " FRAME ,Framing error" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 5. " OVRE ,Overrun error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " TXRDY ,Transmitter ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " RXRDY ,Receiver ready" "Not ready,Ready"
|
|
newline
|
|
endif
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "RHR,UART Receiver Holding Register"
|
|
in
|
|
newline
|
|
wgroup.long 0x1c++0x03
|
|
line.long 0x00 "THR,Transmitter Holding Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXCHR ,Character to be transmitted"
|
|
if ((per.l(ad:0x400E1E00+0xE4)&0x01)==0x00)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock divider"
|
|
line.long 0x04 "CMPR,UART Comparison Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " VAL2 ,Second comparison value for received character"
|
|
bitfld.long 0x04 14. " CMPPAR ,Compare parity" "Not checked,Checked"
|
|
bitfld.long 0x04 12. " CMPMODE ,Comparison mode" "Flag only,Start condition"
|
|
hexmask.long.byte 0x04 0.--7. 1. " VAL1 ,First comparison value for received character"
|
|
else
|
|
rgroup.long 0x20++0x07
|
|
line.long 0x00 "BRGR,UART Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CD ,Clock divider"
|
|
line.long 0x04 "CMPR,UART Comparison Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " VAL2 ,Second comparison value for received character"
|
|
bitfld.long 0x04 14. " CMPPAR ,Compare parity" "Not checked,Checked"
|
|
bitfld.long 0x04 12. " CMPMODE ,Comparison mode" "Flag only,Start condition"
|
|
hexmask.long.byte 0x04 0.--7. 1. " VAL1 ,First comparison value for received character"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect mode register"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "TC (Timer Counter)"
|
|
tree "TC0"
|
|
base ad:0x4000C000
|
|
width 14.
|
|
tree "Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "CCR0,Channel 0 Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software trigger command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter clock disable command" "No effect,Disable"
|
|
bitfld.long 0x00 0. " CLKEN ,Counter clock enable command" "No effect,Enable"
|
|
if ((((per.l(ad:0x4000C000+0x0+0x04))&0x8000)==0x00)&&(((per.l(ad:0x4000C000+0xE4))&0x01)==0x00))
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x4000C000+0x0+0x04))&0x8000)==0x00)&&(((per.l(ad:0x4000C000+0xE4))&0x01)==0x01))
|
|
rgroup.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x4000C000+0x0+0x04))&0x8000)==0x8000)&&(((per.l(ad:0x4000C000+0xE4))&0x01)==0x00))
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
if (((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "SMMR0,Ch 0 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long (0x0+0x08)++0x03
|
|
line.long 0x00 "SMMR0,Ch 0 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("ATSAM4S*")&&!cpuis("ATSAMA5D3*")
|
|
rgroup.long (0x0+0x0C)++0x03
|
|
line.long 0x00 "RAB0,Channel 0 Register AB"
|
|
endif
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "CV0,Channel 0 Counter Value Register"
|
|
sif cpuis("ATSAM4S*")
|
|
if ((((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x4000C000+0x8000))&0x04)==0x8000))
|
|
group.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB0,Channel 0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB0,Channel 0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
endif
|
|
if (((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
else
|
|
rgroup.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
endif
|
|
else
|
|
if ((((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x4000C000+0x8000))&0x04)==0x8000))
|
|
group.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
line.long 0x04 "RB0,Channel 0 Register B"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
line.long 0x04 "RB0,Channel 0 Register B"
|
|
endif
|
|
if (((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
else
|
|
rgroup.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "SR0,Channel 0 Status Register"
|
|
in
|
|
newline
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "IMR0_SET/CLR,Channel 0 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS ,External trigger status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS ,RB loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS ,RA loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS ,RC compare status interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS ,RB compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS ,RA compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS ,Load overrun status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS ,Counter overflow status interrupt" "Masked,Not masked"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
if (((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)
|
|
group.long (0x0+0x30)++0x03
|
|
line.long 0x00 "EMR0,Channel 0 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB0,PWM0,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA0,PWM0,?..."
|
|
else
|
|
rgroup.long (0x0+0x30)++0x03
|
|
line.long 0x00 "EMR0,Channel 0 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB0,PWM0,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA0,PWM0,?..."
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "CCR1,Channel 1 Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software trigger command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter clock disable command" "No effect,Disable"
|
|
bitfld.long 0x00 0. " CLKEN ,Counter clock enable command" "No effect,Enable"
|
|
if ((((per.l(ad:0x4000C000+0x40+0x04))&0x8000)==0x00)&&(((per.l(ad:0x4000C000+0xE4))&0x01)==0x00))
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x4000C000+0x40+0x04))&0x8000)==0x00)&&(((per.l(ad:0x4000C000+0xE4))&0x01)==0x01))
|
|
rgroup.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x4000C000+0x40+0x04))&0x8000)==0x8000)&&(((per.l(ad:0x4000C000+0xE4))&0x01)==0x00))
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
if (((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "SMMR1,Ch 1 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long (0x40+0x08)++0x03
|
|
line.long 0x00 "SMMR1,Ch 1 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("ATSAM4S*")&&!cpuis("ATSAMA5D3*")
|
|
rgroup.long (0x40+0x0C)++0x03
|
|
line.long 0x00 "RAB1,Channel 1 Register AB"
|
|
endif
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "CV1,Channel 1 Counter Value Register"
|
|
sif cpuis("ATSAM4S*")
|
|
if ((((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x4000C000+0x8000))&0x04)==0x8000))
|
|
group.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB1,Channel 1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB1,Channel 1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
endif
|
|
if (((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
else
|
|
rgroup.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
endif
|
|
else
|
|
if ((((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x4000C000+0x8000))&0x04)==0x8000))
|
|
group.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
line.long 0x04 "RB1,Channel 1 Register B"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
line.long 0x04 "RB1,Channel 1 Register B"
|
|
endif
|
|
if (((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
else
|
|
rgroup.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "SR1,Channel 1 Status Register"
|
|
in
|
|
newline
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "IMR1_SET/CLR,Channel 1 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS ,External trigger status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS ,RB loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS ,RA loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS ,RC compare status interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS ,RB compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS ,RA compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS ,Load overrun status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS ,Counter overflow status interrupt" "Masked,Not masked"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
if (((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)
|
|
group.long (0x40+0x30)++0x03
|
|
line.long 0x00 "EMR1,Channel 1 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB1,PWM1,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA1,PWM1,?..."
|
|
else
|
|
rgroup.long (0x40+0x30)++0x03
|
|
line.long 0x00 "EMR1,Channel 1 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB1,PWM1,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA1,PWM1,?..."
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Channel 2"
|
|
wgroup.long (0x80+0x00)++0x03
|
|
line.long 0x00 "CCR2,Channel 2 Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software trigger command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter clock disable command" "No effect,Disable"
|
|
bitfld.long 0x00 0. " CLKEN ,Counter clock enable command" "No effect,Enable"
|
|
if ((((per.l(ad:0x4000C000+0x80+0x04))&0x8000)==0x00)&&(((per.l(ad:0x4000C000+0xE4))&0x01)==0x00))
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x4000C000+0x80+0x04))&0x8000)==0x00)&&(((per.l(ad:0x4000C000+0xE4))&0x01)==0x01))
|
|
rgroup.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x4000C000+0x80+0x04))&0x8000)==0x8000)&&(((per.l(ad:0x4000C000+0xE4))&0x01)==0x00))
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
if (((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "SMMR2,Ch 2 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long (0x80+0x08)++0x03
|
|
line.long 0x00 "SMMR2,Ch 2 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("ATSAM4S*")&&!cpuis("ATSAMA5D3*")
|
|
rgroup.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "RAB2,Channel 2 Register AB"
|
|
endif
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "CV2,Channel 2 Counter Value Register"
|
|
sif cpuis("ATSAM4S*")
|
|
if ((((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x4000C000+0x8000))&0x04)==0x8000))
|
|
group.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB2,Channel 2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB2,Channel 2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
endif
|
|
if (((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
else
|
|
rgroup.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
endif
|
|
else
|
|
if ((((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x4000C000+0x8000))&0x04)==0x8000))
|
|
group.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
line.long 0x04 "RB2,Channel 2 Register B"
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
line.long 0x04 "RB2,Channel 2 Register B"
|
|
endif
|
|
if (((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
else
|
|
rgroup.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long (0x80+0x20)++0x03
|
|
hide.long 0x00 "SR2,Channel 2 Status Register"
|
|
in
|
|
newline
|
|
group.long (0x80+0x2C)++0x03
|
|
line.long 0x00 "IMR2_SET/CLR,Channel 2 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS ,External trigger status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS ,RB loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS ,RA loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS ,RC compare status interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS ,RB compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS ,RA compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS ,Load overrun status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS ,Counter overflow status interrupt" "Masked,Not masked"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
if (((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)
|
|
group.long (0x80+0x30)++0x03
|
|
line.long 0x00 "EMR2,Channel 2 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB2,PWM2,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA2,PWM2,?..."
|
|
else
|
|
rgroup.long (0x80+0x30)++0x03
|
|
line.long 0x00 "EMR2,Channel 2 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB2,PWM2,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA2,PWM2,?..."
|
|
endif
|
|
endif
|
|
tree.end
|
|
newline
|
|
wgroup.long 0xC0++0x03
|
|
line.long 0x00 "BCR,Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC ,Synchro command" "No effect,Assert"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
if ((per.l(ad:0x4000C000+0xE4)&0x01)==0x00)
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "BMR,Block Mode Register"
|
|
sif cpuis("ATSAMA5D2?")||cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 26.--29. " MAXCMP ,Maximum consecutive missing pulses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum filter" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 18. " AUTOC ,Auto-correction of missing pulses" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum filter" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 16. " SWAP ,Swap PHA and PHB" "Not Swapped,Swapped"
|
|
bitfld.long 0x00 15. " INVIDX ,Inverted index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,Inverted PHB" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13. " INVA ,Inverted PHA" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 12. " EDGPHA ,Edge on PHA count mode" "PHA only,PHA/PHB"
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature decoding transparent" "Active,Inactive"
|
|
bitfld.long 0x00 10. " SPEEDEN ,Speed enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " POSEN ,Position enabled" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature decoder enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External clock signal 2 selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External clock signal 1 selection" "TCLK1,,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External clock signal 0 selection" "TCLK0,,TIOA1,TIOA2"
|
|
else
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "BMR,Block Mode Register"
|
|
sif cpuis("ATSAMA5D2?")||cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 26.--29. " MAXCMP ,Maximum consecutive missing pulses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum filter" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 18. " AUTOC ,Auto-correction of missing pulses" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum filter" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 16. " SWAP ,Swap PHA and PHB" "Not Swapped,Swapped"
|
|
bitfld.long 0x00 15. " INVIDX ,Inverted index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,Inverted PHB" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13. " INVA ,Inverted PHA" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 12. " EDGPHA ,Edge on PHA count mode" "PHA only,PHA/PHB"
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature decoding transparent" "Active,Inactive"
|
|
bitfld.long 0x00 10. " SPEEDEN ,Speed enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " POSEN ,Position enabled" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature decoder enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External clock signal 2 selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External clock signal 1 selection" "TCLK1,,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External clock signal 0 selection" "TCLK0,,TIOA1,TIOA2"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "BMR,Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External clock signal 2 selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External clock signal 1 selection" "TCLK1,,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External clock signal 0 selection" "TCLK0,,TIOA1,TIOA2"
|
|
else
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "BMR,Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External clock signal 2 selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External clock signal 1 selection" "TCLK1,,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External clock signal 0 selection" "TCLK0,,TIOA1,TIOA2"
|
|
endif
|
|
endif
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAM4N*")||cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAME70*")||cpuis("ATSAMS7*")||cpuis("ATSAMA5D2?")
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "QIMR_SET/CLR,QDEC Interrupt Mask Register"
|
|
sif cpuis("ATSAMS7*")
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " MPE ,Consecutive missing pulse error" "Masked,Unmasked"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " QERR ,Quadrature error" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DIRCHG ,Direction change" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " IDX ,Index" "Masked,Unmasked"
|
|
sif !cpuis("ATSAMS7*")
|
|
hgroup.long 0xD4++0x03
|
|
hide.long 0x00 "QISR,QDEC Interrupt Status Register"
|
|
in
|
|
else
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "QISR,QDEC Interrupt Status Register"
|
|
bitfld.long 0x00 8. " DIR ,Direction" "0,1"
|
|
bitfld.long 0x00 3. " MPE ,Consecutive missing pulse error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " QERR ,Quadrature error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " DIRCHG ,Direction change" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " IDX ,Index input change" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FMR,Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable compare fault channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable compare fault channel 0" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "FMR,Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable compare fault channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable compare fault channel 0" "Disabled,Enabled"
|
|
endif
|
|
elif cpuis("ATSAMA5D3*")
|
|
if (((per.l(ad:0x4000C000+0xE4))&0x01)==0x00)
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FMR,Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable compare fault channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable compare fault channel 0" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "FMR,Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable compare fault channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable compare fault channel 0" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect key"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TC1"
|
|
base ad:0x40010000
|
|
width 14.
|
|
tree "Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "CCR0,Channel 0 Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software trigger command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter clock disable command" "No effect,Disable"
|
|
bitfld.long 0x00 0. " CLKEN ,Counter clock enable command" "No effect,Enable"
|
|
if ((((per.l(ad:0x40010000+0x0+0x04))&0x8000)==0x00)&&(((per.l(ad:0x40010000+0xE4))&0x01)==0x00))
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x40010000+0x0+0x04))&0x8000)==0x00)&&(((per.l(ad:0x40010000+0xE4))&0x01)==0x01))
|
|
rgroup.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x40010000+0x0+0x04))&0x8000)==0x8000)&&(((per.l(ad:0x40010000+0xE4))&0x01)==0x00))
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
if (((per.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "SMMR0,Ch 0 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long (0x0+0x08)++0x03
|
|
line.long 0x00 "SMMR0,Ch 0 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("ATSAM4S*")&&!cpuis("ATSAMA5D3*")
|
|
rgroup.long (0x0+0x0C)++0x03
|
|
line.long 0x00 "RAB0,Channel 0 Register AB"
|
|
endif
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "CV0,Channel 0 Counter Value Register"
|
|
sif cpuis("ATSAM4S*")
|
|
if ((((per.l(ad:0x40010000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x40010000+0x8000))&0x04)==0x8000))
|
|
group.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB0,Channel 0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB0,Channel 0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
endif
|
|
if (((per.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
else
|
|
rgroup.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
endif
|
|
else
|
|
if ((((per.l(ad:0x40010000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x40010000+0x8000))&0x04)==0x8000))
|
|
group.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
line.long 0x04 "RB0,Channel 0 Register B"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
line.long 0x04 "RB0,Channel 0 Register B"
|
|
endif
|
|
if (((per.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
else
|
|
rgroup.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "SR0,Channel 0 Status Register"
|
|
in
|
|
newline
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "IMR0_SET/CLR,Channel 0 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS ,External trigger status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS ,RB loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS ,RA loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS ,RC compare status interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS ,RB compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS ,RA compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS ,Load overrun status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS ,Counter overflow status interrupt" "Masked,Not masked"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
if (((per.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
group.long (0x0+0x30)++0x03
|
|
line.long 0x00 "EMR0,Channel 0 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB0,PWM0,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA0,PWM0,?..."
|
|
else
|
|
rgroup.long (0x0+0x30)++0x03
|
|
line.long 0x00 "EMR0,Channel 0 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB0,PWM0,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA0,PWM0,?..."
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "CCR1,Channel 1 Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software trigger command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter clock disable command" "No effect,Disable"
|
|
bitfld.long 0x00 0. " CLKEN ,Counter clock enable command" "No effect,Enable"
|
|
if ((((per.l(ad:0x40010000+0x40+0x04))&0x8000)==0x00)&&(((per.l(ad:0x40010000+0xE4))&0x01)==0x00))
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x40010000+0x40+0x04))&0x8000)==0x00)&&(((per.l(ad:0x40010000+0xE4))&0x01)==0x01))
|
|
rgroup.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x40010000+0x40+0x04))&0x8000)==0x8000)&&(((per.l(ad:0x40010000+0xE4))&0x01)==0x00))
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
if (((per.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "SMMR1,Ch 1 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long (0x40+0x08)++0x03
|
|
line.long 0x00 "SMMR1,Ch 1 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("ATSAM4S*")&&!cpuis("ATSAMA5D3*")
|
|
rgroup.long (0x40+0x0C)++0x03
|
|
line.long 0x00 "RAB1,Channel 1 Register AB"
|
|
endif
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "CV1,Channel 1 Counter Value Register"
|
|
sif cpuis("ATSAM4S*")
|
|
if ((((per.l(ad:0x40010000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x40010000+0x8000))&0x04)==0x8000))
|
|
group.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB1,Channel 1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB1,Channel 1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
endif
|
|
if (((per.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
else
|
|
rgroup.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
endif
|
|
else
|
|
if ((((per.l(ad:0x40010000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x40010000+0x8000))&0x04)==0x8000))
|
|
group.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
line.long 0x04 "RB1,Channel 1 Register B"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
line.long 0x04 "RB1,Channel 1 Register B"
|
|
endif
|
|
if (((per.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
else
|
|
rgroup.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "SR1,Channel 1 Status Register"
|
|
in
|
|
newline
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "IMR1_SET/CLR,Channel 1 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS ,External trigger status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS ,RB loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS ,RA loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS ,RC compare status interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS ,RB compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS ,RA compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS ,Load overrun status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS ,Counter overflow status interrupt" "Masked,Not masked"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
if (((per.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
group.long (0x40+0x30)++0x03
|
|
line.long 0x00 "EMR1,Channel 1 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB1,PWM1,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA1,PWM1,?..."
|
|
else
|
|
rgroup.long (0x40+0x30)++0x03
|
|
line.long 0x00 "EMR1,Channel 1 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB1,PWM1,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA1,PWM1,?..."
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Channel 2"
|
|
wgroup.long (0x80+0x00)++0x03
|
|
line.long 0x00 "CCR2,Channel 2 Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software trigger command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter clock disable command" "No effect,Disable"
|
|
bitfld.long 0x00 0. " CLKEN ,Counter clock enable command" "No effect,Enable"
|
|
if ((((per.l(ad:0x40010000+0x80+0x04))&0x8000)==0x00)&&(((per.l(ad:0x40010000+0xE4))&0x01)==0x00))
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x40010000+0x80+0x04))&0x8000)==0x00)&&(((per.l(ad:0x40010000+0xE4))&0x01)==0x01))
|
|
rgroup.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x40010000+0x80+0x04))&0x8000)==0x8000)&&(((per.l(ad:0x40010000+0xE4))&0x01)==0x00))
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
if (((per.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "SMMR2,Ch 2 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long (0x80+0x08)++0x03
|
|
line.long 0x00 "SMMR2,Ch 2 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("ATSAM4S*")&&!cpuis("ATSAMA5D3*")
|
|
rgroup.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "RAB2,Channel 2 Register AB"
|
|
endif
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "CV2,Channel 2 Counter Value Register"
|
|
sif cpuis("ATSAM4S*")
|
|
if ((((per.l(ad:0x40010000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x40010000+0x8000))&0x04)==0x8000))
|
|
group.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB2,Channel 2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB2,Channel 2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
endif
|
|
if (((per.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
else
|
|
rgroup.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
endif
|
|
else
|
|
if ((((per.l(ad:0x40010000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x40010000+0x8000))&0x04)==0x8000))
|
|
group.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
line.long 0x04 "RB2,Channel 2 Register B"
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
line.long 0x04 "RB2,Channel 2 Register B"
|
|
endif
|
|
if (((per.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
else
|
|
rgroup.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long (0x80+0x20)++0x03
|
|
hide.long 0x00 "SR2,Channel 2 Status Register"
|
|
in
|
|
newline
|
|
group.long (0x80+0x2C)++0x03
|
|
line.long 0x00 "IMR2_SET/CLR,Channel 2 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS ,External trigger status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS ,RB loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS ,RA loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS ,RC compare status interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS ,RB compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS ,RA compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS ,Load overrun status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS ,Counter overflow status interrupt" "Masked,Not masked"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
if (((per.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
group.long (0x80+0x30)++0x03
|
|
line.long 0x00 "EMR2,Channel 2 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB2,PWM2,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA2,PWM2,?..."
|
|
else
|
|
rgroup.long (0x80+0x30)++0x03
|
|
line.long 0x00 "EMR2,Channel 2 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB2,PWM2,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA2,PWM2,?..."
|
|
endif
|
|
endif
|
|
tree.end
|
|
newline
|
|
wgroup.long 0xC0++0x03
|
|
line.long 0x00 "BCR,Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC ,Synchro command" "No effect,Assert"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
if ((per.l(ad:0x40010000+0xE4)&0x01)==0x00)
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "BMR,Block Mode Register"
|
|
sif cpuis("ATSAMA5D2?")||cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 26.--29. " MAXCMP ,Maximum consecutive missing pulses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum filter" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 18. " AUTOC ,Auto-correction of missing pulses" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum filter" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 16. " SWAP ,Swap PHA and PHB" "Not Swapped,Swapped"
|
|
bitfld.long 0x00 15. " INVIDX ,Inverted index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,Inverted PHB" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13. " INVA ,Inverted PHA" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 12. " EDGPHA ,Edge on PHA count mode" "PHA only,PHA/PHB"
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature decoding transparent" "Active,Inactive"
|
|
bitfld.long 0x00 10. " SPEEDEN ,Speed enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " POSEN ,Position enabled" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature decoder enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External clock signal 2 selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External clock signal 1 selection" "TCLK1,,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External clock signal 0 selection" "TCLK0,,TIOA1,TIOA2"
|
|
else
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "BMR,Block Mode Register"
|
|
sif cpuis("ATSAMA5D2?")||cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 26.--29. " MAXCMP ,Maximum consecutive missing pulses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum filter" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 18. " AUTOC ,Auto-correction of missing pulses" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum filter" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 16. " SWAP ,Swap PHA and PHB" "Not Swapped,Swapped"
|
|
bitfld.long 0x00 15. " INVIDX ,Inverted index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,Inverted PHB" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13. " INVA ,Inverted PHA" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 12. " EDGPHA ,Edge on PHA count mode" "PHA only,PHA/PHB"
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature decoding transparent" "Active,Inactive"
|
|
bitfld.long 0x00 10. " SPEEDEN ,Speed enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " POSEN ,Position enabled" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature decoder enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External clock signal 2 selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External clock signal 1 selection" "TCLK1,,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External clock signal 0 selection" "TCLK0,,TIOA1,TIOA2"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "BMR,Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External clock signal 2 selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External clock signal 1 selection" "TCLK1,,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External clock signal 0 selection" "TCLK0,,TIOA1,TIOA2"
|
|
else
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "BMR,Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External clock signal 2 selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External clock signal 1 selection" "TCLK1,,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External clock signal 0 selection" "TCLK0,,TIOA1,TIOA2"
|
|
endif
|
|
endif
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAM4N*")||cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAME70*")||cpuis("ATSAMS7*")||cpuis("ATSAMA5D2?")
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "QIMR_SET/CLR,QDEC Interrupt Mask Register"
|
|
sif cpuis("ATSAMS7*")
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " MPE ,Consecutive missing pulse error" "Masked,Unmasked"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " QERR ,Quadrature error" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DIRCHG ,Direction change" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " IDX ,Index" "Masked,Unmasked"
|
|
sif !cpuis("ATSAMS7*")
|
|
hgroup.long 0xD4++0x03
|
|
hide.long 0x00 "QISR,QDEC Interrupt Status Register"
|
|
in
|
|
else
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "QISR,QDEC Interrupt Status Register"
|
|
bitfld.long 0x00 8. " DIR ,Direction" "0,1"
|
|
bitfld.long 0x00 3. " MPE ,Consecutive missing pulse error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " QERR ,Quadrature error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " DIRCHG ,Direction change" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " IDX ,Index input change" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FMR,Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable compare fault channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable compare fault channel 0" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "FMR,Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable compare fault channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable compare fault channel 0" "Disabled,Enabled"
|
|
endif
|
|
elif cpuis("ATSAMA5D3*")
|
|
if (((per.l(ad:0x40010000+0xE4))&0x01)==0x00)
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FMR,Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable compare fault channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable compare fault channel 0" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "FMR,Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable compare fault channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable compare fault channel 0" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect key"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TC2"
|
|
base ad:0x40014000
|
|
width 14.
|
|
tree "Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "CCR0,Channel 0 Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software trigger command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter clock disable command" "No effect,Disable"
|
|
bitfld.long 0x00 0. " CLKEN ,Counter clock enable command" "No effect,Enable"
|
|
if ((((per.l(ad:0x40014000+0x0+0x04))&0x8000)==0x00)&&(((per.l(ad:0x40014000+0xE4))&0x01)==0x00))
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x40014000+0x0+0x04))&0x8000)==0x00)&&(((per.l(ad:0x40014000+0xE4))&0x01)==0x01))
|
|
rgroup.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x40014000+0x0+0x04))&0x8000)==0x8000)&&(((per.l(ad:0x40014000+0xE4))&0x01)==0x00))
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
if (((per.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "SMMR0,Ch 0 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long (0x0+0x08)++0x03
|
|
line.long 0x00 "SMMR0,Ch 0 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("ATSAM4S*")&&!cpuis("ATSAMA5D3*")
|
|
rgroup.long (0x0+0x0C)++0x03
|
|
line.long 0x00 "RAB0,Channel 0 Register AB"
|
|
endif
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "CV0,Channel 0 Counter Value Register"
|
|
sif cpuis("ATSAM4S*")
|
|
if ((((per.l(ad:0x40014000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x40014000+0x8000))&0x04)==0x8000))
|
|
group.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB0,Channel 0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB0,Channel 0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
endif
|
|
if (((per.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
else
|
|
rgroup.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
endif
|
|
else
|
|
if ((((per.l(ad:0x40014000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x40014000+0x8000))&0x04)==0x8000))
|
|
group.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
line.long 0x04 "RB0,Channel 0 Register B"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
line.long 0x04 "RB0,Channel 0 Register B"
|
|
endif
|
|
if (((per.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
else
|
|
rgroup.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "SR0,Channel 0 Status Register"
|
|
in
|
|
newline
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "IMR0_SET/CLR,Channel 0 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS ,External trigger status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS ,RB loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS ,RA loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS ,RC compare status interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS ,RB compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS ,RA compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS ,Load overrun status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS ,Counter overflow status interrupt" "Masked,Not masked"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
if (((per.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
group.long (0x0+0x30)++0x03
|
|
line.long 0x00 "EMR0,Channel 0 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB0,PWM0,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA0,PWM0,?..."
|
|
else
|
|
rgroup.long (0x0+0x30)++0x03
|
|
line.long 0x00 "EMR0,Channel 0 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB0,PWM0,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA0,PWM0,?..."
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "CCR1,Channel 1 Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software trigger command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter clock disable command" "No effect,Disable"
|
|
bitfld.long 0x00 0. " CLKEN ,Counter clock enable command" "No effect,Enable"
|
|
if ((((per.l(ad:0x40014000+0x40+0x04))&0x8000)==0x00)&&(((per.l(ad:0x40014000+0xE4))&0x01)==0x00))
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x40014000+0x40+0x04))&0x8000)==0x00)&&(((per.l(ad:0x40014000+0xE4))&0x01)==0x01))
|
|
rgroup.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x40014000+0x40+0x04))&0x8000)==0x8000)&&(((per.l(ad:0x40014000+0xE4))&0x01)==0x00))
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
if (((per.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "SMMR1,Ch 1 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long (0x40+0x08)++0x03
|
|
line.long 0x00 "SMMR1,Ch 1 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("ATSAM4S*")&&!cpuis("ATSAMA5D3*")
|
|
rgroup.long (0x40+0x0C)++0x03
|
|
line.long 0x00 "RAB1,Channel 1 Register AB"
|
|
endif
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "CV1,Channel 1 Counter Value Register"
|
|
sif cpuis("ATSAM4S*")
|
|
if ((((per.l(ad:0x40014000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x40014000+0x8000))&0x04)==0x8000))
|
|
group.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB1,Channel 1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB1,Channel 1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
endif
|
|
if (((per.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
else
|
|
rgroup.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
endif
|
|
else
|
|
if ((((per.l(ad:0x40014000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x40014000+0x8000))&0x04)==0x8000))
|
|
group.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
line.long 0x04 "RB1,Channel 1 Register B"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
line.long 0x04 "RB1,Channel 1 Register B"
|
|
endif
|
|
if (((per.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
else
|
|
rgroup.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "SR1,Channel 1 Status Register"
|
|
in
|
|
newline
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "IMR1_SET/CLR,Channel 1 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS ,External trigger status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS ,RB loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS ,RA loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS ,RC compare status interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS ,RB compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS ,RA compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS ,Load overrun status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS ,Counter overflow status interrupt" "Masked,Not masked"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
if (((per.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
group.long (0x40+0x30)++0x03
|
|
line.long 0x00 "EMR1,Channel 1 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB1,PWM1,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA1,PWM1,?..."
|
|
else
|
|
rgroup.long (0x40+0x30)++0x03
|
|
line.long 0x00 "EMR1,Channel 1 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB1,PWM1,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA1,PWM1,?..."
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Channel 2"
|
|
wgroup.long (0x80+0x00)++0x03
|
|
line.long 0x00 "CCR2,Channel 2 Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software trigger command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter clock disable command" "No effect,Disable"
|
|
bitfld.long 0x00 0. " CLKEN ,Counter clock enable command" "No effect,Enable"
|
|
if ((((per.l(ad:0x40014000+0x80+0x04))&0x8000)==0x00)&&(((per.l(ad:0x40014000+0xE4))&0x01)==0x00))
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x40014000+0x80+0x04))&0x8000)==0x00)&&(((per.l(ad:0x40014000+0xE4))&0x01)==0x01))
|
|
rgroup.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x40014000+0x80+0x04))&0x8000)==0x8000)&&(((per.l(ad:0x40014000+0xE4))&0x01)==0x00))
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
if (((per.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "SMMR2,Ch 2 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long (0x80+0x08)++0x03
|
|
line.long 0x00 "SMMR2,Ch 2 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("ATSAM4S*")&&!cpuis("ATSAMA5D3*")
|
|
rgroup.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "RAB2,Channel 2 Register AB"
|
|
endif
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "CV2,Channel 2 Counter Value Register"
|
|
sif cpuis("ATSAM4S*")
|
|
if ((((per.l(ad:0x40014000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x40014000+0x8000))&0x04)==0x8000))
|
|
group.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB2,Channel 2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB2,Channel 2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
endif
|
|
if (((per.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
else
|
|
rgroup.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
endif
|
|
else
|
|
if ((((per.l(ad:0x40014000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x40014000+0x8000))&0x04)==0x8000))
|
|
group.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
line.long 0x04 "RB2,Channel 2 Register B"
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
line.long 0x04 "RB2,Channel 2 Register B"
|
|
endif
|
|
if (((per.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
else
|
|
rgroup.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long (0x80+0x20)++0x03
|
|
hide.long 0x00 "SR2,Channel 2 Status Register"
|
|
in
|
|
newline
|
|
group.long (0x80+0x2C)++0x03
|
|
line.long 0x00 "IMR2_SET/CLR,Channel 2 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS ,External trigger status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS ,RB loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS ,RA loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS ,RC compare status interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS ,RB compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS ,RA compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS ,Load overrun status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS ,Counter overflow status interrupt" "Masked,Not masked"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
if (((per.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
group.long (0x80+0x30)++0x03
|
|
line.long 0x00 "EMR2,Channel 2 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB2,PWM2,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA2,PWM2,?..."
|
|
else
|
|
rgroup.long (0x80+0x30)++0x03
|
|
line.long 0x00 "EMR2,Channel 2 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB2,PWM2,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA2,PWM2,?..."
|
|
endif
|
|
endif
|
|
tree.end
|
|
newline
|
|
wgroup.long 0xC0++0x03
|
|
line.long 0x00 "BCR,Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC ,Synchro command" "No effect,Assert"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
if ((per.l(ad:0x40014000+0xE4)&0x01)==0x00)
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "BMR,Block Mode Register"
|
|
sif cpuis("ATSAMA5D2?")||cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 26.--29. " MAXCMP ,Maximum consecutive missing pulses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum filter" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 18. " AUTOC ,Auto-correction of missing pulses" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum filter" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 16. " SWAP ,Swap PHA and PHB" "Not Swapped,Swapped"
|
|
bitfld.long 0x00 15. " INVIDX ,Inverted index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,Inverted PHB" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13. " INVA ,Inverted PHA" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 12. " EDGPHA ,Edge on PHA count mode" "PHA only,PHA/PHB"
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature decoding transparent" "Active,Inactive"
|
|
bitfld.long 0x00 10. " SPEEDEN ,Speed enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " POSEN ,Position enabled" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature decoder enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External clock signal 2 selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External clock signal 1 selection" "TCLK1,,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External clock signal 0 selection" "TCLK0,,TIOA1,TIOA2"
|
|
else
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "BMR,Block Mode Register"
|
|
sif cpuis("ATSAMA5D2?")||cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 26.--29. " MAXCMP ,Maximum consecutive missing pulses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum filter" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 18. " AUTOC ,Auto-correction of missing pulses" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum filter" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 16. " SWAP ,Swap PHA and PHB" "Not Swapped,Swapped"
|
|
bitfld.long 0x00 15. " INVIDX ,Inverted index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,Inverted PHB" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13. " INVA ,Inverted PHA" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 12. " EDGPHA ,Edge on PHA count mode" "PHA only,PHA/PHB"
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature decoding transparent" "Active,Inactive"
|
|
bitfld.long 0x00 10. " SPEEDEN ,Speed enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " POSEN ,Position enabled" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature decoder enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External clock signal 2 selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External clock signal 1 selection" "TCLK1,,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External clock signal 0 selection" "TCLK0,,TIOA1,TIOA2"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "BMR,Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External clock signal 2 selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External clock signal 1 selection" "TCLK1,,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External clock signal 0 selection" "TCLK0,,TIOA1,TIOA2"
|
|
else
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "BMR,Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External clock signal 2 selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External clock signal 1 selection" "TCLK1,,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External clock signal 0 selection" "TCLK0,,TIOA1,TIOA2"
|
|
endif
|
|
endif
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAM4N*")||cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAME70*")||cpuis("ATSAMS7*")||cpuis("ATSAMA5D2?")
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "QIMR_SET/CLR,QDEC Interrupt Mask Register"
|
|
sif cpuis("ATSAMS7*")
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " MPE ,Consecutive missing pulse error" "Masked,Unmasked"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " QERR ,Quadrature error" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DIRCHG ,Direction change" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " IDX ,Index" "Masked,Unmasked"
|
|
sif !cpuis("ATSAMS7*")
|
|
hgroup.long 0xD4++0x03
|
|
hide.long 0x00 "QISR,QDEC Interrupt Status Register"
|
|
in
|
|
else
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "QISR,QDEC Interrupt Status Register"
|
|
bitfld.long 0x00 8. " DIR ,Direction" "0,1"
|
|
bitfld.long 0x00 3. " MPE ,Consecutive missing pulse error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " QERR ,Quadrature error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " DIRCHG ,Direction change" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " IDX ,Index input change" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FMR,Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable compare fault channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable compare fault channel 0" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "FMR,Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable compare fault channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable compare fault channel 0" "Disabled,Enabled"
|
|
endif
|
|
elif cpuis("ATSAMA5D3*")
|
|
if (((per.l(ad:0x40014000+0xE4))&0x01)==0x00)
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FMR,Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable compare fault channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable compare fault channel 0" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "FMR,Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable compare fault channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable compare fault channel 0" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect key"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TC3"
|
|
base ad:0x40054000
|
|
width 14.
|
|
tree "Channel 0"
|
|
wgroup.long (0x0+0x00)++0x03
|
|
line.long 0x00 "CCR0,Channel 0 Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software trigger command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter clock disable command" "No effect,Disable"
|
|
bitfld.long 0x00 0. " CLKEN ,Counter clock enable command" "No effect,Enable"
|
|
if ((((per.l(ad:0x40054000+0x0+0x04))&0x8000)==0x00)&&(((per.l(ad:0x40054000+0xE4))&0x01)==0x00))
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x40054000+0x0+0x04))&0x8000)==0x00)&&(((per.l(ad:0x40054000+0xE4))&0x01)==0x01))
|
|
rgroup.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x40054000+0x0+0x04))&0x8000)==0x8000)&&(((per.l(ad:0x40054000+0xE4))&0x01)==0x00))
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long (0x0+0x04)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
if (((per.l(ad:0x40054000+0xE4))&0x01)==0x00)
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "SMMR0,Ch 0 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long (0x0+0x08)++0x03
|
|
line.long 0x00 "SMMR0,Ch 0 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("ATSAM4S*")&&!cpuis("ATSAMA5D3*")
|
|
rgroup.long (0x0+0x0C)++0x03
|
|
line.long 0x00 "RAB0,Channel 0 Register AB"
|
|
endif
|
|
rgroup.long (0x0+0x10)++0x03
|
|
line.long 0x00 "CV0,Channel 0 Counter Value Register"
|
|
sif cpuis("ATSAM4S*")
|
|
if ((((per.l(ad:0x40054000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x40054000+0x8000))&0x04)==0x8000))
|
|
group.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB0,Channel 0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB0,Channel 0 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
endif
|
|
if (((per.l(ad:0x40054000+0xE4))&0x01)==0x00)
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
else
|
|
rgroup.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
endif
|
|
else
|
|
if ((((per.l(ad:0x40054000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x40054000+0x8000))&0x04)==0x8000))
|
|
group.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
line.long 0x04 "RB0,Channel 0 Register B"
|
|
else
|
|
rgroup.long (0x0+0x14)++0x07
|
|
line.long 0x00 "RA0,Channel 0 Register A"
|
|
line.long 0x04 "RB0,Channel 0 Register B"
|
|
endif
|
|
if (((per.l(ad:0x40054000+0xE4))&0x01)==0x00)
|
|
group.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
else
|
|
rgroup.long (0x0+0x1C)++0x03
|
|
line.long 0x00 "RC0,Channel 0 Register C"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long (0x0+0x20)++0x03
|
|
hide.long 0x00 "SR0,Channel 0 Status Register"
|
|
in
|
|
newline
|
|
group.long (0x0+0x2C)++0x03
|
|
line.long 0x00 "IMR0_SET/CLR,Channel 0 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS ,External trigger status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS ,RB loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS ,RA loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS ,RC compare status interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS ,RB compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS ,RA compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS ,Load overrun status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS ,Counter overflow status interrupt" "Masked,Not masked"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
if (((per.l(ad:0x40054000+0xE4))&0x01)==0x00)
|
|
group.long (0x0+0x30)++0x03
|
|
line.long 0x00 "EMR0,Channel 0 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB0,PWM0,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA0,PWM0,?..."
|
|
else
|
|
rgroup.long (0x0+0x30)++0x03
|
|
line.long 0x00 "EMR0,Channel 0 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB0,PWM0,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA0,PWM0,?..."
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Channel 1"
|
|
wgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "CCR1,Channel 1 Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software trigger command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter clock disable command" "No effect,Disable"
|
|
bitfld.long 0x00 0. " CLKEN ,Counter clock enable command" "No effect,Enable"
|
|
if ((((per.l(ad:0x40054000+0x40+0x04))&0x8000)==0x00)&&(((per.l(ad:0x40054000+0xE4))&0x01)==0x00))
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x40054000+0x40+0x04))&0x8000)==0x00)&&(((per.l(ad:0x40054000+0xE4))&0x01)==0x01))
|
|
rgroup.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x40054000+0x40+0x04))&0x8000)==0x8000)&&(((per.l(ad:0x40054000+0xE4))&0x01)==0x00))
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long (0x40+0x04)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
if (((per.l(ad:0x40054000+0xE4))&0x01)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "SMMR1,Ch 1 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long (0x40+0x08)++0x03
|
|
line.long 0x00 "SMMR1,Ch 1 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("ATSAM4S*")&&!cpuis("ATSAMA5D3*")
|
|
rgroup.long (0x40+0x0C)++0x03
|
|
line.long 0x00 "RAB1,Channel 1 Register AB"
|
|
endif
|
|
rgroup.long (0x40+0x10)++0x03
|
|
line.long 0x00 "CV1,Channel 1 Counter Value Register"
|
|
sif cpuis("ATSAM4S*")
|
|
if ((((per.l(ad:0x40054000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x40054000+0x8000))&0x04)==0x8000))
|
|
group.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB1,Channel 1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB1,Channel 1 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
endif
|
|
if (((per.l(ad:0x40054000+0xE4))&0x01)==0x00)
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
else
|
|
rgroup.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
endif
|
|
else
|
|
if ((((per.l(ad:0x40054000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x40054000+0x8000))&0x04)==0x8000))
|
|
group.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
line.long 0x04 "RB1,Channel 1 Register B"
|
|
else
|
|
rgroup.long (0x40+0x14)++0x07
|
|
line.long 0x00 "RA1,Channel 1 Register A"
|
|
line.long 0x04 "RB1,Channel 1 Register B"
|
|
endif
|
|
if (((per.l(ad:0x40054000+0xE4))&0x01)==0x00)
|
|
group.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
else
|
|
rgroup.long (0x40+0x1C)++0x03
|
|
line.long 0x00 "RC1,Channel 1 Register C"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long (0x40+0x20)++0x03
|
|
hide.long 0x00 "SR1,Channel 1 Status Register"
|
|
in
|
|
newline
|
|
group.long (0x40+0x2C)++0x03
|
|
line.long 0x00 "IMR1_SET/CLR,Channel 1 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS ,External trigger status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS ,RB loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS ,RA loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS ,RC compare status interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS ,RB compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS ,RA compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS ,Load overrun status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS ,Counter overflow status interrupt" "Masked,Not masked"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
if (((per.l(ad:0x40054000+0xE4))&0x01)==0x00)
|
|
group.long (0x40+0x30)++0x03
|
|
line.long 0x00 "EMR1,Channel 1 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB1,PWM1,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA1,PWM1,?..."
|
|
else
|
|
rgroup.long (0x40+0x30)++0x03
|
|
line.long 0x00 "EMR1,Channel 1 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB1,PWM1,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA1,PWM1,?..."
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree "Channel 2"
|
|
wgroup.long (0x80+0x00)++0x03
|
|
line.long 0x00 "CCR2,Channel 2 Control Register"
|
|
bitfld.long 0x00 2. " SWTRG ,Software trigger command" "No effect,Trigger"
|
|
bitfld.long 0x00 1. " CLKDIS ,Counter clock disable command" "No effect,Disable"
|
|
bitfld.long 0x00 0. " CLKEN ,Counter clock enable command" "No effect,Enable"
|
|
if ((((per.l(ad:0x40054000+0x80+0x04))&0x8000)==0x00)&&(((per.l(ad:0x40054000+0xE4))&0x01)==0x00))
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x40054000+0x80+0x04))&0x8000)==0x00)&&(((per.l(ad:0x40054000+0xE4))&0x01)==0x01))
|
|
rgroup.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
bitfld.long 0x00 20.--22. " SBSMPLR ,Loading edge subsampling ratio" "One,Half,Fourth,Eighth,Sixteenth,?..."
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 18.--19. " LDRB ,RB loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 16.--17. " LDRA ,RA loading edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
newline
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CPCTRG ,RC compare trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ABETRG ,TIOA or TIOB external trigger selection" "TIOB,TIOA"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " ETRGEDG ,External trigger edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " LDBDIS ,Counter clock disable with RB loading" "No,Yes"
|
|
bitfld.long 0x00 6. " LDBSTOP ,Counter clock stopped with RB loading" "Not stopped,Stopped"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
elif ((((per.l(ad:0x40054000+0x80+0x04))&0x8000)==0x8000)&&(((per.l(ad:0x40054000+0xE4))&0x01)==0x00))
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
else
|
|
rgroup.long (0x80+0x04)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 30.--31. " BSWTRG ,Software trigger effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 28.--29. " BEEVT ,External event effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 26.--27. " BCPC ,RC compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 24.--25. " BCPB ,RB compare effect on TIOB" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22.--23. " ASWTRG ,Software trigger effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 20.--21. " AEEVT ,External event effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 18.--19. " ACPC ,RC compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
bitfld.long 0x00 16.--17. " ACPA ,RA compare effect on TIOA" "None,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. " WAVE ,Waveform mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 13.--14. " WAVSEL ,Waveform selection (with/without automatic trigger on RC compare)" "UP,UPDOWN,UP_RC,UPDOWN_RC"
|
|
newline
|
|
bitfld.long 0x00 12. " ENETRG ,External event trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " EEVT ,External event selection" "TIOB,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " EEVTEDG ,External event edge selection" "None,Rising edge,Falling edge,Each edge"
|
|
bitfld.long 0x00 7. " CPCDIS ,Counter clock disable with RC compare" "No,Yes"
|
|
bitfld.long 0x00 6. " CPCSTOP ,Counter clock stopped with RC compare" "Not stopped,Stopped"
|
|
bitfld.long 0x00 4.--5. " BURST ,Burst signal selection" "Not gated,XC0,XC1,XC2"
|
|
newline
|
|
bitfld.long 0x00 3. " CLKI ,Clock invert" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " TCCLKS ,Clock selection" "TIMER_CLOCK1,TIMER_CLOCK2,TIMER_CLOCK3,TIMER_CLOCK4,TIMER_CLOCK5,XC0,XC1,XC2"
|
|
endif
|
|
if (((per.l(ad:0x40054000+0xE4))&0x01)==0x00)
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "SMMR2,Ch 2 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long (0x80+0x08)++0x03
|
|
line.long 0x00 "SMMR2,Ch 2 Stepper Motor Mode Register"
|
|
bitfld.long 0x00 1. " DOWN ,Down count" "Up,Down"
|
|
bitfld.long 0x00 0. " GCEN ,Gray count enable" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("ATSAM4S*")&&!cpuis("ATSAMA5D3*")
|
|
rgroup.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "RAB2,Channel 2 Register AB"
|
|
endif
|
|
rgroup.long (0x80+0x10)++0x03
|
|
line.long 0x00 "CV2,Channel 2 Counter Value Register"
|
|
sif cpuis("ATSAM4S*")
|
|
if ((((per.l(ad:0x40054000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x40054000+0x8000))&0x04)==0x8000))
|
|
group.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB2,Channel 2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
hexmask.long.word 0x00 0.--15. 1. " RA ,Register A value"
|
|
line.long 0x04 "RB2,Channel 2 Register B"
|
|
hexmask.long.word 0x04 0.--15. 1. " RB ,Register B value"
|
|
endif
|
|
if (((per.l(ad:0x40054000+0xE4))&0x01)==0x00)
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
else
|
|
rgroup.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
hexmask.long.word 0x00 0.--15. 1. " RC ,Register C value"
|
|
endif
|
|
else
|
|
if ((((per.l(ad:0x40054000+0xE4))&0x01)==0x00)&&(((per.l(ad:0x40054000+0x8000))&0x04)==0x8000))
|
|
group.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
line.long 0x04 "RB2,Channel 2 Register B"
|
|
else
|
|
rgroup.long (0x80+0x14)++0x07
|
|
line.long 0x00 "RA2,Channel 2 Register A"
|
|
line.long 0x04 "RB2,Channel 2 Register B"
|
|
endif
|
|
if (((per.l(ad:0x40054000+0xE4))&0x01)==0x00)
|
|
group.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
else
|
|
rgroup.long (0x80+0x1C)++0x03
|
|
line.long 0x00 "RC2,Channel 2 Register C"
|
|
endif
|
|
endif
|
|
newline
|
|
hgroup.long (0x80+0x20)++0x03
|
|
hide.long 0x00 "SR2,Channel 2 Status Register"
|
|
in
|
|
newline
|
|
group.long (0x80+0x2C)++0x03
|
|
line.long 0x00 "IMR2_SET/CLR,Channel 2 Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " ETRGS ,External trigger status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " LDRBS ,RB loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " LDRAS ,RA loading status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " CPCS ,RC compare status interrupt" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CPBS ,RB compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CPAS ,RA compare status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " LOVRS ,Load overrun status interrupt" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " COVFS ,Counter overflow status interrupt" "Masked,Not masked"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
if (((per.l(ad:0x40054000+0xE4))&0x01)==0x00)
|
|
group.long (0x80+0x30)++0x03
|
|
line.long 0x00 "EMR2,Channel 2 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB2,PWM2,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA2,PWM2,?..."
|
|
else
|
|
rgroup.long (0x80+0x30)++0x03
|
|
line.long 0x00 "EMR2,Channel 2 Extended Mode Register"
|
|
bitfld.long 0x00 8. " NODIVCLK ,No divided clock" "Divided,Not divided"
|
|
bitfld.long 0x00 4.--5. " TRIGSRCB ,Trigger source for input B" "External TIOB2,PWM2,?..."
|
|
bitfld.long 0x00 0.--1. " TRIGSRCA ,Trigger source for input A" "External TIOA2,PWM2,?..."
|
|
endif
|
|
endif
|
|
tree.end
|
|
newline
|
|
wgroup.long 0xC0++0x03
|
|
line.long 0x00 "BCR,Block Control Register"
|
|
bitfld.long 0x00 0. " SYNC ,Synchro command" "No effect,Assert"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
if ((per.l(ad:0x40054000+0xE4)&0x01)==0x00)
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "BMR,Block Mode Register"
|
|
sif cpuis("ATSAMA5D2?")||cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 26.--29. " MAXCMP ,Maximum consecutive missing pulses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum filter" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 18. " AUTOC ,Auto-correction of missing pulses" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum filter" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 16. " SWAP ,Swap PHA and PHB" "Not Swapped,Swapped"
|
|
bitfld.long 0x00 15. " INVIDX ,Inverted index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,Inverted PHB" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13. " INVA ,Inverted PHA" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 12. " EDGPHA ,Edge on PHA count mode" "PHA only,PHA/PHB"
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature decoding transparent" "Active,Inactive"
|
|
bitfld.long 0x00 10. " SPEEDEN ,Speed enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " POSEN ,Position enabled" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature decoder enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External clock signal 2 selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External clock signal 1 selection" "TCLK1,,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External clock signal 0 selection" "TCLK0,,TIOA1,TIOA2"
|
|
else
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "BMR,Block Mode Register"
|
|
sif cpuis("ATSAMA5D2?")||cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 26.--29. " MAXCMP ,Maximum consecutive missing pulses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum filter" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 18. " AUTOC ,Auto-correction of missing pulses" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
newline
|
|
else
|
|
bitfld.long 0x00 20.--25. " MAXFILT ,Maximum filter" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 17. " IDXPHB ,Index pin is PHB pin" "TIOA1,TIOB0"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 16. " SWAP ,Swap PHA and PHB" "Not Swapped,Swapped"
|
|
bitfld.long 0x00 15. " INVIDX ,Inverted index" "Not inverted,Inverted"
|
|
bitfld.long 0x00 14. " INVB ,Inverted PHB" "Not inverted,Inverted"
|
|
bitfld.long 0x00 13. " INVA ,Inverted PHA" "Not inverted,Inverted"
|
|
newline
|
|
bitfld.long 0x00 12. " EDGPHA ,Edge on PHA count mode" "PHA only,PHA/PHB"
|
|
bitfld.long 0x00 11. " QDTRANS ,Quadrature decoding transparent" "Active,Inactive"
|
|
bitfld.long 0x00 10. " SPEEDEN ,Speed enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " POSEN ,Position enabled" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " QDEN ,Quadrature decoder enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External clock signal 2 selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External clock signal 1 selection" "TCLK1,,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External clock signal 0 selection" "TCLK0,,TIOA1,TIOA2"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40054000+0xE4))&0x01)==0x00)
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "BMR,Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External clock signal 2 selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External clock signal 1 selection" "TCLK1,,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External clock signal 0 selection" "TCLK0,,TIOA1,TIOA2"
|
|
else
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "BMR,Block Mode Register"
|
|
bitfld.long 0x00 4.--5. " TC2XC2S ,External clock signal 2 selection" "TCLK2,,TIOA0,TIOA1"
|
|
bitfld.long 0x00 2.--3. " TC1XC1S ,External clock signal 1 selection" "TCLK1,,TIOA0,TIOA2"
|
|
bitfld.long 0x00 0.--1. " TC0XC0S ,External clock signal 0 selection" "TCLK0,,TIOA1,TIOA2"
|
|
endif
|
|
endif
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAM4N*")||cpuis("ATSAM4S*")||cpuis("ATSAMV7*")||cpuis("ATSAME70*")||cpuis("ATSAMS7*")||cpuis("ATSAMA5D2?")
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "QIMR_SET/CLR,QDEC Interrupt Mask Register"
|
|
sif cpuis("ATSAMS7*")
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " MPE ,Consecutive missing pulse error" "Masked,Unmasked"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " QERR ,Quadrature error" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " DIRCHG ,Direction change" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " IDX ,Index" "Masked,Unmasked"
|
|
sif !cpuis("ATSAMS7*")
|
|
hgroup.long 0xD4++0x03
|
|
hide.long 0x00 "QISR,QDEC Interrupt Status Register"
|
|
in
|
|
else
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "QISR,QDEC Interrupt Status Register"
|
|
bitfld.long 0x00 8. " DIR ,Direction" "0,1"
|
|
bitfld.long 0x00 3. " MPE ,Consecutive missing pulse error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " QERR ,Quadrature error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " DIRCHG ,Direction change" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " IDX ,Index input change" "Not occurred,Occurred"
|
|
endif
|
|
if (((per.l(ad:0x40054000+0xE4))&0x01)==0x00)
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FMR,Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable compare fault channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable compare fault channel 0" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "FMR,Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable compare fault channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable compare fault channel 0" "Disabled,Enabled"
|
|
endif
|
|
elif cpuis("ATSAMA5D3*")
|
|
if (((per.l(ad:0x40054000+0xE4))&0x01)==0x00)
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FMR,Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable compare fault channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable compare fault channel 0" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "FMR,Fault Mode Register"
|
|
bitfld.long 0x00 1. " ENCF1 ,Enable compare fault channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENCF0 ,Enable compare fault channel 0" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect key"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "PWM (Pulse Width Modulation Controller)"
|
|
tree "PWM0"
|
|
base ad:0x40020000
|
|
width 14.
|
|
tree "Common Registers"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CLK,PWM Clock Register"
|
|
bitfld.long 0x00 24.--27. " PREB ,Divider input clock" "CLK/1,CLK/2,CLK/4,CLK/8,CLK/16,CLK/32,CLK/64,CLK/128,CLK/256,CLK/512,CLK/1024,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " DIVB ,CLKB divide factor"
|
|
bitfld.long 0x00 8.--11. " PREA ,Divider input clock" "CLK/1,CLK/2,CLK/4,CLK/8,CLK/16,CLK/32,CLK/64,CLK/128,CLK/256,CLK/512,CLK/1024,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,CLKA divide factor"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SR_SET/CLR,PWM Status Set/Clear Register"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CHID3 ,PWM output for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CHID2 ,PWM output for channel 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " CHID1 ,PWM output for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CHID0 ,PWM output for channel 0" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IMR1_SET/CLR,PWM Interrupt Mask Set/Clear Register 1"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " FCHID3 ,Fault protection trigger on channel 3 interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " FCHID2 ,Fault protection trigger on channel 2 interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " FCHID1 ,Fault protection trigger on channel 1 interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " FCHID0 ,Fault protection trigger on channel 0 interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CHID3 ,Counter event on channel 3 interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CHID2 ,Counter event on channel 2 interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " CHID1 ,Counter event on channel 1 interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CHID0 ,Counter event on channel 0 interrupt" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "ISR1,PWM Interrupt Status Register 1"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x40020000+0x20)&0x30000)==0x20000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SCM,PWM Sync Channels Mode Register"
|
|
bitfld.long 0x00 21.--23. " PTRCS ,DMA transfer request comparison selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. " PTRM ,DMA transfer request mode" "At update period end,At comparison match"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " UPDM ,Synchronous channels update mode (write of duty-cycle update registers/update of synchronous channels)" "Manual/manual,Manual/automatic,Automatic/automatic,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " SYNC3 ,Synchronous channel 3" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 2. " SYNC2 ,Synchronous channel 2" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 1. " SYNC1 ,Synchronous channel 1" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 0. " SYNC0 ,Synchronous channel 0" "Not synchronous,Synchronous"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SCM,PWM Sync Channels Mode Register"
|
|
bitfld.long 0x00 21.--23. " PTRCS ,DMA transfer request comparison selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. " PTRM ,DMA transfer request mode (never requested in chosen synchronous channels update mode)" "Never,Never"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " UPDM ,Synchronous channels update mode (write of duty-cycle update registers/update of synchronous channels)" "Manual/manual,Manual/automatic,Automatic/automatic,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " SYNC3 ,Synchronous channel 3" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 2. " SYNC2 ,Synchronous channel 2" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 1. " SYNC1 ,Synchronous channel 1" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 0. " SYNC0 ,Synchronous channel 0" "Not synchronous,Synchronous"
|
|
endif
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "DMAR,DMA Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " DMADUTY ,Duty-cycle holding register for DMA access"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SCUC,PWM Sync Channels Update Control Register"
|
|
bitfld.long 0x00 0. " UPDULOCK ,Synchronous channels update unlock" "No effect,Updated"
|
|
if ((per.l(ad:0x40020000+0x20)&0x30000)==0x30000)
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "SCUP,PWM Sync Channels Update Period Register"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "SCUPUPD,PWM Sync Channels Update Period Update Register"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SCUP,PWM Sync Channels Update Period Register"
|
|
bitfld.long 0x00 4.--7. " UPRCNT ,Update period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " UPR ,Update period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "SCUPUPD,PWM Sync Channels Update Period Update Register"
|
|
bitfld.long 0x00 0.--3. " UPRUPD ,Update period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "IMR2_SET/CLR,PWM Interrupt Mask Register 2"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " CMPU[7] ,Comparison 7 update interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [6] ,Comparison 6 update interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [5] ,Comparison 5 update interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [4] ,Comparison 4 update interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [3] ,Comparison 3 update interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [2] ,Comparison 2 update interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [1] ,Comparison 1 update interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [0] ,Comparison 0 update interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " CMPM[7] ,Comparison 7 match interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [6] ,Comparison 6 match interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [5] ,Comparison 5 match interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [4] ,Comparison 4 match interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [3] ,Comparison 3 match interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [2] ,Comparison 2 match interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [1] ,Comparison 1 match interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [0] ,Comparison 0 match interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " UNRE ,Synchronous channels update underrun error interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " WRDY ,Write ready for synchronous channels update interrupt" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "ISR2,PWM Interrupt Status Register 2"
|
|
in
|
|
newline
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "OOV,PWM Output Override Value Register"
|
|
bitfld.long 0x00 19. " OOVL[3] ,Output override value for PWML output of the channel 3" "Low,High"
|
|
bitfld.long 0x00 18. " [2] ,Output override value for PWML output of the channel 2" "Low,High"
|
|
bitfld.long 0x00 17. " [1] ,Output override value for PWML output of the channel 1" "Low,High"
|
|
bitfld.long 0x00 16. " [0] ,Output override value for PWML output of the channel 0" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " OOVH[3] ,Output override value for PWMH output of the channel 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Output override value for PWMH output of the channel 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Output override value for PWMH output of the channel 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Output override value for PWMH output of the channel 0" "Low,High"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "OS_SET/CLR,PWM Output Selection Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " OSL[3] ,Output selection for PWML output of the channel 3" "DTOL3,OOVL3"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [2] ,Output selection for PWML output of the channel 2" "DTOL2,OOVL2"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [1] ,Output selection for PWML output of the channel 1" "DTOL1,OOVL1"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [0] ,Output selection for PWML output of the channel 0" "DTOL0,OOVL0"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " OSH[3] ,Output selection for PWMH output of the channel 3" "DTOH3,OOVH3"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Output selection for PWMH output of the channel 2" "DTOH2,OOVH2"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Output selection for PWMH output of the channel 1" "DTOH1,OOVH1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Output selection for PWMH output of the channel 0" "DTOH0,OOVH0"
|
|
wgroup.long 0x54++0x07
|
|
line.long 0x00 "OSSUPD,PWM Output Selection Set Update Register"
|
|
bitfld.long 0x00 19. " OSSUPL[3] ,Output selection set for PWML output of the channel 3" "No effect,OOVL3"
|
|
bitfld.long 0x00 18. " [2] ,Output selection set for PWML output of the channel 2" "No effect,OOVL2"
|
|
bitfld.long 0x00 17. " [1] ,Output selection set for PWML output of the channel 1" "No effect,OOVL1"
|
|
bitfld.long 0x00 16. " [0] ,Output selection set for PWML output of the channel 0" "No effect,OOVL0"
|
|
newline
|
|
bitfld.long 0x00 3. " OSSUPH[3] ,Output selection set for PWMH output of the channel 3" "No effect,OOVH3"
|
|
bitfld.long 0x00 2. " [2] ,Output selection set for PWMH output of the channel 2" "No effect,OOVH2"
|
|
bitfld.long 0x00 1. " [1] ,Output selection set for PWMH output of the channel 1" "No effect,OOVH1"
|
|
bitfld.long 0x00 0. " [0] ,Output selection set for PWMH output of the channel 0" "No effect,OOVH0"
|
|
line.long 0x04 "OSCUPD,PWM Output Selection Clear Update Register"
|
|
bitfld.long 0x04 19. " OSCUPL[3] ,Output selection clear for PWML output of the channel 3" "No effect,DTOL3"
|
|
bitfld.long 0x04 18. " [2] ,Output selection clear for PWML output of the channel 2" "No effect,DTOL2"
|
|
bitfld.long 0x04 17. " [1] ,Output selection clear for PWML output of the channel 1" "No effect,DTOL1"
|
|
bitfld.long 0x04 16. " [0] ,Output selection clear for PWML output of the channel 0" "No effect,DTOL0"
|
|
newline
|
|
bitfld.long 0x04 3. " OSCUPH[3] ,Output selection clear for PWMH output of the channel 3" "No effect,DTOH3"
|
|
bitfld.long 0x04 2. " [2] ,Output selection clear for PWMH output of the channel 2" "No effect,DTOH2"
|
|
bitfld.long 0x04 1. " [1] ,Output selection clear for PWMH output of the channel 1" "No effect,DTOH1"
|
|
bitfld.long 0x04 0. " [0] ,Output selection clear for PWMH output of the channel 0" "No effect,DTOH0"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "FMR,PWM Fault Mode Register"
|
|
bitfld.long 0x00 23. " FFIL[7] ,Fault 7 filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,Fault 6 filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,Fault 5 filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,Fault 4 filtering" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Fault 3 filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,Fault 2 filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,Fault 1 filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,Fault 0 filtering" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " FMOD[7] ,Fault 7 activation mode" "Until removed,Until removed and cleared"
|
|
bitfld.long 0x00 14. " [6] ,Fault 6 activation mode" "Until removed,Until removed and cleared"
|
|
bitfld.long 0x00 13. " [5] ,Fault 5 activation mode" "Until removed,Until removed and cleared"
|
|
bitfld.long 0x00 12. " [4] ,Fault 4 activation mode" "Until removed,Until removed and cleared"
|
|
newline
|
|
bitfld.long 0x00 11. " [3] ,Fault 3 activation mode" "Until removed,Until removed and cleared"
|
|
bitfld.long 0x00 10. " [2] ,Fault 2 activation mode" "Until removed,Until removed and cleared"
|
|
bitfld.long 0x00 9. " [1] ,Fault 1 activation mode" "Until removed,Until removed and cleared"
|
|
bitfld.long 0x00 8. " [0] ,Fault 0 activation mode" "Until removed,Until removed and cleared"
|
|
newline
|
|
bitfld.long 0x00 7. " FPOL[7] ,Fault 7 polarity" "Active-low,Active-high"
|
|
bitfld.long 0x00 6. " [6] ,Fault 6 polarity" "Active-low,Active-high"
|
|
bitfld.long 0x00 5. " [5] ,Fault 5 polarity" "Active-low,Active-high"
|
|
bitfld.long 0x00 4. " [4] ,Fault 4 polarity" "Active-low,Active-high"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Fault 3 polarity" "Active-low,Active-high"
|
|
bitfld.long 0x00 2. " [2] ,Fault 2 polarity" "Active-low,Active-high"
|
|
bitfld.long 0x00 1. " [1] ,Fault 1 polarity" "Active-low,Active-high"
|
|
bitfld.long 0x00 0. " [0] ,Fault 0 polarity" "Active-low,Active-high"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "FSR,PWM Fault Status Register"
|
|
bitfld.long 0x00 15. " FS[7] ,Fault 7 status" "Inactive,Active"
|
|
bitfld.long 0x00 14. " [6] ,Fault 6 status" "Inactive,Active"
|
|
bitfld.long 0x00 13. " [5] ,Fault 5 status" "Inactive,Active"
|
|
bitfld.long 0x00 12. " [4] ,Fault 4 status" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 11. " [3] ,Fault 3 status" "Inactive,Active"
|
|
bitfld.long 0x00 10. " [2] ,Fault 2 status" "Inactive,Active"
|
|
bitfld.long 0x00 9. " [1] ,Fault 1 status" "Inactive,Active"
|
|
bitfld.long 0x00 8. " [0] ,Fault 0 status" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " FIV[7] ,Fault input 7 value" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Fault input 6 value" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Fault input 5 value" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Fault input 4 value" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Fault input 3 value" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Fault input 2 value" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Fault input 1 value" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Fault input 0 value" "Low,High"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "FCR,PWM Fault Clear Register"
|
|
bitfld.long 0x00 7. " FCLR[7] ,Fault 7 clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " [6] ,Fault 6 clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [5] ,Fault 5 clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " [4] ,Fault 4 clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Fault 3 clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Fault 2 clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,Fault 1 clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " [0] ,Fault 0 clear" "No effect,Clear"
|
|
group.long 0x68++0x07
|
|
line.long 0x00 "FPV1,PWM Fault Protection Value Register 1"
|
|
bitfld.long 0x00 19. " FPVL[3] ,Fault protection value for PWML output on channel 3" "Low,High"
|
|
bitfld.long 0x00 18. " [2] ,Fault protection value for PWML output on channel 2" "Low,High"
|
|
bitfld.long 0x00 17. " [1] ,Fault protection value for PWML output on channel 1" "Low,High"
|
|
bitfld.long 0x00 16. " [0] ,Fault protection value for PWML output on channel 0" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " FPVH[3] ,Fault protection value for PWMH output on channel 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Fault protection value for PWMH output on channel 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Fault protection value for PWMH output on channel 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Fault protection value for PWMH output on channel 0" "Low,High"
|
|
line.long 0x04 "FPE,PWM Fault Protection Enable Register"
|
|
bitfld.long 0x04 31. " FPE3[7] ,Fault protection enable with fault 7 for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [6] ,Fault protection enable with fault 6 for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [5] ,Fault protection enable with fault 5 for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [4] ,Fault protection enable with fault 4 for channel 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 27. " [3] ,Fault protection enable with fault 3 for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [2] ,Fault protection enable with fault 2 for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [1] ,Fault protection enable with fault 1 for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [0] ,Fault protection enable with fault 0 for channel 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 23. " FPE2[7] ,Fault protection enable with fault 7 for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [6] ,Fault protection enable with fault 6 for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [5] ,Fault protection enable with fault 5 for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [4] ,Fault protection enable with fault 4 for channel 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " [3] ,Fault protection enable with fault 3 for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [2] ,Fault protection enable with fault 2 for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [1] ,Fault protection enable with fault 1 for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [0] ,Fault protection enable with fault 0 for channel 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " FPE1[7] ,Fault protection enable with fault 7 for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [6] ,Fault protection enable with fault 6 for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [5] ,Fault protection enable with fault 5 for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [4] ,Fault protection enable with fault 4 for channel 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [3] ,Fault protection enable with fault 3 for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [2] ,Fault protection enable with fault 2 for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [1] ,Fault protection enable with fault 1 for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [0] ,Fault protection enable with fault 0 for channel 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " FPE0[7] ,Fault protection enable with fault 7 for channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [6] ,Fault protection enable with fault 6 for channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [5] ,Fault protection enable with fault 5 for channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [4] ,Fault protection enable with fault 4 for channel 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Fault protection enable with fault 3 for channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,Fault protection enable with fault 2 for channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [1] ,Fault protection enable with fault 1 for channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [0] ,Fault protection enable with fault 0 for channel 0" "Disabled,Enabled"
|
|
sif cpuis("ATSAMS7*")||cpuis("ATSAME7*")
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "ELMR0,PWM Event Line 0 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ELMR1,PWM Event Line 1 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "ELMR0,PWM Event Line 0 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ELMR1,PWM Event Line 1 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "ELMR2,PWM Event Line 2 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "ELMR3,PWM Event Line 3 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "ELMR4,PWM Event Line 4 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "ELMR5,PWM Event Line 5 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "ELMR6,PWM Event Line 6 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "ELMR7,PWM Event Line 7 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SSPR,Spread Spectrum Register"
|
|
bitfld.long 0x00 24. " SPRDM ,Spread spectrum counter mode" "Triangular,Random"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPRD ,Spread spectrum limit value"
|
|
wgroup.long 0xA4++0x03
|
|
line.long 0x00 "SSPUP,PWM Spread Spectrum Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPRDUP ,Spread spectrum limit value update"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "SMMR,PWM Stepper Motor Mode Register"
|
|
bitfld.long 0x00 17. " DOWN1 ,Down count 1" "Up,Down"
|
|
bitfld.long 0x00 16. " DOWN0 ,Down count 0" "Up,Down"
|
|
bitfld.long 0x00 1. " GCEN1 ,Gray count 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GCEN0 ,Gray count 0 enable" "Disabled,Enabled"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FPV2,Fault Protection Value Register 2"
|
|
bitfld.long 0x00 19. " FPZL[3] ,Fault protection to Hi-Z for PWML output on channel 3" "FPVL3,High impedance"
|
|
bitfld.long 0x00 18. " [2] ,Fault protection to Hi-Z for PWML output on channel 2" "FPVL2,High impedance"
|
|
bitfld.long 0x00 17. " [1] ,Fault protection to Hi-Z for PWML output on channel 1" "FPVL1,High impedance"
|
|
bitfld.long 0x00 16. " [0] ,Fault protection to Hi-Z for PWML output on channel 0" "FPVL0,High impedance"
|
|
newline
|
|
bitfld.long 0x00 3. " FPZH[3] ,Fault protection to Hi-Z for PWMH output on channel 3" "FPVH3,High impedance"
|
|
bitfld.long 0x00 2. " [2] ,Fault protection to Hi-Z for PWMH output on channel 2" "FPVH2,High impedance"
|
|
bitfld.long 0x00 1. " [1] ,Fault protection to Hi-Z for PWMH output on channel 1" "FPVH1,High impedance"
|
|
bitfld.long 0x00 0. " [0] ,Fault protection to Hi-Z for PWMH output on channel 0" "FPVH0,High impedance"
|
|
wgroup.long 0xE4++0x03
|
|
line.long 0x00 "WPCR,PWM Write Protect Control Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect key"
|
|
bitfld.long 0x00 7. " WPRG[5] ,Write protect register group 5" "Disable,Enable"
|
|
bitfld.long 0x00 6. " [4] ,Write protect register group 4" "Disable,Enable"
|
|
bitfld.long 0x00 5. " [3] ,Write protect register group 3" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 4. " [2] ,Write protect register group 2" "Disable,Enable"
|
|
bitfld.long 0x00 3. " [1] ,Write protect register group 1" "Disable,Enable"
|
|
bitfld.long 0x00 2. " [0] ,Write protect register group 0" "Disable,Enable"
|
|
bitfld.long 0x00 0.--1. " WPCMD ,Write protect command" "DISABLE_SW_PROT,ENABLE_SW_PROT,ENABLE_HW_PROT,?..."
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,PWM Write Protect Status Register"
|
|
in
|
|
tree.end
|
|
width 10.
|
|
tree "Comparison Registers"
|
|
if (((per.l(ad:0x40020000+0x200))&0x100)==0x100)
|
|
group.long (0x130+0x0)++0x03 "Comparison 0"
|
|
line.long 0x00 "CMPV0,PWM Comparison 0 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 0 value mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 0 value"
|
|
wgroup.long (0x134+0x0)++0x03
|
|
line.long 0x00 "CMPVUPD0,Comparison 0 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 0 value mode update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 0 value update"
|
|
else
|
|
group.long (0x130+0x0)++0x03 "Comparison 0"
|
|
line.long 0x00 "CMPV0,PWM Comparison 0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 0 value"
|
|
wgroup.long (0x134+0x0)++0x03
|
|
line.long 0x00 "CMPVUPD0,Comparison 0 Value Update"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 0 value update"
|
|
endif
|
|
group.long (0x138+0x0)++0x03
|
|
line.long 0x00 "CMPM0,PWM Comparison 0 Mode Register"
|
|
rbitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 0 update period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 0 update period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 0 period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 0 period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 0 trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 0 enable" "Disabled,Enabled"
|
|
wgroup.long (0x13C+0x0)++0x03
|
|
line.long 0x00 "CMPMUPD0,PWM Comparison 0 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 0 update period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 0 period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 0 trigger update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 0 enable update" "Disable,Enable"
|
|
if (((per.l(ad:0x40020000+0x200))&0x100)==0x100)
|
|
group.long (0x130+0x10)++0x03 "Comparison 1"
|
|
line.long 0x00 "CMPV1,PWM Comparison 1 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 1 value mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 1 value"
|
|
wgroup.long (0x134+0x10)++0x03
|
|
line.long 0x00 "CMPVUPD1,Comparison 1 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 1 value mode update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 1 value update"
|
|
else
|
|
group.long (0x130+0x10)++0x03 "Comparison 1"
|
|
line.long 0x00 "CMPV1,PWM Comparison 1 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 1 value"
|
|
wgroup.long (0x134+0x10)++0x03
|
|
line.long 0x00 "CMPVUPD1,Comparison 1 Value Update"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 1 value update"
|
|
endif
|
|
group.long (0x138+0x10)++0x03
|
|
line.long 0x00 "CMPM1,PWM Comparison 1 Mode Register"
|
|
rbitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 1 update period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 1 update period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 1 period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 1 period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 1 trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 1 enable" "Disabled,Enabled"
|
|
wgroup.long (0x13C+0x10)++0x03
|
|
line.long 0x00 "CMPMUPD1,PWM Comparison 1 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 1 update period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 1 period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 1 trigger update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 1 enable update" "Disable,Enable"
|
|
if (((per.l(ad:0x40020000+0x200))&0x100)==0x100)
|
|
group.long (0x130+0x20)++0x03 "Comparison 2"
|
|
line.long 0x00 "CMPV2,PWM Comparison 2 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 2 value mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 2 value"
|
|
wgroup.long (0x134+0x20)++0x03
|
|
line.long 0x00 "CMPVUPD2,Comparison 2 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 2 value mode update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 2 value update"
|
|
else
|
|
group.long (0x130+0x20)++0x03 "Comparison 2"
|
|
line.long 0x00 "CMPV2,PWM Comparison 2 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 2 value"
|
|
wgroup.long (0x134+0x20)++0x03
|
|
line.long 0x00 "CMPVUPD2,Comparison 2 Value Update"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 2 value update"
|
|
endif
|
|
group.long (0x138+0x20)++0x03
|
|
line.long 0x00 "CMPM2,PWM Comparison 2 Mode Register"
|
|
rbitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 2 update period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 2 update period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 2 period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 2 period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 2 trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 2 enable" "Disabled,Enabled"
|
|
wgroup.long (0x13C+0x20)++0x03
|
|
line.long 0x00 "CMPMUPD2,PWM Comparison 2 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 2 update period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 2 period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 2 trigger update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 2 enable update" "Disable,Enable"
|
|
if (((per.l(ad:0x40020000+0x200))&0x100)==0x100)
|
|
group.long (0x130+0x30)++0x03 "Comparison 3"
|
|
line.long 0x00 "CMPV3,PWM Comparison 3 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 3 value mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 3 value"
|
|
wgroup.long (0x134+0x30)++0x03
|
|
line.long 0x00 "CMPVUPD3,Comparison 3 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 3 value mode update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 3 value update"
|
|
else
|
|
group.long (0x130+0x30)++0x03 "Comparison 3"
|
|
line.long 0x00 "CMPV3,PWM Comparison 3 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 3 value"
|
|
wgroup.long (0x134+0x30)++0x03
|
|
line.long 0x00 "CMPVUPD3,Comparison 3 Value Update"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 3 value update"
|
|
endif
|
|
group.long (0x138+0x30)++0x03
|
|
line.long 0x00 "CMPM3,PWM Comparison 3 Mode Register"
|
|
rbitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 3 update period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 3 update period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 3 period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 3 period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 3 trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 3 enable" "Disabled,Enabled"
|
|
wgroup.long (0x13C+0x30)++0x03
|
|
line.long 0x00 "CMPMUPD3,PWM Comparison 3 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 3 update period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 3 period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 3 trigger update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 3 enable update" "Disable,Enable"
|
|
if (((per.l(ad:0x40020000+0x200))&0x100)==0x100)
|
|
group.long (0x130+0x40)++0x03 "Comparison 4"
|
|
line.long 0x00 "CMPV4,PWM Comparison 4 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 4 value mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 4 value"
|
|
wgroup.long (0x134+0x40)++0x03
|
|
line.long 0x00 "CMPVUPD4,Comparison 4 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 4 value mode update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 4 value update"
|
|
else
|
|
group.long (0x130+0x40)++0x03 "Comparison 4"
|
|
line.long 0x00 "CMPV4,PWM Comparison 4 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 4 value"
|
|
wgroup.long (0x134+0x40)++0x03
|
|
line.long 0x00 "CMPVUPD4,Comparison 4 Value Update"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 4 value update"
|
|
endif
|
|
group.long (0x138+0x40)++0x03
|
|
line.long 0x00 "CMPM4,PWM Comparison 4 Mode Register"
|
|
rbitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 4 update period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 4 update period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 4 period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 4 period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 4 trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 4 enable" "Disabled,Enabled"
|
|
wgroup.long (0x13C+0x40)++0x03
|
|
line.long 0x00 "CMPMUPD4,PWM Comparison 4 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 4 update period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 4 period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 4 trigger update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 4 enable update" "Disable,Enable"
|
|
if (((per.l(ad:0x40020000+0x200))&0x100)==0x100)
|
|
group.long (0x130+0x50)++0x03 "Comparison 5"
|
|
line.long 0x00 "CMPV5,PWM Comparison 5 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 5 value mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 5 value"
|
|
wgroup.long (0x134+0x50)++0x03
|
|
line.long 0x00 "CMPVUPD5,Comparison 5 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 5 value mode update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 5 value update"
|
|
else
|
|
group.long (0x130+0x50)++0x03 "Comparison 5"
|
|
line.long 0x00 "CMPV5,PWM Comparison 5 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 5 value"
|
|
wgroup.long (0x134+0x50)++0x03
|
|
line.long 0x00 "CMPVUPD5,Comparison 5 Value Update"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 5 value update"
|
|
endif
|
|
group.long (0x138+0x50)++0x03
|
|
line.long 0x00 "CMPM5,PWM Comparison 5 Mode Register"
|
|
rbitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 5 update period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 5 update period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 5 period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 5 period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 5 trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 5 enable" "Disabled,Enabled"
|
|
wgroup.long (0x13C+0x50)++0x03
|
|
line.long 0x00 "CMPMUPD5,PWM Comparison 5 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 5 update period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 5 period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 5 trigger update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 5 enable update" "Disable,Enable"
|
|
if (((per.l(ad:0x40020000+0x200))&0x100)==0x100)
|
|
group.long (0x130+0x60)++0x03 "Comparison 6"
|
|
line.long 0x00 "CMPV6,PWM Comparison 6 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 6 value mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 6 value"
|
|
wgroup.long (0x134+0x60)++0x03
|
|
line.long 0x00 "CMPVUPD6,Comparison 6 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 6 value mode update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 6 value update"
|
|
else
|
|
group.long (0x130+0x60)++0x03 "Comparison 6"
|
|
line.long 0x00 "CMPV6,PWM Comparison 6 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 6 value"
|
|
wgroup.long (0x134+0x60)++0x03
|
|
line.long 0x00 "CMPVUPD6,Comparison 6 Value Update"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 6 value update"
|
|
endif
|
|
group.long (0x138+0x60)++0x03
|
|
line.long 0x00 "CMPM6,PWM Comparison 6 Mode Register"
|
|
rbitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 6 update period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 6 update period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 6 period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 6 period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 6 trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 6 enable" "Disabled,Enabled"
|
|
wgroup.long (0x13C+0x60)++0x03
|
|
line.long 0x00 "CMPMUPD6,PWM Comparison 6 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 6 update period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 6 period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 6 trigger update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 6 enable update" "Disable,Enable"
|
|
if (((per.l(ad:0x40020000+0x200))&0x100)==0x100)
|
|
group.long (0x130+0x70)++0x03 "Comparison 7"
|
|
line.long 0x00 "CMPV7,PWM Comparison 7 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 7 value mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 7 value"
|
|
wgroup.long (0x134+0x70)++0x03
|
|
line.long 0x00 "CMPVUPD7,Comparison 7 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 7 value mode update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 7 value update"
|
|
else
|
|
group.long (0x130+0x70)++0x03 "Comparison 7"
|
|
line.long 0x00 "CMPV7,PWM Comparison 7 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 7 value"
|
|
wgroup.long (0x134+0x70)++0x03
|
|
line.long 0x00 "CMPVUPD7,Comparison 7 Value Update"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 7 value update"
|
|
endif
|
|
group.long (0x138+0x70)++0x03
|
|
line.long 0x00 "CMPM7,PWM Comparison 7 Mode Register"
|
|
rbitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 7 update period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 7 update period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 7 period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 7 period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 7 trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 7 enable" "Disabled,Enabled"
|
|
wgroup.long (0x13C+0x70)++0x03
|
|
line.long 0x00 "CMPMUPD7,PWM Comparison 7 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 7 update period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 7 period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 7 trigger update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 7 enable update" "Disable,Enable"
|
|
tree.end
|
|
tree "Channel 0"
|
|
if (((per.l(ad:0x40020000+0x200+0x0))&0x100)==0x100)
|
|
group.long (0x200+0x0)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 19. " PPM ,Push-pull mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-time PWML0 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-time PWMH0 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " DTE ,Dead-time generator enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " TCTS ,Timer counter trigger selection" "Comparator,Counter"
|
|
bitfld.long 0x00 12. " DPOLI ,Disabled polarity inverted" "Same as CPOL,Inverted to CPOL"
|
|
bitfld.long 0x00 11. " UPDS ,Update selection (at the end of [one/half] period after writing the update register)" "One period,Half period"
|
|
bitfld.long 0x00 10. " CES ,Counter event selection (at the end/at the end or at half period after writing the update register)" "End,Half and end"
|
|
newline
|
|
bitfld.long 0x00 9. " CPOL ,Channel polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel pre-scaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0x0)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 19. " PPM ,Push-pull mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-time PWML0 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-time PWMH0 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " DTE ,Dead-time generator enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " TCTS ,Timer counter trigger selection" "Comparator,Counter"
|
|
bitfld.long 0x00 12. " DPOLI ,Disabled polarity inverted" "Same as CPOL,Inverted to CPOL"
|
|
bitfld.long 0x00 11. " UPDS ,Update selection (at the end of [one/half] period after writing the update register)" "One period,One period"
|
|
bitfld.long 0x00 10. " CES ,Counter event selection (at the end/at the end or at half period after writing the update register)" "End,End"
|
|
newline
|
|
bitfld.long 0x00 9. " CPOL ,Channel polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel pre-scaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0x0)++0x03
|
|
line.long 0x00 "CDTY0,PWM Channel 0 Duty Cycle Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel duty-cycle"
|
|
wgroup.long (0x208+0x0)++0x03
|
|
line.long 0x00 "CDTYUPD0,PWM Channel 0 Duty Cycle Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel duty-cycle update"
|
|
group.long (0x20C+0x0)++0x03
|
|
line.long 0x00 "CPRD0,PWM Channel 0 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel period"
|
|
wgroup.long (0x210+0x0)++0x03
|
|
line.long 0x00 "CPRDUPD0,Channel 0 Period Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRDUPD ,Channel period update"
|
|
rgroup.long (0x214+0x0)++0x03
|
|
line.long 0x00 "CCNT0,PWM Channel 0 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Channel counter value"
|
|
group.long (0x218+0x0)++0x03
|
|
line.long 0x00 "DT0,PWM Channel 0 Dead Time Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DTL ,Dead-time value for PWML0 output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTH ,Dead-time value for PWMH0 output"
|
|
wgroup.long (0x21C+0x0)++0x03
|
|
line.long 0x00 "DTUPD0,PWM Channel 0 Dead Time Update Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DTLUPD ,Dead-time value update for PWML0 output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTHUPD ,Dead-time value update for PWMH0 output"
|
|
group.long (0x400+0x0)++0x03
|
|
line.long 0x00 "CMUPD0,PWM Channel Mode Update Register"
|
|
bitfld.long 0x00 13. " CPOLINVUP ,Channel polarity inversion update" "No effect,Inverted"
|
|
bitfld.long 0x00 9. " CPOLUP ,Channel polarity update" "Low level,High level"
|
|
newline
|
|
sif cpuis("ATSAMS7*")
|
|
hgroup.long (0x42C+0x0)++0x03
|
|
hide.long 0x00 "ETRG1,PWM External Trigger 1 Register"
|
|
in
|
|
newline
|
|
group.long (0x430+0x0)++0x03
|
|
line.long 0x00 "LEBR1,PWM External Trigger 1 Register"
|
|
bitfld.long 0x00 19. " PWMHREN ,PWMH rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PWMHFEN ,PWMH falling edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMLREN ,PWML rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMLFEN ,PWML falling edge enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " LEBDELAY ,Leading-edge blanking delay for TRGIN1"
|
|
else
|
|
hgroup.long (0x42C+0x0)++0x03
|
|
hide.long 0x00 "ETRG1,PWM External Trigger 1 Register"
|
|
in
|
|
newline
|
|
group.long (0x430+0x0)++0x03
|
|
line.long 0x00 "LEBR1,PWM External Trigger 1 Register"
|
|
bitfld.long 0x00 19. " PWMHREN ,PWMH rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PWMHFEN ,PWMH falling edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMLREN ,PWML rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMLFEN ,PWML falling edge enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
tree "Channel 1"
|
|
if (((per.l(ad:0x40020000+0x200+0x20))&0x100)==0x100)
|
|
group.long (0x200+0x20)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 19. " PPM ,Push-pull mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-time PWML1 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-time PWMH1 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " DTE ,Dead-time generator enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " TCTS ,Timer counter trigger selection" "Comparator,Counter"
|
|
bitfld.long 0x00 12. " DPOLI ,Disabled polarity inverted" "Same as CPOL,Inverted to CPOL"
|
|
bitfld.long 0x00 11. " UPDS ,Update selection (at the end of [one/half] period after writing the update register)" "One period,Half period"
|
|
bitfld.long 0x00 10. " CES ,Counter event selection (at the end/at the end or at half period after writing the update register)" "End,Half and end"
|
|
newline
|
|
bitfld.long 0x00 9. " CPOL ,Channel polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel pre-scaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0x20)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 19. " PPM ,Push-pull mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-time PWML1 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-time PWMH1 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " DTE ,Dead-time generator enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " TCTS ,Timer counter trigger selection" "Comparator,Counter"
|
|
bitfld.long 0x00 12. " DPOLI ,Disabled polarity inverted" "Same as CPOL,Inverted to CPOL"
|
|
bitfld.long 0x00 11. " UPDS ,Update selection (at the end of [one/half] period after writing the update register)" "One period,One period"
|
|
bitfld.long 0x00 10. " CES ,Counter event selection (at the end/at the end or at half period after writing the update register)" "End,End"
|
|
newline
|
|
bitfld.long 0x00 9. " CPOL ,Channel polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel pre-scaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0x20)++0x03
|
|
line.long 0x00 "CDTY1,PWM Channel 1 Duty Cycle Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel duty-cycle"
|
|
wgroup.long (0x208+0x20)++0x03
|
|
line.long 0x00 "CDTYUPD1,PWM Channel 1 Duty Cycle Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel duty-cycle update"
|
|
group.long (0x20C+0x20)++0x03
|
|
line.long 0x00 "CPRD1,PWM Channel 1 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel period"
|
|
wgroup.long (0x210+0x20)++0x03
|
|
line.long 0x00 "CPRDUPD1,Channel 1 Period Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRDUPD ,Channel period update"
|
|
rgroup.long (0x214+0x20)++0x03
|
|
line.long 0x00 "CCNT1,PWM Channel 1 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Channel counter value"
|
|
group.long (0x218+0x20)++0x03
|
|
line.long 0x00 "DT1,PWM Channel 1 Dead Time Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DTL ,Dead-time value for PWML1 output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTH ,Dead-time value for PWMH1 output"
|
|
wgroup.long (0x21C+0x20)++0x03
|
|
line.long 0x00 "DTUPD1,PWM Channel 1 Dead Time Update Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DTLUPD ,Dead-time value update for PWML1 output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTHUPD ,Dead-time value update for PWMH1 output"
|
|
group.long (0x400+0x20)++0x03
|
|
line.long 0x00 "CMUPD1,PWM Channel Mode Update Register"
|
|
bitfld.long 0x00 13. " CPOLINVUP ,Channel polarity inversion update" "No effect,Inverted"
|
|
bitfld.long 0x00 9. " CPOLUP ,Channel polarity update" "Low level,High level"
|
|
newline
|
|
sif cpuis("ATSAMS7*")
|
|
hgroup.long (0x42C+0x20)++0x03
|
|
hide.long 0x00 "ETRG2,PWM External Trigger 2 Register"
|
|
in
|
|
newline
|
|
group.long (0x430+0x20)++0x03
|
|
line.long 0x00 "LEBR2,PWM External Trigger 2 Register"
|
|
bitfld.long 0x00 19. " PWMHREN ,PWMH rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PWMHFEN ,PWMH falling edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMLREN ,PWML rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMLFEN ,PWML falling edge enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " LEBDELAY ,Leading-edge blanking delay for TRGIN2"
|
|
else
|
|
hgroup.long (0x42C+0x20)++0x03
|
|
hide.long 0x00 "ETRG2,PWM External Trigger 2 Register"
|
|
in
|
|
newline
|
|
group.long (0x430+0x20)++0x03
|
|
line.long 0x00 "LEBR2,PWM External Trigger 2 Register"
|
|
bitfld.long 0x00 19. " PWMHREN ,PWMH rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PWMHFEN ,PWMH falling edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMLREN ,PWML rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMLFEN ,PWML falling edge enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
tree "Channel 2"
|
|
if (((per.l(ad:0x40020000+0x200+0x40))&0x100)==0x100)
|
|
group.long (0x200+0x40)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 19. " PPM ,Push-pull mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-time PWML2 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-time PWMH2 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " DTE ,Dead-time generator enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " TCTS ,Timer counter trigger selection" "Comparator,Counter"
|
|
bitfld.long 0x00 12. " DPOLI ,Disabled polarity inverted" "Same as CPOL,Inverted to CPOL"
|
|
bitfld.long 0x00 11. " UPDS ,Update selection (at the end of [one/half] period after writing the update register)" "One period,Half period"
|
|
bitfld.long 0x00 10. " CES ,Counter event selection (at the end/at the end or at half period after writing the update register)" "End,Half and end"
|
|
newline
|
|
bitfld.long 0x00 9. " CPOL ,Channel polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel pre-scaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0x40)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 19. " PPM ,Push-pull mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-time PWML2 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-time PWMH2 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " DTE ,Dead-time generator enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " TCTS ,Timer counter trigger selection" "Comparator,Counter"
|
|
bitfld.long 0x00 12. " DPOLI ,Disabled polarity inverted" "Same as CPOL,Inverted to CPOL"
|
|
bitfld.long 0x00 11. " UPDS ,Update selection (at the end of [one/half] period after writing the update register)" "One period,One period"
|
|
bitfld.long 0x00 10. " CES ,Counter event selection (at the end/at the end or at half period after writing the update register)" "End,End"
|
|
newline
|
|
bitfld.long 0x00 9. " CPOL ,Channel polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel pre-scaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0x40)++0x03
|
|
line.long 0x00 "CDTY2,PWM Channel 2 Duty Cycle Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel duty-cycle"
|
|
wgroup.long (0x208+0x40)++0x03
|
|
line.long 0x00 "CDTYUPD2,PWM Channel 2 Duty Cycle Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel duty-cycle update"
|
|
group.long (0x20C+0x40)++0x03
|
|
line.long 0x00 "CPRD2,PWM Channel 2 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel period"
|
|
wgroup.long (0x210+0x40)++0x03
|
|
line.long 0x00 "CPRDUPD2,Channel 2 Period Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRDUPD ,Channel period update"
|
|
rgroup.long (0x214+0x40)++0x03
|
|
line.long 0x00 "CCNT2,PWM Channel 2 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Channel counter value"
|
|
group.long (0x218+0x40)++0x03
|
|
line.long 0x00 "DT2,PWM Channel 2 Dead Time Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DTL ,Dead-time value for PWML2 output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTH ,Dead-time value for PWMH2 output"
|
|
wgroup.long (0x21C+0x40)++0x03
|
|
line.long 0x00 "DTUPD2,PWM Channel 2 Dead Time Update Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DTLUPD ,Dead-time value update for PWML2 output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTHUPD ,Dead-time value update for PWMH2 output"
|
|
group.long (0x400+0x40)++0x03
|
|
line.long 0x00 "CMUPD2,PWM Channel Mode Update Register"
|
|
bitfld.long 0x00 13. " CPOLINVUP ,Channel polarity inversion update" "No effect,Inverted"
|
|
bitfld.long 0x00 9. " CPOLUP ,Channel polarity update" "Low level,High level"
|
|
newline
|
|
sif cpuis("ATSAMS7*")
|
|
else
|
|
hgroup.long (0x42C+0x40)++0x03
|
|
hide.long 0x00 "ETRG3,PWM External Trigger 3 Register"
|
|
in
|
|
newline
|
|
group.long (0x430+0x40)++0x03
|
|
line.long 0x00 "LEBR3,PWM External Trigger 3 Register"
|
|
bitfld.long 0x00 19. " PWMHREN ,PWMH rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PWMHFEN ,PWMH falling edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMLREN ,PWML rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMLFEN ,PWML falling edge enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
tree "Channel 3"
|
|
if (((per.l(ad:0x40020000+0x200+0x60))&0x100)==0x100)
|
|
group.long (0x200+0x60)++0x03
|
|
line.long 0x00 "CMR3,Channel 3 Mode Register"
|
|
bitfld.long 0x00 19. " PPM ,Push-pull mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-time PWML3 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-time PWMH3 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " DTE ,Dead-time generator enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " TCTS ,Timer counter trigger selection" "Comparator,Counter"
|
|
bitfld.long 0x00 12. " DPOLI ,Disabled polarity inverted" "Same as CPOL,Inverted to CPOL"
|
|
bitfld.long 0x00 11. " UPDS ,Update selection (at the end of [one/half] period after writing the update register)" "One period,Half period"
|
|
bitfld.long 0x00 10. " CES ,Counter event selection (at the end/at the end or at half period after writing the update register)" "End,Half and end"
|
|
newline
|
|
bitfld.long 0x00 9. " CPOL ,Channel polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel pre-scaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0x60)++0x03
|
|
line.long 0x00 "CMR3,Channel 3 Mode Register"
|
|
bitfld.long 0x00 19. " PPM ,Push-pull mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-time PWML3 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-time PWMH3 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " DTE ,Dead-time generator enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " TCTS ,Timer counter trigger selection" "Comparator,Counter"
|
|
bitfld.long 0x00 12. " DPOLI ,Disabled polarity inverted" "Same as CPOL,Inverted to CPOL"
|
|
bitfld.long 0x00 11. " UPDS ,Update selection (at the end of [one/half] period after writing the update register)" "One period,One period"
|
|
bitfld.long 0x00 10. " CES ,Counter event selection (at the end/at the end or at half period after writing the update register)" "End,End"
|
|
newline
|
|
bitfld.long 0x00 9. " CPOL ,Channel polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel pre-scaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0x60)++0x03
|
|
line.long 0x00 "CDTY3,PWM Channel 3 Duty Cycle Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel duty-cycle"
|
|
wgroup.long (0x208+0x60)++0x03
|
|
line.long 0x00 "CDTYUPD3,PWM Channel 3 Duty Cycle Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel duty-cycle update"
|
|
group.long (0x20C+0x60)++0x03
|
|
line.long 0x00 "CPRD3,PWM Channel 3 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel period"
|
|
wgroup.long (0x210+0x60)++0x03
|
|
line.long 0x00 "CPRDUPD3,Channel 3 Period Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRDUPD ,Channel period update"
|
|
rgroup.long (0x214+0x60)++0x03
|
|
line.long 0x00 "CCNT3,PWM Channel 3 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Channel counter value"
|
|
group.long (0x218+0x60)++0x03
|
|
line.long 0x00 "DT3,PWM Channel 3 Dead Time Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DTL ,Dead-time value for PWML3 output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTH ,Dead-time value for PWMH3 output"
|
|
wgroup.long (0x21C+0x60)++0x03
|
|
line.long 0x00 "DTUPD3,PWM Channel 3 Dead Time Update Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DTLUPD ,Dead-time value update for PWML3 output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTHUPD ,Dead-time value update for PWMH3 output"
|
|
group.long (0x400+0x60)++0x03
|
|
line.long 0x00 "CMUPD3,PWM Channel Mode Update Register"
|
|
bitfld.long 0x00 13. " CPOLINVUP ,Channel polarity inversion update" "No effect,Inverted"
|
|
bitfld.long 0x00 9. " CPOLUP ,Channel polarity update" "Low level,High level"
|
|
newline
|
|
sif cpuis("ATSAMS7*")
|
|
else
|
|
hgroup.long (0x42C+0x60)++0x03
|
|
hide.long 0x00 "ETRG4,PWM External Trigger 4 Register"
|
|
in
|
|
newline
|
|
group.long (0x430+0x60)++0x03
|
|
line.long 0x00 "LEBR4,PWM External Trigger 4 Register"
|
|
bitfld.long 0x00 19. " PWMHREN ,PWMH rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PWMHFEN ,PWMH falling edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMLREN ,PWML rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMLFEN ,PWML falling edge enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "PWM1"
|
|
base ad:0x4005C000
|
|
width 14.
|
|
tree "Common Registers"
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CLK,PWM Clock Register"
|
|
bitfld.long 0x00 24.--27. " PREB ,Divider input clock" "CLK/1,CLK/2,CLK/4,CLK/8,CLK/16,CLK/32,CLK/64,CLK/128,CLK/256,CLK/512,CLK/1024,?..."
|
|
hexmask.long.byte 0x00 16.--23. 1. " DIVB ,CLKB divide factor"
|
|
bitfld.long 0x00 8.--11. " PREA ,Divider input clock" "CLK/1,CLK/2,CLK/4,CLK/8,CLK/16,CLK/32,CLK/64,CLK/128,CLK/256,CLK/512,CLK/1024,?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " DIVA ,CLKA divide factor"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SR_SET/CLR,PWM Status Set/Clear Register"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CHID3 ,PWM output for channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CHID2 ,PWM output for channel 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " CHID1 ,PWM output for channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CHID0 ,PWM output for channel 0" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IMR1_SET/CLR,PWM Interrupt Mask Set/Clear Register 1"
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " FCHID3 ,Fault protection trigger on channel 3 interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " FCHID2 ,Fault protection trigger on channel 2 interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " FCHID1 ,Fault protection trigger on channel 1 interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " FCHID0 ,Fault protection trigger on channel 0 interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " CHID3 ,Counter event on channel 3 interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " CHID2 ,Counter event on channel 2 interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " CHID1 ,Counter event on channel 1 interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CHID0 ,Counter event on channel 0 interrupt" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "ISR1,PWM Interrupt Status Register 1"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x4005C000+0x20)&0x30000)==0x20000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SCM,PWM Sync Channels Mode Register"
|
|
bitfld.long 0x00 21.--23. " PTRCS ,DMA transfer request comparison selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. " PTRM ,DMA transfer request mode" "At update period end,At comparison match"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " UPDM ,Synchronous channels update mode (write of duty-cycle update registers/update of synchronous channels)" "Manual/manual,Manual/automatic,Automatic/automatic,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " SYNC3 ,Synchronous channel 3" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 2. " SYNC2 ,Synchronous channel 2" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 1. " SYNC1 ,Synchronous channel 1" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 0. " SYNC0 ,Synchronous channel 0" "Not synchronous,Synchronous"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SCM,PWM Sync Channels Mode Register"
|
|
bitfld.long 0x00 21.--23. " PTRCS ,DMA transfer request comparison selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 20. " PTRM ,DMA transfer request mode (never requested in chosen synchronous channels update mode)" "Never,Never"
|
|
newline
|
|
bitfld.long 0x00 16.--17. " UPDM ,Synchronous channels update mode (write of duty-cycle update registers/update of synchronous channels)" "Manual/manual,Manual/automatic,Automatic/automatic,?..."
|
|
newline
|
|
bitfld.long 0x00 3. " SYNC3 ,Synchronous channel 3" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 2. " SYNC2 ,Synchronous channel 2" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 1. " SYNC1 ,Synchronous channel 1" "Not synchronous,Synchronous"
|
|
bitfld.long 0x00 0. " SYNC0 ,Synchronous channel 0" "Not synchronous,Synchronous"
|
|
endif
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "DMAR,DMA Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " DMADUTY ,Duty-cycle holding register for DMA access"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SCUC,PWM Sync Channels Update Control Register"
|
|
bitfld.long 0x00 0. " UPDULOCK ,Synchronous channels update unlock" "No effect,Updated"
|
|
if ((per.l(ad:0x4005C000+0x20)&0x30000)==0x30000)
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "SCUP,PWM Sync Channels Update Period Register"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "SCUPUPD,PWM Sync Channels Update Period Update Register"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SCUP,PWM Sync Channels Update Period Register"
|
|
bitfld.long 0x00 4.--7. " UPRCNT ,Update period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " UPR ,Update period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "SCUPUPD,PWM Sync Channels Update Period Update Register"
|
|
bitfld.long 0x00 0.--3. " UPRUPD ,Update period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "IMR2_SET/CLR,PWM Interrupt Mask Register 2"
|
|
setclrfld.long 0x00 23. -0x08 23. -0x04 23. " CMPU[7] ,Comparison 7 update interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 22. -0x08 22. -0x04 22. " [6] ,Comparison 6 update interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 21. -0x08 21. -0x04 21. " [5] ,Comparison 5 update interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 20. -0x08 20. -0x04 20. " [4] ,Comparison 4 update interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x08 19. -0x04 19. " [3] ,Comparison 3 update interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " [2] ,Comparison 2 update interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " [1] ,Comparison 1 update interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " [0] ,Comparison 0 update interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 15. -0x08 15. -0x04 15. " CMPM[7] ,Comparison 7 match interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 14. -0x08 14. -0x04 14. " [6] ,Comparison 6 match interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " [5] ,Comparison 5 match interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " [4] ,Comparison 4 match interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " [3] ,Comparison 3 match interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [2] ,Comparison 2 match interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [1] ,Comparison 1 match interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [0] ,Comparison 0 match interrupt" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " UNRE ,Synchronous channels update underrun error interrupt" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " WRDY ,Write ready for synchronous channels update interrupt" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "ISR2,PWM Interrupt Status Register 2"
|
|
in
|
|
newline
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "OOV,PWM Output Override Value Register"
|
|
bitfld.long 0x00 19. " OOVL[3] ,Output override value for PWML output of the channel 3" "Low,High"
|
|
bitfld.long 0x00 18. " [2] ,Output override value for PWML output of the channel 2" "Low,High"
|
|
bitfld.long 0x00 17. " [1] ,Output override value for PWML output of the channel 1" "Low,High"
|
|
bitfld.long 0x00 16. " [0] ,Output override value for PWML output of the channel 0" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " OOVH[3] ,Output override value for PWMH output of the channel 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Output override value for PWMH output of the channel 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Output override value for PWMH output of the channel 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Output override value for PWMH output of the channel 0" "Low,High"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "OS_SET/CLR,PWM Output Selection Register"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " OSL[3] ,Output selection for PWML output of the channel 3" "DTOL3,OOVL3"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [2] ,Output selection for PWML output of the channel 2" "DTOL2,OOVL2"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [1] ,Output selection for PWML output of the channel 1" "DTOL1,OOVL1"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [0] ,Output selection for PWML output of the channel 0" "DTOL0,OOVL0"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " OSH[3] ,Output selection for PWMH output of the channel 3" "DTOH3,OOVH3"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,Output selection for PWMH output of the channel 2" "DTOH2,OOVH2"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,Output selection for PWMH output of the channel 1" "DTOH1,OOVH1"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,Output selection for PWMH output of the channel 0" "DTOH0,OOVH0"
|
|
wgroup.long 0x54++0x07
|
|
line.long 0x00 "OSSUPD,PWM Output Selection Set Update Register"
|
|
bitfld.long 0x00 19. " OSSUPL[3] ,Output selection set for PWML output of the channel 3" "No effect,OOVL3"
|
|
bitfld.long 0x00 18. " [2] ,Output selection set for PWML output of the channel 2" "No effect,OOVL2"
|
|
bitfld.long 0x00 17. " [1] ,Output selection set for PWML output of the channel 1" "No effect,OOVL1"
|
|
bitfld.long 0x00 16. " [0] ,Output selection set for PWML output of the channel 0" "No effect,OOVL0"
|
|
newline
|
|
bitfld.long 0x00 3. " OSSUPH[3] ,Output selection set for PWMH output of the channel 3" "No effect,OOVH3"
|
|
bitfld.long 0x00 2. " [2] ,Output selection set for PWMH output of the channel 2" "No effect,OOVH2"
|
|
bitfld.long 0x00 1. " [1] ,Output selection set for PWMH output of the channel 1" "No effect,OOVH1"
|
|
bitfld.long 0x00 0. " [0] ,Output selection set for PWMH output of the channel 0" "No effect,OOVH0"
|
|
line.long 0x04 "OSCUPD,PWM Output Selection Clear Update Register"
|
|
bitfld.long 0x04 19. " OSCUPL[3] ,Output selection clear for PWML output of the channel 3" "No effect,DTOL3"
|
|
bitfld.long 0x04 18. " [2] ,Output selection clear for PWML output of the channel 2" "No effect,DTOL2"
|
|
bitfld.long 0x04 17. " [1] ,Output selection clear for PWML output of the channel 1" "No effect,DTOL1"
|
|
bitfld.long 0x04 16. " [0] ,Output selection clear for PWML output of the channel 0" "No effect,DTOL0"
|
|
newline
|
|
bitfld.long 0x04 3. " OSCUPH[3] ,Output selection clear for PWMH output of the channel 3" "No effect,DTOH3"
|
|
bitfld.long 0x04 2. " [2] ,Output selection clear for PWMH output of the channel 2" "No effect,DTOH2"
|
|
bitfld.long 0x04 1. " [1] ,Output selection clear for PWMH output of the channel 1" "No effect,DTOH1"
|
|
bitfld.long 0x04 0. " [0] ,Output selection clear for PWMH output of the channel 0" "No effect,DTOH0"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "FMR,PWM Fault Mode Register"
|
|
bitfld.long 0x00 23. " FFIL[7] ,Fault 7 filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " [6] ,Fault 6 filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " [5] ,Fault 5 filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " [4] ,Fault 4 filtering" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Fault 3 filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " [2] ,Fault 2 filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,Fault 1 filtering" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,Fault 0 filtering" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " FMOD[7] ,Fault 7 activation mode" "Until removed,Until removed and cleared"
|
|
bitfld.long 0x00 14. " [6] ,Fault 6 activation mode" "Until removed,Until removed and cleared"
|
|
bitfld.long 0x00 13. " [5] ,Fault 5 activation mode" "Until removed,Until removed and cleared"
|
|
bitfld.long 0x00 12. " [4] ,Fault 4 activation mode" "Until removed,Until removed and cleared"
|
|
newline
|
|
bitfld.long 0x00 11. " [3] ,Fault 3 activation mode" "Until removed,Until removed and cleared"
|
|
bitfld.long 0x00 10. " [2] ,Fault 2 activation mode" "Until removed,Until removed and cleared"
|
|
bitfld.long 0x00 9. " [1] ,Fault 1 activation mode" "Until removed,Until removed and cleared"
|
|
bitfld.long 0x00 8. " [0] ,Fault 0 activation mode" "Until removed,Until removed and cleared"
|
|
newline
|
|
bitfld.long 0x00 7. " FPOL[7] ,Fault 7 polarity" "Active-low,Active-high"
|
|
bitfld.long 0x00 6. " [6] ,Fault 6 polarity" "Active-low,Active-high"
|
|
bitfld.long 0x00 5. " [5] ,Fault 5 polarity" "Active-low,Active-high"
|
|
bitfld.long 0x00 4. " [4] ,Fault 4 polarity" "Active-low,Active-high"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Fault 3 polarity" "Active-low,Active-high"
|
|
bitfld.long 0x00 2. " [2] ,Fault 2 polarity" "Active-low,Active-high"
|
|
bitfld.long 0x00 1. " [1] ,Fault 1 polarity" "Active-low,Active-high"
|
|
bitfld.long 0x00 0. " [0] ,Fault 0 polarity" "Active-low,Active-high"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "FSR,PWM Fault Status Register"
|
|
bitfld.long 0x00 15. " FS[7] ,Fault 7 status" "Inactive,Active"
|
|
bitfld.long 0x00 14. " [6] ,Fault 6 status" "Inactive,Active"
|
|
bitfld.long 0x00 13. " [5] ,Fault 5 status" "Inactive,Active"
|
|
bitfld.long 0x00 12. " [4] ,Fault 4 status" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 11. " [3] ,Fault 3 status" "Inactive,Active"
|
|
bitfld.long 0x00 10. " [2] ,Fault 2 status" "Inactive,Active"
|
|
bitfld.long 0x00 9. " [1] ,Fault 1 status" "Inactive,Active"
|
|
bitfld.long 0x00 8. " [0] ,Fault 0 status" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " FIV[7] ,Fault input 7 value" "Low,High"
|
|
bitfld.long 0x00 6. " [6] ,Fault input 6 value" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Fault input 5 value" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Fault input 4 value" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Fault input 3 value" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Fault input 2 value" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Fault input 1 value" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Fault input 0 value" "Low,High"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "FCR,PWM Fault Clear Register"
|
|
bitfld.long 0x00 7. " FCLR[7] ,Fault 7 clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " [6] ,Fault 6 clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " [5] ,Fault 5 clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " [4] ,Fault 4 clear" "No effect,Clear"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Fault 3 clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " [2] ,Fault 2 clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " [1] ,Fault 1 clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " [0] ,Fault 0 clear" "No effect,Clear"
|
|
group.long 0x68++0x07
|
|
line.long 0x00 "FPV1,PWM Fault Protection Value Register 1"
|
|
bitfld.long 0x00 19. " FPVL[3] ,Fault protection value for PWML output on channel 3" "Low,High"
|
|
bitfld.long 0x00 18. " [2] ,Fault protection value for PWML output on channel 2" "Low,High"
|
|
bitfld.long 0x00 17. " [1] ,Fault protection value for PWML output on channel 1" "Low,High"
|
|
bitfld.long 0x00 16. " [0] ,Fault protection value for PWML output on channel 0" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " FPVH[3] ,Fault protection value for PWMH output on channel 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Fault protection value for PWMH output on channel 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Fault protection value for PWMH output on channel 1" "Low,High"
|
|
bitfld.long 0x00 0. " [0] ,Fault protection value for PWMH output on channel 0" "Low,High"
|
|
line.long 0x04 "FPE,PWM Fault Protection Enable Register"
|
|
bitfld.long 0x04 31. " FPE3[7] ,Fault protection enable with fault 7 for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " [6] ,Fault protection enable with fault 6 for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " [5] ,Fault protection enable with fault 5 for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " [4] ,Fault protection enable with fault 4 for channel 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 27. " [3] ,Fault protection enable with fault 3 for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " [2] ,Fault protection enable with fault 2 for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " [1] ,Fault protection enable with fault 1 for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " [0] ,Fault protection enable with fault 0 for channel 3" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 23. " FPE2[7] ,Fault protection enable with fault 7 for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " [6] ,Fault protection enable with fault 6 for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " [5] ,Fault protection enable with fault 5 for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " [4] ,Fault protection enable with fault 4 for channel 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " [3] ,Fault protection enable with fault 3 for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " [2] ,Fault protection enable with fault 2 for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " [1] ,Fault protection enable with fault 1 for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " [0] ,Fault protection enable with fault 0 for channel 2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 15. " FPE1[7] ,Fault protection enable with fault 7 for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " [6] ,Fault protection enable with fault 6 for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " [5] ,Fault protection enable with fault 5 for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " [4] ,Fault protection enable with fault 4 for channel 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " [3] ,Fault protection enable with fault 3 for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " [2] ,Fault protection enable with fault 2 for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " [1] ,Fault protection enable with fault 1 for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " [0] ,Fault protection enable with fault 0 for channel 1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 7. " FPE0[7] ,Fault protection enable with fault 7 for channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [6] ,Fault protection enable with fault 6 for channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " [5] ,Fault protection enable with fault 5 for channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [4] ,Fault protection enable with fault 4 for channel 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Fault protection enable with fault 3 for channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,Fault protection enable with fault 2 for channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [1] ,Fault protection enable with fault 1 for channel 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [0] ,Fault protection enable with fault 0 for channel 0" "Disabled,Enabled"
|
|
sif cpuis("ATSAMS7*")||cpuis("ATSAME7*")
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "ELMR0,PWM Event Line 0 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ELMR1,PWM Event Line 1 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
else
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "ELMR0,PWM Event Line 0 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ELMR1,PWM Event Line 1 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "ELMR2,PWM Event Line 2 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "ELMR3,PWM Event Line 3 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "ELMR4,PWM Event Line 4 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "ELMR5,PWM Event Line 5 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "ELMR6,PWM Event Line 6 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "ELMR7,PWM Event Line 7 Register"
|
|
bitfld.long 0x00 7. " CSEL[7] ,Comparison 7 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Comparison 6 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Comparison 5 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Comparison 4 selection" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Comparison 3 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Comparison 2 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Comparison 1 selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Comparison 0 selection" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SSPR,Spread Spectrum Register"
|
|
bitfld.long 0x00 24. " SPRDM ,Spread spectrum counter mode" "Triangular,Random"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPRD ,Spread spectrum limit value"
|
|
wgroup.long 0xA4++0x03
|
|
line.long 0x00 "SSPUP,PWM Spread Spectrum Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SPRDUP ,Spread spectrum limit value update"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "SMMR,PWM Stepper Motor Mode Register"
|
|
bitfld.long 0x00 17. " DOWN1 ,Down count 1" "Up,Down"
|
|
bitfld.long 0x00 16. " DOWN0 ,Down count 0" "Up,Down"
|
|
bitfld.long 0x00 1. " GCEN1 ,Gray count 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " GCEN0 ,Gray count 0 enable" "Disabled,Enabled"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FPV2,Fault Protection Value Register 2"
|
|
bitfld.long 0x00 19. " FPZL[3] ,Fault protection to Hi-Z for PWML output on channel 3" "FPVL3,High impedance"
|
|
bitfld.long 0x00 18. " [2] ,Fault protection to Hi-Z for PWML output on channel 2" "FPVL2,High impedance"
|
|
bitfld.long 0x00 17. " [1] ,Fault protection to Hi-Z for PWML output on channel 1" "FPVL1,High impedance"
|
|
bitfld.long 0x00 16. " [0] ,Fault protection to Hi-Z for PWML output on channel 0" "FPVL0,High impedance"
|
|
newline
|
|
bitfld.long 0x00 3. " FPZH[3] ,Fault protection to Hi-Z for PWMH output on channel 3" "FPVH3,High impedance"
|
|
bitfld.long 0x00 2. " [2] ,Fault protection to Hi-Z for PWMH output on channel 2" "FPVH2,High impedance"
|
|
bitfld.long 0x00 1. " [1] ,Fault protection to Hi-Z for PWMH output on channel 1" "FPVH1,High impedance"
|
|
bitfld.long 0x00 0. " [0] ,Fault protection to Hi-Z for PWMH output on channel 0" "FPVH0,High impedance"
|
|
wgroup.long 0xE4++0x03
|
|
line.long 0x00 "WPCR,PWM Write Protect Control Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect key"
|
|
bitfld.long 0x00 7. " WPRG[5] ,Write protect register group 5" "Disable,Enable"
|
|
bitfld.long 0x00 6. " [4] ,Write protect register group 4" "Disable,Enable"
|
|
bitfld.long 0x00 5. " [3] ,Write protect register group 3" "Disable,Enable"
|
|
newline
|
|
bitfld.long 0x00 4. " [2] ,Write protect register group 2" "Disable,Enable"
|
|
bitfld.long 0x00 3. " [1] ,Write protect register group 1" "Disable,Enable"
|
|
bitfld.long 0x00 2. " [0] ,Write protect register group 0" "Disable,Enable"
|
|
bitfld.long 0x00 0.--1. " WPCMD ,Write protect command" "DISABLE_SW_PROT,ENABLE_SW_PROT,ENABLE_HW_PROT,?..."
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,PWM Write Protect Status Register"
|
|
in
|
|
tree.end
|
|
width 10.
|
|
tree "Comparison Registers"
|
|
if (((per.l(ad:0x4005C000+0x200))&0x100)==0x100)
|
|
group.long (0x130+0x0)++0x03 "Comparison 0"
|
|
line.long 0x00 "CMPV0,PWM Comparison 0 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 0 value mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 0 value"
|
|
wgroup.long (0x134+0x0)++0x03
|
|
line.long 0x00 "CMPVUPD0,Comparison 0 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 0 value mode update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 0 value update"
|
|
else
|
|
group.long (0x130+0x0)++0x03 "Comparison 0"
|
|
line.long 0x00 "CMPV0,PWM Comparison 0 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 0 value"
|
|
wgroup.long (0x134+0x0)++0x03
|
|
line.long 0x00 "CMPVUPD0,Comparison 0 Value Update"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 0 value update"
|
|
endif
|
|
group.long (0x138+0x0)++0x03
|
|
line.long 0x00 "CMPM0,PWM Comparison 0 Mode Register"
|
|
rbitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 0 update period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 0 update period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 0 period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 0 period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 0 trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 0 enable" "Disabled,Enabled"
|
|
wgroup.long (0x13C+0x0)++0x03
|
|
line.long 0x00 "CMPMUPD0,PWM Comparison 0 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 0 update period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 0 period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 0 trigger update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 0 enable update" "Disable,Enable"
|
|
if (((per.l(ad:0x4005C000+0x200))&0x100)==0x100)
|
|
group.long (0x130+0x10)++0x03 "Comparison 1"
|
|
line.long 0x00 "CMPV1,PWM Comparison 1 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 1 value mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 1 value"
|
|
wgroup.long (0x134+0x10)++0x03
|
|
line.long 0x00 "CMPVUPD1,Comparison 1 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 1 value mode update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 1 value update"
|
|
else
|
|
group.long (0x130+0x10)++0x03 "Comparison 1"
|
|
line.long 0x00 "CMPV1,PWM Comparison 1 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 1 value"
|
|
wgroup.long (0x134+0x10)++0x03
|
|
line.long 0x00 "CMPVUPD1,Comparison 1 Value Update"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 1 value update"
|
|
endif
|
|
group.long (0x138+0x10)++0x03
|
|
line.long 0x00 "CMPM1,PWM Comparison 1 Mode Register"
|
|
rbitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 1 update period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 1 update period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 1 period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 1 period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 1 trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 1 enable" "Disabled,Enabled"
|
|
wgroup.long (0x13C+0x10)++0x03
|
|
line.long 0x00 "CMPMUPD1,PWM Comparison 1 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 1 update period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 1 period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 1 trigger update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 1 enable update" "Disable,Enable"
|
|
if (((per.l(ad:0x4005C000+0x200))&0x100)==0x100)
|
|
group.long (0x130+0x20)++0x03 "Comparison 2"
|
|
line.long 0x00 "CMPV2,PWM Comparison 2 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 2 value mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 2 value"
|
|
wgroup.long (0x134+0x20)++0x03
|
|
line.long 0x00 "CMPVUPD2,Comparison 2 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 2 value mode update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 2 value update"
|
|
else
|
|
group.long (0x130+0x20)++0x03 "Comparison 2"
|
|
line.long 0x00 "CMPV2,PWM Comparison 2 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 2 value"
|
|
wgroup.long (0x134+0x20)++0x03
|
|
line.long 0x00 "CMPVUPD2,Comparison 2 Value Update"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 2 value update"
|
|
endif
|
|
group.long (0x138+0x20)++0x03
|
|
line.long 0x00 "CMPM2,PWM Comparison 2 Mode Register"
|
|
rbitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 2 update period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 2 update period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 2 period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 2 period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 2 trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 2 enable" "Disabled,Enabled"
|
|
wgroup.long (0x13C+0x20)++0x03
|
|
line.long 0x00 "CMPMUPD2,PWM Comparison 2 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 2 update period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 2 period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 2 trigger update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 2 enable update" "Disable,Enable"
|
|
if (((per.l(ad:0x4005C000+0x200))&0x100)==0x100)
|
|
group.long (0x130+0x30)++0x03 "Comparison 3"
|
|
line.long 0x00 "CMPV3,PWM Comparison 3 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 3 value mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 3 value"
|
|
wgroup.long (0x134+0x30)++0x03
|
|
line.long 0x00 "CMPVUPD3,Comparison 3 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 3 value mode update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 3 value update"
|
|
else
|
|
group.long (0x130+0x30)++0x03 "Comparison 3"
|
|
line.long 0x00 "CMPV3,PWM Comparison 3 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 3 value"
|
|
wgroup.long (0x134+0x30)++0x03
|
|
line.long 0x00 "CMPVUPD3,Comparison 3 Value Update"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 3 value update"
|
|
endif
|
|
group.long (0x138+0x30)++0x03
|
|
line.long 0x00 "CMPM3,PWM Comparison 3 Mode Register"
|
|
rbitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 3 update period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 3 update period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 3 period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 3 period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 3 trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 3 enable" "Disabled,Enabled"
|
|
wgroup.long (0x13C+0x30)++0x03
|
|
line.long 0x00 "CMPMUPD3,PWM Comparison 3 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 3 update period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 3 period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 3 trigger update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 3 enable update" "Disable,Enable"
|
|
if (((per.l(ad:0x4005C000+0x200))&0x100)==0x100)
|
|
group.long (0x130+0x40)++0x03 "Comparison 4"
|
|
line.long 0x00 "CMPV4,PWM Comparison 4 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 4 value mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 4 value"
|
|
wgroup.long (0x134+0x40)++0x03
|
|
line.long 0x00 "CMPVUPD4,Comparison 4 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 4 value mode update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 4 value update"
|
|
else
|
|
group.long (0x130+0x40)++0x03 "Comparison 4"
|
|
line.long 0x00 "CMPV4,PWM Comparison 4 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 4 value"
|
|
wgroup.long (0x134+0x40)++0x03
|
|
line.long 0x00 "CMPVUPD4,Comparison 4 Value Update"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 4 value update"
|
|
endif
|
|
group.long (0x138+0x40)++0x03
|
|
line.long 0x00 "CMPM4,PWM Comparison 4 Mode Register"
|
|
rbitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 4 update period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 4 update period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 4 period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 4 period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 4 trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 4 enable" "Disabled,Enabled"
|
|
wgroup.long (0x13C+0x40)++0x03
|
|
line.long 0x00 "CMPMUPD4,PWM Comparison 4 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 4 update period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 4 period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 4 trigger update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 4 enable update" "Disable,Enable"
|
|
if (((per.l(ad:0x4005C000+0x200))&0x100)==0x100)
|
|
group.long (0x130+0x50)++0x03 "Comparison 5"
|
|
line.long 0x00 "CMPV5,PWM Comparison 5 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 5 value mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 5 value"
|
|
wgroup.long (0x134+0x50)++0x03
|
|
line.long 0x00 "CMPVUPD5,Comparison 5 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 5 value mode update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 5 value update"
|
|
else
|
|
group.long (0x130+0x50)++0x03 "Comparison 5"
|
|
line.long 0x00 "CMPV5,PWM Comparison 5 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 5 value"
|
|
wgroup.long (0x134+0x50)++0x03
|
|
line.long 0x00 "CMPVUPD5,Comparison 5 Value Update"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 5 value update"
|
|
endif
|
|
group.long (0x138+0x50)++0x03
|
|
line.long 0x00 "CMPM5,PWM Comparison 5 Mode Register"
|
|
rbitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 5 update period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 5 update period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 5 period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 5 period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 5 trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 5 enable" "Disabled,Enabled"
|
|
wgroup.long (0x13C+0x50)++0x03
|
|
line.long 0x00 "CMPMUPD5,PWM Comparison 5 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 5 update period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 5 period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 5 trigger update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 5 enable update" "Disable,Enable"
|
|
if (((per.l(ad:0x4005C000+0x200))&0x100)==0x100)
|
|
group.long (0x130+0x60)++0x03 "Comparison 6"
|
|
line.long 0x00 "CMPV6,PWM Comparison 6 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 6 value mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 6 value"
|
|
wgroup.long (0x134+0x60)++0x03
|
|
line.long 0x00 "CMPVUPD6,Comparison 6 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 6 value mode update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 6 value update"
|
|
else
|
|
group.long (0x130+0x60)++0x03 "Comparison 6"
|
|
line.long 0x00 "CMPV6,PWM Comparison 6 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 6 value"
|
|
wgroup.long (0x134+0x60)++0x03
|
|
line.long 0x00 "CMPVUPD6,Comparison 6 Value Update"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 6 value update"
|
|
endif
|
|
group.long (0x138+0x60)++0x03
|
|
line.long 0x00 "CMPM6,PWM Comparison 6 Mode Register"
|
|
rbitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 6 update period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 6 update period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 6 period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 6 period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 6 trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 6 enable" "Disabled,Enabled"
|
|
wgroup.long (0x13C+0x60)++0x03
|
|
line.long 0x00 "CMPMUPD6,PWM Comparison 6 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 6 update period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 6 period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 6 trigger update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 6 enable update" "Disable,Enable"
|
|
if (((per.l(ad:0x4005C000+0x200))&0x100)==0x100)
|
|
group.long (0x130+0x70)++0x03 "Comparison 7"
|
|
line.long 0x00 "CMPV7,PWM Comparison 7 Value Register"
|
|
bitfld.long 0x00 24. " CVM ,Comparison 7 value mode" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 7 value"
|
|
wgroup.long (0x134+0x70)++0x03
|
|
line.long 0x00 "CMPVUPD7,Comparison 7 Value Update"
|
|
bitfld.long 0x00 24. " CVMUPD ,Comparison 7 value mode update" "Incrementing,Decrementing"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 7 value update"
|
|
else
|
|
group.long (0x130+0x70)++0x03 "Comparison 7"
|
|
line.long 0x00 "CMPV7,PWM Comparison 7 Value Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CV ,Comparison 7 value"
|
|
wgroup.long (0x134+0x70)++0x03
|
|
line.long 0x00 "CMPVUPD7,Comparison 7 Value Update"
|
|
hexmask.long.word 0x00 0.--15. 1. " CVUPD ,Comparison 7 value update"
|
|
endif
|
|
group.long (0x138+0x70)++0x03
|
|
line.long 0x00 "CMPM7,PWM Comparison 7 Mode Register"
|
|
rbitfld.long 0x00 20.--23. " CUPRCNT ,Comparison 7 update period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CUPR ,Comparison 7 update period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. " CPRCNT ,Comparison 7 period counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPR ,Comparison 7 period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " CTR ,Comparison 7 trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CEN ,Comparison 7 enable" "Disabled,Enabled"
|
|
wgroup.long (0x13C+0x70)++0x03
|
|
line.long 0x00 "CMPMUPD7,PWM Comparison 7 Mode Update Register"
|
|
bitfld.long 0x00 16.--19. " CUPRUPD ,Comparison 7 update period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " CPRUPD ,Comparison 7 period update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CTRUPD ,Comparison 7 trigger update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CENUPD ,Comparison 7 enable update" "Disable,Enable"
|
|
tree.end
|
|
tree "Channel 0"
|
|
if (((per.l(ad:0x4005C000+0x200+0x0))&0x100)==0x100)
|
|
group.long (0x200+0x0)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 19. " PPM ,Push-pull mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-time PWML0 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-time PWMH0 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " DTE ,Dead-time generator enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " TCTS ,Timer counter trigger selection" "Comparator,Counter"
|
|
bitfld.long 0x00 12. " DPOLI ,Disabled polarity inverted" "Same as CPOL,Inverted to CPOL"
|
|
bitfld.long 0x00 11. " UPDS ,Update selection (at the end of [one/half] period after writing the update register)" "One period,Half period"
|
|
bitfld.long 0x00 10. " CES ,Counter event selection (at the end/at the end or at half period after writing the update register)" "End,Half and end"
|
|
newline
|
|
bitfld.long 0x00 9. " CPOL ,Channel polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel pre-scaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0x0)++0x03
|
|
line.long 0x00 "CMR0,Channel 0 Mode Register"
|
|
bitfld.long 0x00 19. " PPM ,Push-pull mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-time PWML0 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-time PWMH0 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " DTE ,Dead-time generator enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " TCTS ,Timer counter trigger selection" "Comparator,Counter"
|
|
bitfld.long 0x00 12. " DPOLI ,Disabled polarity inverted" "Same as CPOL,Inverted to CPOL"
|
|
bitfld.long 0x00 11. " UPDS ,Update selection (at the end of [one/half] period after writing the update register)" "One period,One period"
|
|
bitfld.long 0x00 10. " CES ,Counter event selection (at the end/at the end or at half period after writing the update register)" "End,End"
|
|
newline
|
|
bitfld.long 0x00 9. " CPOL ,Channel polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel pre-scaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0x0)++0x03
|
|
line.long 0x00 "CDTY0,PWM Channel 0 Duty Cycle Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel duty-cycle"
|
|
wgroup.long (0x208+0x0)++0x03
|
|
line.long 0x00 "CDTYUPD0,PWM Channel 0 Duty Cycle Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel duty-cycle update"
|
|
group.long (0x20C+0x0)++0x03
|
|
line.long 0x00 "CPRD0,PWM Channel 0 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel period"
|
|
wgroup.long (0x210+0x0)++0x03
|
|
line.long 0x00 "CPRDUPD0,Channel 0 Period Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRDUPD ,Channel period update"
|
|
rgroup.long (0x214+0x0)++0x03
|
|
line.long 0x00 "CCNT0,PWM Channel 0 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Channel counter value"
|
|
group.long (0x218+0x0)++0x03
|
|
line.long 0x00 "DT0,PWM Channel 0 Dead Time Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DTL ,Dead-time value for PWML0 output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTH ,Dead-time value for PWMH0 output"
|
|
wgroup.long (0x21C+0x0)++0x03
|
|
line.long 0x00 "DTUPD0,PWM Channel 0 Dead Time Update Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DTLUPD ,Dead-time value update for PWML0 output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTHUPD ,Dead-time value update for PWMH0 output"
|
|
group.long (0x400+0x0)++0x03
|
|
line.long 0x00 "CMUPD0,PWM Channel Mode Update Register"
|
|
bitfld.long 0x00 13. " CPOLINVUP ,Channel polarity inversion update" "No effect,Inverted"
|
|
bitfld.long 0x00 9. " CPOLUP ,Channel polarity update" "Low level,High level"
|
|
newline
|
|
sif cpuis("ATSAMS7*")
|
|
hgroup.long (0x42C+0x0)++0x03
|
|
hide.long 0x00 "ETRG1,PWM External Trigger 1 Register"
|
|
in
|
|
newline
|
|
group.long (0x430+0x0)++0x03
|
|
line.long 0x00 "LEBR1,PWM External Trigger 1 Register"
|
|
bitfld.long 0x00 19. " PWMHREN ,PWMH rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PWMHFEN ,PWMH falling edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMLREN ,PWML rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMLFEN ,PWML falling edge enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " LEBDELAY ,Leading-edge blanking delay for TRGIN1"
|
|
else
|
|
hgroup.long (0x42C+0x0)++0x03
|
|
hide.long 0x00 "ETRG1,PWM External Trigger 1 Register"
|
|
in
|
|
newline
|
|
group.long (0x430+0x0)++0x03
|
|
line.long 0x00 "LEBR1,PWM External Trigger 1 Register"
|
|
bitfld.long 0x00 19. " PWMHREN ,PWMH rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PWMHFEN ,PWMH falling edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMLREN ,PWML rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMLFEN ,PWML falling edge enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
tree "Channel 1"
|
|
if (((per.l(ad:0x4005C000+0x200+0x20))&0x100)==0x100)
|
|
group.long (0x200+0x20)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 19. " PPM ,Push-pull mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-time PWML1 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-time PWMH1 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " DTE ,Dead-time generator enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " TCTS ,Timer counter trigger selection" "Comparator,Counter"
|
|
bitfld.long 0x00 12. " DPOLI ,Disabled polarity inverted" "Same as CPOL,Inverted to CPOL"
|
|
bitfld.long 0x00 11. " UPDS ,Update selection (at the end of [one/half] period after writing the update register)" "One period,Half period"
|
|
bitfld.long 0x00 10. " CES ,Counter event selection (at the end/at the end or at half period after writing the update register)" "End,Half and end"
|
|
newline
|
|
bitfld.long 0x00 9. " CPOL ,Channel polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel pre-scaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0x20)++0x03
|
|
line.long 0x00 "CMR1,Channel 1 Mode Register"
|
|
bitfld.long 0x00 19. " PPM ,Push-pull mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-time PWML1 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-time PWMH1 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " DTE ,Dead-time generator enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " TCTS ,Timer counter trigger selection" "Comparator,Counter"
|
|
bitfld.long 0x00 12. " DPOLI ,Disabled polarity inverted" "Same as CPOL,Inverted to CPOL"
|
|
bitfld.long 0x00 11. " UPDS ,Update selection (at the end of [one/half] period after writing the update register)" "One period,One period"
|
|
bitfld.long 0x00 10. " CES ,Counter event selection (at the end/at the end or at half period after writing the update register)" "End,End"
|
|
newline
|
|
bitfld.long 0x00 9. " CPOL ,Channel polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel pre-scaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0x20)++0x03
|
|
line.long 0x00 "CDTY1,PWM Channel 1 Duty Cycle Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel duty-cycle"
|
|
wgroup.long (0x208+0x20)++0x03
|
|
line.long 0x00 "CDTYUPD1,PWM Channel 1 Duty Cycle Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel duty-cycle update"
|
|
group.long (0x20C+0x20)++0x03
|
|
line.long 0x00 "CPRD1,PWM Channel 1 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel period"
|
|
wgroup.long (0x210+0x20)++0x03
|
|
line.long 0x00 "CPRDUPD1,Channel 1 Period Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRDUPD ,Channel period update"
|
|
rgroup.long (0x214+0x20)++0x03
|
|
line.long 0x00 "CCNT1,PWM Channel 1 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Channel counter value"
|
|
group.long (0x218+0x20)++0x03
|
|
line.long 0x00 "DT1,PWM Channel 1 Dead Time Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DTL ,Dead-time value for PWML1 output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTH ,Dead-time value for PWMH1 output"
|
|
wgroup.long (0x21C+0x20)++0x03
|
|
line.long 0x00 "DTUPD1,PWM Channel 1 Dead Time Update Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DTLUPD ,Dead-time value update for PWML1 output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTHUPD ,Dead-time value update for PWMH1 output"
|
|
group.long (0x400+0x20)++0x03
|
|
line.long 0x00 "CMUPD1,PWM Channel Mode Update Register"
|
|
bitfld.long 0x00 13. " CPOLINVUP ,Channel polarity inversion update" "No effect,Inverted"
|
|
bitfld.long 0x00 9. " CPOLUP ,Channel polarity update" "Low level,High level"
|
|
newline
|
|
sif cpuis("ATSAMS7*")
|
|
hgroup.long (0x42C+0x20)++0x03
|
|
hide.long 0x00 "ETRG2,PWM External Trigger 2 Register"
|
|
in
|
|
newline
|
|
group.long (0x430+0x20)++0x03
|
|
line.long 0x00 "LEBR2,PWM External Trigger 2 Register"
|
|
bitfld.long 0x00 19. " PWMHREN ,PWMH rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PWMHFEN ,PWMH falling edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMLREN ,PWML rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMLFEN ,PWML falling edge enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " LEBDELAY ,Leading-edge blanking delay for TRGIN2"
|
|
else
|
|
hgroup.long (0x42C+0x20)++0x03
|
|
hide.long 0x00 "ETRG2,PWM External Trigger 2 Register"
|
|
in
|
|
newline
|
|
group.long (0x430+0x20)++0x03
|
|
line.long 0x00 "LEBR2,PWM External Trigger 2 Register"
|
|
bitfld.long 0x00 19. " PWMHREN ,PWMH rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PWMHFEN ,PWMH falling edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMLREN ,PWML rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMLFEN ,PWML falling edge enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
tree "Channel 2"
|
|
if (((per.l(ad:0x4005C000+0x200+0x40))&0x100)==0x100)
|
|
group.long (0x200+0x40)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 19. " PPM ,Push-pull mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-time PWML2 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-time PWMH2 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " DTE ,Dead-time generator enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " TCTS ,Timer counter trigger selection" "Comparator,Counter"
|
|
bitfld.long 0x00 12. " DPOLI ,Disabled polarity inverted" "Same as CPOL,Inverted to CPOL"
|
|
bitfld.long 0x00 11. " UPDS ,Update selection (at the end of [one/half] period after writing the update register)" "One period,Half period"
|
|
bitfld.long 0x00 10. " CES ,Counter event selection (at the end/at the end or at half period after writing the update register)" "End,Half and end"
|
|
newline
|
|
bitfld.long 0x00 9. " CPOL ,Channel polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel pre-scaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0x40)++0x03
|
|
line.long 0x00 "CMR2,Channel 2 Mode Register"
|
|
bitfld.long 0x00 19. " PPM ,Push-pull mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-time PWML2 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-time PWMH2 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " DTE ,Dead-time generator enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " TCTS ,Timer counter trigger selection" "Comparator,Counter"
|
|
bitfld.long 0x00 12. " DPOLI ,Disabled polarity inverted" "Same as CPOL,Inverted to CPOL"
|
|
bitfld.long 0x00 11. " UPDS ,Update selection (at the end of [one/half] period after writing the update register)" "One period,One period"
|
|
bitfld.long 0x00 10. " CES ,Counter event selection (at the end/at the end or at half period after writing the update register)" "End,End"
|
|
newline
|
|
bitfld.long 0x00 9. " CPOL ,Channel polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel pre-scaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0x40)++0x03
|
|
line.long 0x00 "CDTY2,PWM Channel 2 Duty Cycle Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel duty-cycle"
|
|
wgroup.long (0x208+0x40)++0x03
|
|
line.long 0x00 "CDTYUPD2,PWM Channel 2 Duty Cycle Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel duty-cycle update"
|
|
group.long (0x20C+0x40)++0x03
|
|
line.long 0x00 "CPRD2,PWM Channel 2 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel period"
|
|
wgroup.long (0x210+0x40)++0x03
|
|
line.long 0x00 "CPRDUPD2,Channel 2 Period Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRDUPD ,Channel period update"
|
|
rgroup.long (0x214+0x40)++0x03
|
|
line.long 0x00 "CCNT2,PWM Channel 2 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Channel counter value"
|
|
group.long (0x218+0x40)++0x03
|
|
line.long 0x00 "DT2,PWM Channel 2 Dead Time Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DTL ,Dead-time value for PWML2 output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTH ,Dead-time value for PWMH2 output"
|
|
wgroup.long (0x21C+0x40)++0x03
|
|
line.long 0x00 "DTUPD2,PWM Channel 2 Dead Time Update Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DTLUPD ,Dead-time value update for PWML2 output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTHUPD ,Dead-time value update for PWMH2 output"
|
|
group.long (0x400+0x40)++0x03
|
|
line.long 0x00 "CMUPD2,PWM Channel Mode Update Register"
|
|
bitfld.long 0x00 13. " CPOLINVUP ,Channel polarity inversion update" "No effect,Inverted"
|
|
bitfld.long 0x00 9. " CPOLUP ,Channel polarity update" "Low level,High level"
|
|
newline
|
|
sif cpuis("ATSAMS7*")
|
|
else
|
|
hgroup.long (0x42C+0x40)++0x03
|
|
hide.long 0x00 "ETRG3,PWM External Trigger 3 Register"
|
|
in
|
|
newline
|
|
group.long (0x430+0x40)++0x03
|
|
line.long 0x00 "LEBR3,PWM External Trigger 3 Register"
|
|
bitfld.long 0x00 19. " PWMHREN ,PWMH rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PWMHFEN ,PWMH falling edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMLREN ,PWML rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMLFEN ,PWML falling edge enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
tree "Channel 3"
|
|
if (((per.l(ad:0x4005C000+0x200+0x60))&0x100)==0x100)
|
|
group.long (0x200+0x60)++0x03
|
|
line.long 0x00 "CMR3,Channel 3 Mode Register"
|
|
bitfld.long 0x00 19. " PPM ,Push-pull mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-time PWML3 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-time PWMH3 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " DTE ,Dead-time generator enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " TCTS ,Timer counter trigger selection" "Comparator,Counter"
|
|
bitfld.long 0x00 12. " DPOLI ,Disabled polarity inverted" "Same as CPOL,Inverted to CPOL"
|
|
bitfld.long 0x00 11. " UPDS ,Update selection (at the end of [one/half] period after writing the update register)" "One period,Half period"
|
|
bitfld.long 0x00 10. " CES ,Counter event selection (at the end/at the end or at half period after writing the update register)" "End,Half and end"
|
|
newline
|
|
bitfld.long 0x00 9. " CPOL ,Channel polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel pre-scaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,CLKA,CLKB,?..."
|
|
else
|
|
group.long (0x200+0x60)++0x03
|
|
line.long 0x00 "CMR3,Channel 3 Mode Register"
|
|
bitfld.long 0x00 19. " PPM ,Push-pull mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DTLI ,Dead-time PWML3 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 17. " DTHI ,Dead-time PWMH3 output inverted" "Not inverted,Inverted"
|
|
bitfld.long 0x00 16. " DTE ,Dead-time generator enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. " TCTS ,Timer counter trigger selection" "Comparator,Counter"
|
|
bitfld.long 0x00 12. " DPOLI ,Disabled polarity inverted" "Same as CPOL,Inverted to CPOL"
|
|
bitfld.long 0x00 11. " UPDS ,Update selection (at the end of [one/half] period after writing the update register)" "One period,One period"
|
|
bitfld.long 0x00 10. " CES ,Counter event selection (at the end/at the end or at half period after writing the update register)" "End,End"
|
|
newline
|
|
bitfld.long 0x00 9. " CPOL ,Channel polarity" "Low level,High level"
|
|
bitfld.long 0x00 8. " CALG ,Channel alignment" "Left,Center"
|
|
bitfld.long 0x00 0.--3. " CPRE ,Channel pre-scaler" "/1,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,CLKA,CLKB,?..."
|
|
endif
|
|
group.long (0x204+0x60)++0x03
|
|
line.long 0x00 "CDTY3,PWM Channel 3 Duty Cycle Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTY ,Channel duty-cycle"
|
|
wgroup.long (0x208+0x60)++0x03
|
|
line.long 0x00 "CDTYUPD3,PWM Channel 3 Duty Cycle Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CDTYUPD ,Channel duty-cycle update"
|
|
group.long (0x20C+0x60)++0x03
|
|
line.long 0x00 "CPRD3,PWM Channel 3 Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRD ,Channel period"
|
|
wgroup.long (0x210+0x60)++0x03
|
|
line.long 0x00 "CPRDUPD3,Channel 3 Period Update Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPRDUPD ,Channel period update"
|
|
rgroup.long (0x214+0x60)++0x03
|
|
line.long 0x00 "CCNT3,PWM Channel 3 Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Channel counter value"
|
|
group.long (0x218+0x60)++0x03
|
|
line.long 0x00 "DT3,PWM Channel 3 Dead Time Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DTL ,Dead-time value for PWML3 output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTH ,Dead-time value for PWMH3 output"
|
|
wgroup.long (0x21C+0x60)++0x03
|
|
line.long 0x00 "DTUPD3,PWM Channel 3 Dead Time Update Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DTLUPD ,Dead-time value update for PWML3 output"
|
|
hexmask.long.word 0x00 0.--15. 1. " DTHUPD ,Dead-time value update for PWMH3 output"
|
|
group.long (0x400+0x60)++0x03
|
|
line.long 0x00 "CMUPD3,PWM Channel Mode Update Register"
|
|
bitfld.long 0x00 13. " CPOLINVUP ,Channel polarity inversion update" "No effect,Inverted"
|
|
bitfld.long 0x00 9. " CPOLUP ,Channel polarity update" "Low level,High level"
|
|
newline
|
|
sif cpuis("ATSAMS7*")
|
|
else
|
|
hgroup.long (0x42C+0x60)++0x03
|
|
hide.long 0x00 "ETRG4,PWM External Trigger 4 Register"
|
|
in
|
|
newline
|
|
group.long (0x430+0x60)++0x03
|
|
line.long 0x00 "LEBR4,PWM External Trigger 4 Register"
|
|
bitfld.long 0x00 19. " PWMHREN ,PWMH rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PWMHFEN ,PWMH falling edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PWMLREN ,PWML rising edge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " PWMLFEN ,PWML falling edge enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "AFEC (Analog Front-End Controller)"
|
|
tree "AFEC0"
|
|
base ad:0x4003C000
|
|
width 14.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,AFEC Control Register"
|
|
bitfld.long 0x00 1. " START ,Start conversion" "No effect,Start"
|
|
bitfld.long 0x00 0. " SWRST ,Software reset" "No effect,Reset"
|
|
if ((per.l(ad:0x4003C000+0xE4)&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,AFEC Mode Register"
|
|
bitfld.long 0x00 31. " USEQ ,User sequence enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " TRANSFER ,Transfer period" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " TRACKTIM ,Tracking time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " ONE ,Must be one" ",1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " STARTUP ,Start-up time" "0 periods,8 periods,16 periods,24 periods,64 periods,80 periods,96 periods,112 periods,512 periods,576 periods,640 periods,704 periods,768 periods,832 periods,896 periods,960 periods"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCAL ,Prescaler rate selection"
|
|
bitfld.long 0x00 7. " FREERUN ,Free run mode" "Off,On"
|
|
bitfld.long 0x00 6. " FWUP ,Fast wake-up" "Off,On"
|
|
newline
|
|
bitfld.long 0x00 5. " SLEEP ,Sleep mode" "Normal,Sleep"
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger selection" "TRIG0,TRIG1,TRIG2,TRIG3,TRIG4,TRIG5,TRIG6,?..."
|
|
bitfld.long 0x00 0. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4003C000+0x08))&0x200)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EMR,AFEC Extended Mode Register"
|
|
bitfld.long 0x00 28.--29. " SIGNMODE ,Sign mode" "SE_UNSG_DF_SIGN,SE_SIGN_DF_UNSG,ALL_UNSIGNED,ALL_SIGNED"
|
|
bitfld.long 0x00 25. " STM ,Single trigger mode" "Multiple triggers,Single trigger"
|
|
bitfld.long 0x00 24. " TAG ,TAG of the LDCR" "CHNB cleared,CHNB appended"
|
|
sif cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 16.--18. " RES ,Resolution" "12 bits/1,10-bits/1,13 bits/4,14 bits/16,15 bits/64,16 bits/256,?..."
|
|
else
|
|
bitfld.long 0x00 16.--18. " RES ,Resolution" "12 bits/1,13 bits/4,14 bits/16,15 bits/64,16 bits/256,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 12.--13. " CMPFILTER ,Compare event filtering" "0,1,2,3"
|
|
bitfld.long 0x00 9. " CMPALL ,Compare all channels" "No,Yes"
|
|
bitfld.long 0x00 3.--7. " CMPSEL ,Comparison selected channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison mode" "Low,High,In,Out"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EMR,AFEC Extended Mode Register"
|
|
bitfld.long 0x00 28.--29. " SIGNMODE ,Sign mode" "SE_UNSG_DF_SIGN,SE_SIGN_DF_UNSG,ALL_UNSIGNED,ALL_SIGNED"
|
|
bitfld.long 0x00 25. " STM ,Single trigger mode" "Multiple triggers,Single trigger"
|
|
bitfld.long 0x00 24. " TAG ,TAG of the LDCR" "CHNB cleared,CHNB appended"
|
|
sif cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 16.--18. " RES ,Resolution" "12 bits/1,10-bits/1,13 bits/4,14 bits/16,15 bits/64,16 bits/256,?..."
|
|
else
|
|
bitfld.long 0x00 16.--18. " RES ,Resolution" "12 bits/1,13 bits/4,14 bits/16,15 bits/64,16 bits/256,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 12.--13. " CMPFILTER ,Compare event filtering" "0,1,2,3"
|
|
bitfld.long 0x00 9. " CMPALL ,Compare all channels" "No,Yes"
|
|
bitfld.long 0x00 3.--7. " CMPSEL ,Comparison selected channel" "No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect"
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison mode" "Low,High,In,Out"
|
|
endif
|
|
if (((per.l(ad:0x4003C000+0x04))&0x80000000)==0x80000000)
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "SEQ1R,AFEC Channel Sequence 1 Register"
|
|
bitfld.long 0x00 28.--31. " USCH[7] ,User sequence number 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 24.--27. " [6] ,User sequence number 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 20.--23. " [5] ,User sequence number 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--19. " [4] ,User sequence number 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. " [3] ,User sequence number 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 8.--11. " [2] ,User sequence number 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 4.--7. " [1] ,User sequence number 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 0.--3. " [0] ,User sequence number 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
line.long 0x04 "SEQ2R,AFEC Channel Sequence 2 Register"
|
|
sif !cpuis("ATSAME7*")
|
|
bitfld.long 0x04 28.--31. " USCH[15] ,User sequence number 15" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 24.--27. " [14] ,User sequence number 14" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 20.--23. " [13] ,User sequence number 13" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 16.--19. " [12] ,User sequence number 12" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 12.--15. " USCH[11] ,User sequence number 11" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 8.--11. " [10] ,User sequence number 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 4.--7. " [9] ,User sequence number 9" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 0.--3. " [8] ,User sequence number 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "SEQ1R,AFEC Channel Sequence 1 Register"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SEQ2R,AFEC Channel Sequence 2 Register"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CHSR_SET/CLR,AFEC Channel Status Set/Clear Register"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CH[11] ,Channel 11 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Channel 10 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Channel 9 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Channel 8 status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Channel 7 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Channel 6 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Channel 5 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Channel 4 status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Channel 3 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Channel 2 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Channel 1 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Channel 0 status" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,AFEC Mode Register"
|
|
bitfld.long 0x00 31. " USEQ ,User sequence enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " TRANSFER ,Transfer period" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " TRACKTIM ,Tracking time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " ONE ,Must be one" ",1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " STARTUP ,Start-up time" "0 periods,8 periods,16 periods,24 periods,64 periods,80 periods,96 periods,112 periods,512 periods,576 periods,640 periods,704 periods,768 periods,832 periods,896 periods,960 periods"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCAL ,Prescaler rate selection"
|
|
bitfld.long 0x00 7. " FREERUN ,Free run mode" "Off,On"
|
|
bitfld.long 0x00 6. " FWUP ,Fast wake-up" "Off,On"
|
|
newline
|
|
bitfld.long 0x00 5. " SLEEP ,Sleep mode" "Normal,Sleep"
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger selection" "TRIG0,TRIG1,TRIG2,TRIG3,TRIG4,TRIG5,TRIG6,?..."
|
|
bitfld.long 0x00 0. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4003C000+0x08))&0x200)==0x00)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "EMR,AFEC Extended Mode Register"
|
|
bitfld.long 0x00 28.--29. " SIGNMODE ,Sign mode" "SE_UNSG_DF_SIGN,SE_SIGN_DF_UNSG,ALL_UNSIGNED,ALL_SIGNED"
|
|
bitfld.long 0x00 25. " STM ,Single trigger mode" "Multiple triggers,Single trigger"
|
|
bitfld.long 0x00 24. " TAG ,TAG of the LDCR" "CHNB cleared,CHNB appended"
|
|
sif cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 16.--18. " RES ,Resolution" "12 bits/1,10-bits/1,13 bits/4,14 bits/16,15 bits/64,16 bits/256,?..."
|
|
else
|
|
bitfld.long 0x00 16.--18. " RES ,Resolution" "12 bits/1,13 bits/4,14 bits/16,15 bits/64,16 bits/256,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 12.--13. " CMPFILTER ,Compare event filtering" "0,1,2,3"
|
|
bitfld.long 0x00 9. " CMPALL ,Compare all channels" "No,Yes"
|
|
bitfld.long 0x00 3.--7. " CMPSEL ,Comparison selected channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison mode" "Low,High,In,Out"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "EMR,AFEC Extended Mode Register"
|
|
bitfld.long 0x00 28.--29. " SIGNMODE ,Sign mode" "SE_UNSG_DF_SIGN,SE_SIGN_DF_UNSG,ALL_UNSIGNED,ALL_SIGNED"
|
|
bitfld.long 0x00 25. " STM ,Single trigger mode" "Multiple triggers,Single trigger"
|
|
bitfld.long 0x00 24. " TAG ,TAG of the LDCR" "CHNB cleared,CHNB appended"
|
|
sif cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 16.--18. " RES ,Resolution" "12 bits/1,10-bits/1,13 bits/4,14 bits/16,15 bits/64,16 bits/256,?..."
|
|
else
|
|
bitfld.long 0x00 16.--18. " RES ,Resolution" "12 bits/1,13 bits/4,14 bits/16,15 bits/64,16 bits/256,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 12.--13. " CMPFILTER ,Compare event filtering" "0,1,2,3"
|
|
bitfld.long 0x00 9. " CMPALL ,Compare all channels" "No,Yes"
|
|
bitfld.long 0x00 3.--7. " CMPSEL ,Comparison selected channel" "No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect"
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison mode" "Low,High,In,Out"
|
|
endif
|
|
if (((per.l(ad:0x4003C000+0x04))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "SEQ1R,AFEC Channel Sequence 1 Register"
|
|
bitfld.long 0x00 28.--31. " USCH[7] ,User sequence number 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 24.--27. " [6] ,User sequence number 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 20.--23. " [5] ,User sequence number 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--19. " [4] ,User sequence number 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. " [3] ,User sequence number 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 8.--11. " [2] ,User sequence number 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 4.--7. " [1] ,User sequence number 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 0.--3. " [0] ,User sequence number 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
line.long 0x04 "SEQ2R,AFEC Channel Sequence 2 Register"
|
|
bitfld.long 0x04 28.--31. " USCH[15] ,User sequence number 15" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 24.--27. " [14] ,User sequence number 14" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 20.--23. " [13] ,User sequence number 13" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 16.--19. " [12] ,User sequence number 12" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--15. " [11] ,User sequence number 11" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 8.--11. " [10] ,User sequence number 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 4.--7. " [9] ,User sequence number 9" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 0.--3. " [8] ,User sequence number 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "SEQ1R,AFEC Channel Sequence 1 Register"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SEQ2R,AFEC Channel Sequence 2 Register"
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "CHSR,AFEC Channel Status Register"
|
|
bitfld.long 0x00 11. " CH[11] ,Channel 11 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel 10 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel 9 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel 8 status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel 7 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 status" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "LCDR,AFEC Last Converted Data Register"
|
|
in
|
|
newline
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,AFEC Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " TEMPCHG ,Temperature change interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " COMPE ,Comparison event interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " GOVRE ,General overrun error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " DRDY ,Data ready interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOC[11] ,End of conversion interrupt mask 11" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,End of conversion interrupt mask 10" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,End of conversion interrupt mask 9" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,End of conversion interrupt mask 8" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,End of conversion interrupt mask 7" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,End of conversion interrupt mask 6" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,End of conversion interrupt mask 5" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,End of conversion interrupt mask 4" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,End of conversion interrupt mask 3" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,End of conversion interrupt mask 2" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,End of conversion interrupt mask 1" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,End of conversion interrupt mask 0" "Masked,Not masked"
|
|
newline
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "ISR,AFEC Interrupt Status Register"
|
|
in
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "OVER,AFEC Overrun Status Register"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x4003C000+0xE4)&0x01)==0x00)
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "CWR,AFEC Compare Window Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGHTHRES ,High threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOWTHRES ,Low threshold"
|
|
line.long 0x04 "CGR,AFEC Channel Gain Register"
|
|
bitfld.long 0x04 22.--23. " GAIN[11] ,Gain for channel 11" "1,2,4,4"
|
|
bitfld.long 0x04 20.--21. " [10] ,Gain for channel 10" "1,2,4,4"
|
|
bitfld.long 0x04 18.--19. " [9] ,Gain for channel 9" "1,2,4,4"
|
|
bitfld.long 0x04 16.--17. " [8] ,Gain for channel 8" "1,2,4,4"
|
|
newline
|
|
bitfld.long 0x04 14.--15. " [7] ,Gain for channel 7" "1,2,4,4"
|
|
bitfld.long 0x04 12.--13. " [6] ,Gain for channel 6" "1,2,4,4"
|
|
bitfld.long 0x04 10.--11. " [5] ,Gain for channel 5" "1,2,4,4"
|
|
bitfld.long 0x04 8.--9. " [4] ,Gain for channel 4" "1,2,4,4"
|
|
newline
|
|
bitfld.long 0x04 6.--7. " [3] ,Gain for channel 3" "1,2,4,4"
|
|
bitfld.long 0x04 4.--5. " [2] ,Gain for channel 2" "1,2,4,4"
|
|
bitfld.long 0x04 2.--3. " [1] ,Gain for channel 1" "1,2,4,4"
|
|
bitfld.long 0x04 0.--1. " [0] ,Gain for channel 0" "1,2,4,4"
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "DIFFR,AFEC Channel Differential Register"
|
|
bitfld.long 0x00 11. " DIFF[11] ,Differential inputs for channel 11" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 10. " [10] ,Differential inputs for channel 10" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 9. " [9] ,Differential inputs for channel 9" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 8. " [8] ,Differential inputs for channel 8" "Single-ended,Fully-differential"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Differential inputs for channel 7" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 6. " [6] ,Differential inputs for channel 6" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 5. " [5] ,Differential inputs for channel 5" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 4. " [4] ,Differential inputs for channel 4" "Single-ended,Fully-differential"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Differential inputs for channel 3" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 2. " [2] ,Differential inputs for channel 2" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 1. " [1] ,Differential inputs for channel 1" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 0. " [0] ,Differential inputs for channel 0" "Single-ended,Fully-differential"
|
|
line.long 0x04 "CSELR,AFEC Channel Selection Register"
|
|
bitfld.long 0x04 0.--3. " CSEL ,Channel selection" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
else
|
|
rgroup.long 0x50++0x07
|
|
line.long 0x00 "CWR,AFEC Compare Window Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGHTHRES ,High threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOWTHRES ,Low threshold"
|
|
line.long 0x04 "CGR,AFEC Channel Gain Register"
|
|
bitfld.long 0x04 22.--23. " GAIN[11] ,Gain for channel 11" "1,2,4,4"
|
|
bitfld.long 0x04 20.--21. " [10] ,Gain for channel 10" "1,2,4,4"
|
|
bitfld.long 0x04 18.--19. " [9] ,Gain for channel 9" "1,2,4,4"
|
|
bitfld.long 0x04 16.--17. " [8] ,Gain for channel 8" "1,2,4,4"
|
|
newline
|
|
bitfld.long 0x04 14.--15. " [7] ,Gain for channel 7" "1,2,4,4"
|
|
bitfld.long 0x04 12.--13. " [6] ,Gain for channel 6" "1,2,4,4"
|
|
bitfld.long 0x04 10.--11. " [5] ,Gain for channel 5" "1,2,4,4"
|
|
bitfld.long 0x04 8.--9. " [4] ,Gain for channel 4" "1,2,4,4"
|
|
newline
|
|
bitfld.long 0x04 6.--7. " [3] ,Gain for channel 3" "1,2,4,4"
|
|
bitfld.long 0x04 4.--5. " [2] ,Gain for channel 2" "1,2,4,4"
|
|
bitfld.long 0x04 2.--3. " [1] ,Gain for channel 1" "1,2,4,4"
|
|
bitfld.long 0x04 0.--1. " [0] ,Gain for channel 0" "1,2,4,4"
|
|
rgroup.long 0x60++0x07
|
|
line.long 0x00 "DIFFR,AFEC Channel Differential Register"
|
|
bitfld.long 0x00 11. " DIFF[11] ,Differential inputs for channel 11" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 10. " [10] ,Differential inputs for channel 10" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 9. " [9] ,Differential inputs for channel 9" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 8. " [8] ,Differential inputs for channel 8" "Single-ended,Fully-differential"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Differential inputs for channel 7" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 6. " [6] ,Differential inputs for channel 6" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 5. " [5] ,Differential inputs for channel 5" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 4. " [4] ,Differential inputs for channel 4" "Single-ended,Fully-differential"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Differential inputs for channel 3" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 2. " [2] ,Differential inputs for channel 2" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 1. " [1] ,Differential inputs for channel 1" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 0. " [0] ,Differential inputs for channel 0" "Single-ended,Fully-differential"
|
|
line.long 0x04 "CSELR,AFEC Channel Selection Register"
|
|
bitfld.long 0x04 0.--3. " CSEL ,Channel selection" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
endif
|
|
newline
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "CDR,AFEC Channel Data Register"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x4003C000+0xE4)&0x01)==0x00)
|
|
sif cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "COCR,AFEC Channel Offset Compensation Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " AOFF ,Analog offset"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "COCR,AFEC Channel Offset Compensation Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " AOFF ,Analog offset"
|
|
endif
|
|
if (((per.l(ad:0x4003C000+0x04))&0x01)==0x01)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TEMPMR,AFEC Temperature Sensor Mode Register"
|
|
bitfld.long 0x00 4.--5. " TEMPCMPMOD ,Temperature comparison mode" "Low,High,In,Out"
|
|
bitfld.long 0x00 0. " RTCT ,Temperature sensor RTC trigger mode" "Not triggered,Triggered"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TEMPMR,AFEC Temperature Sensor Mode Register"
|
|
bitfld.long 0x00 4.--5. " TEMPCMPMOD ,Temperature comparison mode" "Low,High,In,Out"
|
|
bitfld.long 0x00 0. " RTCT ,Temperature sensor RTC trigger mode" "Not triggered,?..."
|
|
endif
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TEMPCWR,AFEC Temperature Compare Window Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " THIGHTHRES ,Temperature high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " TLOWTHRES ,Temperature low threshold"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "ACR,AFEC Analog Control Register"
|
|
bitfld.long 0x00 8.--9. " IBCTL ,AFE bias current control" "0,1,2,3"
|
|
bitfld.long 0x00 3. " PGA1EN ,PGA1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PGA0EN ,PGA0 enable" "Disabled,Enabled"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SHMR,AFEC Sample & Hold Mode Register"
|
|
bitfld.long 0x00 11. " DUAL[11] ,Dual sample & hold for channel 11" "Single,Dual"
|
|
bitfld.long 0x00 10. " [10] ,Dual sample & hold for channel 10" "Single,Dual"
|
|
bitfld.long 0x00 9. " [9] ,Dual sample & hold for channel 9" "Single,Dual"
|
|
bitfld.long 0x00 8. " [8] ,Dual sample & hold for channel 8" "Single,Dual"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Dual sample & hold for channel 7" "Single,Dual"
|
|
bitfld.long 0x00 6. " [6] ,Dual sample & hold for channel 6" "Single,Dual"
|
|
bitfld.long 0x00 5. " [5] ,Dual sample & hold for channel 5" "Single,Dual"
|
|
bitfld.long 0x00 4. " [4] ,Dual sample & hold for channel 4" "Single,Dual"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Dual sample & hold for channel 3" "Single,Dual"
|
|
bitfld.long 0x00 2. " [2] ,Dual sample & hold for channel 2" "Single,Dual"
|
|
bitfld.long 0x00 1. " [1] ,Dual sample & hold for channel 1" "Single,Dual"
|
|
bitfld.long 0x00 0. " [0] ,Dual sample & hold for channel 0" "Single,Dual"
|
|
group.long 0xD0++0x0B
|
|
line.long 0x00 "COSR,AFEC Correction Select Register"
|
|
bitfld.long 0x00 0. " CSEL ,Sample & hold unit correction select" "0,1"
|
|
line.long 0x04 "CVR,AFEC Correction Values Register"
|
|
sif cpuis("ATSAMS7*")
|
|
hexmask.long.word 0x04 16.--31. 1. " GAINCORR ,Gain correction"
|
|
else
|
|
hexmask.long.word 0x04 16.--27. 1. " GAINCORR ,Gain correction"
|
|
endif
|
|
hexmask.long.word 0x04 0.--11. 1. " OFFSETCORR ,Offset correction"
|
|
line.long 0x08 "CECR,AFEC Channel Error Correction Register"
|
|
bitfld.long 0x08 11. " ECORR[11] ,Error correction enable for channel 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [10] ,Error correction enable for channel 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [9] ,Error correction enable for channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [8] ,Error correction enable for channel 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,Error correction enable for channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [6] ,Error correction enable for channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [5] ,Error correction enable for channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [4] ,Error correction enable for channel 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,Error correction enable for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Error correction enable for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [1] ,Error correction enable for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [0] ,Error correction enable for channel 0" "Disabled,Enabled"
|
|
else
|
|
sif cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "COCR,AFEC Channel Offset Compensation Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " AOFF ,Analog offset"
|
|
else
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "COCR,AFEC Channel Offset Compensation Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " AOFF ,Analog offset"
|
|
endif
|
|
if (((per.l(ad:0x4003C000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "TEMPMR,AFEC Temperature Sensor Mode Register"
|
|
bitfld.long 0x00 4.--5. " TEMPCMPMOD ,Temperature comparison mode" "Low,High,In,Out"
|
|
bitfld.long 0x00 0. " RTCT ,Temperature sensor RTC trigger mode" "Not triggered,Triggered"
|
|
else
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "TEMPMR,AFEC Temperature Sensor Mode Register"
|
|
bitfld.long 0x00 4.--5. " TEMPCMPMOD ,Temperature comparison mode" "Low,High,In,Out"
|
|
bitfld.long 0x00 0. " RTCT ,Temperature sensor RTC trigger mode" "Not triggered,?..."
|
|
endif
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "TEMPCWR,AFEC Temperature Compare Window Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " THIGHTHRES ,Temperature high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " TLOWTHRES ,Temperature low threshold"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ACR,AFEC Analog Control Register"
|
|
bitfld.long 0x00 8.--9. " IBCTL ,AFE bias current control" "0,1,2,3"
|
|
bitfld.long 0x00 3. " PGA1EN ,PGA1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PGA0EN ,PGA0 enable" "Disabled,Enabled"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "SHMR,AFEC Sample & Hold Mode Register"
|
|
bitfld.long 0x00 11. " DUAL[11] ,Dual sample & hold for channel 11" "Single,Dual"
|
|
bitfld.long 0x00 10. " [10] ,Dual sample & hold for channel 10" "Single,Dual"
|
|
bitfld.long 0x00 9. " [9] ,Dual sample & hold for channel 9" "Single,Dual"
|
|
bitfld.long 0x00 8. " [8] ,Dual sample & hold for channel 8" "Single,Dual"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Dual sample & hold for channel 7" "Single,Dual"
|
|
bitfld.long 0x00 6. " [6] ,Dual sample & hold for channel 6" "Single,Dual"
|
|
bitfld.long 0x00 5. " [5] ,Dual sample & hold for channel 5" "Single,Dual"
|
|
bitfld.long 0x00 4. " [4] ,Dual sample & hold for channel 4" "Single,Dual"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Dual sample & hold for channel 3" "Single,Dual"
|
|
bitfld.long 0x00 2. " [2] ,Dual sample & hold for channel 2" "Single,Dual"
|
|
bitfld.long 0x00 1. " [1] ,Dual sample & hold for channel 1" "Single,Dual"
|
|
bitfld.long 0x00 0. " [0] ,Dual sample & hold for channel 0" "Single,Dual"
|
|
rgroup.long 0xD0++0x0B
|
|
line.long 0x00 "COSR,AFEC Correction Select Register"
|
|
bitfld.long 0x00 0. " CSEL ,Sample & hold unit correction select" "0,1"
|
|
line.long 0x04 "CVR,AFEC Correction Values Register"
|
|
sif cpuis("ATSAMS7*")
|
|
hexmask.long.word 0x04 16.--31. 1. " GAINCORR ,Gain correction"
|
|
else
|
|
hexmask.long.word 0x04 16.--27. 1. " GAINCORR ,Gain correction"
|
|
endif
|
|
hexmask.long.word 0x04 0.--11. 1. " OFFSETCORR ,Offset correction"
|
|
line.long 0x08 "CECR,AFEC Channel Error Correction Register"
|
|
bitfld.long 0x08 11. " ECORR[11] ,Error correction enable for channel 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [10] ,Error correction enable for channel 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [9] ,Error correction enable for channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [8] ,Error correction enable for channel 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,Error correction enable for channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [6] ,Error correction enable for channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [5] ,Error correction enable for channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [4] ,Error correction enable for channel 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,Error correction enable for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Error correction enable for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [1] ,Error correction enable for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [0] ,Error correction enable for channel 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,AFEC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protection KEY password"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,AFEC Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "AFEC1"
|
|
base ad:0x40064000
|
|
width 14.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,AFEC Control Register"
|
|
bitfld.long 0x00 1. " START ,Start conversion" "No effect,Start"
|
|
bitfld.long 0x00 0. " SWRST ,Software reset" "No effect,Reset"
|
|
if ((per.l(ad:0x40064000+0xE4)&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,AFEC Mode Register"
|
|
bitfld.long 0x00 31. " USEQ ,User sequence enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " TRANSFER ,Transfer period" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " TRACKTIM ,Tracking time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " ONE ,Must be one" ",1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " STARTUP ,Start-up time" "0 periods,8 periods,16 periods,24 periods,64 periods,80 periods,96 periods,112 periods,512 periods,576 periods,640 periods,704 periods,768 periods,832 periods,896 periods,960 periods"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCAL ,Prescaler rate selection"
|
|
bitfld.long 0x00 7. " FREERUN ,Free run mode" "Off,On"
|
|
bitfld.long 0x00 6. " FWUP ,Fast wake-up" "Off,On"
|
|
newline
|
|
bitfld.long 0x00 5. " SLEEP ,Sleep mode" "Normal,Sleep"
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger selection" "TRIG0,TRIG1,TRIG2,TRIG3,TRIG4,TRIG5,TRIG6,?..."
|
|
bitfld.long 0x00 0. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40064000+0x08))&0x200)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EMR,AFEC Extended Mode Register"
|
|
bitfld.long 0x00 28.--29. " SIGNMODE ,Sign mode" "SE_UNSG_DF_SIGN,SE_SIGN_DF_UNSG,ALL_UNSIGNED,ALL_SIGNED"
|
|
bitfld.long 0x00 25. " STM ,Single trigger mode" "Multiple triggers,Single trigger"
|
|
bitfld.long 0x00 24. " TAG ,TAG of the LDCR" "CHNB cleared,CHNB appended"
|
|
sif cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 16.--18. " RES ,Resolution" "12 bits/1,10-bits/1,13 bits/4,14 bits/16,15 bits/64,16 bits/256,?..."
|
|
else
|
|
bitfld.long 0x00 16.--18. " RES ,Resolution" "12 bits/1,13 bits/4,14 bits/16,15 bits/64,16 bits/256,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 12.--13. " CMPFILTER ,Compare event filtering" "0,1,2,3"
|
|
bitfld.long 0x00 9. " CMPALL ,Compare all channels" "No,Yes"
|
|
bitfld.long 0x00 3.--7. " CMPSEL ,Comparison selected channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison mode" "Low,High,In,Out"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EMR,AFEC Extended Mode Register"
|
|
bitfld.long 0x00 28.--29. " SIGNMODE ,Sign mode" "SE_UNSG_DF_SIGN,SE_SIGN_DF_UNSG,ALL_UNSIGNED,ALL_SIGNED"
|
|
bitfld.long 0x00 25. " STM ,Single trigger mode" "Multiple triggers,Single trigger"
|
|
bitfld.long 0x00 24. " TAG ,TAG of the LDCR" "CHNB cleared,CHNB appended"
|
|
sif cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 16.--18. " RES ,Resolution" "12 bits/1,10-bits/1,13 bits/4,14 bits/16,15 bits/64,16 bits/256,?..."
|
|
else
|
|
bitfld.long 0x00 16.--18. " RES ,Resolution" "12 bits/1,13 bits/4,14 bits/16,15 bits/64,16 bits/256,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 12.--13. " CMPFILTER ,Compare event filtering" "0,1,2,3"
|
|
bitfld.long 0x00 9. " CMPALL ,Compare all channels" "No,Yes"
|
|
bitfld.long 0x00 3.--7. " CMPSEL ,Comparison selected channel" "No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect"
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison mode" "Low,High,In,Out"
|
|
endif
|
|
if (((per.l(ad:0x40064000+0x04))&0x80000000)==0x80000000)
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "SEQ1R,AFEC Channel Sequence 1 Register"
|
|
bitfld.long 0x00 28.--31. " USCH[7] ,User sequence number 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 24.--27. " [6] ,User sequence number 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 20.--23. " [5] ,User sequence number 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--19. " [4] ,User sequence number 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. " [3] ,User sequence number 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 8.--11. " [2] ,User sequence number 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 4.--7. " [1] ,User sequence number 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 0.--3. " [0] ,User sequence number 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
line.long 0x04 "SEQ2R,AFEC Channel Sequence 2 Register"
|
|
sif !cpuis("ATSAME7*")
|
|
bitfld.long 0x04 28.--31. " USCH[15] ,User sequence number 15" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 24.--27. " [14] ,User sequence number 14" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 20.--23. " [13] ,User sequence number 13" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 16.--19. " [12] ,User sequence number 12" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x04 12.--15. " USCH[11] ,User sequence number 11" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 8.--11. " [10] ,User sequence number 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 4.--7. " [9] ,User sequence number 9" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 0.--3. " [8] ,User sequence number 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "SEQ1R,AFEC Channel Sequence 1 Register"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SEQ2R,AFEC Channel Sequence 2 Register"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CHSR_SET/CLR,AFEC Channel Status Set/Clear Register"
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " CH[11] ,Channel 11 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,Channel 10 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,Channel 9 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,Channel 8 status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,Channel 7 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,Channel 6 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,Channel 5 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,Channel 4 status" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,Channel 3 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,Channel 2 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,Channel 1 status" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,Channel 0 status" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,AFEC Mode Register"
|
|
bitfld.long 0x00 31. " USEQ ,User sequence enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28.--29. " TRANSFER ,Transfer period" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " TRACKTIM ,Tracking time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " ONE ,Must be one" ",1"
|
|
newline
|
|
bitfld.long 0x00 16.--19. " STARTUP ,Start-up time" "0 periods,8 periods,16 periods,24 periods,64 periods,80 periods,96 periods,112 periods,512 periods,576 periods,640 periods,704 periods,768 periods,832 periods,896 periods,960 periods"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRESCAL ,Prescaler rate selection"
|
|
bitfld.long 0x00 7. " FREERUN ,Free run mode" "Off,On"
|
|
bitfld.long 0x00 6. " FWUP ,Fast wake-up" "Off,On"
|
|
newline
|
|
bitfld.long 0x00 5. " SLEEP ,Sleep mode" "Normal,Sleep"
|
|
bitfld.long 0x00 1.--3. " TRGSEL ,Trigger selection" "TRIG0,TRIG1,TRIG2,TRIG3,TRIG4,TRIG5,TRIG6,?..."
|
|
bitfld.long 0x00 0. " TRGEN ,Trigger enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40064000+0x08))&0x200)==0x00)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "EMR,AFEC Extended Mode Register"
|
|
bitfld.long 0x00 28.--29. " SIGNMODE ,Sign mode" "SE_UNSG_DF_SIGN,SE_SIGN_DF_UNSG,ALL_UNSIGNED,ALL_SIGNED"
|
|
bitfld.long 0x00 25. " STM ,Single trigger mode" "Multiple triggers,Single trigger"
|
|
bitfld.long 0x00 24. " TAG ,TAG of the LDCR" "CHNB cleared,CHNB appended"
|
|
sif cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 16.--18. " RES ,Resolution" "12 bits/1,10-bits/1,13 bits/4,14 bits/16,15 bits/64,16 bits/256,?..."
|
|
else
|
|
bitfld.long 0x00 16.--18. " RES ,Resolution" "12 bits/1,13 bits/4,14 bits/16,15 bits/64,16 bits/256,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 12.--13. " CMPFILTER ,Compare event filtering" "0,1,2,3"
|
|
bitfld.long 0x00 9. " CMPALL ,Compare all channels" "No,Yes"
|
|
bitfld.long 0x00 3.--7. " CMPSEL ,Comparison selected channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison mode" "Low,High,In,Out"
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "EMR,AFEC Extended Mode Register"
|
|
bitfld.long 0x00 28.--29. " SIGNMODE ,Sign mode" "SE_UNSG_DF_SIGN,SE_SIGN_DF_UNSG,ALL_UNSIGNED,ALL_SIGNED"
|
|
bitfld.long 0x00 25. " STM ,Single trigger mode" "Multiple triggers,Single trigger"
|
|
bitfld.long 0x00 24. " TAG ,TAG of the LDCR" "CHNB cleared,CHNB appended"
|
|
sif cpuis("ATSAMS7*")
|
|
bitfld.long 0x00 16.--18. " RES ,Resolution" "12 bits/1,10-bits/1,13 bits/4,14 bits/16,15 bits/64,16 bits/256,?..."
|
|
else
|
|
bitfld.long 0x00 16.--18. " RES ,Resolution" "12 bits/1,13 bits/4,14 bits/16,15 bits/64,16 bits/256,?..."
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 12.--13. " CMPFILTER ,Compare event filtering" "0,1,2,3"
|
|
bitfld.long 0x00 9. " CMPALL ,Compare all channels" "No,Yes"
|
|
bitfld.long 0x00 3.--7. " CMPSEL ,Comparison selected channel" "No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect,No effect"
|
|
bitfld.long 0x00 0.--1. " CMPMODE ,Comparison mode" "Low,High,In,Out"
|
|
endif
|
|
if (((per.l(ad:0x40064000+0x04))&0x80000000)==0x80000000)
|
|
rgroup.long 0x0C++0x07
|
|
line.long 0x00 "SEQ1R,AFEC Channel Sequence 1 Register"
|
|
bitfld.long 0x00 28.--31. " USCH[7] ,User sequence number 7" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 24.--27. " [6] ,User sequence number 6" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 20.--23. " [5] ,User sequence number 5" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 16.--19. " [4] ,User sequence number 4" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--15. " [3] ,User sequence number 3" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 8.--11. " [2] ,User sequence number 2" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 4.--7. " [1] ,User sequence number 1" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x00 0.--3. " [0] ,User sequence number 0" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
line.long 0x04 "SEQ2R,AFEC Channel Sequence 2 Register"
|
|
bitfld.long 0x04 28.--31. " USCH[15] ,User sequence number 15" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 24.--27. " [14] ,User sequence number 14" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 20.--23. " [13] ,User sequence number 13" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 16.--19. " [12] ,User sequence number 12" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--15. " [11] ,User sequence number 11" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 8.--11. " [10] ,User sequence number 10" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 4.--7. " [9] ,User sequence number 9" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
bitfld.long 0x04 0.--3. " [8] ,User sequence number 8" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
else
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "SEQ1R,AFEC Channel Sequence 1 Register"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "SEQ2R,AFEC Channel Sequence 2 Register"
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "CHSR,AFEC Channel Status Register"
|
|
bitfld.long 0x00 11. " CH[11] ,Channel 11 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Channel 10 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Channel 9 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Channel 8 status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Channel 7 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Channel 6 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Channel 5 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Channel 4 status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Channel 3 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Channel 2 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Channel 1 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Channel 0 status" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
hgroup.long 0x20++0x03
|
|
hide.long 0x00 "LCDR,AFEC Last Converted Data Register"
|
|
in
|
|
newline
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,AFEC Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 30. -0x08 30. -0x04 30. " TEMPCHG ,Temperature change interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 26. -0x08 26. -0x04 26. " COMPE ,Comparison event interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 25. -0x08 25. -0x04 25. " GOVRE ,General overrun error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 24. -0x08 24. -0x04 24. " DRDY ,Data ready interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 11. -0x08 11. -0x04 11. " EOC[11] ,End of conversion interrupt mask 11" "Masked,Not masked"
|
|
setclrfld.long 0x00 10. -0x08 10. -0x04 10. " [10] ,End of conversion interrupt mask 10" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " [9] ,End of conversion interrupt mask 9" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " [8] ,End of conversion interrupt mask 8" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 7. -0x08 7. -0x04 7. " [7] ,End of conversion interrupt mask 7" "Masked,Not masked"
|
|
setclrfld.long 0x00 6. -0x08 6. -0x04 6. " [6] ,End of conversion interrupt mask 6" "Masked,Not masked"
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " [5] ,End of conversion interrupt mask 5" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " [4] ,End of conversion interrupt mask 4" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " [3] ,End of conversion interrupt mask 3" "Masked,Not masked"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " [2] ,End of conversion interrupt mask 2" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " [1] ,End of conversion interrupt mask 1" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " [0] ,End of conversion interrupt mask 0" "Masked,Not masked"
|
|
newline
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "ISR,AFEC Interrupt Status Register"
|
|
in
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "OVER,AFEC Overrun Status Register"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x40064000+0xE4)&0x01)==0x00)
|
|
group.long 0x50++0x07
|
|
line.long 0x00 "CWR,AFEC Compare Window Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGHTHRES ,High threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOWTHRES ,Low threshold"
|
|
line.long 0x04 "CGR,AFEC Channel Gain Register"
|
|
bitfld.long 0x04 22.--23. " GAIN[11] ,Gain for channel 11" "1,2,4,4"
|
|
bitfld.long 0x04 20.--21. " [10] ,Gain for channel 10" "1,2,4,4"
|
|
bitfld.long 0x04 18.--19. " [9] ,Gain for channel 9" "1,2,4,4"
|
|
bitfld.long 0x04 16.--17. " [8] ,Gain for channel 8" "1,2,4,4"
|
|
newline
|
|
bitfld.long 0x04 14.--15. " [7] ,Gain for channel 7" "1,2,4,4"
|
|
bitfld.long 0x04 12.--13. " [6] ,Gain for channel 6" "1,2,4,4"
|
|
bitfld.long 0x04 10.--11. " [5] ,Gain for channel 5" "1,2,4,4"
|
|
bitfld.long 0x04 8.--9. " [4] ,Gain for channel 4" "1,2,4,4"
|
|
newline
|
|
bitfld.long 0x04 6.--7. " [3] ,Gain for channel 3" "1,2,4,4"
|
|
bitfld.long 0x04 4.--5. " [2] ,Gain for channel 2" "1,2,4,4"
|
|
bitfld.long 0x04 2.--3. " [1] ,Gain for channel 1" "1,2,4,4"
|
|
bitfld.long 0x04 0.--1. " [0] ,Gain for channel 0" "1,2,4,4"
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "DIFFR,AFEC Channel Differential Register"
|
|
bitfld.long 0x00 11. " DIFF[11] ,Differential inputs for channel 11" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 10. " [10] ,Differential inputs for channel 10" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 9. " [9] ,Differential inputs for channel 9" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 8. " [8] ,Differential inputs for channel 8" "Single-ended,Fully-differential"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Differential inputs for channel 7" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 6. " [6] ,Differential inputs for channel 6" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 5. " [5] ,Differential inputs for channel 5" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 4. " [4] ,Differential inputs for channel 4" "Single-ended,Fully-differential"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Differential inputs for channel 3" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 2. " [2] ,Differential inputs for channel 2" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 1. " [1] ,Differential inputs for channel 1" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 0. " [0] ,Differential inputs for channel 0" "Single-ended,Fully-differential"
|
|
line.long 0x04 "CSELR,AFEC Channel Selection Register"
|
|
bitfld.long 0x04 0.--3. " CSEL ,Channel selection" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
else
|
|
rgroup.long 0x50++0x07
|
|
line.long 0x00 "CWR,AFEC Compare Window Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " HIGHTHRES ,High threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " LOWTHRES ,Low threshold"
|
|
line.long 0x04 "CGR,AFEC Channel Gain Register"
|
|
bitfld.long 0x04 22.--23. " GAIN[11] ,Gain for channel 11" "1,2,4,4"
|
|
bitfld.long 0x04 20.--21. " [10] ,Gain for channel 10" "1,2,4,4"
|
|
bitfld.long 0x04 18.--19. " [9] ,Gain for channel 9" "1,2,4,4"
|
|
bitfld.long 0x04 16.--17. " [8] ,Gain for channel 8" "1,2,4,4"
|
|
newline
|
|
bitfld.long 0x04 14.--15. " [7] ,Gain for channel 7" "1,2,4,4"
|
|
bitfld.long 0x04 12.--13. " [6] ,Gain for channel 6" "1,2,4,4"
|
|
bitfld.long 0x04 10.--11. " [5] ,Gain for channel 5" "1,2,4,4"
|
|
bitfld.long 0x04 8.--9. " [4] ,Gain for channel 4" "1,2,4,4"
|
|
newline
|
|
bitfld.long 0x04 6.--7. " [3] ,Gain for channel 3" "1,2,4,4"
|
|
bitfld.long 0x04 4.--5. " [2] ,Gain for channel 2" "1,2,4,4"
|
|
bitfld.long 0x04 2.--3. " [1] ,Gain for channel 1" "1,2,4,4"
|
|
bitfld.long 0x04 0.--1. " [0] ,Gain for channel 0" "1,2,4,4"
|
|
rgroup.long 0x60++0x07
|
|
line.long 0x00 "DIFFR,AFEC Channel Differential Register"
|
|
bitfld.long 0x00 11. " DIFF[11] ,Differential inputs for channel 11" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 10. " [10] ,Differential inputs for channel 10" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 9. " [9] ,Differential inputs for channel 9" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 8. " [8] ,Differential inputs for channel 8" "Single-ended,Fully-differential"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Differential inputs for channel 7" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 6. " [6] ,Differential inputs for channel 6" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 5. " [5] ,Differential inputs for channel 5" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 4. " [4] ,Differential inputs for channel 4" "Single-ended,Fully-differential"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Differential inputs for channel 3" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 2. " [2] ,Differential inputs for channel 2" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 1. " [1] ,Differential inputs for channel 1" "Single-ended,Fully-differential"
|
|
bitfld.long 0x00 0. " [0] ,Differential inputs for channel 0" "Single-ended,Fully-differential"
|
|
line.long 0x04 "CSELR,AFEC Channel Selection Register"
|
|
bitfld.long 0x04 0.--3. " CSEL ,Channel selection" "0,1,2,3,4,5,6,7,8,9,10,11,?..."
|
|
endif
|
|
newline
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "CDR,AFEC Channel Data Register"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x40064000+0xE4)&0x01)==0x00)
|
|
sif cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "COCR,AFEC Channel Offset Compensation Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " AOFF ,Analog offset"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "COCR,AFEC Channel Offset Compensation Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " AOFF ,Analog offset"
|
|
endif
|
|
if (((per.l(ad:0x40064000+0x04))&0x01)==0x01)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TEMPMR,AFEC Temperature Sensor Mode Register"
|
|
bitfld.long 0x00 4.--5. " TEMPCMPMOD ,Temperature comparison mode" "Low,High,In,Out"
|
|
bitfld.long 0x00 0. " RTCT ,Temperature sensor RTC trigger mode" "Not triggered,Triggered"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TEMPMR,AFEC Temperature Sensor Mode Register"
|
|
bitfld.long 0x00 4.--5. " TEMPCMPMOD ,Temperature comparison mode" "Low,High,In,Out"
|
|
bitfld.long 0x00 0. " RTCT ,Temperature sensor RTC trigger mode" "Not triggered,?..."
|
|
endif
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TEMPCWR,AFEC Temperature Compare Window Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " THIGHTHRES ,Temperature high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " TLOWTHRES ,Temperature low threshold"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "ACR,AFEC Analog Control Register"
|
|
bitfld.long 0x00 8.--9. " IBCTL ,AFE bias current control" "0,1,2,3"
|
|
bitfld.long 0x00 3. " PGA1EN ,PGA1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PGA0EN ,PGA0 enable" "Disabled,Enabled"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SHMR,AFEC Sample & Hold Mode Register"
|
|
bitfld.long 0x00 11. " DUAL[11] ,Dual sample & hold for channel 11" "Single,Dual"
|
|
bitfld.long 0x00 10. " [10] ,Dual sample & hold for channel 10" "Single,Dual"
|
|
bitfld.long 0x00 9. " [9] ,Dual sample & hold for channel 9" "Single,Dual"
|
|
bitfld.long 0x00 8. " [8] ,Dual sample & hold for channel 8" "Single,Dual"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Dual sample & hold for channel 7" "Single,Dual"
|
|
bitfld.long 0x00 6. " [6] ,Dual sample & hold for channel 6" "Single,Dual"
|
|
bitfld.long 0x00 5. " [5] ,Dual sample & hold for channel 5" "Single,Dual"
|
|
bitfld.long 0x00 4. " [4] ,Dual sample & hold for channel 4" "Single,Dual"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Dual sample & hold for channel 3" "Single,Dual"
|
|
bitfld.long 0x00 2. " [2] ,Dual sample & hold for channel 2" "Single,Dual"
|
|
bitfld.long 0x00 1. " [1] ,Dual sample & hold for channel 1" "Single,Dual"
|
|
bitfld.long 0x00 0. " [0] ,Dual sample & hold for channel 0" "Single,Dual"
|
|
group.long 0xD0++0x0B
|
|
line.long 0x00 "COSR,AFEC Correction Select Register"
|
|
bitfld.long 0x00 0. " CSEL ,Sample & hold unit correction select" "0,1"
|
|
line.long 0x04 "CVR,AFEC Correction Values Register"
|
|
sif cpuis("ATSAMS7*")
|
|
hexmask.long.word 0x04 16.--31. 1. " GAINCORR ,Gain correction"
|
|
else
|
|
hexmask.long.word 0x04 16.--27. 1. " GAINCORR ,Gain correction"
|
|
endif
|
|
hexmask.long.word 0x04 0.--11. 1. " OFFSETCORR ,Offset correction"
|
|
line.long 0x08 "CECR,AFEC Channel Error Correction Register"
|
|
bitfld.long 0x08 11. " ECORR[11] ,Error correction enable for channel 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [10] ,Error correction enable for channel 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [9] ,Error correction enable for channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [8] ,Error correction enable for channel 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,Error correction enable for channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [6] ,Error correction enable for channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [5] ,Error correction enable for channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [4] ,Error correction enable for channel 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,Error correction enable for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Error correction enable for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [1] ,Error correction enable for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [0] ,Error correction enable for channel 0" "Disabled,Enabled"
|
|
else
|
|
sif cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "COCR,AFEC Channel Offset Compensation Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " AOFF ,Analog offset"
|
|
else
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "COCR,AFEC Channel Offset Compensation Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " AOFF ,Analog offset"
|
|
endif
|
|
if (((per.l(ad:0x40064000+0x04))&0x01)==0x01)
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "TEMPMR,AFEC Temperature Sensor Mode Register"
|
|
bitfld.long 0x00 4.--5. " TEMPCMPMOD ,Temperature comparison mode" "Low,High,In,Out"
|
|
bitfld.long 0x00 0. " RTCT ,Temperature sensor RTC trigger mode" "Not triggered,Triggered"
|
|
else
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "TEMPMR,AFEC Temperature Sensor Mode Register"
|
|
bitfld.long 0x00 4.--5. " TEMPCMPMOD ,Temperature comparison mode" "Low,High,In,Out"
|
|
bitfld.long 0x00 0. " RTCT ,Temperature sensor RTC trigger mode" "Not triggered,?..."
|
|
endif
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "TEMPCWR,AFEC Temperature Compare Window Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " THIGHTHRES ,Temperature high threshold"
|
|
hexmask.long.word 0x00 0.--15. 1. " TLOWTHRES ,Temperature low threshold"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ACR,AFEC Analog Control Register"
|
|
bitfld.long 0x00 8.--9. " IBCTL ,AFE bias current control" "0,1,2,3"
|
|
bitfld.long 0x00 3. " PGA1EN ,PGA1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PGA0EN ,PGA0 enable" "Disabled,Enabled"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "SHMR,AFEC Sample & Hold Mode Register"
|
|
bitfld.long 0x00 11. " DUAL[11] ,Dual sample & hold for channel 11" "Single,Dual"
|
|
bitfld.long 0x00 10. " [10] ,Dual sample & hold for channel 10" "Single,Dual"
|
|
bitfld.long 0x00 9. " [9] ,Dual sample & hold for channel 9" "Single,Dual"
|
|
bitfld.long 0x00 8. " [8] ,Dual sample & hold for channel 8" "Single,Dual"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Dual sample & hold for channel 7" "Single,Dual"
|
|
bitfld.long 0x00 6. " [6] ,Dual sample & hold for channel 6" "Single,Dual"
|
|
bitfld.long 0x00 5. " [5] ,Dual sample & hold for channel 5" "Single,Dual"
|
|
bitfld.long 0x00 4. " [4] ,Dual sample & hold for channel 4" "Single,Dual"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Dual sample & hold for channel 3" "Single,Dual"
|
|
bitfld.long 0x00 2. " [2] ,Dual sample & hold for channel 2" "Single,Dual"
|
|
bitfld.long 0x00 1. " [1] ,Dual sample & hold for channel 1" "Single,Dual"
|
|
bitfld.long 0x00 0. " [0] ,Dual sample & hold for channel 0" "Single,Dual"
|
|
rgroup.long 0xD0++0x0B
|
|
line.long 0x00 "COSR,AFEC Correction Select Register"
|
|
bitfld.long 0x00 0. " CSEL ,Sample & hold unit correction select" "0,1"
|
|
line.long 0x04 "CVR,AFEC Correction Values Register"
|
|
sif cpuis("ATSAMS7*")
|
|
hexmask.long.word 0x04 16.--31. 1. " GAINCORR ,Gain correction"
|
|
else
|
|
hexmask.long.word 0x04 16.--27. 1. " GAINCORR ,Gain correction"
|
|
endif
|
|
hexmask.long.word 0x04 0.--11. 1. " OFFSETCORR ,Offset correction"
|
|
line.long 0x08 "CECR,AFEC Channel Error Correction Register"
|
|
bitfld.long 0x08 11. " ECORR[11] ,Error correction enable for channel 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " [10] ,Error correction enable for channel 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " [9] ,Error correction enable for channel 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " [8] ,Error correction enable for channel 8" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,Error correction enable for channel 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " [6] ,Error correction enable for channel 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " [5] ,Error correction enable for channel 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " [4] ,Error correction enable for channel 4" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,Error correction enable for channel 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " [2] ,Error correction enable for channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " [1] ,Error correction enable for channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " [0] ,Error correction enable for channel 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,AFEC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protection KEY password"
|
|
bitfld.long 0x00 0. " WPEN ,Write protection enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,AFEC Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "DACC (Digital-to-Analog Converter Controller)"
|
|
base ad:0x40040000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,DACC Control Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software reset" "No effect,Reset"
|
|
if ((per.l(ad:0x40040000+0xE4)&0x01)==0x00)
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "MR,DACC Mode Register"
|
|
bitfld.long 0x00 24.--27. " PRESCALER ,Peripheral clock to DAC clock ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " DIFF ,Differential mode" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("ATSAMS70*")||cpuis("ATSAME70*")
|
|
bitfld.long 0x00 5. " ZERO ,Must always be written to 0" "0,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 4. " WORD ,Word transfer mode" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("ATSAMV7?J*")&&!cpuis("ATSAMS70J*")&&!cpuis("ATSAME70J*")
|
|
bitfld.long 0x00 1. " MAXS1 ,Max speed mode for channel 1" "TRIG_EVENT,MAXIMUM"
|
|
bitfld.long 0x00 0. " MAXS0 ,Max speed mode for channel 0" "TRIG_EVENT,MAXIMUM"
|
|
else
|
|
bitfld.long 0x00 0. " MAXS0 ,Max speed mode for channel 0" "TRIG_EVENT,MAXIMUM"
|
|
endif
|
|
line.long 0x04 "TRIGR,DACC Trigger Register"
|
|
sif !cpuis("ATSAMV7?J*")&&!cpuis("ATSAMS70J*")&&!cpuis("ATSAME70J*")
|
|
bitfld.long 0x04 20.--22. " OSR1 ,Over sampling ratio of channel 1" "1,2,4,8,16,32,?..."
|
|
bitfld.long 0x04 16.--18. " OSR0 ,Over sampling ratio of channel 0" "1,2,4,8,16,32,?..."
|
|
bitfld.long 0x04 8.--10. " TRGSEL1 ,Trigger selection of channel 1" "TC0 output,TC1 output,TC2 output,PWM0 event 0,PWM0 event 1,PWM1 event 0,PWM1 event 1,?..."
|
|
newline
|
|
bitfld.long 0x04 4.--6. " TRGSEL0 ,Trigger selection of channel 0" "TC0 output,TC1 output,TC2 output,PWM0 event 0,PWM0 event 1,PWM1 event 0,PWM1 event 1,?..."
|
|
bitfld.long 0x04 1. " TRGEN1 ,Trigger enable of channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TRGEN0 ,Trigger enable of channel 0" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x04 16.--18. " OSR0 ,Over sampling ratio of channel 0" "1,2,4,8,16,32,?..."
|
|
bitfld.long 0x04 4.--6. " TRGSEL0 ,Trigger selection of channel 0" "TC0 output,TC1 output,TC2 output,PWM0 event 0,PWM0 event 1,PWM1 event 0,PWM1 event 1,?..."
|
|
bitfld.long 0x04 0. " TRGEN0 ,Trigger enable of channel 0" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CHSR,DACC Channel Status Register"
|
|
sif !cpuis("ATSAMV7?J*")&&!cpuis("ATSAMS70J*")&&!cpuis("ATSAME70J*")
|
|
rbitfld.long 0x00 9. " DACRDY1 ,DAC 1 ready flag" "Not ready,Ready"
|
|
rbitfld.long 0x00 8. " DACRDY0 ,DAC 0 ready flag" "Not ready,Ready"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " CH1_SET/CLR ,Channel 1 status set/clear" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CH0_SET/CLR ,Channel 0 status set/clear" "Disabled,Enabled"
|
|
else
|
|
rbitfld.long 0x00 8. " DACRDY0 ,DAC 0 ready flag" "Not ready,Ready"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CH0_SET/CLR ,Channel 0 status set/clear" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
rgroup.long 0x04++0x07
|
|
line.long 0x00 "MR,DACC Mode Register"
|
|
bitfld.long 0x00 24.--27. " PRESCALER ,Peripheral clock to DAC clock ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " DIFF ,Differential mode" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("ATSAMS70*")||cpuis("ATSAME70*")
|
|
bitfld.long 0x00 5. " ZERO ,Must always be written to 0" "0,?..."
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 4. " WORD ,Word transfer mode" "Disabled,Enabled"
|
|
newline
|
|
sif !cpuis("ATSAMV7?J*")&&!cpuis("ATSAMS70J*")&&!cpuis("ATSAME70J*")
|
|
bitfld.long 0x00 1. " MAXS1 ,Max speed mode for channel 1" "TRIG_EVENT,MAXIMUM"
|
|
bitfld.long 0x00 0. " MAXS0 ,Max speed mode for channel 0" "TRIG_EVENT,MAXIMUM"
|
|
else
|
|
bitfld.long 0x00 0. " MAXS0 ,Max speed mode for channel 0" "TRIG_EVENT,MAXIMUM"
|
|
endif
|
|
line.long 0x04 "TRIGR,DACC Trigger Register"
|
|
sif !cpuis("ATSAMV7?J*")&&!cpuis("ATSAMS70J*")&&!cpuis("ATSAME70J*")
|
|
bitfld.long 0x04 20.--22. " OSR1 ,Over sampling ratio of channel 1" "1,2,4,8,16,32,?..."
|
|
bitfld.long 0x04 16.--18. " OSR0 ,Over sampling ratio of channel 0" "1,2,4,8,16,32,?..."
|
|
bitfld.long 0x04 8.--10. " TRGSEL1 ,Trigger selection of channel 1" "TC0 output,TC1 output,TC2 output,PWM0 event 0,PWM0 event 1,PWM1 event 0,PWM1 event 1,?..."
|
|
newline
|
|
bitfld.long 0x04 4.--6. " TRGSEL0 ,Trigger selection of channel 0" "TC0 output,TC1 output,TC2 output,PWM0 event 0,PWM0 event 1,PWM1 event 0,PWM1 event 1,?..."
|
|
bitfld.long 0x04 1. " TRGEN1 ,Trigger enable of channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TRGEN0 ,Trigger enable of channel 0" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x04 16.--18. " OSR0 ,Over sampling ratio of channel 0" "1,2,4,8,16,32,?..."
|
|
bitfld.long 0x04 4.--6. " TRGSEL0 ,Trigger selection of channel 0" "TC0 output,TC1 output,TC2 output,PWM0 event 0,PWM0 event 1,PWM1 event 0,PWM1 event 1,?..."
|
|
bitfld.long 0x04 0. " TRGEN0 ,Trigger enable of channel 0" "Disabled,Enabled"
|
|
endif
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "CHSR,DACC Channel Status Register"
|
|
sif !cpuis("ATSAMV7?J*")&&!cpuis("ATSAMS70J*")&&!cpuis("ATSAME70J*")
|
|
bitfld.long 0x00 9. " DACRDY1 ,DAC 1 ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 8. " DACRDY0 ,DAC 0 ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 1. " CH1 ,Channel 1 status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CH0 ,Channel 0 status" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 8. " DACRDY0 ,DAC 0 ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " CH0 ,Channel 0 status" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "CDR0,DACC Conversion Data Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " DATA1 ,Data to convert for channel 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA0 ,Data to convert for channel 0"
|
|
sif !cpuis("ATSAMV7?J*")&&!cpuis("ATSAMS70J*")&&!cpuis("ATSAME70J*")
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "CDR1,DACC Conversion Data Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " DATA1 ,Data to convert for channel 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA0 ,Data to convert for channel 1"
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,DACC Interrupt Mask Register"
|
|
sif cpuis("ATSAMS70J*")
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " EOC0 ,End of conversion interrupt mask of channel 0" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXRDY0 ,Transmit ready interrupt mask of channel 0" "Masked,Not masked"
|
|
elif cpuis("ATSAMS7*")
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " EOC1 ,End of conversion interrupt mask of channel 1" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " EOC0 ,End of conversion interrupt mask of channel 0" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY1 ,End of conversion interrupt mask of channel 1" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXRDY0 ,Transmit ready interrupt mask of channel 0" "Masked,Not masked"
|
|
elif !cpuis("ATSAMV7?J*")&&!cpuis("ATSAME70*")
|
|
setclrfld.long 0x00 13. -0x08 13. -0x04 13. " TXBUFE1 ,Transmit buffer empty interrupt mask of channel 1" "Masked,Not masked"
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " TXBUFE0 ,Transmit buffer empty interrupt mask of channel 0" "Masked,Not masked"
|
|
setclrfld.long 0x00 9. -0x08 9. -0x04 9. " ENDTX1 ,End of transmit buffer interrupt mask of channel 1" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ENDTX0 ,End of transmit buffer interrupt mask of channel 0" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 5. -0x08 5. -0x04 5. " EOC1 ,End of conversion interrupt mask of channel 1" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " EOC0 ,End of conversion interrupt mask of channel 0" "Masked,Not masked"
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " TXRDY1 ,End of conversion interrupt mask of channel 1" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXRDY0 ,Transmit ready interrupt mask of channel 0" "Masked,Not masked"
|
|
else
|
|
setclrfld.long 0x00 12. -0x08 12. -0x04 12. " TXBUFE0 ,Transmit buffer empty interrupt mask of channel 0" "Masked,Not masked"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " ENDTX0 ,End of transmit buffer interrupt mask of channel 0" "Masked,Not masked"
|
|
setclrfld.long 0x00 4. -0x08 4. -0x04 4. " EOC0 ,End of conversion interrupt mask of channel 0" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXRDY0 ,Transmit ready interrupt mask of channel 0" "Masked,Not masked"
|
|
endif
|
|
newline
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "ISR,DACC Interrupt Status Register"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x40040000+0xE4)&0x01)==0x00)
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "ACR,DACC Analog Current Register"
|
|
sif !cpuis("ATSAMV7?J*")&&!cpuis("ATSAMS70J*")&&!cpuis("ATSAME70J*")
|
|
bitfld.long 0x00 2.--3. " IBCTLCH1 ,Analog output current control 1" "0.01 mA,0.1 mA,,0.2 mA"
|
|
bitfld.long 0x00 0.--1. " IBCTLCH0 ,Analog output current control 0" "0.01 mA,0.1 mA,,0.2 mA"
|
|
else
|
|
bitfld.long 0x00 0.--1. " IBCTLCH0 ,Analog output current control 0" "0.01 mA,0.1 mA,,0.2 mA"
|
|
endif
|
|
else
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ACR,DACC Analog Current Register"
|
|
sif !cpuis("ATSAMV7?J*")&&!cpuis("ATSAMS70J*")&&!cpuis("ATSAME70J*")
|
|
bitfld.long 0x00 2.--3. " IBCTLCH1 ,Analog output current control 1" "0.01 mA,0.1 mA,,0.2 mA"
|
|
bitfld.long 0x00 0.--1. " IBCTLCH0 ,Analog output current control 0" "0.01 mA,0.1 mA,,0.2 mA"
|
|
else
|
|
bitfld.long 0x00 0.--1. " IBCTLCH0 ,Analog output current control 0" "0.01 mA,0.1 mA,,0.2 mA"
|
|
endif
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,DACC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,DACC Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "ACC (Analog Comparator Controller)"
|
|
base ad:0x40044000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,ACC Control Register"
|
|
bitfld.long 0x00 0. " SWRST ,Software reset" "No effect,Reset"
|
|
if ((per.l(ad:0x40044000+0xE4)&0x01)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,ACC Mode Register"
|
|
bitfld.long 0x00 14. " FE ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SELFS ,Selection of fault source" "CE,Analog comparator"
|
|
bitfld.long 0x00 12. " INV ,Invert comparator output" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " EDGETYP ,EDGE TYPE" "Rising,Falling,Any,?..."
|
|
newline
|
|
bitfld.long 0x00 8. " ACEN ,Analog comparator enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
bitfld.long 0x00 4.--6. " SELPLUS ,Selection for PLUS comparator input" "AFE0_AD0,AFE0_AD1,AFE0_AD2,AFE0_AD3,AFE0_AD4,AFE0_AD5,AFE1_AD0,AFE1_AD1"
|
|
bitfld.long 0x00 0.--2. " SELMINUS ,Selection for MINUS comparator input" "TS,VREFP,DAC0,DAC1,AFE0_AD0,AFE0_AD1,AFE0_AD2,AFE0_AD3"
|
|
else
|
|
bitfld.long 0x00 4.--6. " SELPLUS ,Selection for PLUS comparator input" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7"
|
|
bitfld.long 0x00 0.--2. " SELMINUS ,Selection for MINUS comparator input" "TS,ADVREF,DAC0,DAC1,AD0,AD1,AD2,AD3"
|
|
endif
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "MR,ACC Mode Register"
|
|
bitfld.long 0x00 14. " FE ,Fault enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SELFS ,Selection of fault source" "CE,Analog comparator"
|
|
bitfld.long 0x00 12. " INV ,Invert comparator output" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " EDGETYP ,EDGE TYPE" "Rising,Falling,Any,?..."
|
|
newline
|
|
bitfld.long 0x00 8. " ACEN ,Analog comparator enable" "Disabled,Enabled"
|
|
newline
|
|
sif cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
bitfld.long 0x00 4.--6. " SELPLUS ,Selection for PLUS comparator input" "AFE0_AD0,AFE0_AD1,AFE0_AD2,AFE0_AD3,AFE0_AD4,AFE0_AD5,AFE1_AD0,AFE1_AD1"
|
|
bitfld.long 0x00 0.--2. " SELMINUS ,Selection for MINUS comparator input" "TS,VREFP,DAC0,DAC1,AFE0_AD0,AFE0_AD1,AFE0_AD2,AFE0_AD3"
|
|
else
|
|
bitfld.long 0x00 4.--6. " SELPLUS ,Selection for PLUS comparator input" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7"
|
|
bitfld.long 0x00 0.--2. " SELMINUS ,Selection for MINUS comparator input" "TS,ADVREF,DAC0,DAC1,AD0,AD1,AD2,AD3"
|
|
endif
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IMR_SET/CLR,ACC Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " CE ,Comparison edge" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "ISR,ACC Interrupt Status Register"
|
|
in
|
|
newline
|
|
if ((per.l(ad:0x40044000+0xE4)&0x01)==0x00)
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "ACR,ACC Analog Control Register"
|
|
bitfld.long 0x00 1.--2. " HYST ,Hysteresis selection" "0mV,15-50mV,15-50mV,30-90mV"
|
|
bitfld.long 0x00 0. " ISEL ,Current selection" "Low power,High speed"
|
|
else
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "ACR,ACC Analog Control Register"
|
|
bitfld.long 0x00 1.--2. " HYST ,Hysteresis selection" "0mV,15-50mV,15-50mV,30-90mV"
|
|
bitfld.long 0x00 0. " ISEL ,Current selection" "Low power,High speed"
|
|
endif
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "WPMR,ACC Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " WPKEY ,Write protect KEY"
|
|
bitfld.long 0x00 0. " WPEN ,Write protect enable" "Disabled,Enabled"
|
|
newline
|
|
hgroup.long 0xE8++0x03
|
|
hide.long 0x00 "WPSR,ACC Write Protect Status Register"
|
|
in
|
|
width 0x0B
|
|
tree.end
|
|
tree "ICM (Integrity Check Monitor)"
|
|
base ad:0x40048000
|
|
width 13.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CFG,ICM Configuration Register"
|
|
bitfld.long 0x00 13.--15. " UALGO ,User SHA algorithm" "SHA1,SHA256,,,SHA224,?..."
|
|
bitfld.long 0x00 12. " UIHASH ,User initial hash value" "Not programmable,Programmable"
|
|
bitfld.long 0x00 9. " DUALBUFF ,Dual input buffer" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCD ,Automatic switch to compare digest" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " BBC ,Bus burden control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 2. " SLBDIS ,Secondary list branching disable" "Permitted,Forbidden"
|
|
bitfld.long 0x00 1. " EOMDIS ,End of monitoring disable" "Permitted,Forbidden"
|
|
bitfld.long 0x00 0. " WBDIS ,Write back disable" "Permitted,Forbidden"
|
|
if (((per.l((ad:0x40048000+0x08)))&0xF000)==0x00)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CTRL,ICM Control Register"
|
|
bitfld.long 0x00 15. " RMEN[3] ,Region 3 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 14. " [2] ,Region 2 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 13. " [1] ,Region 1 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 12. " [0] ,Region 0 monitoring enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 11. " RMDIS[3] ,Region 3 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 10. " [2] ,Region 2 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 9. " [1] ,Region 1 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " [0] ,Region 0 monitoring disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 7. " REHASH[3] ,Recompute internal hash in region 3" "No effect,Recompute"
|
|
bitfld.long 0x00 6. " REHASH[2] ,Recompute internal hash in region 2" "No effect,Recompute"
|
|
bitfld.long 0x00 5. " REHASH[1] ,Recompute internal hash in region 1" "No effect,Recompute"
|
|
bitfld.long 0x00 4. " REHASH[0] ,Recompute internal hash in region 0" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 2. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " DISABLE ,ICM disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ENABLE ,ICM enable" "No effect,Enable"
|
|
elif (((per.l((ad:0x40048000+0x08)))&0xF000)==0x1000)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CTRL,ICM Control Register"
|
|
bitfld.long 0x00 15. " RMEN[3] ,Region 3 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 14. " [2] ,Region 2 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 13. " [1] ,Region 1 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 12. " [0] ,Region 0 monitoring enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 11. " RMDIS[3] ,Region 3 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 10. " [2] ,Region 2 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 9. " [1] ,Region 1 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " [0] ,Region 0 monitoring disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 7. " REHASH[3] ,Recompute internal hash in region 3" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 6. " REHASH[2] ,Recompute internal hash in region 2" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 5. " REHASH[1] ,Recompute internal hash in region 1" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 2. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " DISABLE ,ICM disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ENABLE ,ICM enable" "No effect,Enable"
|
|
elif (((per.l((ad:0x40048000+0x08)))&0xF000)==0x2000)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CTRL,ICM Control Register"
|
|
bitfld.long 0x00 15. " RMEN[3] ,Region 3 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 14. " [2] ,Region 2 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 13. " [1] ,Region 1 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 12. " [0] ,Region 0 monitoring enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 11. " RMDIS[3] ,Region 3 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 10. " [2] ,Region 2 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 9. " [1] ,Region 1 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " [0] ,Region 0 monitoring disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 7. " REHASH[3] ,Recompute internal hash in region 3" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 6. " REHASH[2] ,Recompute internal hash in region 2" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 4. " REHASH[0] ,Recompute internal hash in region 0" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 2. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " DISABLE ,ICM disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ENABLE ,ICM enable" "No effect,Enable"
|
|
elif (((per.l((ad:0x40048000+0x08)))&0xF000)==0x3000)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CTRL,ICM Control Register"
|
|
bitfld.long 0x00 15. " RMEN[3] ,Region 3 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 14. " [2] ,Region 2 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 13. " [1] ,Region 1 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 12. " [0] ,Region 0 monitoring enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 11. " RMDIS[3] ,Region 3 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 10. " [2] ,Region 2 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 9. " [1] ,Region 1 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " [0] ,Region 0 monitoring disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 7. " REHASH[3] ,Recompute internal hash in region 3" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 6. " REHASH[2] ,Recompute internal hash in region 2" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 2. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " DISABLE ,ICM disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ENABLE ,ICM enable" "No effect,Enable"
|
|
elif (((per.l((ad:0x40048000+0x08)))&0xF000)==0x4000)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CTRL,ICM Control Register"
|
|
bitfld.long 0x00 15. " RMEN[3] ,Region 3 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 14. " [2] ,Region 2 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 13. " [1] ,Region 1 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 12. " [0] ,Region 0 monitoring enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 11. " RMDIS[3] ,Region 3 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 10. " [2] ,Region 2 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 9. " [1] ,Region 1 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " [0] ,Region 0 monitoring disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 7. " REHASH[3] ,Recompute internal hash in region 3" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 5. " REHASH[1] ,Recompute internal hash in region 1" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 4. " REHASH[0] ,Recompute internal hash in region 0" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 2. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " DISABLE ,ICM disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ENABLE ,ICM enable" "No effect,Enable"
|
|
elif (((per.l((ad:0x40048000+0x08)))&0xF000)==0x5000)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CTRL,ICM Control Register"
|
|
bitfld.long 0x00 15. " RMEN[3] ,Region 3 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 14. " [2] ,Region 2 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 13. " [1] ,Region 1 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 12. " [0] ,Region 0 monitoring enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 11. " RMDIS[3] ,Region 3 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 10. " [2] ,Region 2 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 9. " [1] ,Region 1 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " [0] ,Region 0 monitoring disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 7. " REHASH[3] ,Recompute internal hash in region 3" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 5. " REHASH[1] ,Recompute internal hash in region 1" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 2. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " DISABLE ,ICM disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ENABLE ,ICM enable" "No effect,Enable"
|
|
elif (((per.l((ad:0x40048000+0x08)))&0xF000)==0x6000)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CTRL,ICM Control Register"
|
|
bitfld.long 0x00 15. " RMEN[3] ,Region 3 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 14. " [2] ,Region 2 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 13. " [1] ,Region 1 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 12. " [0] ,Region 0 monitoring enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 11. " RMDIS[3] ,Region 3 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 10. " [2] ,Region 2 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 9. " [1] ,Region 1 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " [0] ,Region 0 monitoring disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 7. " REHASH[3] ,Recompute internal hash in region 3" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 4. " REHASH[0] ,Recompute internal hash in region 0" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 2. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " DISABLE ,ICM disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ENABLE ,ICM enable" "No effect,Enable"
|
|
elif (((per.l((ad:0x40048000+0x08)))&0xF000)==0x7000)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CTRL,ICM Control Register"
|
|
bitfld.long 0x00 15. " RMEN[3] ,Region 3 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 14. " [2] ,Region 2 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 13. " [1] ,Region 1 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 12. " [0] ,Region 0 monitoring enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 11. " RMDIS[3] ,Region 3 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 10. " [2] ,Region 2 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 9. " [1] ,Region 1 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " [0] ,Region 0 monitoring disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 7. " REHASH[3] ,Recompute internal hash in region 3" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 2. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " DISABLE ,ICM disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ENABLE ,ICM enable" "No effect,Enable"
|
|
elif (((per.l((ad:0x40048000+0x08)))&0xF000)==0x8000)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CTRL,ICM Control Register"
|
|
bitfld.long 0x00 15. " RMEN[3] ,Region 3 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 14. " [2] ,Region 2 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 13. " [1] ,Region 1 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 12. " [0] ,Region 0 monitoring enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 11. " RMDIS[3] ,Region 3 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 10. " [2] ,Region 2 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 9. " [1] ,Region 1 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " [0] ,Region 0 monitoring disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 6. " REHASH[2] ,Recompute internal hash in region 2" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 5. " REHASH[1] ,Recompute internal hash in region 1" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 4. " REHASH[0] ,Recompute internal hash in region 0" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 2. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " DISABLE ,ICM disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ENABLE ,ICM enable" "No effect,Enable"
|
|
elif (((per.l((ad:0x40048000+0x08)))&0xF000)==0x9000)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CTRL,ICM Control Register"
|
|
bitfld.long 0x00 15. " RMEN[3] ,Region 3 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 14. " [2] ,Region 2 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 13. " [1] ,Region 1 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 12. " [0] ,Region 0 monitoring enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 11. " RMDIS[3] ,Region 3 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 10. " [2] ,Region 2 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 9. " [1] ,Region 1 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " [0] ,Region 0 monitoring disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 6. " REHASH[2] ,Recompute internal hash in region 2" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 5. " REHASH[1] ,Recompute internal hash in region 1" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 2. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " DISABLE ,ICM disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ENABLE ,ICM enable" "No effect,Enable"
|
|
elif (((per.l((ad:0x40048000+0x08)))&0xF000)==0xA000)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CTRL,ICM Control Register"
|
|
bitfld.long 0x00 15. " RMEN[3] ,Region 3 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 14. " [2] ,Region 2 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 13. " [1] ,Region 1 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 12. " [0] ,Region 0 monitoring enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 11. " RMDIS[3] ,Region 3 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 10. " [2] ,Region 2 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 9. " [1] ,Region 1 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " [0] ,Region 0 monitoring disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 6. " REHASH[2] ,Recompute internal hash in region 2" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 4. " REHASH[0] ,Recompute internal hash in region 0" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 2. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " DISABLE ,ICM disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ENABLE ,ICM enable" "No effect,Enable"
|
|
elif (((per.l((ad:0x40048000+0x08)))&0xF000)==0xB000)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CTRL,ICM Control Register"
|
|
bitfld.long 0x00 15. " RMEN[3] ,Region 3 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 14. " [2] ,Region 2 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 13. " [1] ,Region 1 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 12. " [0] ,Region 0 monitoring enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 11. " RMDIS[3] ,Region 3 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 10. " [2] ,Region 2 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 9. " [1] ,Region 1 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " [0] ,Region 0 monitoring disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 6. " REHASH[2] ,Recompute internal hash in region 2" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 2. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " DISABLE ,ICM disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ENABLE ,ICM enable" "No effect,Enable"
|
|
elif (((per.l((ad:0x40048000+0x08)))&0xF000)==0xC000)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CTRL,ICM Control Register"
|
|
bitfld.long 0x00 15. " RMEN[3] ,Region 3 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 14. " [2] ,Region 2 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 13. " [1] ,Region 1 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 12. " [0] ,Region 0 monitoring enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 11. " RMDIS[3] ,Region 3 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 10. " [2] ,Region 2 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 9. " [1] ,Region 1 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " [0] ,Region 0 monitoring disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 5. " REHASH[1] ,Recompute internal hash in region 1" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 4. " REHASH[0] ,Recompute internal hash in region 0" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 2. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " DISABLE ,ICM disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ENABLE ,ICM enable" "No effect,Enable"
|
|
elif (((per.l((ad:0x40048000+0x08)))&0xF000)==0xD000)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CTRL,ICM Control Register"
|
|
bitfld.long 0x00 15. " RMEN[3] ,Region 3 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 14. " [2] ,Region 2 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 13. " [1] ,Region 1 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 12. " [0] ,Region 0 monitoring enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 11. " RMDIS[3] ,Region 3 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 10. " [2] ,Region 2 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 9. " [1] ,Region 1 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " [0] ,Region 0 monitoring disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 5. " REHASH[1] ,Recompute internal hash in region 1" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 2. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " DISABLE ,ICM disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ENABLE ,ICM enable" "No effect,Enable"
|
|
elif (((per.l((ad:0x40048000+0x08)))&0xF000)==0xE000)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CTRL,ICM Control Register"
|
|
bitfld.long 0x00 15. " RMEN[3] ,Region 3 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 14. " [2] ,Region 2 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 13. " [1] ,Region 1 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 12. " [0] ,Region 0 monitoring enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 11. " RMDIS[3] ,Region 3 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 10. " [2] ,Region 2 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 9. " [1] ,Region 1 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " [0] ,Region 0 monitoring disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 4. " REHASH[0] ,Recompute internal hash in region 0" "No effect,Recompute"
|
|
newline
|
|
bitfld.long 0x00 2. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " DISABLE ,ICM disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ENABLE ,ICM enable" "No effect,Enable"
|
|
elif (((per.l((ad:0x40048000+0x08)))&0xF000)==0xF000)
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "CTRL,ICM Control Register"
|
|
bitfld.long 0x00 15. " RMEN[3] ,Region 3 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 14. " [2] ,Region 2 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 13. " [1] ,Region 1 monitoring enable" "No effect,Enable"
|
|
bitfld.long 0x00 12. " [0] ,Region 0 monitoring enable" "No effect,Enable"
|
|
newline
|
|
bitfld.long 0x00 11. " RMDIS[3] ,Region 3 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 10. " [2] ,Region 2 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 9. " [1] ,Region 1 monitoring disable" "No effect,Disable"
|
|
bitfld.long 0x00 8. " [0] ,Region 0 monitoring disable" "No effect,Disable"
|
|
newline
|
|
bitfld.long 0x00 2. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 1. " DISABLE ,ICM disable" "No effect,Disable"
|
|
bitfld.long 0x00 0. " ENABLE ,ICM enable" "No effect,Enable"
|
|
endif
|
|
sif !cpuis("ATSAMS7*")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SR,ICM Status Register"
|
|
bitfld.long 0x00 15. " RMDIS[3] ,Region 3 monitoring disabled status" "Activated,Deactivated"
|
|
bitfld.long 0x00 14. " [2] ,Region 2 monitoring disabled status" "Activated,Deactivated"
|
|
bitfld.long 0x00 13. " [1] ,Region 1 monitoring disabled status" "Activated,Deactivated"
|
|
bitfld.long 0x00 12. " [0] ,Region 0 monitoring disabled status" "Activated,Deactivated"
|
|
newline
|
|
bitfld.long 0x00 11. " RAWRMDIS[3] ,RAW region 3 monitoring disabled status" "Activated,Deactivated"
|
|
bitfld.long 0x00 10. " [2] ,RAW region 2 monitoring disabled status" "Activated,Deactivated"
|
|
bitfld.long 0x00 9. " [1] ,RAW region 1 monitoring disabled status" "Activated,Deactivated"
|
|
bitfld.long 0x00 8. " [0] ,RAW region 0 monitoring disabled status" "Activated,Deactivated"
|
|
newline
|
|
bitfld.long 0x00 0. " ENABLE ,ICM controller enable register" "Disabled,Enabled"
|
|
newline
|
|
else
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SR,ICM Status Register"
|
|
bitfld.long 0x00 15. " RMDIS[3] ,Region 3 monitoring disabled status" "Activated,Deactivated"
|
|
bitfld.long 0x00 14. " [2] ,Region 2 monitoring disabled status" "Activated,Deactivated"
|
|
bitfld.long 0x00 13. " [1] ,Region 1 monitoring disabled status" "Activated,Deactivated"
|
|
bitfld.long 0x00 12. " [0] ,Region 0 monitoring disabled status" "Activated,Deactivated"
|
|
newline
|
|
bitfld.long 0x00 11. " RAWRMDIS[3] ,RAW region 3 monitoring disabled status" "Activated,Deactivated"
|
|
bitfld.long 0x00 10. " [2] ,RAW region 2 monitoring disabled status" "Activated,Deactivated"
|
|
bitfld.long 0x00 9. " [1] ,RAW region 1 monitoring disabled status" "Activated,Deactivated"
|
|
bitfld.long 0x00 8. " [0] ,RAW region 0 monitoring disabled status" "Activated,Deactivated"
|
|
newline
|
|
bitfld.long 0x00 0. " ENABLE ,ICM controller enable register" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IMR_SET/CLR,ICM Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 24. -0x04 24. -0x08 24. " URAD ,Undefined register access detection interrupt mask" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 23. -0x04 23. -0x08 23. " RSU[3] ,Region status updated interrupt mask (for region 3)" "Masked,Unmasked"
|
|
setclrfld.long 0x00 22. -0x04 22. -0x08 22. " [2] ,Region status updated interrupt mask (for region 2)" "Masked,Unmasked"
|
|
setclrfld.long 0x00 21. -0x04 21. -0x08 21. " [1] ,Region status updated interrupt mask (for region 1)" "Masked,Unmasked"
|
|
setclrfld.long 0x00 20. -0x04 20. -0x08 20. " [0] ,Region status updated interrupt mask (for region 0)" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 19. -0x04 19. -0x08 19. " REC[3] ,Region end bit condition detected interrupt mask (for region 3)" "Masked,Unmasked"
|
|
setclrfld.long 0x00 18. -0x04 18. -0x08 18. " [2] ,Region end bit condition detected interrupt mask (for region 2)" "Masked,Unmasked"
|
|
setclrfld.long 0x00 17. -0x04 17. -0x08 17. " [1] ,Region end bit condition detected interrupt mask (for region 1)" "Masked,Unmasked"
|
|
setclrfld.long 0x00 16. -0x04 16. -0x08 16. " [0] ,Region end bit condition detected interrupt mask (for region 0)" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 15. -0x04 15. -0x08 15. " RWC[3] ,Region wrap condition detected interrupt mask (for region 3)" "Masked,Unmasked"
|
|
setclrfld.long 0x00 14. -0x04 14. -0x08 14. " [2] ,Region wrap condition detected interrupt mask (for region 2)" "Masked,Unmasked"
|
|
setclrfld.long 0x00 13. -0x04 13. -0x08 13. " [1] ,Region wrap condition detected interrupt mask (for region 1)" "Masked,Unmasked"
|
|
setclrfld.long 0x00 12. -0x04 12. -0x08 12. " [0] ,Region wrap condition detected interrupt mask (for region 0)" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 11. -0x04 11. -0x08 11. " RBE[3] ,Region bus error interrupt mask (for region 3)" "Masked,Unmasked"
|
|
setclrfld.long 0x00 10. -0x04 10. -0x08 10. " [2] ,Region bus error interrupt mask (for region 2)" "Masked,Unmasked"
|
|
setclrfld.long 0x00 9. -0x04 9. -0x08 9. " [1] ,Region bus error interrupt mask (for region 1)" "Masked,Unmasked"
|
|
setclrfld.long 0x00 8. -0x04 8. -0x08 8. " [0] ,Region bus error interrupt mask (for region 0)" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 7. -0x04 7. -0x08 7. " RDM[3] ,Region digest mismatch interrupt mask (for region 3)" "Masked,Unmasked"
|
|
setclrfld.long 0x00 6. -0x04 6. -0x08 6. " [2] ,Region digest mismatch interrupt mask (for region 2)" "Masked,Unmasked"
|
|
setclrfld.long 0x00 5. -0x04 5. -0x08 5. " [1] ,Region digest mismatch interrupt mask (for region 1)" "Masked,Unmasked"
|
|
setclrfld.long 0x00 4. -0x04 4. -0x08 4. " [0] ,Region digest mismatch interrupt mask (for region 0)" "Masked,Unmasked"
|
|
newline
|
|
setclrfld.long 0x00 3. -0x04 3. -0x08 3. " RHC[3] ,Region hash completed interrupt mask (for region 3)" "Masked,Unmasked"
|
|
setclrfld.long 0x00 2. -0x04 2. -0x08 2. " [2] ,Region hash completed interrupt mask (for region 2)" "Masked,Unmasked"
|
|
setclrfld.long 0x00 1. -0x04 1. -0x08 1. " [1] ,Region hash completed interrupt mask (for region 1)" "Masked,Unmasked"
|
|
setclrfld.long 0x00 0. -0x04 0. -0x08 0. " [0] ,Region hash completed interrupt mask (for region 0)" "Masked,Unmasked"
|
|
rgroup.long 0x1C++0x07
|
|
line.long 0x00 "ISR,ICM Interrupt Status Register"
|
|
bitfld.long 0x00 24. " URAD ,Undefined register access detection interrupt status" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 23. " RSU[3] ,Region status updated interrupt status (for region 3)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 22. " [2] ,Region status updated interrupt status (for region 2)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 21. " [1] ,Region status updated interrupt status (for region 1)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 20. " [0] ,Region status updated interrupt status (for region 0)" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 19. " REC[3] ,Region end bit condition detected interrupt status (for region 3)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 18. " [2] ,Region end bit condition detected interrupt status (for region 2)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 17. " [1] ,Region end bit condition detected interrupt status (for region 1)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " [0] ,Region end bit condition detected interrupt status (for region 0)" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 15. " RWC[3] ,Region wrap condition detected interrupt status (for region 3)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " [2] ,Region wrap condition detected interrupt status (for region 2)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 13. " [1] ,Region wrap condition detected interrupt status (for region 1)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " [0] ,Region wrap condition detected interrupt status (for region 0)" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 11. " RBE[3] ,Region bus error interrupt status (for region 3)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 10. " [2] ,Region bus error interrupt status (for region 2)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 9. " [1] ,Region bus error interrupt status (for region 1)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 8. " [0] ,Region bus error interrupt status (for region 0)" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 7. " RDM[3] ,Region digest mismatch interrupt status (for region 3)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " [2] ,Region digest mismatch interrupt status (for region 2)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " [1] ,Region digest mismatch interrupt status (for region 1)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " [0] ,Region digest mismatch interrupt status (for region 0)" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 3. " RHC[3] ,Region hash completed interrupt status (for region 3)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " [2] ,Region hash completed interrupt status (for region 2)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " [1] ,Region hash completed interrupt status (for region 1)" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " [0] ,Region hash completed interrupt status (for region 0)" "No interrupt,Interrupt"
|
|
line.long 0x04 "UASR,ICM Undefined Access Status Register"
|
|
bitfld.long 0x04 0.--2. " URAT ,Undefined register access trace" "UNSPEC_STRUCT_MEMBER,ICM_CFG_MODIFIED,CM_DSCR_MODIFIED,ICM_HASH_MODIFIED,READ_ACCESS,?..."
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "DSCR,ICM Descriptor Area Start Address Register"
|
|
hexmask.long 0x00 6.--31. 0x40 " DASA ,Descriptor area start address"
|
|
line.long 0x04 "HASH,ICM Hash Area Start Address Register"
|
|
hexmask.long 0x04 7.--31. 0x80 " HASA ,Hash area start address"
|
|
if (((per.l((ad:0x40048000)))&0x1000)==0x1000)
|
|
wgroup.long 0x38++0x03
|
|
line.long 0x00 "UIHVAL0,ICM User Initial Hash Value Register 0"
|
|
wgroup.long 0x3C++0x03
|
|
line.long 0x00 "UIHVAL1,ICM User Initial Hash Value Register 1"
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "UIHVAL2,ICM User Initial Hash Value Register 2"
|
|
wgroup.long 0x44++0x03
|
|
line.long 0x00 "UIHVAL3,ICM User Initial Hash Value Register 3"
|
|
wgroup.long 0x48++0x03
|
|
line.long 0x00 "UIHVAL4,ICM User Initial Hash Value Register 4"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "UIHVAL5,ICM User Initial Hash Value Register 5"
|
|
wgroup.long 0x50++0x03
|
|
line.long 0x00 "UIHVAL6,ICM User Initial Hash Value Register 6"
|
|
wgroup.long 0x54++0x03
|
|
line.long 0x00 "UIHVAL7,ICM User Initial Hash Value Register 7"
|
|
else
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "UIHVAL0,ICM User Initial Hash Value Register 0 (Not User-programmable)"
|
|
hgroup.long 0x3C++0x03
|
|
hide.long 0x00 "UIHVAL1,ICM User Initial Hash Value Register 1 (Not User-programmable)"
|
|
hgroup.long 0x40++0x03
|
|
hide.long 0x00 "UIHVAL2,ICM User Initial Hash Value Register 2 (Not User-programmable)"
|
|
hgroup.long 0x44++0x03
|
|
hide.long 0x00 "UIHVAL3,ICM User Initial Hash Value Register 3 (Not User-programmable)"
|
|
hgroup.long 0x48++0x03
|
|
hide.long 0x00 "UIHVAL4,ICM User Initial Hash Value Register 4 (Not User-programmable)"
|
|
hgroup.long 0x4C++0x03
|
|
hide.long 0x00 "UIHVAL5,ICM User Initial Hash Value Register 5 (Not User-programmable)"
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "UIHVAL6,ICM User Initial Hash Value Register 6 (Not User-programmable)"
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "UIHVAL7,ICM User Initial Hash Value Register 7 (Not User-programmable)"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0x40070000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,TRNG Control Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " KEY ,Security key"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the TRNG to provide random values" "Disable,Enable"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IMR_SET/CLR,TRNG Interrupt Mask Register"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DATRDY ,Data ready" "Masked,Unmasked"
|
|
newline
|
|
hgroup.long 0x1C++0x03
|
|
hide.long 0x00 "ISR,TRNG Interrupt Status Register"
|
|
in
|
|
newline
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "ODATA,TRNG Output Data Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "AES (Advanced Encryption Standard)"
|
|
base ad:0x4006C000
|
|
width 13.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
sif cpuis("ATSAMV7*")
|
|
bitfld.long 0x00 16. " LOADSEED ,Random number generator seed loading" "No effect,Restart"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 8. " SWRST ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " START ,Start processing" "No effect,Start"
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
sif cpuis("ATSAMV7*")
|
|
bitfld.long 0x00 29. " CMTYP6 ,Countermeasure type 6 (IDLECURRENT)" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " CMTYP5 ,Countermeasure type 5 (ADDACCESS)" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " CMTYP4 ,Countermeasure type 4 (RESTART)" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 26. " CMTYP3 ,Countermeasure type 3 (DUMMY)" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " CMTYP2 ,Countermeasure type 2 (PAUSE)" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " CMTYP1 ,Countermeasure type 1 (EXTKEY)" "Disabled,Enabled"
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x00 20.--23. 1. " CKEY ,Key"
|
|
bitfld.long 0x00 16.--18. " CFBS ,Cipher feedback data size" "128-bit,64-bit,32-bit,16-bit,8-bit,?..."
|
|
bitfld.long 0x00 15. " LOD ,Last output data mode" "No effect,Enabled"
|
|
newline
|
|
sif cpuis("ATSAMA5D2*")
|
|
bitfld.long 0x00 12.--14. " OPMOD ,Operation mode" "ECB,CBC,OFB,CFB,CTR,GCM,XTS,?..."
|
|
else
|
|
bitfld.long 0x00 12.--14. " OPMOD ,Operation mode" "ECB,CBC,OFB,CFB,CTR,GCM,?..."
|
|
endif
|
|
bitfld.long 0x00 10.--11. " KEYSIZE ,Key size" "128 bits,192 bits,256 bits,?..."
|
|
bitfld.long 0x00 8.--9. " SMOD ,Start mode" "Manual,Auto,IDATAR0,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " PROCDLY ,Processing delay (processing time = N * (PROCDLY+1))" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 3. " DUALBUFF ,Dual input buffer" "Inactive,Active"
|
|
bitfld.long 0x00 1. " GTAGEN ,GCM automatic tag generation enable" "Inactive,Active"
|
|
newline
|
|
bitfld.long 0x00 0. " CIPHER ,Processing mode" "Decrypt,Encrypt"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MR,Mode Register"
|
|
hexmask.long.byte 0x00 20.--23. 1. " CKEY ,Key"
|
|
bitfld.long 0x00 16.--18. " CFBS ,Cipher feedback data size" "128-bit,64-bit,32-bit,16-bit,8-bit,?..."
|
|
bitfld.long 0x00 15. " LOD ,Last output data mode" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 12.--14. " OPMOD ,Operation mode" "ECB,CBC,OFB,CFB,CTR,?..."
|
|
bitfld.long 0x00 10.--11. " KEYSIZE ,Key size" "128 bits,192 bits,256 bits,?..."
|
|
bitfld.long 0x00 8.--9. " SMOD ,Start mode" "Manual,Auto,IDATAR0,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. " PROCDLY ,Processing delay (processing time = N * (PROCDLY+1))" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 3. " DUALBUFF ,Dual input buffer" "Inactive,Active"
|
|
bitfld.long 0x00 0. " CIPHER ,Processing mode" "Decrypt,Encrypt"
|
|
endif
|
|
newline
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " TAGRDY ,Tag ready interrupt interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " URAD ,Unspecified register access detection interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DATRDY ,Data ready interrupt mask" "Masked,Not masked"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 16. " TAGRDY ,GCM tag ready" "Not ready,Ready"
|
|
bitfld.long 0x00 12.--15. " URAT ,Unspecified register access" "IDR_WR_PROCESSING,ODR_RD_PROCESSING,MR_WR_PROCESSING,ODR_RD_SUBKGEN,MR_WR_SUBKGEN,WOR_RD_ACCESS,?..."
|
|
newline
|
|
bitfld.long 0x00 8. " URAD ,Unspecified register access detection status" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " DATRDY ,Data ready" "Not ready,Ready"
|
|
elif cpuis("ATSAMA5D2?")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 18. -0x08 18. -0x04 18. " PLENERR ,Padding length error interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 17. -0x08 17. -0x04 17. " EOPAD ,End of padding interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 16. -0x08 16. -0x04 16. " TAGRDY ,Tag ready interrupt interrupt mask" "Masked,Not masked"
|
|
newline
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " URAD ,Unspecified register access detection interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DATRDY ,Data ready interrupt mask" "Masked,Not masked"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 18. " PLENERR ,Padding length error" "Not occurred,Occurred"
|
|
bitfld.long 0x00 17. " EOPAD ,End of padding" "Not over,Over"
|
|
bitfld.long 0x00 16. " TAGRDY ,GCM tag ready" "Not ready,Ready"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " URAT ,Unspecified register access" "IDR_WR_PROCESSING,ODR_RD_PROCESSING,MR_WR_PROCESSING,ODR_RD_SUBKGEN,MR_WR_SUBKGEN,WOR_RD_ACCESS,?..."
|
|
newline
|
|
bitfld.long 0x00 8. " URAD ,Unspecified register access detection status" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " DATRDY ,Data ready" "Not ready,Ready"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IMR_SET/CLR,Interrupt Mask Set/Clear Register"
|
|
setclrfld.long 0x00 8. -0x08 8. -0x04 8. " URAD ,Unspecified register access detection interrupt mask" "Masked,Not masked"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " DATRDY ,Data ready interrupt mask" "Masked,Not masked"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x00 12.--15. " URAT ,Unspecified register access" "IDR_WR_PROCESSING,ODR_RD_PROCESSING,MR_WR_PROCESSING,ODR_RD_SUBKGEN,MR_WR_SUBKGEN,WOR_RD_ACCESS,?..."
|
|
newline
|
|
bitfld.long 0x00 8. " URAD ,Unspecified register access detection status" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " DATRDY ,Data ready" "Not ready,Ready"
|
|
endif
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "KEYWR0,Key Word Register 0"
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "KEYWR1,Key Word Register 1"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "KEYWR2,Key Word Register 2"
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "KEYWR3,Key Word Register 3"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "KEYWR4,Key Word Register 4"
|
|
wgroup.long 0x34++0x03
|
|
line.long 0x00 "KEYWR5,Key Word Register 5"
|
|
wgroup.long 0x38++0x03
|
|
line.long 0x00 "KEYWR6,Key Word Register 6"
|
|
wgroup.long 0x3C++0x03
|
|
line.long 0x00 "KEYWR7,Key Word Register 7"
|
|
wgroup.long 0x40++0x03
|
|
line.long 0x00 "IDATAR0,Input Data Register 0"
|
|
wgroup.long 0x44++0x03
|
|
line.long 0x00 "IDATAR1,Input Data Register 1"
|
|
wgroup.long 0x48++0x03
|
|
line.long 0x00 "IDATAR2,Input Data Register 2"
|
|
wgroup.long 0x4C++0x03
|
|
line.long 0x00 "IDATAR3,Input Data Register 3"
|
|
newline
|
|
hgroup.long 0x50++0x03
|
|
hide.long 0x00 "ODATAR0,Output Data Register 0"
|
|
in
|
|
hgroup.long 0x54++0x03
|
|
hide.long 0x00 "ODATAR0,Output Data Register 1"
|
|
in
|
|
hgroup.long 0x58++0x03
|
|
hide.long 0x00 "ODATAR0,Output Data Register 2"
|
|
in
|
|
hgroup.long 0x5C++0x03
|
|
hide.long 0x00 "ODATAR0,Output Data Register 3"
|
|
in
|
|
newline
|
|
if (((per.l((ad:0x4006C000+0x04)))&0x7000)==0x00)
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "IVR0,Initialization Vector Register 0 (Must Not Be Written In ECB Mode)"
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "IVR1,Initialization Vector Register 1 (Must Not Be Written In ECB Mode)"
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "IVR2,Initialization Vector Register 2 (Must Not Be Written In ECB Mode)"
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "IVR3,Initialization Vector Register 3 (Must Not Be Written In ECB Mode)"
|
|
else
|
|
wgroup.long 0x60++0x0F
|
|
line.long 0x00 "IVR0,Initialization Vector Register 0"
|
|
line.long 0x04 "IVR1,Initialization Vector Register 1"
|
|
line.long 0x08 "IVR2,Initialization Vector Register 2"
|
|
line.long 0x0C "IVR3,Initialization Vector Register 3"
|
|
endif
|
|
sif cpuis("ATSAMA5D4*")||cpuis("ATSAMV7*")||cpuis("ATSAMS7*")||cpuis("ATSAME70*")||cpuis("ATSAMA5D2?")
|
|
tree "GCM (Galois/Counter Mode) Registers"
|
|
group.long 0x70++0x17
|
|
line.long 0x00 "AADLENR,Additional Authenticated Data Length"
|
|
line.long 0x04 "CLENR,Plaintext/Ciphertext Length"
|
|
line.long 0x08 "GHASHR0,GCM Intermediate Hash Word Register 0"
|
|
line.long 0x0C "GHASHR1,GCM Intermediate Hash Word Register 1"
|
|
line.long 0x10 "GHASHR2,GCM Intermediate Hash Word Register 2"
|
|
line.long 0x14 "GHASHR3,GCM Intermediate Hash Word Register 3"
|
|
rgroup.long 0x88++0x13
|
|
line.long 0x00 "TAGR0,GCM Authentication Tag Word Register 0"
|
|
line.long 0x04 "TAGR1,GCM Authentication Tag Word Register 1"
|
|
line.long 0x08 "TAGR2,GCM Authentication Tag Word Register 2"
|
|
line.long 0x0C "TAGR3,GCM Authentication Tag Word Register 3"
|
|
line.long 0x10 "CTRR,GCM Encryption Counter Value Register"
|
|
group.long 0x9C++0x0F
|
|
line.long 0x00 "GCMHR0,GCM H Word Register 0"
|
|
line.long 0x04 "GCMHR1,GCM H Word Register 1"
|
|
line.long 0x08 "GCMHR2,GCM H Word Register 2"
|
|
line.long 0x0C "GCMHR3,GCM H Word Register 3"
|
|
tree.end
|
|
newline
|
|
endif
|
|
sif cpuis("ATSAMA5D2?")
|
|
group.long 0xB0++0x07
|
|
line.long 0x00 "EMR,AES Extended Mode Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NHEAD ,IPSEC next header"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PADLEN ,Auto padding length"
|
|
bitfld.long 0x00 5. " PLIPD ,Protocol layer improved performance decipher" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PLIPEN ,Protocol layer improved performance enable" "No,Yes"
|
|
bitfld.long 0x00 1. " APM ,Auto padding mode" "IPSEC,SSL"
|
|
bitfld.long 0x00 0. " APEN ,Auto padding enable" "No,Yes"
|
|
line.long 0x04 "BCNT,AES Byte Counter Register"
|
|
group.long 0xC0++0x0F
|
|
line.long 0x00 "TWR0,AES Tweak Word Register 0"
|
|
line.long 0x04 "TWR1,AES Tweak Word Register 1"
|
|
line.long 0x08 "TWR2,AES Tweak Word Register 2"
|
|
line.long 0x0C "TWR3,AES Tweak Word Register 3"
|
|
wgroup.long 0xD0++0x0F
|
|
line.long 0x00 "ALPHAR0,AES Alpha Word Register 0"
|
|
line.long 0x04 "ALPHAR1,AES Alpha Word Register 1"
|
|
line.long 0x08 "ALPHAR2,AES Alpha Word Register 2"
|
|
line.long 0x0C "ALPHAR3,AES Alpha Word Register 3"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
newline
|